- Micron Technology, Inc.

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128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM Features DDR SDRAM Small-Outline DIMM MT5VDDT1672H – 128MB MT5VDDT3272H – 256MB For component data sheets, refer to Micron’s Web site: www.micron.com Features Figure 1: • 200-pin, small-outline dual in-line memory module (SODIMM) • Fast data transfer rates: PC-2100, PC-2700, or PC-3200 • 128MB2 (16 Meg x 72) and 256MB (32 Meg x 72) • Supports ECC error detection and correction • VDD = VDDQ = +2.5V • VDDSPD = +2.3V to +3.6V • JEDEC-standard 2.5V I/O (SSTL_2-compatible) • Commands entered on each positive CK edge • DQS edge-aligned with data for READs; centeraligned with data for WRITEs • Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle • Bidirectional data strobe (DQS) transmitted/ received with data (source-synchronous data capture) • Differential clock inputs (CK and CK#) • Four internal device banks for concurrent operation • Selectable burst lengths (BL): 2, 4, or 8 • Auto precharge option • Auto refresh and self refresh modes: 7.8125µs maximum average periodic refresh interval • Serial presence-detect (SPD) with EEPROM • Selectable READ CAS latency for maximum compatibility • Gold edge contacts Table 1: 200-Pin SODIMM (MO-224 R/C C) Module height: 31.75mm (1.25in) Options Marking • Operating temperature1 – Commercial (0°C ≤ TA ≤ +70°C) None – Industrial (–40°C ≤ TA ≤ +85°C) I • Package – 200-pin SODIMM (standard)2 G – 200-pin SODIMM (Pb-free) Y • Memory clock, frequency, CAS latency – 5ns (200 MHz), 400 MT/s, CL = 3 -40B3 – 6ns (167 MHz), 333 MT/s, CL = 2.5 -335 – 7.5ns (133 MHz), 266 MT/s, CL = 2 -262 – 7.5ns (133 MHz), 266 MT/s, CL = 2 -26A – 7.5ns (133 MHz), 266 MT/s, CL = 2.5 -265 • PCB height – 31.75mm (1.25in) Notes: 1. Contact Micron for industrial temperature module offerings. 2. Consult factory for product availability. 3. -40B only available for 256MB modules. Key Timing Parameters Data Rate (MT/s) Speed Grade Industry Nomenclature CL = 3 CL = 2.5 -40B -335 -262 -26A -265 PC-3200 PC-2700 PC-2100 PC-2100 PC-2100 400 – – – – 333 333 266 266 266 PDF: 09005aef80a8e793/Source: 09005aef80a8e767 dd5c16_32x72h.fm - Rev. F 2/07 EN 1 t t t CL = 2 RCD (ns) RP (ns) RC (ns) 266 266 266 266 200 15 15 15 20 20 15 15 15 20 20 55 60 60 65 65 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM Features Table 2: Addressing Refresh count Row addressing Device bank addressing Device configuration Column addressing Module rank addressing Table 3: 256MB 8K 8K (A0–A12) 4 (BA0, BA1) 256Mb (16 Meg x 16) 512 (A0–A8) 1 (SO#) 8K 8K (A0–A12) 4 (BA0, BA1) 512Mb (32 Meg x 16) 1K (A0–A9) 1 (SO#) – Part Numbers and Timing Parameters Base device: 128MB MT46V16M161, 256Mb DDR SDRAM Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Latency (CL-tRCD-tRP) 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 2.7 GB/s 2.7 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 6ns/333 MT/s 6ns/333 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 Part Number2 MT5VDDT1672H(I)G-335__ MT5VDDT1672H(I)Y-335__ MT5VDDT1672H(I)G-262__ MT5VDDT1672H(I)Y-262__ MT5VDDT1672H(I)G-26A__ MT5VDDT1672H(I)Y-26A__ MT5VDDT1672H(I)G-265__ MT5VDDT1672H(I)Y-265__ Table 4: 128MB – Part Numbers and Timing Parameters 256MB Base device: MT46V32M161, 512Mb DDR SDRAM Part Number2 MT5VDDT3272H(I)G-40B__ MT5VDDT3272H(I)Y-40B__ MT5VDDT3272H(I)G-335__ MT5VDDT3272H(I)Y-335__ Notes: PDF: 09005aef80a8e793/Source: 09005aef80a8e767 dd5c16_32x72h.fm - Rev. F 2/07 EN Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Latency (CL-tRCD-tRP) 256MB 256MB 256MB 256MB 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 3.2 GB/s 3.2 GB/s 2.7 GB/s 2.7 GB/s 5ns/400 MT/s 5ns/400 MT/s 6ns/333 MT/s 6ns/333 MT/s 3-3-3 3-3-3 2.5-3-3 2.5-3-3 1. Data sheets for the base device parts can be found on Micron’s Web site. 2. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT5VDDT1672HG-335F3. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 5: Pin Assignments 200-Pin SODIMM Front Pin Symbol Pin Symbol 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 CK0# VSS DQ16 DQ17 VDD DQS2 DQ18 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD CB0 CB1 VSS DQS8 CB2 VDD CB3 NC VSS CK2 CK2# VDD NC NC A12 PDF: 09005aef80a8e793/Source: 09005aef80a8e767 dd5c16_32x72h.fm - Rev. F 2/07 EN Pin 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 200-Pin SODIMM Back Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol A9 VSS A7 A5 A3 A1 VDD A10 BA0 WE# S0# NC VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDDSPD NC 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 3 VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS DQ20 DQ21 VDD DM2 DQ22 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD CB4 CB5 VSS DM8 CB6 VDD CB7 NC VSS VSS VDD VDD CKE0 NC A11 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 A8 VSS A6 A4 A2 A0 VDD BA1 RAS# CAS# NC NC VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DQ46 DQ47 VDD CK1# CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 NC Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM Pin Assignments and Descriptions Table 6: Pin Descriptions Symbol Type Description WE#, CAS#, RAS# CK0, CK0#, CK1, CK1#, CK2, CK2# Input CKE0 Input S0# Input BA0, BA1 Input A0–A12 Input DM0–DM8 Input SDA SCL Input/ Output Input SA0–SA2 Input DQS0–DQS8 Input/ Output Input/ Output Input/ Output Supply Supply Supply Supply – Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Clocks: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS) is referenced to the crossings of CK and CK#. Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. Bank address: BA0 and BA1 define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. Data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. Serial clock for presence-detect: SCL is used to synchronize the presencedetect data transfer to and from the module. Presence-detect address inputs: These pins are used to configure the presence-detect device. Data strobe: Output with READ data, input with WRITE data. DQS is edgealigned with READ data, centered in WRITE data. Used to capture data. Check bits. CB0–CB7 DQ0–DQ63 VREF VDD VSS VDDSPD NC PDF: 09005aef80a8e793/Source: 09005aef80a8e767 dd5c16_32x72h.fm - Rev. F 2/07 EN Input Data input/output: Data bus. SSTL_2 reference voltage. Power supply: +2.5V ±0.2V. (-40B speed grade requires 2.6V ±0.1V) Ground. Serial EEPROM positive power supply: +2.3V to +3.6V. No connect: These pins should be left unconnected. 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram S0# CS# DQS0 DM0 DQS4 DM4 UDQS UDM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ DQ DQ DQ DQ DQ DQ DQ DQS1 DM1 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 UDQS UDM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ DQ DQ DQ DQ DQ DQ DQ DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 LDQS LDM DQ DQ DQ DQ DQ DQ DQ DQ DQS3 DM3 BA0–BA1 A0–A12 (128MB, 256MB) RAS# CAS# WE# CKE0 CK0 CK0# PDF: 09005aef80a8e793/Source: 09005aef80a8e767 dd5c16_32x72h.fm - Rev. F 2/07 EN DQ DQ DQ DQ DQ DQ DQ DQ DQS5 DM5 LDQS LDM DQ DQ DQ DQ DQ DQ DQ DQ DQS6 DM6 DDR SDRAM CK1 CK1# CS# U6 LDQS LDM DQ DQ DQ DQ DQ DQ DQ DQ CS# U5 DQ DQ DQ DQ DQ DQ DQ DQ SPD EEPROM U3 SCL WP A0 VSS A1 A2 SDA SA0 SA1 SA2 DDR SDRAM DDR SDRAM DDR SDRAM U1, U2 UDQS UDM DQ DQ DQ DQ DQ DQ DQ DQ LDQS LDM DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DDR SDRAM VDD VDD NC NC NC NC NC NC NC NC DQ DQ DQ DQ DQ DQ DQ DQ DQS7 DM7 DDR SDRAM DDR SDRAM U4 UDQS UDM DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U2 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 LDQS LDM DQ DQ DQ DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CS# DQS8 DM8 CS# UDQS UDM DDR SDRAM U4, U5 5 VDDSPD SPD EEPROM VDD DDR SDRAM VREF DDR SDRAM VSS DDR SDRAM CK2 CK2# DDR SDRAM U6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM General Description General Description The MT5VDDT1672H and MT5VDDT3272H are high-speed CMOS, dynamic randomaccess, 128MB and 256MB memory modules organized in a x72 (ECC) configuration. DDR SDRAM modules use internally configured quad-bank DDR SDRAM devices. DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for DDR SDRAM modules effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edgealigned with data for READs and center-aligned with data for WRITEs. DDR SDRAM modules operate from differential clocks (CK, CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Serial Presence-Detect (SPD) Operation DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA(2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to VSS on the module, permanently disabling hardware write protect. PDF: 09005aef80a8e793/Source: 09005aef80a8e767 dd5c16_32x72h.fm - Rev. F 2/07 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 7 may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions above those indicated in each device’s data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 7: Symbol VDD VREF VTT VIH(DC) VIL(DC) II IOZ IOH IOL IOH IOL TA Absolute Maximum Ratings Parameter/Condition VDD supply voltage relative to VSS I/O reference voltage I/O termination voltage (system) Input high (logic 1) voltage Input low (logic 0) voltage Input leakage current; Any input 0V ≤ VIN ≤ VDD; VREF pin 0V ≤ VIN ≤ 1.35V (All other pins not under test = 0V) Command/address, RAS#, CAS#, WE#, CKE, S#, BA CK0, CK0#, CK1, CK1# DM, CK2, CK2# DQ, DQS Output leakage current (DQ pins are disabled; 0V ≤ VOUT ≤ VDDQ) Output levels High current (VOUT = VDDQ - 0.373V, MIN VREF, MIN VTT) Low current (VOUT = 0.373V, MAX VREF, MAX VTT) Output levels (reduced drive option) High current (VOUT = VDDQ - 0.373V, MIN VREF, MIN VTT) Low current (VOUT = 0.373V, MAX VREF, MAX VTT) Module ambient operating temperature Commercial Industrial Min Max Units 2.3 0.49 × VDDQ VREF - 0.04 VREF + 0.15 –0.3 –10 2.7 0.51 × VDDQ VREF + 0.04 VDD + 0.3 VREF - 0.15 10 V V V V V µA –4 4 –2 –5 2 5 µA –16.8 16.8 – – mA mA –9 9 – – mA mA 0 –40 +70 +85 °C Input Capacitance Micron encourages designers to simulate the performance of the module to achieve optimum values. Simulations are significantly more accurate and realistic than a gross estimation of module capacitance when inductance and delay parameters associated with trace lengths are used in simulations. JEDEC modules are currently designed using simulations to close timing budgets. PDF: 09005aef80a8e793/Source: 09005aef80a8e767 dd5c16_32x72h.fm - Rev. F 2/07 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM Electrical Specifications Component AC Timing and Operating Conditions Recommended AC operating conditions are given in the DDR component data sheets. Component specifications are available on Micron’s Web site. Module speed grades correlate with component speed grades, as shown in Table 8. Table 8: Module and Component Speed Grades Module Speed Grade Component Speed Grade -40B -335 -262 -26A -265 -5B -6 -75E -75Z -75 PDF: 09005aef80a8e793/Source: 09005aef80a8e767 dd5c16_32x72h.fm - Rev. F 2/07 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM Electrical Specifications IDD Specifications Table 9: DDR IDD Specifications and Conditions – 128MB Values shown for MT46V16M16 DDR SDRAM only and are computed from values specified in the 256Mb (16 Meg x 16) component data sheet Parameter/Condition Operating one bank active-precharge current: t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles Operating one bank active-read-precharge current: Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle Precharge power-down standby current: All device banks idle; Powerdown mode; tCK = tCK (MIN); CKE = (LOW) Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS, and DM Active power-down standby current: One device bank active; Powerdown mode; tCK = tCK (MIN); CKE = LOW Active standby current: CS# = HIGH; CKE = HIGH; One device bank; Active-precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Operating current: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA Operating current: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC = tRFC (MIN) Auto refresh current tREFC = 7.8125µs Self refresh current: CKE ≤ 0.2V Operating current: Four device bank interleaving READs (BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands PDF: 09005aef80a8e793/Source: 09005aef80a8e767 dd5c16_32x72h.fm - Rev. F 2/07 EN 9 Symbol -335 -262 -26A/ -265 Units IDD0 625 625 525 mA IDD1 900 850 775 mA IDD2P 20 20 20 mA IDD2F 250 225 225 mA IDD3P 150 125 125 mA IDD3N 300 250 250 mA IDD4R 1,100 925 925 mA IDD4W 900 725 725 mA IDD5 IDD5A IDD6 IDD7 1,275 30 20 2,200 1,175 30 20 1,900 1,175 30 20 1,900 mA mA mA mA Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM Electrical Specifications Table 10: DDR IDD Specifications and Conditions – 256MB Values shown for MT46V32M16 DDR SDRAM only and are computed from values specified in the 512Mb (32 Meg x 16) component data sheet Parameter/Condition t t Operating one bank active-precharge current: RC = RC (MIN); t CK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles Operating one bank active-read-precharge current: Burst = 4; t RC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle Precharge power-down standby current: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS, and DM Active power-down standby current: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW Active standby current: CS# = HIGH; CKE = HIGH; One device bank; Activeprecharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Operating current: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA Operating current: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC = tRFC (MIN) Auto refresh current tREFC = 7.8125µs Self refresh current: CKE ≤ 0.2V Operating current: Four device bank interleaving READs (BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands PDF: 09005aef80a8e793/Source: 09005aef80a8e767 dd5c16_32x72h.fm - Rev. F 2/07 EN 10 Symbol -40B -335 Units IDD0 775 650 mA IDD1 925 800 mA IDD2P 25 25 mA IDD2F 275 225 mA IDD3P 225 175 mA IDD3N 300 250 mA IDD4R 950 825 mA IDD4W 975 775 mA IDD5 1,725 55 25 2,250 1,450 50 25 2,025 mA mA mA mA IDD5A IDD6 IDD7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM Serial Presence-Detect Serial Presence-Detect Table 11: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage: IOUT = 3mA Input leakage current: VIN = GND to VDD Output leakage current: VOUT = GND to VDD Standby current: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD Power supply current: SCL clock frequency = 100 kHz Table 12: Symbol Min Max Units VDDSPD VIH VIL VOL ILI ILO ISB ICC 2.3 VDDSPD × 0.7 –1 – – – – – 3.6 VDDSPD + 0.5 VDDSPD × 0.3 0.4 10 10 30 2 V V V V µA µA µA mA Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V Parameter/Condition SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time Notes: PDF: 09005aef80a8e793/Source: 09005aef80a8e767 dd5c16_32x72h.fm - Rev. F 2/07 EN Symbol Min Max Units Notes tAA 0.2 1.3 200 – 0 0.6 0.6 – 1.3 – – 100 0.6 0.6 – 0.9 – – 300 – – – 50 – 0.3 400 – – – 10 µs µs ns ns µs µs µs ns µs µs kHz ns µs µs ms 1 tBUF tDH tF tHD:DAT tHD:STA tHIGH tI tLOW tR fSCL tSU:DAT tSU:STA tSU:STO t WRC 2 2 3 4 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistance, and the EEPROM does not respond to its slave address. 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM Serial Presence-Detect Table 13: Byte Serial Presence-Detect Matrix (-335, -26A, and -265 Speed Grades) Description 0 1 2 3 4 5 6 7 8 9 Number of SPD bytes used by Micron Total number of bytes in SPD device Fundamental memory type Number of row addresses on assembly Number of column addresses on assembly Number of physical ranks on DIMM Module data width Module data width (continued) Module voltage interface levels SDRAM cycle time, tCK, CL = 2.5 10 SDRAM access from clock, tAC, CL = 2.5 11 12 13 14 15 16 17 18 19 20 21 22 23 Module configuration type Refresh rate/type SDRAM device width (primary DDR SDRAM) Error-checking DDR SDRAM data width MIN clock delay, back-to-back random column access Burst lengths supported Number of banks on DDR SDRAM device CAS latencies supported CS latency WE latency SDRAM module attributes SDRAM device attributes: general SDRAM cycle time, tCK, CL = 2 24 SDRAM access from clock, tAC, CL = 2 25 26 27 SDRAM cycle time, tCK, CL = 1.5 SDRAM access from CK, tAC, CL = 1.5 MIN row precharge time, tRP4 28 MIN row active-to-row active, tRRD 29 MIN RAS#-to-CAS# delay, tRCD4 30 MIN RAS# pulse width, tRAS2 31 32 Module rank density Address and command setup time, tIS3 PDF: 09005aef80a8e793/Source: 09005aef80a8e767 dd5c16_32x72h.fm - Rev. F 2/07 EN Entry (Version) 128MB 256MB 128 256 DDR SDRAM 12,13 9, 10 1 72 0 SSTL 2.5V 6ns (-335) 7ns (-262/-26A) 7.5ns (-265) 0.7ns (-335) 0.75ns (-262/-26A/ -265) ECC 15.62µs, 7.8µs/SELF 16 16 1 clock 80 08 07 0D 09 01 48 00 04 60 70 75 70 75 80 08 07 0D 0A 01 48 00 04 60 70 75 70 75 02 82 10 10 01 02 82 10 10 01 2, 4, 8 4 2.5, 2 0 1 Unbuffered/diff. clock Fast/concurrent AP 7.5ns (-335/-262/-26A) 10ns (-265) 0.7ns (-335) 0.75ns (-262/-26A/ -265) 0E 04 0C 01 02 20 C1 75 A0 70 75 0E 04 0C 01 02 20 C1 75 A0 70 75 00 00 48 3C 50 30 3C 48 3C 50 2A 2D 20 80 A0 00 00 48 3C 50 30 3C 48 3C 50 2A 2D 40 80 A0 18ns (-335) 15ns (-262) 20ns (-26A/-265) 12ns (-335) 15ns (-262/-26A/-265) 18ns (-335) 15ns (-262) 20ns (-26A/-265) 42ns (-335) 45ns (-262/-26A/-265) 128MB, 256MB 0.8ns (-335) 1.0ns (-262/-26A/-265) 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM Serial Presence-Detect Table 13: Byte Serial Presence-Detect Matrix (-335, -26A, and -265 Speed Grades) (continued) Description tIH3 33 Address and command hold time, 34 Data/data mask input setup time, tDS 35 Data/data mask input hold time, tDH 36–40 Reserved 41 MIN active-to-active/refresh time, tRC 42 MIN AUTO REFRESH-to-ACTIVE/AUTO REFRESH command period, tRFC 43 SDRAM device MAX cycle time, tCK (MAX) 44 SDRAM device MAX DQS–DQ skew time, tDQSQ 45 SDRAM device MAX read data hold skew factor, tQHS 46 Reserved 47 DIMM height 48–61 Reserved 62 SPD revision 63 Checksum for bytes 0–62 64 65–71 72 73–90 91 92 93 94 95–98 99– 127 Entry (Version) 128MB 256MB 0.8ns (-335) 1.0ns (-262/-26A/-265) 0.45ns (-335) 0.5ns (-262/-26A/-265) 0.45ns (-335) 0.5ns (-262/-26A/-265) 0 60ns (-335/-262) 65ns (-26A/-265) 72ns (-335) 75ns (-262/-26A/-265) 12ns (-335) 13ns (-262/-26A/-265) 0.45ns (-335) 0.5ns (-262/-26A/-265) 0.55ns (-335) 0.75ns (-262/-26A/-265) 0 80 A0 45 50 45 50 00 3C 41 48 4B 30 34 2D 32 55 75 00 01 00 10 29 BC E9 19 2C 00 01–0C Variable data 01–09 00 Variable data Variable data Variable data 00 80 A0 45 50 45 50 00 3C 41 48 4B 30 34 2D 32 55 75 00 01 00 10 4A DD 0A 3A 2C 00 01–0C Variable data 01–09 00 Variable data Variable data Variable data 00 0 Release 1.0 -335 -262 -26A -265 MICRON (continued) 1–12 – 1–9 0 – – – Manufacturer’s JEDEC ID code Manufacturer’s JEDEC ID code Manufacturing location Module part number (ASCII) PCB identification code Identification code (continued) Year of manufacture in BCD Week of manufacture in BCD Module serial number Reserved for manufacturer-specific data Notes: PDF: 09005aef80a8e793/Source: 09005aef80a8e767 dd5c16_32x72h.fm - Rev. F 2/07 EN 1. The value for -26A tCK set to 7ns (0 x 70) for optimum BIOS compatibility. Actual device specification value is 7.5ns. 2. The value of tRAS used for -262/-26A/-265 modules is calculated from tRC - tRP. Actual device specification value is 40ns. 3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worstcase (slow slew rate) value is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster minimum slew rate is met. 4. The value of tRP, tRCD, and tRAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR SDRAM device specification is 15ns. 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM Serial Presence-Detect Table 14: Serial Presence-Detect Matrix (-40B Speed Grade) Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36–40 41 42 43 44 45 46 47 Description Number of SPD bytes used by Micron Total number of bytes in SPD device Fundamental memory type Number of row addresses on assembly Number of column addresses on assembly Number of physical ranks on DIMM Module data width Module data width (continued) Module voltage interface levels SDRAM cycle time, tCK, CL = 3 SDRAM access from clock, tAC, CL = 3 Module configuration type Refresh rate/type SDRAM device width (primary DDR SDRAM) Error-checking DDR SDRAM data width MIN clock delay, back-to-back random column access Burst lengths supported Number of banks on DDR SDRAM device CAS latencies supported CS latency WE latency SDRAM module attributes SDRAM device attributes: general SDRAM cycle time, tCK, CL = 2.5 SDRAM access from clock, tAC, CL = 2.5 SDRAM cycle time, tCK, CL = 2 SDRAM access from CK, tAC, CL = 2 MIN row precharge time, tRP MIN row active-to-row active, tRRD MIN RAS#-to-CAS# delay, tRCD MIN RAS# pulse width, tRAS Module rank density Address and command setup time, tIS Address and command hold time, tIH Data/data mask input setup time, tDS Data/data mask input hold time, tDH Reserved MIN active-to-active/refresh time, tRC MIN AUTO REFRESH-to-ACTIVE/AUTO REFRESH command period, tRFC SDRAM device MAX cycle time,tCK (MAX) SDRAM device MAX DQS–DQ skew time, tDQSQ SDRAM device MAX read data hold skew factor, tQHS Reserved DIMM height PDF: 09005aef80a8e793/Source: 09005aef80a8e767 dd5c16_32x72h.fm - Rev. F 2/07 EN 14 Entry (Version) 256MB 128 256 DDR SDRAM 13 10 1 72 0 SSTL 2.5V 5ns 0.7ns ECC 7.8µs/SELF 16 16 1 clock 2, 4, 8 4 3, 2.5, 2 0 1 Unbuffered/diff. clock Fast/concurrent AP 6ns 0.7ns (-335 compatibility) 7.5ns 0.75ns (-265 compatibility) 15ns 10ns 15ns 40ns 256MB 0.6ns 0.6ns 0.4ns 0.4ns 0 55ns 70ns 80 08 07 0D 0A 01 48 00 04 50 70 02 82 10 10 01 0E 04 1C 01 02 20 C1 60 70 75 75 3C 28 3C 28 40 60 60 40 40 00 37 46 12ns 0.4ns 0.5ns 0 30 28 50 00 01 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM Serial Presence-Detect Table 14: Serial Presence-Detect Matrix (-40B Speed Grade) (continued) Byte 48–61 62 63 64 65–71 72 73–90 91 92 93 94 95–98 99–127 Description Reserved SPD revision Checksum for bytes 0–62 Manufacturer’s JEDEC ID code Manufacturer’s JEDEC ID code Manufacturing location Module part number (ASCII) PCB identification code Identification code (continued) Year of manufacture in BCD Week of manufacture in BCD Module serial number Reserved for manufacturer-specific data PDF: 09005aef80a8e793/Source: 09005aef80a8e767 dd5c16_32x72h.fm - Rev. F 2/07 EN 15 Entry (Version) 256MB 0 Release 1.1 – MICRON (continued) 1–12 – 1–9 0 – – – 00 11 A3 2C 00 01–0C Variable data 01–09 00 Variable data Variable data Variable data 00 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM Module Dimensions Module Dimensions Figure 3: 200-Pin SODIMM Dimensions Front view 3.80 (0.150) MAX 67.75 (2.667) 67.45 (2.656) 2.00 (0.079) R (2X) U1 U2 1.80 (0.071) (2X) U4 U5 31.90 (1.256) 31.60 (1.244) U3 20.00 (0.787) TYP 6.00 (0.236) 2.44 (0.096) 2.00 (0.079) 1.10 (0.043) 0.90 (0.035) 0.99 (0.039) TYP 0.46 (0.018) TYP 0.61 (0.024) TYP PIN 199 PIN 1 63.60 (2.504) TYP Back view U6 PIN 200 Notes: PIN 2 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for complete design dimensions. ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 [email protected] www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef80a8e793/Source: 09005aef80a8e767 dd5c16_32x72h.fm - Rev. F 2/07 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved.