Preview only show first 10 pages with watermark. For full document please download

Ml506 Gerber Plots

   EMBED

Share

Transcript

ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415 ARTMASTER # 0531630 Designed by Xilinx Oct 04 2006 LAYER: 01 OF 25 L1_TOP ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415 ARTMASTER # 0531630 Designed by Xilinx Oct 04 2006 LAYER: 02 OF 25 L2_PWR ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415 ARTMASTER # 0531630 Designed by Xilinx Oct 04 2006 LAYER: 03 OF 25 L3_GND ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415 ARTMASTER # 0531630 Designed by Xilinx Oct 04 2006 LAYER: 04 OF 25 L4_SIG ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415 ARTMASTER # 0531630 Designed by Xilinx Oct 04 2006 LAYER: 05 OF 25 L5_SIG ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415 ARTMASTER # 0531630 Designed by Xilinx Oct 04 2006 LAYER: 06 OF 25 L6_GND ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415 ARTMASTER # 0531630 Designed by Xilinx Oct 04 2006 LAYER: 07 OF 25 L7_SIG ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415 ARTMASTER # 0531630 Designed by Xilinx Oct 04 2006 LAYER: 08 OF 25 L8_SIG ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415 ARTMASTER # 0531630 Designed by Xilinx Oct 04 2006 LAYER: 09 OF 25 L9_GND ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415 ARTMASTER # 0531630 Designed by Xilinx Oct 04 2006 LAYER: 10 OF 25 L10_SIG ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415 ARTMASTER # 0531630 Designed by Xilinx Oct 04 2006 LAYER: 11 OF 25 L11_PWR ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415 ARTMASTER # 0531630 Designed by Xilinx Oct 04 2006 LAYER: 12 OF 25 L12_GND ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415 ARTMASTER # 0531630 Designed by Xilinx Oct 04 2006 LAYER: 13 OF 25 L13_GND KEYB C321 J54 C308 C371 C303 R38 C309 TCK GND DS41 R199 VCC5V C275 C396 R61 R62 CP12 2006 Xilinx, Incorporated ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415 ARTMASTER # 0531630 VCC3V3 E SW8 S J77 c P21 Designed by Xilinx Oct 04 2006 LAYER: 19 OF 25 SILK-SCREEN TOP DS22 SW11 C416 DONE SW12 C SW14 C399 MH7 1 CP13 CONTRAST J80 R63 R60 INIT DS3 DS4 DS1 DS2 SACE 7 STAT ERR GPI/O 5 6 RP20 W DS23 3V3 GPIO DIP SW RP58 RP59 RP54 RP55 RP53 GPI/O RP14 SW2 DS24 SW13 50 52 54 56 58 64 GND DIFF 2V5 PINS ENCODER DS21 U4 PLAT FASH 1 44 46 48 SCL 64 SDA SW10 U6B RP11 RP35 4 DUP 1 2 3 1FAN BYP RP10 DS17 DS16 DS15 DS13 DS14 DS12 DS11 DS10 SW4 PCIE FINGER 1X U27 Q8 DS20 N TP12 TP10 0 CPU J32 RST ENET LEDS TP11 Q9 R85 C392 RP52 J40 SATA HOST 2 SW7 DS33 DS35 DS34 DS30 DS31 DS32 SW5 VIRTEX-5 ML505-ML509 REV A Systems Engineering Group SYSACE RST CP40 CHAR LCD J41 C290 C47 C295 SOFTOUCH PRO C317 C62 C58 C395 TP13 U3 40 42 U8 C66 MH6 36 38 SWW LEDS SWS B27 U1 R163 ERR1 PROG FB40 U31 J8 10 100 DS5 1000 DS6 ERR2 C401 N 1 J11 1 DIFF CLK IN J33 1 J24 J10 FB30 SATA P CLK SEL R87 U26 J23 J56 C103 C102 DVI FB31 C93 SATA HOST 1 TX RX R110 U17 USB ABORT BOOT SWC LEDW LED2 LED3 J16 A27 C415 30 32 34 LEDE SWE LED0 LED1 X2 RP50 3V3 U18 1 ENET MODE SEL J22 U38 R78 C414 RP28 RP26 37 P7 B1 C60 CP38 1 SPI PROG C61 TDO J43 FAN 38 2 A1 26 28 TDI LEDN SWN LEDC RP29 RP25 INIT TMS TDI C403 J45 TRACE/DEBUG P22 1 J2 10/100/1000 ETHERNET MGT C244 J42 U33 RXP R171 J44 TXP P6 TCK TDO C63 FB77 U16 R138 TMS RP30 RP27 C311 P8 1V8 REG C294 RP31 C333 RXN C276 R139 C159 C158 PIEZO CP130 U19 2 4 6 8 10 12 14 16 18 20 22 24 SP1 P U30 TXN U23 J12 C67 A1 ON SW1 J5 J6 X8 C141 C318 C53 3V3 REG U35 C280 DIFF CLK OUT C375 R37 R35 X7 BATT C305 C391 U45 C315 LVDS CLKOUT SEL 1 OFF J7 XGI J4 C319 C316 1 R137 C152 R222 R223 R67 C21 R69 SUPRCLK USR OSC FB55 FRONT PANEL AUDIO J28 R95 RP9 1 X1 J13 TP1 R140 R96 X3 R157 U22 C157 FB8 X5 R221 C20 C288 C260 C23 C434 C372 C205 C206 1 SACE FAILSAFE VIDEO IN J19 J18 1 C162 X4 PC4 JTAG 1V0 REG R141 C156 C22 FB3 CFG0 MOD2 MOD1 MOD0 R194 U37 C143 USR CLOCK J15 2V5 3V3 VCCO_SEL 1 J20 1 C163 J17 AVDD SEL C164 C279 R30 R31 R91 C282 1V8 J70 CP1 C204 C400 C2 J61 FB2 C14 R84 BDM SYSMON HDR U9 1 FB94 R210 P10 HEADPHONE P11 LINE IN MICROPHONE N P13 R220 R224 CLK GEN JTAG 5V R36 + U29 R52 R191 P20 1 R195 20 C261 C398 R53 R190 P19 SFP C177 C44 FB14 FB11 C43 R83 C417 1 P12 LINE OUT R211 R80 J21 CFG1 CFG2 J1 1 11 U13 J51 C38 C39 R79 1 J3 J83 RTSEL 1 COM1 J60 COM2 J9 C42 C41 Q12 RP22 C264 1 J81 RP6 FALL BCK R150 C170 SW3 RP2 1 CP3 1 FB95 10 MOUSE 1 SACE EN R173 1 CLK JTAG 1 J26 PROG Q11 J82 USB TX DISAB R145 R147 R146 C166 SFP DS40 LNK 1 Q13 Q14 FB10 PS/2 1 C40 J14 COM1 1 RP21 RP15 J62 J63 P18 C46 PS/2 FB12 MOUSE C45 FB13 USB PERIPH P17 R151 FB60 SPDIF FB61 P14 P5 P4 J25 KEYB + + USB HOST C171 60 62 64 GND PIN ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415 ARTMASTER # 0531630 Designed by Xilinx Oct 04 2006 LAYER: 15 OF 25 MASK TOP ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415 ARTMASTER # 0531630 Designed by Xilinx Oct 04 2006 LAYER: 17 OF 25 PASTE TOP P5 P17 P3 P4 SW1 J15 P18 DS41 C276 C275 R139 C315 C316 R96 R95 C294 R37 C319 R35 R36 C67 C375 A1 J6 C260 R137 C152 C164 FB8 C303 J5 C371 U35 C290 R223 R222 C206 C205 C308 C309 J7 J19 B1 C305 MH1 B1 C318 C53 A1 U19 P8 SP1 J4 C288 J12 J28 U38 J18 C321 C391 X7 C204 C400 R195 R211 C177 R210 X8 J54 R38 FB95 R69 U29 C158 R157 R30 R31 R67 U37 X5 J3 FB94 C21 R221 R220 R224 CP3 C372 R79 J1 C20 R191 R190 C261 J21 20 R52 U45 C141 C157 X3 + R80 R194 R145 R53 11 C23 C22 J81 J83 R146 RP6 C434 C264 C398 TP1 C156 FB55 X4 FB3 J70 CP1 P19 J13 R140 R141 U9 RP9 C417 C279 DS40 RP2 R173 C166 J82 C39 RP22 U22 C47 C282 R91 J9 C38 SW3 J17 C170 C42 U13 Q12 C163 C41 Q11 C159 C162 MH3 P14 X1 J20 MH4 R199 FB2 C40 + + J14 Q14 R147 1 J61 J51 Q13 10 C2 J60 C14 R83 P10 R138 J62 RP21 C43 J63 J26 R84 FB14 FB11 J25 P11 P13 C143 FB61 R150 R151 C44 FB12 FB13 C46 FB60 C45 C171 RP15 FB10 P20 P12 RP31 C280 RP30 C333 U30 J44 RP27 C63 CP130 C295 RP29 J42 C311 J16 C244 RP25 C60 R171 U1 C317 FB77 U23 X2 RP28 C61 U33 RP26 C62 J43 CP38 38 U8 B27 A27 C414 R78 2 P6 J2 C403 C58 J45 U16 J31 P22 RP50 C66 C415 MH2 U31 C102 C103 U17 RP55 RP54 RP58 RP59 CP40 J33 R163 TP12 TP11 DS24 R62 C93 FB31 DS21 U26 J41 J10 RP14 U6B R61 J8 FB30 Q8 SW10 TP10 J56 Q9 DS20 U27 TP13 MH6 C395 RP53 J40 J23 J24 R85 C392 R87 C396 U18 RP52 J11 J22 SW2 R110 37 C401 U3 SW13 SW14 SW12 MH5 U4 P7 RP20 RP11 CP13 DS2 DS1 DS4 DS3 DS10 DS11 DS12 DS14 DS15 DS13 DS6 DS16 DS5 DS17 DS32 DS31 DS30 DS34 DS33 J80 MH7 J77 P21 DS35 R86 C399 R60 RP35 CP12 SW7 C416 SW4 MH8 DS22 ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415 ARTMASTER # 0531630 Designed by Xilinx Oct 04 2006 LAYER: 22 OF 25 ASSY_TOP SW11 SW8 RP10 SW5 FB40 R63 DS23 J32 KEYB C321 J54 C308 C371 C303 R38 C309 TCK GND DS41 R199 VCC5V C275 C396 R61 R62 CP12 2006 Xilinx, Incorporated ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415 ARTMASTER # 0531630 VCC3V3 E SW8 S J77 c P21 Designed by Xilinx Oct 04 2006 LAYER: 22 OF 25 ASSY_TOP 19 OF 25 SILK-SCREEN TOP DS22 SW11 C416 DONE SW12 C SW14 C399 MH7 1 CP13 CONTRAST J80 R63 R60 INIT DS3 DS4 DS1 DS2 SACE 7 STAT ERR GPI/O 5 6 RP20 W DS23 3V3 GPIO DIP SW RP58 RP59 RP54 RP55 RP53 GPI/O RP14 SW2 DS24 SW13 50 52 54 56 58 64 GND DIFF 2V5 PINS ENCODER DS21 U4 PLAT FASH 1 44 46 48 SCL 64 SDA SW10 U6B RP11 RP35 4 DUP 1 2 3 1FAN BYP RP10 DS17 DS16 DS15 DS13 DS14 DS12 DS11 DS10 SW4 PCIE FINGER 1X U27 Q8 DS20 N TP12 TP10 0 CPU J32 RST ENET LEDS TP11 Q9 R85 C392 RP52 J40 SATA HOST 2 SW7 DS33 DS35 DS34 DS30 DS31 DS32 SW5 VIRTEX-5 ML505-ML509 REV A Systems Engineering Group SYSACE RST CP40 CHAR LCD J41 C290 C47 C295 SOFTOUCH PRO C317 C62 C58 C395 TP13 U3 40 42 U8 C66 MH6 36 38 SWW LEDS SWS B27 U1 R163 ERR1 PROG FB40 U31 J8 10 100 DS5 1000 DS6 ERR2 C401 N 1 J11 1 DIFF CLK IN J33 1 J24 J10 FB30 SATA P CLK SEL R87 U26 J23 J56 C103 C102 DVI FB31 C93 SATA HOST 1 TX RX R110 U17 USB ABORT BOOT SWC LEDW LED2 LED3 J16 A27 C415 30 32 34 LEDE SWE LED0 LED1 X2 RP50 3V3 U18 1 ENET MODE SEL J22 U38 R78 C414 RP28 RP26 37 P7 B1 C60 CP38 1 SPI PROG C61 TDO J43 FAN 38 2 A1 26 28 TDI LEDN SWN LEDC RP29 RP25 INIT TMS TDI C403 J45 TRACE/DEBUG P22 1 J2 10/100/1000 ETHERNET MGT C244 J42 U33 RXP R171 J44 TXP P6 TCK TDO C63 FB77 U16 R138 TMS RP30 RP27 C311 P8 1V8 REG C294 RP31 C333 RXN C276 R139 C159 C158 PIEZO CP130 U19 2 4 6 8 10 12 14 16 18 20 22 24 SP1 P U30 TXN U23 J12 C67 A1 ON SW1 J5 J6 X8 C141 C318 C53 3V3 REG U35 C280 DIFF CLK OUT C375 R37 R35 X7 BATT C305 C391 U45 C315 LVDS CLKOUT SEL 1 OFF J7 XGI J4 C319 C316 1 R137 C152 R222 R223 R67 C21 R69 SUPRCLK USR OSC FB55 FRONT PANEL AUDIO J28 R95 RP9 1 X1 J13 TP1 R140 R96 X3 R157 U22 C157 FB8 X5 R221 C20 C288 C260 C23 C434 C372 C205 C206 1 SACE FAILSAFE VIDEO IN J19 J18 1 C162 X4 PC4 JTAG 1V0 REG R141 C156 C22 FB3 CFG0 MOD2 MOD1 MOD0 R194 U37 C143 USR CLOCK J15 2V5 3V3 VCCO_SEL 1 J20 1 C163 J17 AVDD SEL C164 C279 R30 R31 R91 C282 1V8 J70 CP1 C204 C400 C2 J61 FB2 C14 R84 BDM SYSMON HDR U9 1 FB94 R210 P10 HEADPHONE P11 LINE IN MICROPHONE N P13 R220 R224 CLK GEN JTAG 5V R36 + U29 R52 R191 P20 1 R195 20 C261 C398 R53 R190 P19 SFP C177 C44 FB14 FB11 C43 R83 C417 1 P12 LINE OUT R211 R80 J21 CFG1 CFG2 J1 1 11 U13 J51 C38 C39 R79 1 J3 J83 RTSEL 1 COM1 J60 COM2 J9 C42 C41 Q12 RP22 C264 1 J81 RP6 FALL BCK R150 C170 SW3 RP2 1 CP3 1 FB95 10 MOUSE 1 SACE EN R173 1 CLK JTAG 1 J26 PROG Q11 J82 USB TX DISAB R145 R147 R146 C166 SFP DS40 LNK 1 Q13 Q14 FB10 PS/2 1 C40 J14 COM1 1 RP21 RP15 J62 J63 P18 C46 PS/2 FB12 MOUSE C45 FB13 USB PERIPH P17 R151 FB60 SPDIF FB61 P14 P5 P4 J25 KEYB + + USB HOST C171 60 62 64 GND PIN