Transcript
Module Introduction PURPOSE: The intent of this module is to present the purpose and design of MPC5200 peripherals and their ports as well as information about some of the related protocols. OBJECTIVES: • Describe the ports and their configuration requirements for MPC5200 peripherals. • Discuss PSCs and their functions. • Describe the Ethernet protocol and its hardware implementations. • Identify the characteristics of the USB and IrDA . • Describe the features of the I2C Controller. • List the features of MSCAN and the purpose of the CAN 2.0A/B protocol. • Describe the features of the J1850 Byte Data Link Controller and how it is used. • Recognize the features of the SPI. • Describe the Timer functions and the availability of GPIO pins. • Describe the design and functions of the RTC. CONTENT: - 38 pages - 7 questions LEARNING TIME: - 75 minutes
The intent of this module is to present the purpose and design of MPC5200 peripherals. You will be able to identify PSCs, USB, IrDA, I2C, MSCAN, J1850, SPI, GPIO, and RTC. Port configurations for peripherals are also covered. Finally, throughout this module, you will learn about some of the related protocols such as Ethernet and CAN 2.0A/B.
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M S C A N
SDRAM CS1
S P I
System chip selects
TSIZE_1 4
G P I O
I 2 C
4
T I M E R S 4
P S C 1
8
P S C 5
Ports
P S C 2
5
5
P S C 3
5
P S C 4
5
4
2
E T H E R 5
U S B
P2
10 100 7
2
ATA chip selects
P S C 6
J 1 8 5 0
I R
P1
10 10
18
2
Reset Conf. 2
mux 1
2
4
mux
8
2
5
4
5
10
mux
mux
mux
mux
8 Pins
5 pins
5 pins
10 pins
14 mux mux
8
2
5
4
mux
mux
18 pins
10 pins
4 pins
Ethernet Group
USB Group
IrDA Group
1
Dedicated GPIO
4 pins
I2 C Group
Timer Group
PSC1 Group
PSC2 Group
PSC3 Group
The peripheral elements of the MPC5200, such as the Programmable Serial Control (PSC) modules and Ethernet, are connected to the external package pins through a set of multiplexers. There are eight ports: PSC1, PSC2, PSC3, I2C, Timer, Ethernet, USB and PSC6. The ports themselves have different numbers of pins. For instance, the Timer port has eight pins and the PSC3 port has ten pins. Each peripheral module can be connected to one or more of the ports. However, in no case can a single peripheral module be connected to more than one port at a time. It is possible to reconfigure a port so that a particular module is disconnected. Then, the same peripheral module can be assigned to another port—if that configuration is allowed. Here you can see the allowable connections between the peripheral modules and the ports. For instance, the PSC2 port can accommodate the Scalable Controller Area Network (MSCAN) module, the PSC2 module, and the General Purpose Input Output (GPIO) module. The MSCAN module can be routed to the Inter-Integrated Circuit (I2C) port, the Timer Port, or the PSC2 port. Remember that an internal peripheral module can only be connected to one port at a time. The port configurations are dictated by the respective port configuration registers. For instance, it is possible to connect MSCAN, PSC2 and GPIO to port PSC2, but not all of these functions can be programmed to appear on the PSC2 port at the same time. Only predefined combinations are allowed. To determine exactly what combination of functions are possible for a port, you need to consult that port’s configuration register. Finally, it is not possible to route all internal peripheral modules to external package pins through the ports at the same time. This routing would require more external package pins than are available. It is possible to dynamically reconfigure a port to another set of available functions using the port’s associated configuration. However, the external hardware must be able to accommodate any port reconfigurations.
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Port Configuration Register Mouse over the CS1, Rsvd, and Ether bit fields in the Configuration Register to see their descriptions.
The various ports of the MPC5200 can be programmed to perform a variety of functions. Each port is associated with a configuration register. In the present example, bits 12 to 15 of the GPS Port Configuration Register are used to configure the Ethernet port. Unimplemented codes should never be used. The results will be unpredictable and can change in future versions of the chip. In this case, the first choice is to make all 18 Ethernet Port pins into GPIO. The configuration of this port is limited to these choices. Once a choice is made, individual pins cannot be reprogrammed. Once a port is configured, it must remain in that configuration until another configuration is chosen. The ports can be reconfigured at any time by reprogramming the necessary configuration register. The system designer is responsible for ensuring that the external hardware can accommodate any port reconfiguration.
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Question What are the ports for MPC5200 peripherals? Select the correct answer and then click Done. a. PSC1, PSC2, PSC3, PSC6, I2C, Ethernet, USB, Timer b. PSC1, PSC4, PSC5, PSC6 Ethernet, Timer c. PSC1, PSC2, USB, I2C, Timer, Ethernet, USB d. PSC1, PSC2, PSC3, PSC4, PSC5, PSC6, USB, Ethernet
Consider this question regarding MPC5200 ports.
Answer: There are eight ports: PSC1, PSC2, PSC3, I2C, Timer, Ethernet, USB, and PSC6.
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Programmable Serial Controllers Six PSC modules Each PSC module is identical, but each is pinned out differently. Five PSC functions: • UART Interface Mode • Full External Modem Interface Mode (UART with Carrier Detect) • CODEC Interface Mode • I2S Mode • AC97 Mode
There are six PSC modules. PSC1 to PSC5 are identical. However, because of pin out limitations, not all of these PSCs can perform all of the possible functions. PSC6 is identical to the other PSCs except that it also has infrared data (IrDA) capability. Here you can see that the PSCs can perform the Universal Asynchronous Receiver Transmitter (UART), Full Modem Interface, CODEC Interface, Inter-Integrated Circuit Sound Bus (I2S), and AC97 Modes. The UART mode implements a standard UART. That is, there is a transmit pin (TxD), a receive pin (RxD), a Request to Send pin (RTS), and a Clear to Send pin (CTS). The full external modem interface mode is similar to UART, but it also has a Carrier Detect pin (CD). The CODEC mode is used to interface to an external CODEC chip. A true CODEC includes an Analog-to-Digital converter and a Digital-to-Analog converter. These functions are not included on the MPC5200. However, CODECs generally have standard interfaces for which the PSC module is compatible. The I2S and the AC97 modes, also implemented in the PSC modules, are used to interface to various audio chip interfaces. AC97 and I2S are defined specifications governing serial data transmission. Both formats are used with audio chip type applications.
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Programmable Serial Controllers PSC UART mode: Each is clocked by an internal clock source (IP Bus clock),eliminating the need for an external crystal Programmable data format: • Five to eight data bits plus parity • Odd, even, no parity, or force parity • One, one-and-a-half, or two STOP bits Parity, framing, and overrun error detection False-start bit detection Line-break detection and generation Detection of breaks originating in the middle of a character Start/end break interrupt/status
The UARTs are clocked by the internal IP Bus clock. The IP Bus clock is divided by a programmable register inside the PSC module to obtain the baud rate clock. The UART is capable of transmitting and receiving 5- to 8- bit data fields along with parity. Both odd and even parity are programmable along with one, one-and-a-half, or two STOP bits. The normal status flags, such as parity error, framing error, overrun error, and false start bit detection, are available.
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Programmable Serial Controllers Each channel is programmable to normal (full-duplex), automatic echo, local, loop-back, or remote loop-back mode Automatic Wake-up mode for multidrop applications 6 maskable interrupt conditions
Each of the UARTs are programmable for full-duplex operation. The UARTs can also perform loop-back operation. This feature internally connects the transmit and the receive pins together so that transmitted data is immediately routed back into the receiver. The UARTs have automatic wake-up features that allow them to remain idle until the incoming receive line has been idle for a certain number of receive clock times. This feature allows the UART to be placed in a state where the incoming data is ignored. Once the Receive line is idle for greater than the amount of time required to receive one full character along with start, stop, and parity bits, the receiver will wake up and start responding to incoming messages. The UART generates both flags and interrupts for such conditions as Receive Data Register Full, Transmit Data Register Empty, Parity Error, Framing Error and Overrun Error. While an error flag will be generated for various error conditions, the associated interrupt can be masked.
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Programmable Serial Controllers PSC Rx and Tx FIFOs can be programmed to interrupt the BestComm DMA whenever the FIFOs are about to underflow or overflow. Receiver (Rx) FIFO is 512 bytes. Transmitter (Tx) FIFO is 512 bytes. Rx FIFO has an associated ALARM register. System designer must choose the ALARM register value carefully.
Each PSC module has a Receiver (Rx) First-In-First-Out (FIFO) and a Transmitter (Tx) FIFO. Both FIFOs are 512 bytes in size. When data is transmitted, the UART automatically takes the data from the Transmit FIFO and transmits the data. As long as data is in the FIFO and the UART is enabled, the UART will automatically fetch data from the Transmit FIFO and then transmit that data. Likewise, when the UART receives data, the data is automatically transferred to the Receive FIFO. The Receive FIFO has an associated ALARM register. The ALARM Register points to a location in the Receive FIFO. As data is transferred from the Receive Data Register of the UART to the Receive FIFO, the Data Pointer for the FIFO will decrease. When the Data Pointer matches the ALARM Register, an interrupt to the CPU or a request for service by BestComm can be generated. You need to consider several factors when choosing the ALARM value. If the ALARM value is very close to the top of the Receive FIFO, the BestComm module will be interrupted frequently. If the ALARM value is very close to the bottom of the Receive FIFO, the UART might overflow the FIFO before the FIFO is serviced by either the CPU or BestComm. The system designer must choose the ALARM value based on how much data the system designer is willing to let wait in the Receive FIFO before it is serviced. Also, the system designer must consider the speed at which data is received and what potential system latencies might exist. If data is coming in very rapidly and system latencies can create a significant delay before BestComm or the CPU services the FIFO, an Overrun can occur if the ALARM value is too close to the bottom of the FIFO.
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Question Is the following statement true or false? “The PSCs can only perform UART, UART with Full Modem Interface, CODEC Interface, and AC97 Modes.” True False
Consider this question regarding the PSCs. Answer: In addition to performing UART, UART with Full Modem Interface, CODEC Interface, and AC97 Modes, the PSCs can perform I2S.”
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Ethernet Ethernet is a high-speed, asynchronous serial interface. Ethernet provides a method to connect large numbers of devices on a loop. Each Ethernet device can initiate a transmission. A Physical Interface chip connects the MPC5200 Ethernet port to the Ethernet bus.
Ethernet is an asynchronous serial protocol that allows large numbers of nodes to be connected to a large loop. Ethernet has become a very common data transmission protocol partly because it has a well-defined specification. It also allows for high data transmission rates.
Ethernet is very flexible in the implementation of the hardware. Any node on the loop can become a bus master and initiate a transmission when the node determines that the loop is idle. There is a defined protocol for handling bus collisions created when two nodes try to capture the bus at the same time. The Ethernet interface on the MPC5200 implements the standard Ethernet protocol. An external Physical Interface chip is required to connect the MPC5200 Ethernet port to the Ethernet bus.
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Ethernet 10-Mbit ETHERNET (10-pin interface) 100-Mbit ETHERNET (18-pin interface) Ethernet port
Both 10-Mbit and 100-Mbit Ethernet is implemented. The Ethernet port is an 18-pin port. The Ethernet port is sometimes represented as an 8-bit port and a 10-bit port. However, both of these ports are configured with the same “config bits.” Therefore, both ports always operate in the same “mode.” You will learn more about Port configuration later in this module.
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Ethernet
IEEE 802.3 Full Duplex Flow Control Programmable max frame length Full duplex 200 Mbps with 50 MHz clock Half duplex 100 Mbps with 25 MHz clock
The Ethernet module on the MPC5200 implements the IEEE 802.3 Full Duplex Flow Control protocol. The maximum frame length for an ethernet transmission is programmable. When operating in full duplex, a data rate of 200 Mbps can be obtained using a 50 MHz clock. In half-duplex, a 100 Mbps rate is obtained with a 25 MHz clock.
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Ethernet Retransmission from Transmit FIFO following a collision Automatic internal flushing of Rx FIFO for collision fragments and address recognition rejects
The Ethernet protocol specifies the method in which a node can gain control of the Ethernet bus. In general, an Ethernet node will monitor the Ethernet bus. If the bus is idle, any node can begin a transmission. The possibility always exists that two or more nodes will begin transmission at the same time. In this case, a collision occurs, and the Ethernet Module automatically ceases transmission and then resets itself to the state where the transmission starts. Then, the Ethernet node attempts to gain control of the Ethernet bus again. It is possible for a collision to occur and for some data to be transmitted. For instance, if two nodes started transmitting exactly the same data at exactly the same time, the nodes would not realize that a collision was occurring. The collision would not be recognized until the nodes tried to transmit different data. As a result, receiving nodes may take in partial message fragments. These fragments are automatically flushed as soon as the receiver is signaled that a collision has occurred.
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Ethernet Address Recognition • Frames with broadcast address may be always accepted or always rejected • Exact match for 48-bit individual addresses • Promiscuous Mode
Here you can see a list of Ethernet address recognition features. Ethernet protocol has an address field with each packet of information. Receiving nodes interpret this address field in the incoming data to determine whether or not they should respond to this message. A node can be programmed to respond to all messages with a Broadcast address. The address field for a Broadcast message is set to all 1’s. A node can be programmed to respond only to messages where the 48-bit address field of an incoming message matches the address of the node. In Promiscuous Mode, an Ethernet node listens to all ethernet packets. An ethernet HUB port can use Promiscuous Mode to listen to all incoming messages and then route individual messages to their appropriate destination, based on the address field in the data packet.
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Question Ethernet has a defined protocol for handling bus collisions created when two nodes try to capture the bus at the same time. Place the steps involved in a handling a bus collision in order by dragging the numbers on the left to their corresponding step descriptions on the right. Click “Done” when you are finished.
1
5
The Ethernet node attempts to gain control of the Ethernet bus again.
2
2
If the Ethernet bus is idle, the Ethernet node begins transmission.
3
4
4
1
The Ethernet node monitors the Ethernet bus.
5
3
Two or more nodes begin transmission at the same time, so a collision occurs.
Done
The Ethernet Module automatically ceases transmission and resets itself to state where the transmission starts.
Reset
Show Solution
Let’s review Ethernet node data transmission.
Answer: In general, an Ethernet node will monitor the Ethernet bus. If the bus is idle, any node can begin a transmission. If two nodes begin transmission at the same time, a collision occurs, and the Ethernet Module automatically ceases transmission and then resets itself to the state where the transmission starts. Then, the Ethernet node attempts to gain control of the Ethernet bus again.
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Universal Serial Bus Two channels available USB version 1.1 master 12 Mbit transfer rate
Two USB channels are available, and they both use USB version 1.1. Both of these channels operate in master mode. Each has a 12 Mbit transfer rate.
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Infrared Data IrDA (receive) IrDA 1.0 Slow Infrared (SIR) mode (115.2 Kbps)
Here you can see some of the IrDA features. The PSC6 port contains the UART functions and IrDA as well.
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I2C Controller Two I2C channels supported 485 Kbps with 33 MHz crystal frequency
The MPC5200 supports two independent channels of I2C. When using an external crystal of 33 MHz, it is possible to program the I2C channel to a bit rate of 485 Kbps.
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I2C Controller I2C Interface Registers—MBAR + 0x3D00 Compatible with I2C bus standard Multi-master operation Software programmable for one of 64 different serial clock frequencies Software selectable acknowledge bit Interrupt driven Byte-by-Byte data transfer
The I2C Interface Registers are MBAR + 0x3D00. The I2C Controller is compatible with the I2C bus standard and features multi-master operation. The I2C Controller is software programmable for one of 64 different serial clock frequencies based on the system clock frequency. In addition, it has a software selectable acknowledge bit and interrupt driven Byte-by-Byte data transfer.
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I2C Controller Arbitration loss with automatic mode switching from master to slave Calling address identification interrupt Start and stop signal generation/detection Repeated start signal generation Acknowledge bit generation/detection Bus busy detection
Here you can see a list of more I2C Controller features.
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Question I2C
How many channels does the MPC5200 support? Select the correct answer and then click Done. a. one b. two c. three d. four
Here is a question to check your understanding of I2C. Answer: The MPC5200 supports two independent channels of I2C.
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MSCAN Implementation of the CAN 2.0A/B protocol: • Standard and extended data frames • 0 to 8 bytes data length • Programmable bit rate up to 1 Mbps • Support for remote frames • Four receive buffers with FIFO storage scheme Asynchronous transmission format Collision handling Programmable sampling time for each bit
The MPC5200 MSCAN module implements the Control Area Network (CAN) 2.0A/B protocol. The CAN protocol is designed for short, control-oriented messages over a serial bus. It features standard and extended data frames. This protocol was originally developed for automotive applications, but it has found acceptance in other control-oriented network environments. CAN is used to send messages with a length of 0 to 8 bytes. The bit rate is programmable up to 1 Mbps depending on the actual bit timing and the clock jitter of the Phase Locked Loop (PLL). However, two commonly used bit rates are 250 Kbps and 1 Mbps. Another feature of this protocol are support for remote frames. Also, there are four individual receive buffers for incoming messages. The CAN protocol is asynchronous in nature, similar to a standard UART. Any CAN node can capture the CAN network and start transmitting whenever the CAN bus is idle. This methodology is very similar to the way Ethernet works. When a CAN node determines that no other node is transmitting and that it’s own receive input is idle, it can start transmitting. In the CAN methodology, collisions are handled as follows. When two nodes start to transmit at exactly the same time, both are allowed to continue transmitting until the nodes attempt to send different data. In this case, one node will be attempting to send a 1 and the other node will be attempting to send a 0. Since the transmitting nodes are essentially open collector, the node sending the logic 0 will control the bus and the node attempting to send the logic 1 will be pulled to a logic 0. When the node attempting to send the logic 1 determines that the bus has been pulled to a logic 0, it will immediately relinquish the bus and allow the other node to continue transmitting. Thus, the node that wins the bus will continue transmitting as though a collision never occurred. CAN networks run at fairly high speeds. This makes the serial bus sensitive to the clock jitter that occurs in the system clock for each individual node. To minimize the effects of clock jitter between nodes, the CAN implementation provides for a programmable sampling time for each bit.
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MSCAN Three transmit buffers Flexible maskable identifier filter Programmable wake-up functionality Programmable loop back mode Programmable listen-only mode
MSCAN has three transmit buffers with internal prioritization using a local priority concept. The flexible maskable identifier filter supports two full size extended identifier filters. This includes two 32-bit filters, four 16-bit filters or eight 8-bit filters.
MSCAN has several programmable features, including a programmable wake-up functionality, a programmable loop back mode that supports selftest operation, and a programmable listen-only mode for monitoring of CAN bus.
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MSCAN Separate signaling and interrupt capabilities for all CAN receiver and transmitter error states Programmable MSCAN clock source Internal timer for time-stamping Three low power modes: Sleep, Power Down and MSCAN Enable Global initialization of configuration registers
MSCAN has separate signaling and interrupt capabilities for all CAN receiver and transmitter error states, including Warning, Error Passive and Bus-Off. The programmable MSCAN clock source is either a Bus clock or an Oscillator clock. There is an internal timer for time-stamping of received and transmitted messages.
MSCAN features three low power modes: Sleep, Power Down and MSCAN Enable.
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Question What are some of the programmable features of MSCAN? Select all options that apply. Programmable wake-up functionality Programmable alarm at a set time of day Programmable loop back mode that supports self-test operation Programmable listen-only mode for monitoring of CAN bus
Consider this question regarding MSCAN features. Answer: MSCAN has several programmable features, including a programmable wake-up functionality, a programmable loop back mode that supports selftest operation, and a programmable listen-only mode for monitoring of CAN bus.
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J1850 Byte Data Link Controller
10.4 Kbps Variable Pulse Width (VPW) bit format Collision detection CRC generation and checking Digital noise filter J1850 Class B Data Communications for automotive applications
The J1850 Byte Data Link controller features a 10.4 Kbps Variable Pulse Width (VPW) bit format. It uses an asynchronous protocol for serial communications and automatically generates CRC error checking. The J1850 controller also includes other features such as digital noise filtering. The J1850 protocol is used primarily in automotive environments. However, nothing specific about the J1850 protocol limits it use to automotive applications.
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J1850 Byte Data Link Controller
4X Mode Block Mode Receive/Transmit Inframe Response Types 0, 1, 2, and 3 Wake up on J1850 message
The J1850 Byte Data Link Controller fully implements the 4X mode. This provides for faster serial communications. It also supports the Block Mode Receive and Transmit and the Inframe Response Types 0, 1, 2, and 3. The J1850 module can also be used to “wake up” the 603 G2_LE core when the 603 G2_LE core is in a low power mode, such as NAP, DOSE or SLEEP. The “wake up” event is the reception of an incoming message.
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Serial Peripheral Interface
Full duplex Master and slave modes 20 Mbit operation Programmable clock polarity Programmable clock phase
The Serial Peripheral Interface (SPI) is a very simple synchronous 4-wire interface. Data is transmitted on one pin, received on another pin, and a clock signal is implemented on a third pin. If the SPI is configured as a master, the clock line is an output. As a slave, the clock line is an input. Since this interface is synchronous in nature, that is, a clock signal is synchronized with the data, this serial interface can work at much higher speeds than asynchronous interfaces such as a UART or CAN. The clock phase and polarity are programmable. In other words, the SPI can transmit on either the leading or trailing edge of the clock and receive on the opposite edge. The clock polarity can be high or low. This flexibility allows the SPI to communicate with almost all synchronous interfaces.
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SPI Features The SPI has the following features: Master mode and slave mode Slave-select output Double-buffered operation Serial clock with programmable polarity and phase Control of SPI operation during wait mode Mode fault error flag with CPU interrupt capability
Here you can see many of the SPI’s features. The SPI operates in both a Master and a Slave mode. As a Master, data is transmitted on the Master Out/Slave In pin and is received on the Master In/Slave Out pin. The clock line is an output and drives the clock input of the SPI devices operating in a Slave mode. As a Slave, data is transmitted and received only when the Slave’s clock line is driven by a Master SPI device. When configured as a Master SPI, a Slave Select line is asserted during each SPI transmission. The Slave SPI receives this signal on its Slave Select line, which enables the Slave to receive the incoming data.
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Question Is the following statement true or false? “The SPI can work at much higher speeds than asynchronous interfaces such as a UART or CAN.” True False
Consider this question about the SPI.
Answer: Since the SPI is synchronous in nature, this serial interface can work at much higher speeds than asynchronous interfaces such as a UART or CAN.
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SPI Timing Diagram
The SPI involves four different transmission formats. Data can be received or transmitted on the leading or trailing edge of the clock. The leading edge of the clock can be either a positive or negative going edge. Since the SPI has these four combinations, it can be programmed to be compatible with a wide range of external devices. In this diagram, the Clock Phase is 0. This means that data is received on the leading edge of the clock and transmitted on the trailing edge of the clock. As soon as the SPI is enabled as a Master, the Master Out/Slave In pin (MOSI) drives the Most Significant Bit (msb) onto the Master Out/Slave In pin.
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SPI Timing Diagram
In this diagram, the Clock Phase is 1. This means that data is received on the trailing edge of the clock and transmitted on the leading edge of the clock. As soon as the SPI is enabled as a Master, the Master Out/Slave In pin drives the Least Significant Bit (lsb) of the last transmission onto the Master Out/Slave In pin. The Master shifts out the Most Significant Bit (msb) of the current transmission on the leading edge of the clock so that the data can be sampled by the Slave on the trailing edge of the clock.
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Timers Eight Timer channels Timer functions: • Pulse Width Modulation • Input Capture • Output Compare • GPIO Each Timer channel is individually programmable Timer channel 0 can be used as watchdog timer Timer channels 6 and 7 of above support wake-up capability
The TIMER module is actually part of the System Interface Unit (SIU). However, the eight Timer channels are routed to the TIMER Port. The Timer functions are Input Capture, Output Compare, Pulse Width Modulation, and GPIO. The TIMER Port pins can be individually configured to any of these four functions. The GPIO function of the TIMER Port is controlled by the TIMER, not by port data and port data direction registers.
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Timers/GPIO Eight dedicated GPIO pins with full timer capability: • Input Capture • Output Compare • Pulse Width Modulation • Four Programmable Registers per Timer
The TIMER module has eight independent channels. Each channel can perform Input Capture, Output Compare, Pulse Width Modulation, and GPIO functions. The Input Capture function captures the value of a 16-bit free running counter. This counter is driven by a 16-bit programmable divider whose clock source is the IP Bus clock. This makes the range of the counter structure 32 bits. However, the accuracy is only 16 bits due to the fact that the value in the prescaler cannot be read. By capturing the value of the free running counter on successive edges, the time between two events, expressed in IP Bus clock counts, can be determined. The Output Compare function is used to create an Output Compare event when the specified output compare value matches the value in the free-running counter. An Output Compare event can be a low-to-high transition, a high-to-low transition, a positive- or negative-going pulse, or a toggle from the present state. Each Timer channel can output a Pulse Width Modulated signal with a programmable duty cycle and frequency. Each timer channel has four associated registers that are used to set up and control the various timer functions. Timer 0 can be used as a watchdog. A value is programmed into a General Purpose Timer (GPT) Register that specifies a number of IP Bus clock counts. If this counter decrements to zero, a system reset will occur. The system software is responsible for resetting the watchdog before it times out. Each time the software resets the watchdog, the watchdog restarts from the original programmed count. Timer channels 6 and 7 can be used as Wake-Up interrupts. When the CPU is in a power down mode, these pins can cause the CPU to return to a fully powered state and resume operation.
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General Purpose Input/Output
Wake-up capability on some GPIO pins Interrupt capability on some GPIO pins UP TO 56 GPIO (depending on port configurations) TIMER GPIO controlled by Timer Modules All other GPIO controlled by SIU Registers
The GPIO lines are distributed among the various ports, and these lines vary in capability. Some have the ability to wake up the processor from a low power mode, some can interrupt the processor and others can simply function as Input I/O pins. The number of pins available as GPIO varies according to the number of internal modules, such as UART and Ethernet, that are enabled. For instance, PSC1 port can be configured as GPIO or UARTe, but not both. If the UART function is configured for the PSC1 port, then only one of the PSC1 port pins is available for GPIO. Timer Modules control the TIMER GPIO. The SIU Register controls all the other GPIOs.
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Question Which of the following functions can the eight channels of the TIMER Module perform? Select all options that apply. Input Capture Output Capture Clock Capture Pulse Width Modulation GPIO functions
Consider this question regarding the TIMER Module.
Answer: The TIMER module has eight independent channels. Each channel can perform Input Capture, Output Compare, Pulse Width Modulation, and GPIO functions.
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MPC5200 Chip Overview Real Time Clock: 1 second resolution Alarm Stop watch Periodic interrupts • Second • Minute • Midnight Calendar (day/date/year)
The Real Time Clock (RTC) is a module contained within the System Integration Unit. The RTC uses its own internal oscillator driven by an external 32.7689 KHz crystal as a timing source. The RTC clock input, that is, the external 32.768 KHz crystal input, is divided by a 215 divider chain. The output of this divider chain yields 1-second tick marks. A 32.768 KHz crystal is used because its frequency is a power of 2. Also, since these types of crystals are very widely used in timing applications such as wrist watches, they are widely available and use a very mature manufacturing technology. The RTC has several functions in addition to keeping the time of day in hours, minutes, and seconds. It can cause an alarm at a set time of day or be used as a stop watch. Periodic interrupts of 1 second, 1 minute, and midnight rollover can be selected. The RTC also has a calendar function that keeps track of day/date/year functions.
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Module Summary
PSCs USB IrDA I2C MSCAN J1850 Byte Data Link Controller SPI GPIO RTC
Now that you have completed this module, you should be able to describe the purpose and design of MPC5200 peripherals. You should be able to identify PSCs, USB, IrDA, I2C, MSCAN, J1850, SPI, GPIO, and RTC. You should also be able to discuss port configurations for peripherals. Finally, you should be able to describe some of the related protocols such as Ethernet and CAN 2.0A/B.
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