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CONFIDENTIAL DTC and TDC IC Design for Ultra-Low-Power ADPLL Master of Science Thesis Peng Chen Microelectronics mscconfidential DTC and TDC IC Design for Ultra-Low-Power ADPLL Master of Science Thesis For the degree of Master of Science in EEMCS at Delft University of Technology Peng Chen September 18, 2014 Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS) · Delft University of Technology The work in this thesis was supported by IMEC-NL. Their cooperation is hereby gratefully acknowledged. c Microelectronics, Electrical Engineering (ME) Copyright All rights reserved. Delft University of Technology Department of Microelectronics, Electrical Engineering (ME) The undersigned hereby certify that they have read and recommend to the Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS) for acceptance a thesis entitled DTC and TDC IC Design for Ultra-Low-Power ADPLL by Peng Chen in partial fulfillment of the requirements for the degree of Master of Science EEMCS Dated: September 18, 2014 Supervisor(s): Prof. Dr. Robert. B. Staszewski Dr. XiongChuan Huang Reader(s): Prof. Edoardo Charbon Prof. Michiel Pertijs Ir. Augusto Ximenes Abstract The technology scaling favors the Digital PLLs, which is reconfigurable. In the traditional fractional-N ADPLL, whether counter-based or divider based, DCO and TDC are the main two power consuming blocks. Modifying the phase detection part based on phase prediction makes the architecture more energy-efficient. The new architecture leads to the first wireless ADPLL breaking 1mW barrier. However, the in-band spurs are very high and DTC gain calibration does not work very well. This thesis proposes a pseudo phase domain model to determine the in-band spur level and validates the accuracy through simulations. It also improves the LMS DTC gain calibration algorithm to solve the problem when FCW fractional part is small DTC gain cannot calibrate correctly. Furthermore, pre-distortion is used to cancel DTC nonlinearity. Apart from theoretically analysis, a first-order Σ − ∆ TDC is taped-out, to measure DTC’s nonlinearity. Master of Science Thesis CONFIDENTIAL Peng Chen ii Peng Chen CONFIDENTIAL Master of Science Thesis Table of Contents Acknowledgements xi 1 Introduction 1-1 Frequency Synthesizer in Wireless Transceivers . 1-2 Introduction to the DTC-based ADPLL . . . . 1-3 Introduction to DTC . . . . . . . . . . . . . . 1-4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 DTC-based ADPLL 2-1 Work Principle . . . . . . . . . . . . . . . . . . . . . . 2-1-1 Transfer Function . . . . . . . . . . . . . . . . 2-1-2 Phase Noise . . . . . . . . . . . . . . . . . . . 2-1-3 Phase Prediction . . . . . . . . . . . . . . . . 2-1-4 Snapshotting and CKR Generation . . . . . . . 2-2 DTC Nonlinearity’s Influence on Fractional Spurs . . . 2-2-1 Traditional Method . . . . . . . . . . . . . . . 2-2-2 Pseudo Phase Domain Method . . . . . . . . . 2-3 DTC Gain Calibration . . . . . . . . . . . . . . . . . . 2-3-1 Noise Cancellation Theory . . . . . . . . . . . 2-3-2 DTC Gain Calibration with LMS . . . . . . . . 2-3-3 Measurement Results and Explanation . . . . . 2-4 TDC Quantization’s Influence on Fractional Spurs . . . 2-5 Investigation on Fractional Spurs . . . . . . . . . . . . 2-5-1 Non-ideal effects introduced in measurement . 2-5-2 Misalignment of φ0 s integer and fractional part 2-5-3 Wrong estimation of DTC control word . . . . 2-5-4 Voltage Drop . . . . . . . . . . . . . . . . . . 2-5-5 DTC mismatch . . . . . . . . . . . . . . . . . Master of Science Thesis CONFIDENTIAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 2 4 6 . . . . . . . . . . . . . . . . . . . 7 7 8 9 11 11 12 12 13 18 20 20 27 29 30 31 33 33 33 34 Peng Chen iv Table of Contents 3 Test Circuit Design for Built-in DTC Measurement 35 3-1 Time Domain First-Order Sigma-Delta Mechanism . . . . . . . . . . . . . . . . 35 3-1-1 Mathematical Explanation . . . . . . . . . . . . . . . . . . . . . . . . . 36 3-1-2 Top View Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3-2 Noise and Nonlinearity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3-2-1 Z Domain Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3-2-2 Techniques to Reduce Nonlinearity . . . . . . . . . . . . . . . . . . . . . 38 4 Top Level Implementation 43 4-1 Digital to Time Converter (DTC) . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4-2 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4-3 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4-4 RTL flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Other Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Top Level Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 54 56 5 Measurements 5-1 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 59 5-1-1 5-1-2 Test PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 59 5-2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2-1 Duty-cycle Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 60 60 5-2-2 Sigma-Delta Measurement . . . . . . . . . . . . . . . . . . . . . . . . . 62 5-2-3 Post Processing for Measurement Data . . . . . . . . . . . . . . . . . . 64 5-2-4 Comparison of the Two Results . . . . . . . . . . . . . . . . . . . . . . . 67 6 Conclusions 6-1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 73 73 A Fractional Spur Estimation 75 A-1 Fractional Spur Level Theoretically Derivation . . . . . . . . . . . . . . . . . . . 75 Glossary 81 List of Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peng Chen CONFIDENTIAL 81 Master of Science Thesis List of Figures 1-1 Low power transceiver block diagram. . . . . . . . . . . . . . . . . . . . . . . . 2 1-2 ADPLL types: (a) divider-based ADPLL (b) counter-based ADPLL . . . . . . . . 3 1-3 Current steered DTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Coarse and fine DTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Tri-stage inverter based DTC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 6 2-1 Architecture of DTC-assisted ADPLL. . . . . . . . . . . . . . . . . . . . . . . . 2-2 s-domain model of type-II ADPLL. . . . . . . . . . . . . . . . . . . . . . . . . . 8 9 2-3 Principle of phase prediction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2-4 Timing diagram of the phase prediction technique. . . . . . . . . . . . . . . . . 12 2-5 Pseudo Phase Domain ADPLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Assumed DTC INL characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Fractional spur level estimation. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 15 2-8 Traditional-Pseudo Ratio versus α and Fractional Spur Frequency. . . . . . . . . 19 2-9 Traditional-pseudo Ratio versus Fractional Spur Frequency, α = 2−7 . . . . . . . . 19 2-10 LMS Adaptive Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2-11 Diagram of DTC Gain Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . 21 2-12 DTC transfer function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 DTC transfer function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Pre-Distortion to Cancel Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . 22 22 23 2-15 Adaptation constant’s influence on settling time . . . . . . . . . . . . . . . . . . 24 2-16 Adaptation constant’s influence on phase noise. . . . . . . . . . . . . . . . . . . 24 2-17 Sign versus complete value when F CWf rac is near integer. . . . . . . . . . . . . 25 2-18 Small fractional number, no sign LMS algorithhm is used . . . . . . . . . . . . . 26 2-19 Small fractional number, detecting maximum Φ2e method is used . . . . . . . . . 26 2-20 Fractional spur level’s sensitivity (1) . . . . . . . . . . . . . . . . . . . . . . . . 27 Master of Science Thesis CONFIDENTIAL Peng Chen vi List of Figures 2-21 Fractional spur level’s sensitivity (2) . . . . . . . . . . . . . . . . . . . . . . . . 27 2-22 Fractional spur level’s sensitivity (3) . . . . . . . . . . . . . . . . . . . . . . . . 28 2-23 Phase error when DTC gain is not correct and there is no nonlinearity in DTC. . 28 2-24 TDC remain blinded for several reference cycles at near-integer channels in traditional counter-based ADPLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 Dithering help randomize TDC quantization noise. . . . . . . . . . . . . . . . . 29 30 2-26 Architecture of DTC-assisted ADPLL. . . . . . . . . . . . . . . . . . . . . . . . 2-27 Measurement results of DTC nonlinearity. . . . . . . . . . . . . . . . . . . . . . 31 32 2-28 Simulated results of DTC nonlinearity. . . . . . . . . . . . . . . . . . . . . . . . 32 2-29 DTC unit delay versus voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3-1 Simplified Top Level Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . 36 3-2 Implementation Details of Top Level Architecture. . . . . . . . . . . . . . . . . . 39 3-3 Z domain analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3-4 Comparison of Capacitor’s voltage with/without comparator’s offset. . . . . . . . 40 3-5 Error caused by charge pump’s nonlinearity. . . . . . . . . . . . . . . . . . . . . 40 3-6 Capacitor voltage variation is at the order of 200 mV. . . . . . . . . . . . . . . . 41 3-7 Capacitor voltage variation is at the order of 20 mV. . . . . . . . . . . . . . . . 41 4-1 Top view of tri-state buffer-self-loaded DTC. . . . . . . . . . . . . . . . . . . . . 44 4-2 Circuit of DTC unit cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 DNL/INL of the old DTC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 45 4-4 DNL/INL of the new DTC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4-5 Circuit of Charge Pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4-6 Output impedance calculation of Charge Pump. . . . . . . . . . . . . . . . . . . 47 4-7 Output impedance of Charge Pump during charging. . . . . . . . . . . . . . . . 48 4-8 Output impedance of Charge Pump during discharging. . . . . . . . . . . . . . . 48 4-9 Output current variation upon output voltage. . . . . . . . . . . . . . . . . . . . 49 4-10 Circuit of Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4-11 Comparator noise’s influence on resolution. . . . . . . . . . . . . . . . . . . . . . 53 4-12 RTL part of the Sigma-Delta TDC. . . . . . . . . . . . . . . . . . . . . . . . . . 53 4-13 internal clocks generated by clock generation block. . . . . . . . . . . . . . . . . 54 4-14 Self biased inverter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 Phase noise of DTC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 Simple ESD protection circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 55 56 4-17 Top Level Layout of the Chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5-1 PCB Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Measurement Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 60 5-3 Measured Duty Cycle and Delay versus DTC Control Code for "Old" DTC (Board 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Peng Chen CONFIDENTIAL Master of Science Thesis List of Figures vii 5-4 Measured "Old" DTC INL (ps) using duty-cycle method (Board 1). . . . . . . . . 62 5-5 Measured Duty Cycle and Delay versus DTC Control Code for new DTC (Board 1). 63 5-6 Measured new DTC INL (ps) using duty-cycle method (Board 1). . . . . . . . . . 63 5-7 Measured Duty Cycle and Delay versus DTC Control Code for "Old" DTC (Board 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5-8 Measured "Old" DTC INL (ps) using duty-cycle method (Board 2). . . . . . . . . 64 5-9 Measured Duty Cycle and Delay versus DTC Control Code for new DTC (Board 2). 65 5-10 Measured new DTC INL (ps) using duty-cycle method (Board 2). . . . . . . . . . 65 5-11 Measured Results (Board 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5-12 Measured Results (Board 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5-13 Measured Results (Board 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5-14 Measured Results (Board 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5-15 Measured Results (Board 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5-16 Measured Results (Board 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5-17 Measured INL (ps) Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5-18 Spur level, based on the post-processed measurement data . . . . . . . . . . . . 69 5-19 Measured DNL (ps) Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5-20 Post-processing for Board 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5-21 Post-processing for Board 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5-22 Post-processing for Board 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Master of Science Thesis CONFIDENTIAL Peng Chen viii Peng Chen List of Figures CONFIDENTIAL Master of Science Thesis List of Tables 4-1 Monte-Carlo simulation results. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Integrated noise summary (in V) of the comparator. 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Master of Science Thesis CONFIDENTIAL 45 52 Peng Chen x Peng Chen List of Tables CONFIDENTIAL Master of Science Thesis Acknowledgements I would like to thank my supervisor Robert Bogdan Staszewski for his assistance in this master project. I hope I haven’t let him down. I would also thank Kathleen Philips to give me this chance to do this project. I’d like to give my sincere thanks to my daily supervisor, Coby XiongChuan Huang, who is always patient and positive. He gives me too much. I want to thank Yao-Hong Liu, who gives me lots of suggestions on the ADPLL and sigmadelta TDC. I appreciate the discussions we have had. Many thanks to my colleagues: Ming Ding, who helps me synthesize the RTL code and Cui Zhou, who shares the charge pump. During the past year, Jialue Wang, Dongni Fan, Colin Lin, Ao Ba and Bo Liu share much memorable time together in IMEC-NL. Thanks for your company and help. My friends, in the Netherlands, China and other places, accompany me during the past year. Thank you! Thanks to the people who appear in my life, who make who I am today. Last but not least, thanks my family from my heart. Delft, University of Technology September 18, 2014 Master of Science Thesis Peng Chen CONFIDENTIAL Peng Chen xii Peng Chen Acknowledgements CONFIDENTIAL Master of Science Thesis Chapter 1 Introduction Abstract This chapter first describes the application background of ADPLL (All-Digital Phase-Locked Loops), which is in wireless transceivers. Then different architectures of ADPLL are summarized, followed by the introduction to DTC (Digital to Time Converter). At last, the thesis organization is described. 1-1 Frequency Synthesizer in Wireless Transceivers The last passed years have seen an increase in wireless applications. The market benefits from the continuous shrinking of the feature sizes of MOSFETs. Except from the traditional smart mobile devices market, the developing technology reveals many new opportunities in wireless application, such as WBAN and WSN. The short-range low-cost wireless networks made of autonomous sensor-nodes are applied in health care monitoring, home automation and environment sensing. The sensor nodes’ key characteristic is their autonomous operation. An analysis of the power budget of the sensor nodes shows that the transceiver dominates the whole power consumption. One of the key building blocks, frequency synthesizer, consumes a significant portion of the total power of the transceivers. Thus the power consumption of the frequency synthesizer is expected to be as low as possible, without sacrificing its performance too much. A low power transceiver architecture is shown in Figure 1-1. In the receiver path the frequency synthesizer as a Local Oscillator (LO) is used in down conversion mixer. In the transmitter path, direct modulation is preferred in the low power application [1]. The heterodyne topology is not chosen because it needs off-chip image rejection filters. The direct conversion receiver is suitable for fully integration low power application, even though it is susceptible to the dynamic DC offsets originating from the mixer’s second order nonlinearity. The received RF signals are first amplified by the LNA before down-converted to Master of Science Thesis CONFIDENTIAL Peng Chen 2 Introduction Low-pass filter Mixer I ADC PGA RX data LO I LNA LO Q Q ADC PGA RX data Frequency synthesizer PA FM TX data AM Figure 1-1: Low power transceiver block diagram. the intermediate frequency. The down conversion is operated in the mixer for both in-phase and quadrature signals. Then the signals are low-passed and amplified by low-pass filter and programmable gain amplifier respectively. At last, the signals after amplification is fed into the ADC before they are processed by the digital baseband. For the transmitter, the direct up-conversion topology has the advantage of no need for mixing and low-pass filtering. While its disadvantage is the side lobes cannot be further suppressed, which are still tolerable. Above all, the frequency synthesizer is a key block in both transmitter path and receiver path. 1-2 Introduction to the DTC-based ADPLL ADPLL has the advantage of flexibility, transfer function precision, fast settling speed, frequency modulation capability et al.. Over the past several years, as the technology scales, it consumes less power, area, cost and achieves better performance over the traditional analogintensive charge-pump PLL [2], in which the charge pump is a critical block to design because of the mismatch [3][4]. The ADPLLs are mainly divided into two categories: divider-based ADPLL [5] and counterbased ADPLL [6], [7], as shown in Figure 1-2. The former is similar with the traditional fractional-N charge-pump PLL with ∆Σ dithering of the modulus divider. Those two architectures in Figure 1-2 have something in common, compared with the analog charge-pump PLLs. The DCO takes the place of VCO for generating CKV (output variable clock). TDC (Time to Digital Converter) acts as a PFD (phase/frequency detector) and charge pump. The loop filter replaces the analog RC filter. The sigma-delta tuning part, which is not necessary, is also implemented by digital circuits. Peng Chen CONFIDENTIAL Master of Science Thesis 1-2 Introduction to the DTC-based ADPLL FREF Phase error TDC (fR) tv[k] 3 DCO Loop Filter (fv) Tune Edge Divider CKV 1/N FCW Dither (a) FCW Reference phase Phase error FREF (fR) DCO Loop Filter (fv) Tune TDC Variable phase tv[k] CKV (b) Figure 1-2: ADPLL types: (a) divider-based ADPLL (b) counter-based ADPLL The difference of divider-based ADPLL and counter-based ADPLL is the way in which CKV is fed back into TDC. In the divider-based ADPLL, before fed into TDC, CKV frequency is divided by N. The average period of the signal after divider is ideally the same as the reference signal (FREF). Take fREF = 32 M Hz, tT DC_res = 20 ps (they stand for reference signal frequency and TDC resolution respectively) for example, TREF = 31.25 ns, then 31.25 ns/20 ps = 1562.5 ≈ 1563 stages of TDC unit cells are needed. It consumes a lot of power to implement such a large range TDC. What’s more, as the measurement range extends, nonlinearity becomes even worse. At the price of hardware complexity, a frequency detector can be implemented in this architecture to help reduce the measurement range. Another issue of this architecture is that the dithering of the modulus divider also contributes an increase of several CKV clock cycles to the TDC range. The TDC in counter-based ADPLL only has to cover one period of CKV, whose range is tens of times smaller. Secondly, this architecture can handle the fractional frequency ratio essentially. But in both architectures, phase errors have periodic patterns, which originate from fractional numbers of frequency control word and contribute to the fractional spurs. In addition, CKV-edge counter can be used to extend the TDC range. This kind of architecture has the advantage of performance, power consumption, cost over the traditional approaches and takes up about 33% of the new mobile phones. Considering the TDC range approximately as one CKV period, take fCKV = 900 M Hz for example, 1/900 M Hz/20 ps ≈ 56 TDC unit stages. This number is still very large. What’s more, the detected phase error has a periodic pattern if no more calibration is applied. These two shortcomings produce the need to make some modifications in the architecture level. Master of Science Thesis CONFIDENTIAL Peng Chen 4 Introduction Thus a DTC-based ADPLL appears, both in divider-based ADPLL [5] [8] and counter-based ADPLL [9]. Phase prediction is realized by taking the advantage of the fractional part of the frequency control word. Since the fractional part is known, the periodic pattern of the TDC output in the traditional ADPLL is known. By DTC, ckv and the reference signal are almost aligned. The time difference to be measured is greatly reduced. The advantage of introducing DTC into the feedback path is that it reduces TDC measurement range, which resulting in much less power consumption and better linearity performance of TDC. This idea is called phase interpolation or phase prediction, requiring a few stages of TDC to quantize the thermal, flick noise and DCO quantization noise from the circuit. 1-3 Introduction to DTC Generally, as described in [10], a DTC takes a digital input and converts it to the form of a time instant. In this chapter, the DTC (Digital to Time Converter) is essentially a delay line, which is controlled by the input digital code. Each stage in the delay line can be a inverter or a buffer. The delay time of each stage determines DTC’s resolution. DTC is an essential block in the new architecture. Because the linearity requirement put on TDC is now transferred to DTC. What’s more, originally ckv period is required to be estimated correctly to normalize the TDC output. Otherwise, fractional spur is generated. Now this requirement is changed to estimate DTC gain correctly. But as will be explained in the chapter 2, DTC nonlinearity can deteriorate the DTC gain calibration. Therefore, a linear DTC is very important in the DTC-based (phase prediction) ADPLL. In the following, several DTC architectures are introduced. In [11], a current-controlled DTC is implemented as shown in Figure 1-3(a). There are 16 digital controlling bits, which control the on/off state of the PMOS. The time, when the signal is transferred from the input port to the output port, is related with the current of the buffer. The larger the current the buffer operates, the faster the signal is transferred. The advantage of this architecture is the resolution can be achieved as small as 4 ps. The number of the MOSs is small. The disadvantage is its nonlinearity. Another type is shown in Figure 1-3(b), which is a unit delay cell of the DTC. The MOSCAP is controlled by the input digital code. Thus the delay time of one unit delay cell changes as the input code. To compensate the fixed delay of the unit cell, Vernier delay line is chosen when adopts this architecture. In [12], two DTCs appear: a coarse one and a fine one. The fine one is similar with the one in Figure 1-3(b). The coarse one is in Figure 1-4 (a). The coarse DTC is made up of controllable inverters. The inverter only has two MOSs from VDD to ground, which is suitable for low-voltage operation. The disadvantage is the stringent power-resolution trade-off. Calibration technique is usually used to improve DTC’s linearity. Next, DTC with analog calibration or digital calibration are introduced. A DLL (delay-locked loop) is one kind of DTC which can provide high PSRR, with the help of analog calibration. The voltage-controlled delay unit is controlled by the output from the filter, to provide a stable delay time [10]. The negative feedback provides a desired phase relationship between the input signal and the output signal from the last stage of delay chain. Peng Chen CONFIDENTIAL Master of Science Thesis 1-3 Introduction to DTC 5 (b) Another current steered DTC (a) Current steered DTC Figure 1-3: Current steered DTC (b) Fine DTC (a) Coarse DTC Figure 1-4: Coarse and fine DTC Each node at the delay unit output port has a delayed version of the input signal. The delay time is related with the number of delays. From another point of view, the delay time is calibrated in an analog manner. The calibration is at the expense of extra phase detector and filter. Analog calibration techniques, such as anti-imaging time-mode filter design[13], always consume more area and power. Compared with analog calibration, digital calibration is preferred in many low-power designs. [14],[15]. With digital calibration, the DTC design can be much simplified. In [14], a digitally controlled vernier delay line is used to implement the DTC. The delay element is made of two cascaded inverters, both of which are loaded by tunable capacitors. The offset in the DTC transfer function of this architecture is large due to the Vernier principle. Luckily, the loop operation can tolerate even larger offset. One advantage of this architecture is the resolution can be improved by cascading a fine DTC after a coarse one. The disadvantage is the large area it consumes and nonlinearity. The nonlinearity is caused by the mismatch between two Master of Science Thesis CONFIDENTIAL Peng Chen 6 Introduction delay lines and the precision of the loaded capacitors. Due to the large number of delay elements, [15] provide a single-cell DTC implementation. The idea is based on the fact that only one phase is needed at the DTC output. As shown in Figure 1-4(b), non-minimum inversion-mode MOS capacitors are adopted. Linearity and DTC range are corrected by the background digital calibration. Algorithms adopted from LMS are usually implemented into the digital part [16] [15] [8]. Among which, [8] introduces a pre-distortion technique to mitigate the DTC nonlinearity with a very good performance. The DTC chosen in this chapter is adapted from [17]. The input signal is connected to one port of the "AND" gates. The digital control codes are connected to another port of the "AND" gates. Considering a specific case, the second unit stage is chosen. Then the second "AND" gate is enabled. From here, the input signal is passed through the next stages. At the same time, since the first "AND" gate is not enabled, the output resistance of the first unit stage is high impedance, which do not alter the input signal propagation. Figure 1-5: Tri-stage inverter based DTC. 1-4 Thesis Organization The project background is firstly described. There is already one state-of-the-art ADPLL. And there are large fractional spurs in the measurement. The goal is to reduce the fractional spurs. So a DTC transfer function measurement circuit is taped out. Meanwhile, the new DTC is used in another ADPLL tape-out. The thesis is organized as follows. Chapter 2 introduces the DTC-based ADPLL and analyzes DTC’s influence on the fractional spurs’ level in the previous chip. With lots of details, the analysis is completed with a proposed pseudo phase domain model. What’s more, improved LMS algorithms are implemented. To figure out DTC’s precise transfer function, a test circuit is designed. Chapter 3 propose a first-order sigma-delta method, which gives a general description of the test chip. The implementation details are described in the next chapter. Then the measurement results are shown and analyzed, followed by a conclusion of this thesis project. Peng Chen CONFIDENTIAL Master of Science Thesis Chapter 2 DTC-based ADPLL Abstract In this chapter, mechanism of DTC-based ADPLL is introduced. Then attention is paid on DTC nonlinearity’s influence on fractional spurs, as well as other factors contributing to fractional spurs. At last, along with measurement and simulation data, assumptions and validations about the fractional spurs appeared in the previous chip are given. 2-1 Work Principle As discussed before, ADPLL used in wireless application now can mainly be divided into two categories: counter-based ADPLL (or called divider-less ADPLL) and divider-based ADPLL. DTC has been used in both architectures [9], [8]. DTC-based ADPLL here only refers to counter-based ADPLL. Figure 2-1 shows the architecture of the DTC-based ADPLL. Compared with the traditional counter-based ADPLL [7], it adds DTC into the feedback path, which delays the reference signal (FREF) phase according to the fractional part of FCW. Ideally, the rising edge of fref _dly (the delayed reference signal from DTC) fluctuates very closely to the rising edge of CKV D2s (the divided CKV signal processed by snapshot). This makes the TDC detection range greatly reduced, which now is determined by DTC quantization noise, DCO quantization noise and thermal noise in the circuit. The advantage of this architecture is that it consumes less power, which is attributed to two reasons. One is the phase-prediction mechanism, executed by the DTC path. It narrows down the TDC detection range. What’s more, the snapshot circuit reduces TDC operating frequency from fckv to fref . Secondly, a frequency divider (/2) after DCO buffer is used. This brings down the working frequency of the whole phase detection circuits. There is another advantage when the TDC detecting range reduces. TDC’s nonlinearity is improved and TDC’s specification is relaxed. F CWf rac related fractional spur is determined by DTC, rather than TDC in this architecture. Compared with TDC, DTC consumes less power and more linear. Master of Science Thesis CONFIDENTIAL Peng Chen 8 DTC-based ADPLL Tx modulation data FCW 1/KDCO_HF FMHF FMLF dPHR FCWint CKR FCWfrac Digital Loop Filter å CKR dPHEF CKR CKV 1/KDCO_LF å CKR DCO buffer dPHV /2 PHRF 1/KDTC Phase sampler 1-Z-1 KDTC calibration 1-Z-1 1/KTDC DTCctrl Fref Phase accumulator PHV CKR 64 stage DTC Fref_dly 16 stage TDC CKVD2s CKR CKVD2 Snapshot & CKR gen Figure 2-1: Architecture of DTC-assisted ADPLL. More detailed descriptions about this architecture are as following. 2-1-1 Transfer Function Even the DTC is added in the feedback path, the transfer function of the whole loop can still be analyzed in the traditional way. DTC improves the performance of the phase detection part, but not affects the loop dynamics response. When ADPLL locks, it is in tracking mode and switches to Type-II PLL. A s-domain model from Figure 4.45 in [18] is redrawn in Figure 2-2. If DCO gain is correctly estimated, the open loop transfer function is Hol = (α + ρfR fR αfR s + ρfR2 ) = s s s2 (2-1) Where α and ρ are the loop filter coefficients. fR represents the reference frequency. The closed-loop transfer function for the DCO phase noise is Hcl,v (s) = Peng Chen 1 s2 = 2 1 + Hol s + αfR s + ρfR2 CONFIDENTIAL (2-2) Master of Science Thesis 2-1 Work Principle 9 Loop Filter Phase Detector Normalized DCO (nDCO) N + ΦE - fR/LSB 1 KDCO S 2πKDCO α 1 ΦV fR 2π S ρ Figure 2-2: s-domain model of type-II ADPLL. The closed-loop transfer function for the reference noise is Hcl,F REF (s) = N Hol αfR s + ρfR2 =N 2 1 + Hol s + αfR s + ρfR2 (2-3) The closed-loop transfer function for TDC noise is Hcl,F REF (s) = 2-1-2 αfR s + ρfR2 Hol = 2 1 + Hol s + αfR s + ρfR2 (2-4) Phase Noise Phase noise is the excess phase variations in the period, also called jitter in time domain. In frequency domain, it exhibits a "skirt" around the center frequency and spreads into nearby frequencies. In ADPLL, the information is stored in the zero-crossing timestamps, which benefits from the deep-submicrometer CMOS process technology in that better resolution can be achieved in the time domain. From [19], the rms jitter and phase noise relationship is: σ∆T T0 ≈ 2π s Z fH 2 fL Sφ (f )df (2-5) where Sφ (f ) is the phase noise spectrum, in rad2 /Hz. TDC’s influence on phase noise TDC is one kind of data converter, as ADC (Analog to Digital Converter). Assuming the quantization step is ∆tres , phase noise spectrum of the ADPLL due to TDC finite quantization is expressed as L= Master of Science Thesis (2π)2 ∆tres 2 1 ( ) 12 TV fR CONFIDENTIAL (2-6) Peng Chen 10 DTC-based ADPLL For example, ∆tres = 10ps, fV = 2.4GHz, TV = 417ps, fR = 40M Hz, the single sided phase noise is obtained as L = −103.25dBc/Hz. The phase noise due to TDC is low passed by the loop. Thus it dominates the in-band noise of ADPLL. Reference signal’s noise is low passed as well, but usually smaller compared with TDC quantization noise. DCO’s influence on phase noise DCO phase noise is high passed by the loop. It dominates the out-band phase noise of ADPLL. In wireless application, it is challenging to meet the phase noise specification in out-band at some points, for example, 20 MHz offset. DCO itself can generate phase noise beyond the spectrum mask. So the ADPLL should be designed in a way which makes DCO phase noise dominates in out-band. In the following, DCO quantization effect on phase noise is discussed. Define ∆fres as the DCO frequency resolution and the quantization error is uniformed distributed. Then the random variable ∆fV has white noise spectral characteristics. 2 = σ∆f V (∆fres )2 12 (2-7) As with TDC, the total frequency noise is spread uniformly over (0, fR /2). The single sided spectral density is 2 σ∆f 1 V S∆f = 2 fR (2-8) The frequency variation can be transfered to phase variation by multiplying 2π/s. The single sided phase noise at the output is given by L(∆f ) = 1 ∆fres 2 1 ( ) 12 ∆f fR (2-9) Considering the DCO input samples are constant between updates, not random distributed, the sinc function is multiplied as a result of the zero-order hold operation. L(∆f ) = ∆f 2 1 ∆fres 2 1 ( ) (sinc ) 12 ∆f fR fR (2-10) Multiplying the above phase noise by its corresponding closed-loop transfer function, gives the output phase noise. Take Type-I PLL for example, Hcl,∆fV (s) = 2π/s 2π 1 = 1 + Hol αfR 1 + s/(αfR ) (2-11) the power spectral density is flat within the loop bandwidth L= Peng Chen (2π)2 ∆fres 2 1 1 ( ) 12 ∆f fR α2 CONFIDENTIAL (2-12) Master of Science Thesis 2-1 Work Principle 11 Comparing equations 2-6 and 2-12, a relationship between the DCO quantization noise (with dithering effect) and the TDC quantization noise within bandwidth can be obtained. ∆fV,res ∆tres = α fV TR (2-13) For ∆tres = 10 ps, fV = 2.4 GHz, TV = 417 ps, fR = 40 M Hz, α = 2−8 , DCO with a resolures tion ∆fV,res = fV ∆tTR α = 3.75KHz can generate the same amount of noise as the TDC. 2-1-3 Phase Prediction The phase prediction is based on the fact that once the loop is locked in the steady-state, the fractional phase error is pre-known theoretically. The principle is illustrated in Figure 2-3. The top two lines are the rising edge timestamps of CKV and FREF respectively. FCW=2.25, whose unit is defined as one CKV period. Because the fractional part of the frequency control word is non-zero, the timing deviation between FREF and the next CKV has a periodic pattern: 0, 0.75, 0.5, 0.25, 0. Since the periodic pattern can be got from the fractional part of FCW, DTC is used to delay CKV (it is CKVD2 in this chapter) according Example to F CWf rac , so that the risingN=2+1/4 edge of FREF and the next CKV is well aligned theoretically. As a result, TDC only has to cover a few quantization levels, to account for phase noise and DTC quantization noise. 0 1 2 3 4 5 6 7 8 9 10 11 12 Variable clock edges 0 2.25 4.5 6.75 9 11.25 0 3/4 ½ 1/4 0 3/4 Reference clock edges Delay to align the clocks Figure 2-3: Principle of phase prediction. Another power efficient technique adopted is the clock gating. It is CKV D2 that is fed into TDC, reducing TDC work frequency from CKV D2 (1.2 GHz, for example) to FREF (32 MHz, for example). The clock gating timing diagram is shown in Figure 2-4. CKV D2 has the same frequency as the reference signal. F REFdly and CKV D2s are fed into TDC. Both paths have delays before the two signals really go into TDC core. The timing offset is caused by controlling gates, extra buffers and single to differential-ended signal converter. The two paths’ delay difference is expressed as TDC offset in Figure 2-4. Master of Science Thesis CONFIDENTIAL Peng Chen 12 DTC-based ADPLL TDC offset (with TDC dithering) Delay of the DTC Phase error to be quantized by the TDC (signed output) FREF FREFD FREFD´ CKV CKV_G TDC output Figure 2-4: Timing diagram of the phase prediction technique. 2-1-4 Snapshotting and CKR Generation As described above, clock gating technique is used to save power. CKV D2, which contains the phase information in DCO output path and which is to be measured by TDC, is replaced with CKV D2s. CKV D2s is the signal of CKV D2 after clock gating, also called snapshotting, as shown in Figure 2-4. F REFdly is got by delaying the reference signal, the delay time of which is controlled by DTC. F REFdly is used to trigger the clock gating circuit. When F REFdly is high, the first rising edge of CKV D2 is used to trigger CKV D2s. Actually, it is also possible that the second rising edge of CKV D2 is used, which depends on the offset in the circuit. But it is not a problem since the offset is constant. By the clock gating circuit, we can get CKR additionally. The complexity and power of the circuit are thus reduced. In the traditional counter-based ADPLL [19], both the rising edge and falling edge of CKV are used to sample FREF, to overcome the metastability problem. In this architecture, F REFdly and CKV D2s rising edges are almost aligned. Theoretically, there is a small offset since F REFdly triggers the clock gating circuit. That is to say CKV D2s 0 . F REF rising edge is always after F REFdly dly can be used to directly sample CKVG . The signal after sampling is not used directly as CKR, but delayed by two CKV D2 circles, to provide enough processing time for TDC and phase incrementer. 2-2 DTC Nonlinearity’s Influence on Fractional Spurs When applied in wireless application, one important limitation is the in-band fractional spur. This section quantitatively explains the relationship between DTC nonlinearity and fractional spur’s level by two different methods. One is the traditional method; another is the pseudo phase domain method. Peng Chen CONFIDENTIAL Master of Science Thesis 2-2 DTC Nonlinearity’s Influence on Fractional Spurs 2-2-1 13 Traditional Method The traditional method starts from the DCO output signal. The information needed is the amplitude deviation of NTW (Normalized Tuning Word). Due to the periodic operation of DTC, NTW has a frequency component corresponding to the fractional number of FCW, which is F CWf rac · fref . The ADPLL is frequently modulated. Generally, DCO output signal can be written as Vout = Asin(w0 t + θ(t)) (2-14) where A is defined as the signal’s amplitude. w0 = 2πf0 is the carrier frequency. θ(t) takes account of initial phase and phase variation. Ideally, there is only one tone at Vout frequency spectrum. The amplitude is A. In this case, θ(t) is a constant. However, as thermal and flicker noise exist inside DCO, there is phase noise, making θ(t) vibrate versus time. Consider a special case, a single sinusoidal tone is in the phase: θ(t) = θp · sin(wm t), where wm (t) is the modulation frequency. When the peak phase deviation, θp , is much smaller than one, the DCO output signal can be deduced into Vout (t) = Asin[w0 t + θp sin(wm t)] Aθp ≈ Asin(w0 t) + {sin[(w0 + wm )t] − sin[(w0 − wm )t]} 2 (2-15) (2-16) Then the single sided spectral density is SV out (w) = θp2 θp2 A2 [δ(w − w0 ) + δ(w − w0 − wm ) + δ(w − w0 + wm )] 2 4 4 (2-17) It can be found that the phase noise is shifted towards the carrier frequency and distributed at both sides of the carrier frequency, at a distance of modulation frequency. Assuming the jitter at the DCO output is σ∆τ as a first-order approximation, σ∆τ T0 20 ps = 2π 417 ps = 0.30rad θp = 2π (2-18) (2-19) (2-20) Where T0 is the period of Vout , assuming output frequency is 2.4 GHz. And the maximum DTC INL reaches 1 LSB, in which one LSB corresponds to 20 ps. Because the in-band phase error transfer function is flat and the value is around 1. DTC’s INL can be regarded as DCO’s jitter. The fractional spur level can be written as L∆wm θp2 ) 4 = −16.48 dBc = 10log10 ( (2-21) (2-22) Since 0.3 is not too small, a more stringent mathematical derivation can be found in the appendix A, where the Bessel function of first kind is used to quantize the frequency modulation effect. Master of Science Thesis CONFIDENTIAL Peng Chen 14 2-2-2 DTC-based ADPLL Pseudo Phase Domain Method The architecture of the pseudo phase domain ADPLL is shown in Figure 2-5. It is pseudo because the phase is in the unit of 2π rad rather than 1 rad. Basically, one period of Tckv corresponds to a phase of 2π rad. Figure 2-5: Pseudo Phase Domain ADPLL. In Figure 2-5, Φrn consists of the reference signal noise and DTC nonlinearity. Because the reference signal noise is added after FCW, the noise transfer function is 1/F CW times the reference transfer function in the architecture in Figure 2-2. The working principle of the DTC-based counter-based ADPLL, reveals that the DTC nonlinearity directly phase P modulates the reference signal. RR [k] = kl=1 F CW + ΦDT C,n . In the following analysis, assume that TDC has a resolution small enough to neglect the quantization noise and there is also no DCO quantization noise and thermal noise. Only two non-ideal effects are taken into consideration: reference noise and DTC nonlinearity. Assume DTC has a sinusoid INL curve when the digital control word sweeps from 0 to 64. IN Lpp = 0.2. DTC unit delay is 25 ps. In the ADPLL, the reference frequency is 50 MHz and FCW equals 80. DCO’s center frequency is 3.6 GHz. When locked, DCO output frequency should be 4 GHz. Tckv = 250 ps. Assumed DTC INL characteristic 0.15 DTC INL (LSB) 0.1 0.05 0 −0.05 −0.1 0 10 20 30 40 DTC control code 50 60 Figure 2-6: Assumed DTC INL characteristic. As shown in Figure 2-6, IN Lpp means when DTC digital input control code is 16, INL is 0.1 LSB; when the control code is 48, INL is -0.1 LSB. After DTC, the delay FREF is 2.5 ps away Peng Chen CONFIDENTIAL Master of Science Thesis 2-2 DTC Nonlinearity’s Influence on Fractional Spurs 15 from the expected timestamp. The variance of timing uncertainty is σt2 = ( IN Lpp · TDT C 2 √ ) 2 2 (2-23) Normalized to the unit interval and multiplying by 2π radians: σφ = 2π σt TV (2-24) Different from TDC quantization noise derivation, the fractional signal’s power centers around the fractional frequency. That means, in FFT calculation, the scaling factor of the signal is different from that of the noise floor. So σφ2 does not have to be divided by fsampling /2 to get the single-sided spectral density. However, it has to be divided by 2, to transfer the singlesided spectrum into double-sided spectrum. Thus the fractional spur level can be written as L= π 2 IN Lpp TDT C 2 ( ) 4 Tckv (2-25) With CppSim [20], a phase domain counter-based ADPLL is modeled. DTC nonlinearity is added to the reference signal. In type-II ADPLL, the closed-loop transfer function for the DTC nonlinearity is Hcl,DT C (s) = αfR s + ρfR2 s2 + αfR s + ρfR2 (2-26) Within in-band, the gain of the loop is flat and equals 1. That explains the validation of formula (2-23). To validate the effectiveness of the formulas above, a simulation result is given in Figure 2-7. The reference noise is −114 dBc/Hz. α = 0.156. fR = 50 M Hz. Because in this phase domain model, the PLL closed-loop bandwidth is around fBW = 1 α · fR = 1.24 M Hz 2π (2-27) The fractional spur level is simulated to be −28.80 dBc/Hz. IN Lpp is set to 0.2 LSB. 1 π 2 IN Lpp TDT C 2 ( ) 2 2 Tckv π2 = · 0.022 4 = −30.06 dBc/Hz L = (2-28) (2-29) (2-30) The estimation error of the fractional spur level is only 1.26 dB, which is small enough to be accepted. It proves that formula 2-25 is very helpful to determine the in-band spur level. About the reference noise floor level, this paragraph will explain how it is generated and how the noise floor level is determined. The reference noise which is defined above, should be Master of Science Thesis CONFIDENTIAL Peng Chen 16 DTC-based ADPLL CppSim Simulated Phase Noise for Cell: ADPLL_sue, Lib: PC_ADPLL, Sim: test.par Phase Noise −60 −19 −39 −100 −59 −120 −79 −140 −99 −160 −119 0.01 0.1 1 Frequency Offset from Carrier (MHz) Spurs (dBc) L(f) (dBc/Hz) -28.80 dBc −80 10 Figure 2-7: Fractional spur level estimation. divided by FCW to get the true reference noise floor. In this model, the reference noise power is defined as 10−15 W att/Hz, which is -150 dB. The simulation time step is constant, which is taken as the sampling period. Thus, the reference noiseqis sampled at T s = 10−10 s = 0.1 ps. −15 Its output amplitude is Gaussian distributed, which is 10 ≈ 3.16 ∗ 10−3 . Referred to the 10−10 output signal of the ADPLL, the phase noise level is 12 (2π·3.16·10−3 )2 · f1r = −114.04 dBc/Hz. The 12 is to transfer the single-sided spectrum to double-sided spectrum. The f1r is because the noise is sampled by ckr is this model. Therefore, the total phase noise power is spread uniformly over the span from dc to the Nyquist frequency. The theoretical value is close to the simulation result. The above theoretical formula is more accurate when the fractional frequency is much smaller than the closed-loop bandwidth. Because during one fractional period, more data from ∆Φckv are just the inversion of ∆Φf ref , when assuming ΦE approaches to zero after DTC control code changes. The settling behavior depends on the loop filter parameters. When fractional spur locates in-band, this local settling time is usually much smaller than the loop settling time. However, actually, ΦE is also phase modulated signal. The formula 2-21 then can be used to calculate fractional spur level. But it is a approximate formula. What’s more, it is used in the analog PLL. Small changes need to be updated to get more accurate results. To close the gap between the simulation result and the theoretical value, a discrete time Peng Chen CONFIDENTIAL Master of Science Thesis 2-2 DTC Nonlinearity’s Influence on Fractional Spurs 17 analysis is done as following. In Figure 2-5, there are several relationships. ΦE [k] = ΦR [k] − ΦV [k] (2-31) ΦR [k] = k · F CW + Φrn [k] (2-32) k X f0 + N T W [n] fr n=1 ΦV [k] = k · N T W [k] = αΦE [k] + ρ k X ΦE [n] (2-33) (2-34) n=1 ¯E = 0 Φ (2-35) What interests us is how ΦE and N T W change as Φrn . To simplify the derivation, Z-transform is used, not in a stringent way. Formula 2-34 can be written as N T W [k] = kc + αΦE [k] + P P f0 ρ kn=m ΦE [n]. kc is a constant, given by ρ m−1 n=1 ΦE [n], which approximates F CW − fr . Formula 2-31, formula 2-32 and formula 2-33 give ΦE [k] = k · F CW + Φrn [k] − k · = k · (F CW − k X k f0 X − N T W [n] fr n=1 f0 − kc ) + Φrn [k] − fr (αΦE [l] − ρ l X ΦE [n]) (2-36) (2-37) (2-38) n=m l=2 To simplify the formula above, take kc = F CW − ffr0 . This will not affect the result. The simplification is based on the fact that in Type-II system, the phase error approaches zero. As the above equation shows, the first term should be zero, independent of k. Then the last terms also equal zero and we get ΦE [k] + k X l=2 (αΦE [l] + ρ l X ΦE [n]) = Φrn [k] (2-39) n=m The equation above reveals the nonlinear relationship between ΦE and Φrn . By z-transform, this relation can be written 1 − 2z −1 + z −2 ΦE = Φrn (2-40) (1 + α + ρ) − (α + 2)z −1 + z −2 z = esTr ≈ 1 + sTr = 1 + 2jπfrn Tr . If we only consider DTC nonlinearity, then frn is the frac1−2z −1 +z −2 tional spur’s frequency, which is 200 KHz in the above simulation. Then | (1+α+ρ)−(α+2)z −1 +z −2 Φrn | = 0.1367. On the other hand, formula 2-34 can be written as ρ N T W = (α + )ΦE (2-41) 1 − Z −1 The value |α + 1−Zρ −1 | = 0.1976. Next recall three formulas OT W = fr NTW ˆ KDCO (2-42) Z Vout = Asin(2πf0 t + 2πKDCO = Asin[w0 t + θp sin(wm t)] Master of Science Thesis CONFIDENTIAL OT W dt) (2-43) (2-44) Peng Chen 18 DTC-based ADPLL OTW is a sinusoid wave, with the fractional spur’s frequency. So wm = 2πfrn . Then 1 |N T W | 2πfrn fr ρ 1 − 2z −1 + z −2 = |α + || |AΦE frn 1 − z −1 (1 + α + ρ) − (α + 2)z −1 + z −2 50 M Hz = · 0.1976 · 0.1367 · 0.01 200 KHz = 0.0675 |θp | = 2πfr (2-45) (2-46) (2-47) (2-48) With the traditional method, the fractional spur level is L∆wm θp2 ) 4 = −29.43 dBc/Hz = 10log10 ( (2-49) (2-50) The Bessel function in the Appendix also yields the same value. It can be concluded that −29.43 dBc is the theoretical fractional spur level. It is closer to the simulation result 28.80 dBc in the simulation. The 0.63 dB gap is due to the computational error. The traditional method can give the accurate fractional spur level, while θp should be known first. However, when analyzing the fractional spur due to DTC, it is hard to find an obvious link between OTW amplitude and DTC INL’s amplitude. Because the closed-loop transfer function for the DTC nonlinearity is close to 1 in low frequencies. It is reasonable to assume OTW amplitude equals DTC INL’s amplitude. Then the formula 2-21 in traditional method is the same as the formula 2-25 in pseudo phase domain method. The pseudo phase domain method can directly calculate the fractional spur’s level according to DTC’s nonlinearity information. But it is a approximate algorithm and the error becomes very large when the fractional spur’s frequency goes beyond several hundred kilo-hertz. A ratio can be defined to evaluate the accuracy of the pseudo phase domain method. The traditional-pseudo ratio, ktp is ktp = fr ff rac |α + ρ 1 − 2z −1 + z −2 || | −1 1−z (1 + α + ρ) − (α + 2)z −1 + z −2 (2-51) p Fix the damping factor of the loop filter to 1/ (2). Reference frequency is chosen to be 50 MHz. Sweep α and fractional spur frequency, the traditional-pseudo ratio is shown in Figure 2-8. If the ratio is larger than 1, then the pseudo phase domain method gives a smaller value. If the ratio is smaller than 1, then the pseudo phase domain method gives a larger value. It can be seen that especially in narrow-band PLL, the pseudo phase domain method results in a very large error when the fractional spur frequency goes high. Fix α to 2−7 . Scale the traditional-pseudo ratio into dB format, shown in Figure 2-9. The y-axis is also the error caused by pseudo phase domain method. Plus this error, the result from pseudo phase domain method is compensated. Peng Chen CONFIDENTIAL Master of Science Thesis 2-3 DTC Gain Calibration 19 Traditional−pseudo Ratio 1.4 1.2 1 k tp 0.8 0.6 0.4 0.2 0 2 0.04 1.5 0.03 1 5 x 10 0.02 0.5 0.01 0 Fractional Spur Frequency (Hz) 0 alpha Figure 2-8: Traditional-Pseudo Ratio versus α and Fractional Spur Frequency. The Error by Pseudo Phase Domain Method 2 0 Error (dB) −2 −4 −6 −8 −10 0 0.5 1 1.5 2 2.5 3 Fractional Spur Frequency (Hz) 3.5 4 4.5 5 5 x 10 Figure 2-9: Traditional-pseudo Ratio versus Fractional Spur Frequency, α = 2−7 . 2-3 DTC Gain Calibration In the traditional counter-based ADPLL, TDC gain calibration is very important. Otherwise, fractional spurs appear at ff rac = F CWf rac · fref and its harmonic frequencies. When DTC is added in the feedback path, there is no need to calibrate TDC gain. The ckv period can be roughly calculated through FCW and reference frequency. This value can be used to calibrate Master of Science Thesis CONFIDENTIAL Peng Chen 20 DTC-based ADPLL TDC gain. Since TDC do not have to cover the whole ckv period, such fractional spurs are not generated. However, DTC has to cover the whole ckv period. DTC gain has to be correctly estimated to overcome the PVT variation. Practically, DTC gain is adaptively calibrated by LMS algorithm. Least mean squares (LMS) algorithm is to find the filter coefficients to produce the least mean squares of the error signal, the difference between the desired signal and the actual signal. In the following, the theory of noise cancellation by LMS algorithm is introduced, followed by how it is applied in DTC gain calibration. 2-3-1 Noise Cancellation Theory The stringent definition and derivation of LMS algorithm can be found in many textbooks, such as [21], [22]. This part only describe the LMS adaptive filter briefly, for easier understanding the gain calibration part. Figure 2-10: LMS Adaptive Filter. In Figure 2-10, s denotes the signal and n denotes the noise. r correlates to the noise n by a system H. W is the coefficient updated by LMS algorithm. n ˆ is the estimation of the noise signal. Ideally, eˆ only contains the signal information. W updates in the following way. W (k + 1) = W (k) + 2µˆ e(k)r(k) (2-52) When W = Wopt , the W fluctuate around a stable value. E{ˆ e(k)r(k)} = 0. Then eˆ will not correlate with r. Two conclusions can be drawn. 1. LMS algorithm removes the correlation between the error signal and the noise. 2. W is an estimation of 2-3-2 1 H. DTC Gain Calibration with LMS DTC increases the input signal’s phase by Φd , according to the DTC control code D[m]. Considering PVT variation, Φd should cover the range from 0 to 1, in the unit of 2π rad. One Peng Chen CONFIDENTIAL Master of Science Thesis 2-3 DTC Gain Calibration 21 Tckv consists of 2π. D = m. m is the natural number from 0 to 64. The transfer function 40ps 1 = 2000ps of DTC is Φd = Φof f set + m · ∆D . ∆D0 = DT C Tresolution = 50 , for example. If the ckv DTC unit delay is enlarged by PVT variation, then the transfer curve has a larger slope. In Figure 2-11, DTC is modeled as an ideal DTC. The unit delay variation is modeled by the noise added at the output of DTC. n[m] = (∆D1 − ∆D0 ) · m (2-53) P HRF is the fractional part of the accumulated result of FCW. Thus, 1 − P HRF = 1− X F CWf rac 1 − P HRF [k] = 1 − Ff · k + bFf · kc (2-54) (2-55) in which k = 1, 2, ... is FREF clock transition index number and Ff denotes the fractional number of FCW. 1 − P HRF [k] c KDT C0 = D[k] · ∆D0 + n[D[k]] D[k] = b Φref _dly (2-56) (2-57) Ideally, the total contribution of other phases before the phase detection component is D[k] · ∆D0 . Then phase error eˆ = n[D[k]] 1 − P HRF [k] = (∆D1 − ∆D0 ) · b c KDT C0 (2-58) (2-59) Thus, 1 − P HRF is approximately linearly correlated with the noise n. 1/KDT C is the coefficient needed to be updated. At its optimum point, eˆ do not have the part correlated with 1 − P HRF . It is around zero at last. LMS will shift the transfer function slope in Figure 2-12 to the normal value. Figure 2-11: Diagram of DTC Gain Calibration. The noise in Figure 2-11 is almost linearly dependent on 1 − P HRF . This linear relationship is used to remove that noise. But except DTC unit delay variation, DTC has other nonlinear effects, such as INL. INL can be directly added into the noise in the model. The LMS Master of Science Thesis CONFIDENTIAL Peng Chen 22 DTC-based ADPLL DTC transfer function 1.8 1.6 Phase Delayed by DTC (2π rad) 1.4 1.2 1 0.8 0.6 Normal Delay Enlarged Delay by PVT 0.4 0.2 0 0 10 20 30 40 DTC Control Code 50 60 70 60 70 Figure 2-12: DTC transfer function. DTC transfer function 1.8 Normal Delay Enlarged Delay by PVT PVT Variation Plus INL 1.6 Phase Delayed by DTC (2π rad) 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 10 20 30 40 DTC Control Code 50 Figure 2-13: DTC transfer function. algorithm we adopted so far can only compensate the linear related error. That means only the slope of the DTC transfer function is possible to be adjusted. If INL is applied as in Figure 2-13, LMS algorithm has to be updated. To simplify the analysis, INL is first assumed to be a sinusoid wave, as shown in Figure 2-13. Divide the DTC control words into 4 equal parts. Each contains 8 control numbers. In each part, the correlation between the detected phase error and 1 − P HRF still exists. That makes it practical to calibrate DTC gain with four Peng Chen CONFIDENTIAL Master of Science Thesis 2-3 DTC Gain Calibration 23 segments. There are some common points with the Piecewise-Linear Pre-Distortion method in [8]. Take a further step, let’s compare those two DTC nonlinearity cancellation method. In the LMS algorithm, Piecewise-Linear Pre-Distortion method uses several specific points of phase error every Tref /F CWf rac period. LMS makes those points fluctuate around zero. Segementgain based method takes the information of all points of the phase error. This method is to update the gain of each segement, rather then the value of the specific points. Obviously, pre-distortion method computes less, at the expense of bad trade-off between precision and converge speed. In practical application, PVT doesn’t change rapidly, pre-distortion can meet the specification. It should be mentioned that the pre-distortion used here is different from the one in [8], because they are used in two different architectures and the DTC control code here doesn’t have a negative value. To illustrate the effectiveness of pre-distortion algorithm, Figure 2-14 is shown. The nonlinearity applied is 0.1 Tckv . It is so large that the spur level can be -16.86 dBc if traditional DTC gain calibration algorithm is used. When pre-distortion is used, even though only 3 points are to be estimated, the highest spur level is reduced to -42.03 dBc. 3 points means only when phrf=0.25, phrf=0.5, phrf=0.75 (along with phrf=0.0), the phase error is fed into the LMS algorithm. With more points, even lower spur level can be achieved. In one word, with multiple coefficients, the LMS can cancel the nonlinearity. DTC Transfer Function Nonlinearity Cancellation, rbw=10 KHz −20 1 Without Nonlinearity Cancellation With 3 points Nonlinearity Cancellation 0.8 −60 Phase Noise (dBc) Delay Time (/Tckv) −40 0.6 0.4 0.2 0 0 −80 −100 −120 −140 −160 −180 20 40 DTC Control Code Modelled Ideal 60 −200 −220 5 10 6 10 7 10 Frequenc (Hz) (a) DTC Transfer Function. (b) Phase Noise Comparison Figure 2-14: Pre-Distortion to Cancel Nonlinearity The conclusions of this part goes below: DTC nonlinearity is not a limitation of this kind ADPLL, because it can be digitally calibrated. Adaptation Constant In formula 2-52, µ is the step size, also called adaptation constant. It controls the convergence rate and the stability. Trade-off exists between the convergence rate and the convergence accuracy. To illustrate how the adaptation constant affect that trade-off and give guidance to the practical implementation, Figure 2-15 is shown. In that figure, three different adaptation Master of Science Thesis CONFIDENTIAL Peng Chen 24 DTC-based ADPLL constants are chosen: 10−6 , 5 ∗ 10−6 , 10 ∗ 10−6 . Figure 2-15 (left) shows DTC gain converges to 25 which is the right value. Figure 2-15 (right) shows the gain error in dB format as the calibration keeps working. Larger adaptation constant results in a faster settling behavior, while gives higher estimation error when calibration is stable. µ’s influence on settling time µ’s influence on settling time 31 20 100u 500u 1000u 30 100u 500u 1000u 10 0 −10 DTC gain (dB) DTC gain 29 28 27 −20 −30 −40 −50 26 −60 25 −70 24 −80 0 0.5 1 1.5 2 2.5 time (s) 3 3.5 4 4.5 5 0 0.5 1 1.5 2 −3 x 10 2.5 time (s) 3 3.5 4 4.5 5 −3 x 10 (b) DTC gain error in dB (a) DTC gain converges to 25 Figure 2-15: Adaptation constant’s influence on settling time To verify the trade-off directly on phase noise, Figure 2-16 is plotted. µ’s influence on phase noise −80 −90 −100 Reference Signal Nosie Floor Phase Noise (dBc/Hz) −110 −120 −130 −140 −150 −160 −170 −180 4 10 100u 500u 1000u 5 10 6 10 Frequency (Hz) 7 10 Figure 2-16: Adaptation constant’s influence on phase noise. Peng Chen CONFIDENTIAL Master of Science Thesis 2-3 DTC Gain Calibration 25 Small Fractional Number Calibration Problem During the measurement, it is found that when the fractional number is very small, the fractional spur is very high. It seems that the DTC gain calibration does not work. This problem is also verified by the simulation, both in Simulink and CppSim. The current LMS algorithm cannot work very well when fractional number is near integer. The algorithm correlates the phase error Φe and 1 − P HRF . In previous chip, only the sign of the number is used. This method simplify hardware implementation but not suitable when fractional number of FCW is near integer. Taking the whole value into LMS algorithm makes the performance better. The algorithm can process smaller F CWf rac . When F CWf rac = 0.01, Figure 2-17 shows DTC gain’s response when two different algorithms are applied. No sign algorithm means LMS takes the complete value of Φe and 1 − P HRF . Sign algorithm means LMS only takes the sign of the values. In Figure 2-17, DTC gain cannot converge to the right value when sign algorithm is adopted. By contrast, no sign algorithm approaches to the right value: 64, even though it converges slowly. Sign versus No Sign in LMS algorithm 60.575 −10 60.5745 60.574 4.7 −15 4.75 4.8 4.85 time (s) 4.9 4.95 5 DTC gain for sign DTC gain for no sign No Sign for both Sign for both −20 −3 x 10 Figure 2-17: Sign versus complete value when F CWf rac is near integer. When using complete value (no-sign) LMS algorithm, F CWf rac = 0.01, its phase error, P HRF and DTC gain response are shown in Figure 2-18. Here P HRF rather than 1−P HRF is used. The adaptation constant is therefore a negative value. In the right zoomed in figure, after P HRF goes over 1 and drops back to 0, the DTC gain first increases for a short time, then it decreases. That is related with the phase error response. What we expected is that the DTC gain increases over one fractional period Tf rac = Tref /F CWf rac . However the simulation results give another scenery. That is due to the overshoot in the Φe step response. It is observed that the overshoot (the region where the phase error is smaller than 0) lasts a longer time the the region where the phase error is larger than 0. This phenomenon does not exist when F CWf rac is close to 0.5. So those values can result in a good DTC gain estimation. To overcome this problem, one optional method is to detect the peak of Φ2e and Master of Science Thesis CONFIDENTIAL Peng Chen 26 DTC-based ADPLL check at this timestamp what the sign of Φe and P HRF are. Only use the sign information at the specific time and update DTC gain over one Tf rac period, rather than one Tref period. This method updates slower if we want to keep the same phase noise floor when DTC gain is stable. Luckily, it can make DTC gain converge into the right direction however small the F CWf rac is. The limitation of this method is that it cannot cover F CWf rac from 0 to 1. Figure 2-19 shows the case in which this method is adopted. In the left figure, DTC gain centers around the right value of 64. In the right figure, there is fractional spur whose level is greatly reduced, compared with the case when DTC gain is not estimated correctly. It can be reduced further by decreasing the adaptation constant. 1 PHRf PHRf 1 0.5 0.5 0 0 5.05 5.1 5.15 5.2 5.25 5.195 5.3 5.2 5.205 5.21 5.215 5.22 5.225 5.23 −4 −4 x 10 x 10 0.04 Phase Error Phase Error 0.2 0.15 0.1 0.05 0 0.02 0 −0.02 5.05 5.1 5.15 5.2 5.25 5.195 5.3 5.2 5.205 5.21 5.215 5.22 5.225 −4 57 DTC gain 57.5 DTC gain 5.23 x 10 −4 x 10 57 56.9 56.8 56.7 56.5 5.05 5.1 5.15 time (s) 5.2 5.25 5.195 5.3 −4 5.2 5.205 5.21 time (s) 5.215 5.22 5.225 5.23 −4 x 10 x 10 (b) Left figure zoomed in (a) No sign LMS algorithm, F CWf rac = 0.01 Figure 2-18: Small fractional number, no sign LMS algorithhm is used Simulated Signals for Cell: ADPLL_sue, Lib: PC_ADPLL, Sim: test.par 1 CppSim Simulated Phase Noise for Cell: ADPLL_sue, Lib: PC_ADPLL, Sim: test.par PHRF phase noise −90 −49 0.5 -55dBc −100 −59 −110 −69 −120 −79 −130 −89 −140 −99 −150 −109 −160 −119 0 7.495 7.5 7.505 7.51 0.01 0.005 0 −0.005 Spurs (dBc) L(f) (dBc/Hz) phie −0.01 7.495 7.5 7.505 7.51 64.05 DTC gain 64 63.95 7.495 7.5 7.505 Time (milliseconds) 7.51 0.01 (a) Transient signals when stable 0.1 1 Frequency Offset from Carrier (MHz) 10 (b) Phase noise Figure 2-19: Small fractional number, detecting maximum Φ2e method is used Peng Chen CONFIDENTIAL Master of Science Thesis 2-3 DTC Gain Calibration 27 Fractional Spur Level Sensitivity to DTC Gain Wrong DTC gain produces fractional spurs, locating at fref /F CWf rac and its harmonic frequencies, even though DTC doe not have nonlinearity. The induced phase error behaves like a saw wave in the time domain. The following six figures give how sensitive the fractional spurs level are to DTC gain. From those simulation results, it can be concluded that to keep the fractional spur level below -38 dBc, DTC gain should be calibrated within 1% error. To leave a margin, even smaller error is required. CppSim Simulated Phase Noise for Cell: ADPLL_sue, Lib: PC_ADPLL, Sim: test.par CppSim Simulated Phase Noise for Cell: ADPLL_sue, Lib: PC_ADPLL, Sim: test.par freqfilt freqfilt −110 −72 −90 −52 -59.13 dBc −130 −92 −140 −102 −150 −112 −160 −122 0.01 0.1 1 Frequency Offset from Carrier (MHz) 10 −62 -65.6 dBc −110 −72 −120 −82 −130 −92 −140 −102 −150 −112 −160 −122 0.01 (a) DTC gain is correct (64) 0.1 1 Frequency Offset from Carrier (MHz) Spurs (dBc) −82 Spurs (dBc) L(f) (dBc/Hz) L(f) (dBc/Hz) −100 −120 10 (b) DTC gain has 0.1% error (63.936) Figure 2-20: Fractional spur level’s sensitivity (1) CppSim Simulated Phase Noise for Cell: ADPLL_sue, Lib: PC_ADPLL, Sim: test.par CppSim Simulated Phase Noise for Cell: ADPLL_sue, Lib: PC_ADPLL, Sim: test.par freqfilt freqfilt −32 −70 -38.09 dBc −90 −52 −100 −62 −110 −72 −120 −82 −130 −92 −140 −102 0.01 −80 −42 -45.71 dBc 0.1 1 Frequency Offset from Carrier (MHz) Spurs (dBc) L(f) (dBc/Hz) L(f) (dBc/Hz) −80 -33.06 dBc −32 -39.68 dBc -42.44 dBc -44.52 dBc −42 −90 −52 −100 −62 −110 −72 −120 −82 −130 −92 −140 −102 −150 −112 −160 −122 10 (a) DTC gain has 1% error (63.36) 0.1 1 Frequency Offset from Carrier (MHz) Spurs (dBc) −70 10 (b) DTC gain has 2% error (62.72) Figure 2-21: Fractional spur level’s sensitivity (2) Master of Science Thesis CONFIDENTIAL Peng Chen 28 DTC-based ADPLL CppSim Simulated Phase Noise for Cell: ADPLL_sue, Lib: PC_ADPLL, Sim: test.par CppSim Simulated Phase Noise for Cell: ADPLL_sue, Lib: PC_ADPLL, Sim: test.par freqfilt −50 −12 -19.07 dBc −60 −32 −80 −42 −90 −52 −100 −62 −110 −72 −22 -25.69 dBc −70 −32 −80 −42 −90 −52 −100 −62 −110 −72 −120 −82 −120 −82 −130 −92 −130 −92 −140 −102 −140 −102 0.1 1 Frequency Offset from Carrier (MHz) 10 0.1 1 Frequency Offset from Carrier (MHz) (a) DTC gain has 5% error (60.8) Spurs (dBc) -31.71 dBc 34.46 dBc -36.56 dBc −70 L(f) (dBc/Hz) freqfilt −22 -25.10 dBc Spurs (dBc) L(f) (dBc/Hz) −60 10 (b) DTC gain has 10% error (57.6) Figure 2-22: Fractional spur level’s sensitivity (3) 2-3-3 Measurement Results and Explanation If DTC does not have nonlinearity, when its gain is correctly calibrated, the spurs are also removed. That is because the phase error behaves like a sawtooth wave, as shown in Figure 2-23. It is in the unit of A · Tckv , where A is proportional to the DTC gain error. When DTC gain is not correct 1 0.9 phase error (A⋅Tckv) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.5 1 time 1.5 2 Figure 2-23: Phase error when DTC gain is not correct and there is no nonlinearity in DTC. In the following calculation, phase error is in the unit of Tckv , then Φe = = t ,0 < t < T T ∞ A X A − sin(nΩt) 2 n=1 nπ (2-60) (2-61) in which T = Tref /F CWf rac , Ω = 2π/T . Take DTC nonlinearity into consideration. Assume Peng Chen CONFIDENTIAL Master of Science Thesis 2-4 TDC Quantization’s Influence on Fractional Spurs 29 it can be written as Φe,IN L = a1 sin(Ωt + θ1 ) + a2 sin(2Ωt + θ2 ) + · · · (2-62) Wrong DTC gain and DTC nonlinearity’s total contribution is Φe,tot = = A A A + (a1 sin(Ωt + θ1 ) − sin(Ωt)) + (a2 sin(2Ωt + θ2 ) − sin(2Ωt)) + ·(2-63) ·· 2 s π 2π A A + (a1 cos(θ1 ) − )2 + (a1 sin(θ1 ))2 sin(Ωt + θ10 ) + (2-64) 2 π s (a2 cos(θ2 ) − A 2 ) + (a2 sin(θ2 ))2 sin(2Ωt + θ20 ) + · · · 2π (2-65) To simplify the explanation, assume θ1 = 0, θ2 = 0. Then Φe,tot = A A A + (a1 − )sin(Ωt) + (a2 − )sin(2Ωt) + · · · 2 π 2π (2-66) When DTC gain is tuned manually, the first spur can be suppressed by making A = a1 π. However, other spurs’ level may go to even higher values. For example, the phase error amplitude corresponding to the second spur has an amplitude of a2 − a1 /2. If a1 and a2 have different polarities, the second spur’s level is larger than -36 dBc, taking IN Lpp = 0.2LSB into calculation. However, it should be noticed that if θ1 , θ2 ... are not neglected, the second spur level is not that bad. 2-4 TDC Quantization’s Influence on Fractional Spurs In the traditional counter-based ADPLL, Tckv is estimated to normalize the TDC output. If the estimation error is larger than expected, there will be fractional spur at the frequency of min(F CWF , 1 − F CWF ) × fr and its harmonics. In this new architecture, this problem is shifted to DTC. Apart from this, if the TDC quantization noise is non-uniformity, especially when the frequency control word is closer to integer, mysterious idle tones may appear inband. Short dithering sequences technique is used to compensate this problem, as described in [11]. Near integer channels exhibit higher integer jitters. The reason is that the CKV clock edges become synchronous to the FREF clock edge, resulting that the TDC is unable to detect the phase error for a certain FREF cycles. Denote ∆tdc as the TDC resolution. The phase error should be accumulated to be larger than one ∆tdc to make TDC output change. At each FREF cycle, the phase error increases by F CWf rac Tckv . As shown in Figure 2-24, such a pattern F CWf rac Tckv manifests spurs location at fr and its harmonics. That is the ideal analysis. ∆tdc Actually, since ADPLL is unable to track effectively, the spurs’ locations may change. In the new architecture, DTC is also included in the phase detect part, making it more complex. Anyway, what matters is to randomize the TDC quantization, rather than estimate such kind of spurs. As shown in Figure 2-25, the black line is the phase noise when TDC resolution is extremely small. The reference noise dominates the in-band noise floor. The blue line shows the case when TDC resolution is 1/40Tckv , which corresponds to -103 dBc/Hz in-band noise Master of Science Thesis CONFIDENTIAL Peng Chen DTC-based ADPLL R Δtdc ø -ø V 30 FCWfracTckv t Figure 2-24: TDC remain blinded for several reference cycles at near-integer channels in traditional counter-based ADPLL. floor. When TDC quantization noise is not fully randomized, more noise is concentrated at lower frequencies. It can be seen that at higher frequencies, the phase noise is even lower when TDC quantization is not fully randomized. Increasing the reference noise floor by 10 dB, the new in-band phase noise level is around -100 dBc/Hz, as the red line shows. −70 ∆ <1fs, L=−114 dBc/Hz ∆ =0.025Tckv, L=−114 dBc/Hz Phase Noise (dBc/Hz) −80 ∆ =0.025Tckv, L=−104 dBc/Hz −90 −100 −110 −120 −130 −140 −150 −160 4 10 5 10 6 10 7 10 Frequency (Hz) Figure 2-25: Dithering help randomize TDC quantization noise. Above all, the DTC-counter-based ADPLL aligns the FREF and CKV at the input of TDC, making this architecture suffers more severer from TDC quantization non-uniformity. Right now, the DTC thermal noise and nonlinearity can help randomize the TDC quantization. In future higher performance designs, when DTC has lower dithering effect, additional dithering technique is desired to be used. Since DTC is already in this architecture, dithering is very convenient. Peng Chen CONFIDENTIAL Master of Science Thesis 2-5 Investigation on Fractional Spurs 2-5 31 Investigation on Fractional Spurs Figure 2-26: Architecture of DTC-assisted ADPLL. Figure 2-26 is the architecture of the DTC-assisted ADPLL. The fractional spur originates from the components and coefficients marked in the red circle. ff rac = min{F CWf rac fref , (1 − F CWf rac )fref } (2-67) Traditionally, the fractional spur locates ff rac from the desired output frequency. This is partially true. There is one spur at the expected location indeed. But there are also some other spurs in-band. For example, when FREF=50 MHz, F CWF =0.5078125, the traditional desired spur locates at 25.390625 MHz. However, both from the simulation and measurement, it is found that there is also a spur locating at 781.25 KHz. This is not due to the finite bits of FCW, but due to the nature of accumulated fractional number rotating. This kind of spur is usually close to in-band or just in in-band, is not significantly filtered out by the loop filter, usually manifests a larger spur level than the spur level at 25.390625 MHz. Considering DTC is essentially controlled by digital block, the fractional spur’s locations should be give by one of the two following formulas. ff rac1 = (M × F CWf rac − bM × F CWf rac c)fref (2-68) ff rac2 = fref − (M × F CWf rac − bM × F CWf rac c)fref (2-69) ff rac = min{ff rac1 , ff rac2 } (2-70) M is the natural number starting from 1 to infinity. Master of Science Thesis CONFIDENTIAL Peng Chen 32 DTC-based ADPLL DNL 3 2 LSB 1 0 −1 −2 −3 0 10 20 30 40 DTC resolution: 20.034 ps 50 60 70 50 60 70 INL 3 2 LSB 1 0 −1 −2 −3 0 10 20 30 40 DTC input code Figure 2-27: Measurement results of DTC nonlinearity. 0.4 DNL 0.3 LSB 0.2 0.1 0 −0.1 −0.2 −0.3 0 10 20 30 40 DTC resolution: 20.7847 ps 50 60 70 0.3 INL LSB 0.2 0.1 0 −0.1 0 10 20 30 40 DTC input code 50 60 70 Figure 2-28: Simulated results of DTC nonlinearity. In the previous tape-out, the simulation and measurement results of DTC nonlinearity are shown in Figure 2-27 and Figure 2-28. The INL peak-to-peak can reach 4 LSB in the measurement. If this is true, the DTC nonlinearity should be responsible for the very large fractional spur in in-band. The following describes five assumptions in the fractional spur investigation, based on simulation and measurement results. 2-5-1 Non-ideal effects introduced in measurement The DTC measurement puts a stringent requirement on the measurement equipments. DTC resolution is in the order of tens of picoseconds. The equipment should be able to measure 1 ps time difference to give reasonable results. The signal fed into DTC should also have a small phase noise. The signal path of F REFdly from DTC output to output buffer has a large resistance. Because Peng Chen CONFIDENTIAL Master of Science Thesis 2-5 Investigation on Fractional Spurs 33 that path is thin and long in the layout. What’s more, the output buffer is not big enough to drive the off-chip buffers, whose input capacitances are usually several pico-farad. One of the DTC measurement methods takes information from the duty cycle of F REFdly . With this method, the falling edge of F REFdly is required to have a small jitter. However, in this DTC architecture, only the rising edge of F REF is optimized. Much jitter is injected at the falling edge of F REF signal. During the measurement, it is found that when the output buffer is enabled, the ADPLL noise floor is shifted to a higher level, so does the fractional spur level. It is concluded that the offchip noise injects into the chip when output buffer is enabled. And considering the output buffer shares the same supply voltage with DTC, the voltage fluctuation on the output buffer is coupled to the DTC supply voltage. So the output buffer in-chip should not share the supply voltage with the sensitive components. But it is still not immediately realized in this tape-out. Above all, only with the on-chip sigma-delta measurement can we determine the measurement non-ideal effects’ influences. This assumption is used to check whether the DTC INL is responsible for the fractional spurs. 2-5-2 Misalignment of φ0 s integer and fractional part After checking the digital code, it is possible that the CKV phase’s integer part and fractional part are mis-aligned. Before synthesis, each operation’s delay time is only approximately defined. And part of the code is written in a manner that is sensitive to the delay, which may cause misalignment issues. The spur level yield that the misalignment does not occur 1 every Tf rac = F CWf rac ·fref period. This fact reduces the possibility of the validation of the assumption. 2-5-3 Wrong estimation of DTC control word As described in phase prediction part, the correct DTC gain estimation plays an important role in minimizing the fractional spur level. Only the correct DTC gain gives the correct DTC control word. If the DTC control word is wrong estimated, every cycle the DTC delay sweeps from 0 to TV (one period of CKV), the undesired phase error repeats. The fractional spur is introduced in this way. Some figures in the above section give how the fractional spur level changes as the DTC gain is wrong estimated. 2-5-4 Voltage Drop In the measurement, it is found that increasing the supply voltage helps reduce the fractional spur level. It is also noticed that the supply voltage of the DTC in the layout is not symmetric. The decoupling capacitors are a bit far from the DTC. Then this assumption is brought up: the inner voltage of DTC is not stable during the operation. To illustrate voltage influence on DTC unit cell’s delay, which is also called DTC resolution, Figure 2-29 is shown. DTC is very sensitive to the supply voltage. If the voltages applied on 64 stages of DTC are not the same, the mismatch causes the fractional spur. In one word, the lack of decoupling capacitors can cause large inner voltage drop and causing fractional spurs. Master of Science Thesis CONFIDENTIAL Peng Chen 34 DTC-based ADPLL 27.5 Unit Delay (ps) 25 22.5 20 17.5 15 0.9 0.95 1.0 1.05 1.1 VDD (V) Figure 2-29: DTC unit delay versus voltage. 2-5-5 DTC mismatch The mismatch in DTC causes each unit’s delay time variating. That is reflected in the DNL and INL. The INL is random distributed. This characteristic is in accordance with the measurement result. However, the INL level in the measurement is larger. Peng Chen CONFIDENTIAL Master of Science Thesis Chapter 3 Test Circuit Design for Built-in DTC Measurement Abstract The off-chip measurement method feeds DTC output signal directly into the scope. The on-chip output buffer switches fast, coupled to the supply voltage. The modulated supply voltage contaminates the linearity of DTC. To get the accurate nonlinearity information of DTC, one on-chip measurement method is proposed. This chapter first explains first-order Σ − ∆ measurement circuit mathematically and gives a top view description. Then with a z-domain model, noise and nonlinearity are analyzed. At last, techniques to reduce the nonlinearities in the circuit are described. 3-1 Time Domain First-Order Sigma-Delta Mechanism Sigma-Delta Modulation is usually used in Analog-to-Digital Converters (ADC), which operates in voltage domain. The information can be stored on the capacitor in this domain. In contrast, it is hard to directly handle the time information. To process the time information, we have to firstly converter it to another domain, for example, like voltage domain or current domain. In this article, a charge-pump is used to converter time information to current domain. Then one capacitor is used to converter the current to voltage domain. Essentially, the architecture of test circuit used in this article is a Time-to-Digital Converter (TDC). For TDC, generally, the quantization noise is limited by its resolution, which is typically 10∼20 ps when inverter delay line is used in 40 nm technology. Sub-gate resolution TDC architectures can provide resolution smaller than 10 ps. In this article, with first-order Σ∆ test circuit, subgate resolution can also be achieved. With proper design, even sub-picoseconds resolution can be achieve with good accuracy. Master of Science Thesis CONFIDENTIAL Peng Chen 36 3-1-1 Test Circuit Design for Built-in DTC Measurement Mathematical Explanation In [23], a Σ∆ − P W D architecture is proposed to process the pulse signals. The pulse width information is digitized. The basic idea can be applied here to measure the DTC delay. As shown in Figure 3-1, first-order time domain sigma-delta test circuit is developed. The information is first transfered from digital value to pulse width by a digital-to-PW conversion circuit. Then the pulse width information is converted to current flowing into the loop capacitor, by employing a PW-to-current conversion circuit. The operating principle is similar in this article. In Figure 3-1, the digital signal coming out from the comparator selects which pulse to be fed into the feedback path. The two pulses, FREF1 and FREF2, are generated by an input clock with higher frequency. As shown in this figure, FREF1 has a duty cycle of 50% and FREF2 has a duty cycle of 25%. Because they are generated by the same input signal, the phase difference is precisely controlled. DTC reduces the duty cycle with a constant value, which corresponds to the DTC delay. Through charge pump, pulse width information is reflected on the amount of current flowing into or out of the loop capacitor. The loop capacitor is then acted as an integrator. Comparator is used here to compare the voltage on the capacitor and the reference voltage. FREF1 FREF2 T/2 CP+ X1+ X2+ T/4 CP- X3=X2+ T/4-DTC_delay X2 V(n) : DTC delay X3 : Pulse width of FREF2 FREF2 X2+ T/4 x3 X1/x2 Charge Pump V(n) Vref s(n) Comparator FREF1 FREF2 X1+ DTC X2+ DTC Control Code FREFdly Figure 3-1: Simplified Top Level Architecture. As shown in figure 3-1, charge pump is controlled by two signals. One signal has a duty cycle of 25 percent, charging the capacitor constantly. Another signal is controlled by the loop. Roughly, it has a duty cycle from 0 to 50 percent and discharges the capacitor. The average output current of the charge pump is zero when the loop is in stable. The information is read out by recording comparator’s output. The output stream will be fed into a decimation filter. Rectangular filter is enough, based on simulation results and system analysis. The simplest way to realize rectangular filter is to count how many "1" appears within a fixed period. Counters can also ease the hardware implementation. To give a mathematical view, the relationship between counter output and DTC delay is derived. Peng Chen CONFIDENTIAL Master of Science Thesis 3-2 Noise and Nonlinearity Analysis 37 s(n) = sgn[V (n) − Vref ] (3-1) V (n) = V (n − 1) + x3 − [x2 + s(n)(x1 − x2 )] V (N ) − V (0) = N (x3 − x2 ) + (x1 − x2 ) N X s(n) (3-2) (3-3) n=0 = N (x3 − x2 ) + N s(x1 − x2 ) (3-4) (3-5) Since V(n) is bounded, V (N ) − V (0) N →∞ N lim = x3 − x2 + s(x1 − x2 ) = 0 s = x3 − x2 x1 − x2 (3-6) (3-7) Let ∆ represents DTC’s delay, then x2 = x3 − ∆, x1 = 2x3 − ∆ (3-8) ∆ = sx3 (3-9) In the above equations, s is the probability of the appearance of "1" in the comparator’s output. And x3 is one quarter of the operation period. Take 32MHz for example, x3 = T4 = 7.8125ns. 3-1-2 Top View Explanation Figure 3-2 shows a more detailed scenery of the top level architecture. Similar with the traditional sigma-delta ADC, capacitor voltage is quantized by the comparator (one-bit ADC). Selector and DTC act as a one-bit DAC. Its output is subtracted in the charge pump. In this test circuit, DTC delay is measured one by one. That means delay is fixed. So alternating pattern of "0"s and "1"s will appear at the comparator’s output. And there is no slope clipping problem. We can also change the length of the rectangular decimation filter to give more information about data analysis. Continuous measurement can be realized by increasing DTC control signal at a fixed time step. Counter corresponds to the sinc decimator. It saves area (only 32 DFFs) and very easy to implement. If we do not care about area, recording all comparator’s output, with hanning window, about 0.1 fs resolution can be achieved. The above simulation is done with 21 6 sampling periods. Higher resolution can be got when taking longer periods. 3-2 3-2-1 Noise and Nonlinearity Analysis Z Domain Description To analysis how the noise and nonlinearity in the analog components affect the test circuit’s performance, a z-domain model is set up in Figure 3-3. Vosi stands for the integrator offset. Master of Science Thesis CONFIDENTIAL Peng Chen 38 Test Circuit Design for Built-in DTC Measurement It represents for the charge and discharge currents’ offset. This offset will be added into DTC’s offset, which we do not care about in the ADPLL application. Vosq stands for the quantizer offset. It represents for the input offset voltage of the comparator. It only shifts integrator swing. Generally, quantizer nonlinearities do not deteriorate the performance. α stands for the charge pump’s nonlinearity. This limits measurement’s resolution. Look-up table is planned to be used to reduce the error. The main factor limiting measurement resolution is charge pump’s nonlinearity. 2% nonlinearity can bring 1 LSB error, as a thumb of rule from system simulation. Look-up table should be taken good care of to dismiss this effect. Figure 3-4 shows the comparison of the voltage on capacitor with or without comparator’s offset. It is found that Vosq only affects the average voltage on the capacitor. Since the comparator’s threshold voltage also changes as Vosq , comparator’s output stream will keep the same, except the first several periods. Figure 3-5 reveals the relationship between the charge pump’s nonlinearity and the corresponding error. This error cannot be reduced by enlarging counter’s bits. It exists as a systematic error. When nonlinearity is 5 percent and DTC delay is 2 ns, this error is almost 50 ps. This is so large that post-processing techniques are needed. 3-2-2 Techniques to Reduce Nonlinearity The loop capacitor is connected to the output of the charge pump. When the voltage on the capacitor accumulates, the voltage of the charge pump’s output port also variates. The charge and discharge currents are not totally independent of the output voltage. That is how the charge pump nonlinearity develops. One way to alleviate the nonlinear effect is to reduce the voltage variation on the capacitor. Figure 3-6 shows the transient output voltage when output voltage variation is at the order of 200 mV. When the output voltage is around 325 mV, the charge current is larger. At one operation period, the voltage increases by 19.9 mV. When the output voltage increases around 500 mV, |Vds | of the PMOS controlling charging is smaller. Then the charge current is smaller. At one operation period, only 10.7 mV is added on the capacitor voltage. To reduce the charge pump output voltage variation, capacitor value is ten times large as it used to be, which limits the voltage variation to the order of 20 mV. Charge pump is much linear now, as shown in Figure 3-7. Another method to reduce the capacitor voltage variation is to increase the input signal’s frequency. Then FREF1 and FREF2 frequencies are increased. Each cycle, the pulse width of those two signal is smaller. Less current flows in or out of the capacitor. As a result, the voltage variation is smaller, at the cost of reducing measurement range. Peng Chen CONFIDENTIAL Master of Science Thesis CONFIDENTIAL pin pin pin pin pin CP_OFF2 pin UPP UPN DWP Charge Pump DWN ICP COUNTER_OUT<31: 0> RST DTC_ctrl_code<5:0> CP_OFF1 CP_OFF2 CP_ENB counter_uplimit<5:0> DTC_select frefdlyout_en counter_out_en counter_start<31:0> CP_OFF1 FREF2 VDD_CP pin GND_CP CP_ENB Iout RST FREF FREF3 FREF1 Q FREF2 1 0 ctrl DTC_ctrl Frefdlyout_en counter clk Q D FREF FREF1 FREF2 FREF3 counter_uplimit<5:0> counter_start<31:0> counter_out_en Vref clock_gen rst clock_in RST RST FREF REF EKK<0:64> EN<0:63> COUNTER_OUT<31:0> EN<0:63> DTC_select EKK<0:64> I REF pin EKK<0:64> EN<0:63> EKK<0:64> EN<0:63> DTC_ctrl DTC_select RST code<5:0> DTC5_main VDD pin GND BD_DTC VDD Master of Science Thesis GND pin REF_DLY2 1 0 ctrl DTC_select REF_DLY 1 FREF1 frefdlyout_en pin 3-2 Noise and Nonlinearity Analysis 39 Figure 3-2: Implementation Details of Top Level Architecture. Peng Chen SPI 40 Test Circuit Design for Built-in DTC Measurement Vosi Vosq Xi Wi Z-1 Q Yi α Figure 3-3: Z domain analysis. Comparison of Capacitor voltage with/witout Vosq 0.56 without Vosq with Vosq 0.54 Voltage on Capacitor (V) 0.52 0.5 0.48 0.46 0.44 0.42 0 0.5 1 1.5 2 2.5 3 3.5 time (s) −6 x 10 Figure 3-4: Comparison of Capacitor’s voltage with/without comparator’s offset. −11 5 error versus DTC delay (nonlinearity=0.05) x 10 4.5 4 nonlinearity error (s) 3.5 3 2.5 2 1.5 1 0.5 0 0 0.2 0.4 0.6 0.8 1 1.2 DTC delay (s) 1.4 1.6 1.8 2 −9 x 10 Figure 3-5: Error caused by charge pump’s nonlinearity. Peng Chen CONFIDENTIAL Master of Science Thesis 3-2 Noise and Nonlinearity Analysis 41 525 10.7mv capacitor voltage (mv) 500 475 450 425 400 375 350 19.9mv 325 100 200 300 400 500 600 700 time (ns) Figure 3-6: Capacitor voltage variation is at the order of 200 mV. 1.59 mv capacitor voltage (mv) 500 497.5 495 492.5 490 487.5 485 482.5 1.7 mV time (ns) 480 100 200 300 400 500 600 700 800 900 Figure 3-7: Capacitor voltage variation is at the order of 20 mV. Master of Science Thesis CONFIDENTIAL Peng Chen 42 Peng Chen Test Circuit Design for Built-in DTC Measurement CONFIDENTIAL Master of Science Thesis Chapter 4 Top Level Implementation Abstract The implementation details go in this chapter. Several important blocks: DTC, charge pump and RTL are described. 4-1 Digital to Time Converter (DTC) The DTC used in this chapter is shown in Figure 4-1. Self-loaded buffer is the main component. The input signal is distributed over 64 selection inverters. Unit cell of the DTC is made up two parts: the selection set and output-enabled buffer. The schematic of one unit cell is shown in Figure 4-2. M5,M6 and M7 form a transmission-gate-based logic AND. Compared with the typical logic AND made up of 4 MOSs, this one consumes less power but introduces larger phase noise. In low power application, transmission-gate-based logic AND is preferred. What’s more, in this DTC architecture, every time only one selection set is chosen, resulting in a non-accumulative phase noise generated from logic AND. M8 and M9 acts as an inverter when this stage’s selection set is chosen. Otherwise, the output port of the selection set has a high impedance. This inverter and the logic AND forms the selection set. For the output-enabled buffer, M10 and M14 are enabled by the digital input code. When the input signal goes through this buffer, "EN" is zero, vice versa. M13 and M17 are controlled by the input signal, to save power. After the first inverter in the selection set, the signal’s rising edge becomes a falling edge. For those buffers, it is the falling edge that matters. Therefore M10, M11, M16 and M17 have a relatively large size, to decrease the delay time of the falling edge. Master of Science Thesis CONFIDENTIAL Peng Chen 44 Top Level Implementation Figure 4-1: Top view of tri-state buffer-self-loaded DTC. Figure 4-2: Circuit of DTC unit cell. Mismatch between the unit delay cells are very important for the linearity performance. In the new application, DTC’s resolution is 41 ps. To keep the mismatch still at a low level, the specification is defined to be smaller 1 ps. DNL and INL represents DTC’s nonlinearity. The post-layout simulation results of the old DTC is shown in Figure 4-3. Before going on, it should be mentioned that three different bond-wire models are used to simulate the DNL/INL of the old DTC. It is found that different bond-wire models only make a difference at the schematic level simulation. In post-layout simulation, the differences are little. It can be concluded that the capacitance from the DTC itself is much larger than in the schematic model, making it nonsensitive to the bond-wires. From the above figure, it can be seen that the there is a pulse in the middle of the INL curve. This introduces periodic pattern to the phase error in ADPLL system, causing fractional spur. This pulse is found to be caused by the folding in the layout. The new design puts all 64 stages of delay in one line and puts decoupling capacitors around the DTC. Thus the inner Peng Chen CONFIDENTIAL Master of Science Thesis 4-1 Digital to Time Converter (DTC) 45 DNL/INL of the old DTC 0.4 DNL 0.3 DNL (LSB) 0.2 0.1 0 −0.1 −0.2 −0.3 0 10 20 30 40 DTC resolution: 20.7847 ps 50 60 70 0.3 INL INL (LSB) 0.2 0.1 0 −0.1 0 10 20 30 40 DTC input code 50 60 70 Figure 4-3: DNL/INL of the old DTC. voltage drop of each stage is overcome. The new DTC’s nonlinearity information is shown in Figure 4-4. DNL/INL of the new DTC 0.02 DNL DNL (LSB) 0.015 0.01 0.005 0 −0.005 −0.01 0 10 20 30 40 DTC resolution: 39.6 ps 50 60 70 0.14 INL 0.12 INL (LSB) 0.1 0.08 0.06 0.04 0.02 0 0 10 20 30 40 DTC input code 50 60 70 Figure 4-4: DNL/INL of the new DTC. Table 4-1: Monte-Carlo simulation results. name σnew (ps) meannew (ps) σold (ps) meanold (ps) t1 3.77 50.9 5.17 68.7 t2 2.66 39.2 2.45 31.4 t3 2.74 39.6 1.12 19.7 t4 2.76 39.6 1.28 19.5 t5 2.87 39.6 1.11 19.4 t6 2.75 39.6 1.14 19.5 t7 2.70 39.5 1.26 19.5 Table 4-1 shows the MC (Monte-Carlo) simulation results of the two DTCs. The second and fourth lines represent the standard deviations of the delays. The third and fifth lines represent Master of Science Thesis CONFIDENTIAL Peng Chen 46 Top Level Implementation the average time of the delays. To quantitatively describe the mismatch of each delay, a DTC mismatch factor based on the MC simulation results is defined. kmc = σ t¯ (4-1) t¯ represents the mean value of the delay. Take t7 for example. For the new DTC, kmc = 6.84%. While for the old DTC, kmc = 6.46%. Indeed the new DTC seems do not have a better mismatch characteristic. But t1 and t2 are closer to the rest values. At the same time, the layout is more balanced in the new Design. The power of the new DTC is 30.81 µW. 4-2 Charge Pump In wireless applications, charge pump in one essential part of the charge pump based analog PLLs, which are widely used because it has the advantage of wide capture range and no systematic phase offset. Single-ended charge pump is commonly seen in analog PLLs. Traditionally, CMOS charge pump makes use of MOS switches. But due to its non-ideal behavior, charge injection and clock feedthrough for example, some error components are generated. Thus current steering technique is used because of its fast switching speed and low charge injection error. Along with positive feedback and current reuse, [24] uses current steering achieving a faster switching speed and low power consumption. But it has an undesirable hysteresis effect which swallows narrow input pulses. In [25], a novel charge pump is proposed to eliminate high frequency glitches at the price of decreasing the operational frequency. In [26], wide-swing current mirrors is used in the charge pump to stable the output current when the output voltage is not near the rails. Figure 4-5: Circuit of Charge Pump. Figure 4-5 is the circuit implementation of single-ended charge pump used in the tape out. Current flows into M1. M2∼M5 are current mirrors. M13∼M16 provide controllable offset Peng Chen CONFIDENTIAL Master of Science Thesis 4-2 Charge Pump 47 currents. M6 and M7 are input ports of the charging currents. M8 and M9 are the input ports of the discharging currents. M11 and M12 can be taken as resistors. They, the diode connected transistors, are used to bias both output branches of the charge pump to a similar voltage. Thus, an amplifier is replaced. This charge pump is originally used in a wide-range low-power fractional-N PLL [27]. It is a current steering topology, having a better supply rejection than the current switching topology [27, 28]. M13 M16, providing adjustable offset current is used to improve the phase to current linearity and shift away the dead-zone in that article. Now in this chapter, both charging and discharging are enabled. Therefore there is no need to enable this adjustable offset current. During the charging or discharging, the charge pump acts as a current source. One way to measure the performance of the current source is to measure the output impedance. Theoretically, the output impedance of an ideal current source is infinite, since its current does not change as the output voltage. Rout = ∆V /∆I = ∞. However because of the channel length modulation, the current from the charge pump changes a bit as the output voltage. This nonideal effect is one key limitation of this system performance. In the following, theoretically calculation and simulation results of the output resistance are shown. Take the charging process for example. M7 and M8 are enabled while M6 and M9 are not. To simplify the calculation, M6 and M9 have the infinite impedance. In the offset compensation current paths, M15 and M16 are not enabled so that they are also ignored. Thus, the simplified circuit is shown in Figure 4-6. Figure 4-6: Output impedance calculation of Charge Pump. Actually, UPP is set to zero. That is to say, M3 is in triode region. Considering the output voltage stables at 500 mV and the absolute value of the threshold voltage is more than 400 mV, M3 is still taken as in saturation region for simplicity. Assuming the intrinsic output impedance of M2 is Rc and M3 is Ro , from [29], the output impedance can be written as Rout = (1 + gm7 Ro )Rc + Ro ≈ 600KΩ Master of Science Thesis CONFIDENTIAL (4-2) (4-3) Peng Chen 48 Top Level Implementation It should be mentioned that since the capacitances are not taken into consideration, the output impedance calculated here is only applied to the low frequencies. As shown in Figure 4-6 is the simulated output impedance during charging, varying as the operation frequency. When simulating the output impedance, an AC voltage source is applied on the output port. Measure the output current, which divides AC voltage amplitude to get the results shown in Figure 4-7. 5 7 Output impedance during charging x 10 Rout at low frequencies is 680 KΩ Rout at 32 MHz is 90 KΩ 6 Output Impedance (Ω) 5 4 3 2 1 0 3 10 4 10 5 10 6 7 8 10 10 10 Operation Frequency (Hz) 9 10 10 10 11 10 Figure 4-7: Output impedance of Charge Pump during charging. At low frequencies, the simulated result and the theoretical value is at the same order, which proves the simple model to calculate the output resistance is useful. When operating at 32 MHz, the output impedance drops to 90 KΩ, which is due to the large sizes of the MOSs. Figure 4-8 shows the output resistance during the discharging process. The resistance at 32 MHz is 24 KΩ. 5 6 Output impedance during discharging x 10 5 Output Impedance (Ω) 4 3 2 Rout at low frequencies is 560 KΩ Rout at 32 MHz is 24 KΩ 1 0 3 10 4 10 5 10 6 7 8 10 10 10 Operation Frequency (Hz) 9 10 10 10 11 10 Figure 4-8: Output impedance of Charge Pump during discharging. The output resistances are not high enough at 32 MHz. If higher values are wanted, the operation frequency should be lower. Then the charging or discharging time is relatively Peng Chen CONFIDENTIAL Master of Science Thesis 4-2 Charge Pump 49 longer. To keep the same output voltage swing of the charge pump, larger load capacitor is desired. This is what can be improved in future design, where adjustable load capacitor is implemented. Come back to this tape out, a fixed load capacitor, the value of which is 10 pF, is chosen. The operating frequency is 32 MHz. To illustrate the output current variation upon the output voltage, Figure 4-9 shows this relationship. −5 5 Output current variation upon output voltage x 10 4.8 4.6 Output Current (A) 4.4 4.2 4 At 0.45 V, charging 49.14 uA, discharging 48.95 uA At 0.55 V, charging 48.99 uA, discharging 49.14 uA 3.8 3.6 3.4 3.2 3 0.1 0.2 0.3 0.4 0.5 0.6 Output Voltage (V) 0.7 0.8 0.9 Figure 4-9: Output current variation upon output voltage. To quantitatively define the current variation, a mismatch factor is defined as kmm = |I550mV − I450mV | I500mV (4-4) in which I500 mV = 49.08 uA. From the simulation result, the output voltage variation ranges from 470 mV to 510 mV. Taking margin and simplicity into account, 450 mV and 550 mV is chosen to be the upper and lower limits respectively. For charging process, the mismatch factor is kmm = 0.0031. While for discharging process, the mismatch factor is kmm = 0.0039. To further model the output current variation, assume that the charging current is Iup and the discharging current is Idown ; charging time during one operation cycle is tup while the discharging time is tdown . The load capacitor has a value of C. During one cycle, the increased voltage on it is ∆V = Iup tup − Idown tdown C (4-5) At a certain output voltage, define Iup = Idown + Idif f , where Idif f is the current difference between charging and discharging. tup = T /4 = 1/4f = 1/(4 ∗ 32 M Hz) = 7.8125 ns. Assuming DTC delay is tdtc , tdown has two possible values: T /4 − tdtc and T /2 − tdtc . Take Master of Science Thesis CONFIDENTIAL Peng Chen 50 Top Level Implementation T /4 − tdtc for example in the following analysis. ∆V (Idown + Idif f )T /4 − Idown (T /4 − tdtc ) C Idif f T + 4Idown tdtc 4C Idif f T + 4Idown (tdtc0 + tdtc1 ) 4C Idif f T Idown (tdtc0 + tdtc1 + ) C 4Idown = = = = (4-6) (4-7) (4-8) (4-9) In the above equations, tdtc0 refers to the offset of DTC while tdtc1 refers to the digitally controlled part of DTC. At different voltages, Idif f is different. The DC component from Idif f is folded into tdtc0 . Thus it does not deteriorate the linearity measurement of DTC. Thus, assume Idif f does not have DC component. The mismatch factor is so small that the following approximation is valid Idown ≈ I500 mV (4-10) DTC measurement systematic error can be written as Idif f T 4Idown kmm I500mV T ≤ 4Idown kmm T ≈ 4 = 7.6 ps (when kmm equals 0.0039) edtc = (4-11) (4-12) (4-13) (4-14) This error is very large, resulting in a bad design. Actually, charging and discharging should not be enabled at the same time. It can be improved by making a small modification in the digital part. In that case, the relative error’s upper limit is kmm , which is smaller than 1%. From the simulation results shown above, there are mainly two non-ideal effects. One is the mismatch between charging and discharging currents. Another is the output current variation over the output voltage. As explained in the systematic analysis, the latter dominates the non-ideal factors. In general, fully differential charge pump is preferred over the conventional single-ended charge pump because of two main advantages listed below. Firstly, the charging and discharging currents’ mismatch is reduced, because matching requirement between NMOS transistors and PMOS transistors are relaxed to the matching between NMOS or PMOS transistors respectively. Secondly, the differential topology doubles the range of the output voltage compliance compared to the single-ended charge pump. This suppresses the output current variation dependent on the output voltage. What’s more, a fully differential charge pump has the advantages of the immunity to common-mode noise and power supply variation. Even though the fully differential architecture is so attractive, but right now it is not adopted because of its complex design. To validate the time domain first-order sigma-delta concept is the first option at this stage. But in future work, to give a better performance, differential Peng Chen CONFIDENTIAL Master of Science Thesis 4-3 Comparator 51 charge pump should be designed. In the following, more studies about differential charge pump are described. Paper [23] gives a simplified typical fully differential charge pump schematic, with common mode feedback. Paper [30] proposed another charge pump with two identical output paths for charging and discharging the load. One variation suppression circuit is proposed in [31]. To suppress the current variation dependent on the output voltage, the variation suppression circuit can dynamically adjust the bias voltages to adjust the charge pump bias current. When the output voltage is higher than the common-mode level, the compensation circuit stay off. When the output voltage goes low enough, compensation circuit injects current into the bias current for the charge pump. 4-3 Comparator The comparator is a widely-used electronic component. It can be used to detect whether a signal is greater or smaller than zero, or to compare the value of one signal with another. The output of an ideal comparator is a logic level (’1’ or ’0’ level) that depends on the instantaneous polarity of its differential input voltage. A practical comparator needs to have a sufficiently large differential input signal (’overdrive’) to produce a proper logic level, and moreover, it requires finite time to do so. Traditionally there are two main classes of comparators, continuous-time comparators and discrete-time comparators. The first kind of comparator is to use an open-loop opamp (without frequency compensation). Accompanied by auto-zeroing and multi-stage design, it can achieve very low input offset. However, the output of the opamp has to slew a large amount of output voltage and will settle slowly, thus resulting in a slow response time. This is the main drawback of the open loop opamp. The comparators realized in the other way are called latched comparators. One popular topology consists of two stages, preamplification followed by a track and latch stage. The preamplifier is used to mitigate kickback and reduce the requirements placed upon the latch stage. The comparator in this chapter is reused from [32]. Figure 4-10: Circuit of Comparator. Figure 4-10 shows the circuit of the comparator. This is a typical two-stage architecture. Master of Science Thesis CONFIDENTIAL Peng Chen 52 Top Level Implementation The first stage is a pre-amplifier, consisting of M1 M5. The second stage is a latch. To get a better isolation of the noise from the previous component, the comparator acts once per period. C1 C4 are used to enhance its phase noise performance. The input-referred noise is around 1 LSB in 12 bit mode, which is around 0.25 mV when the supply voltage is 1 V. This can be validated through the simulation. In the simulation setup, the sampling clock frequency is selected to be 32 MHz. It is got that the output referred noise is 791 mV and the comparator’s gain during transition is 2836. The input referred noise mV is calculated as Vn,in = 791 = 0.28 mV . The noise is mainly from the input pair M1 2836 and M2. The thermal noise of the input pair’s contribution to the input referred noise is 2 Vid,M 1 = 4KT γ/gm . The transconductance of the input pair should be very large, resulting in a large width of M1 and M2. The large width can also help reduce the flick noise of the input pair. The noise contribution of the comparator is listed in Table 4-2. The results listed in the table are the input referred noise voltages. Table 4-2: Integrated noise summary (in V) of the comparator. Device M2 M1 M2 M1 M10 M11 Param thermal noise thermal noise flicker noise flicker noise flicker noise flicker noise Noise Contribution (V) 2.1m 2.1m 92u 92u 36u 36u of Total (%) 39.58 39.33 7.67 7.63 1.18 1.17 Assuming the input-referred noise is Gaussian distributed, the standard deviation is 0.28 mV. Add this noise into the system model to figure out its effect on the system measurement accuracy. Figure 4-11 shows the absolute error versus different delays. When DTC delay is very small, the error is very large, reaching 14 ps. However, DTC has at least 200 ps offset. This region is avoided. Normally, 0.28 mV brings error no more than 2 ps. This simulation result is got when the operation cycle is 220 . If the counter counts more cycles, then this error can be reduced further. It is found that this noise is not a limiting factor of the whole system. The input noise is small enough to be acceptable. 4-4 RTL flow RTL logic is shown in the red parts in Figure 4-12. There are mainly four sub-parts. One is the clock generation block, shown in A. Another is DTC control signal translation block, shown in B. The third part, shown in C, consists a counter, a DFF, a switch of FREF1 and FREF2, a switch of two DTCs. The fourth part shown in D consists other blocks, which are complementary. Part A generates several signals of difference frequencies and phases used in other blocks in the system. The input signal, clock_in, is a high frequency signal. Its frequency can be Peng Chen CONFIDENTIAL Master of Science Thesis 4-4 RTL flow 53 −12 2 error versus delay time due to comparator noise x 10 0 −2 −4 error (s) −6 −8 −10 −12 −14 −16 0 0.5 1 1.5 DTC delay (s) 2 2.5 3 −9 x 10 Figure 4-11: Comparator noise’s influence on resolution. pin FREF DTC_ctrl pin pin RST DTC_ctrl EKK<0:64> EN<0:63> COUNTER_OUT<31:0> VDD I REF EKK<0:64> EN<0:63> Q rst FREF counter_uplimit<5:0> counter_start<31:0> counter_out_en BD_DTC FREF1 REF_DLY2 GND REF EKK<0:64> EN<0:63> pin 1 0 VDD DTC_select clk Q frefdlyout_en ctrl pin EKK<0:64> EN<0:63> REF_DLY 1 GND Vref FREF3 DTC5_main DTC_select DTC_select RST SPI pin RST DTC_ctrl_code<5:0> CP_OFF1 CP_OFF2 CP_ENB counter_uplimit<5:0> DTC_select frefdlyout_en counter_out_en counter_start<31:0> 1 0 ctrl FREF2 Iout Frefdlyout_en CP_ENB FREF1 D pin code<5:0> pin GND_CP VDD_CP CP_OFF2 CP_OFF1 UPP UPN DWP Charge Pump DWN ICP pin FREF FREF1 FREF2 FREF3 clock_gen pin pin FREF2 clock_in RST counter COUNTER_OUT<31:0> RST Figure 4-12: RTL part of the Sigma-Delta TDC. any value among the order of megahertz. Specially, take 128 MHz for example. The results are shown in Figure 4-13. Actually, FREF and FREF1 are the same. The reason to differ them is that FREF is used to synchronize the system while FREF1 is used as a signal with a fixed pulse width. It can be 50% duty cycle or other values. FREF2 is a 32 MHz signal with 25% duty cycle. FREF3 is similar with FREF2 except the initial phase difference. The comparator is clocked by FERF/FREF1, When the value is low, the comparator is enabled and the result is fed into the flip flop. After a certain time when the comparator result is stable, FREF3’s rising edge enables the flip flop and takes the comparator result. DTC control signal translation part translate the six bits DTC control code to the thermomeMaster of Science Thesis CONFIDENTIAL Peng Chen 54 Top Level Implementation clock_in 1 0 −1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 −7 x 10 FREF1 1 0 −1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 −7 x 10 FREF2 1 0 −1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 −7 x 10 FREF3 1 0 −1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 −7 x 10 Figure 4-13: internal clocks generated by clock generation block. ter format. It is synthesized by FREF, which is a 32M Hz square wave with duty cycle of 50%. EKK controls from which stage FREF goes into. EN controls the open condition of the buffers in each stage. The counter in the third part counts how many "1" appear from the output of the comparator. Before the "1" enters into the counter, a flip flop is used to sample the comparator output, to stable the signal. When Frefdlyout_en is low, the value in the counter is not read out and reset to zero. That is to say, the loop is working and counting up. The comparator output selects whether FREF1 or FREF2 to be fed into the DTC. If the output is "1", which means the capacitor voltage is larger than the reference voltage of 500 mV, the charge pump should discharge some currents in the next cycle. At the input ports of the charge pump, DWP should have a larger duty cycle. Thus FREF1 is chosen, vice versa. Here there are two DTCs to be measured. Thus the selection procedure is made into the RTL part. In the fourth part, the output of the DTC which is being measured is chosen in the feedback path. From the working principle of this kind of DTC, the falling edge of the output signal is synchronized with the input signal. However, there is a 200 ps delay offset. To synchronize the falling edge as the ideal case, a logic AND is added. 4-5 Other Blocks Controllable voltage divider is used to give the reference voltage for the comparator. In this tape-out, the reference voltage is chosen to be 500 mV. Since this voltage divider is made up of several resistors in serials, its PSRR performance is very bad. To filter output the high frequencies components from the supply voltage, a decoupling capacitor is added at the output of the voltage divider. Peng Chen CONFIDENTIAL Master of Science Thesis 4-5 Other Blocks 55 The clock_in signal is desired to be a square wave. However, to overcome the possible limitations from the lab, the chip should also work if only sinusoid wave is provided. Thus, a circuit on chip to transfer the sinusoid wave to square wave should be designed. For differential input signals, to transfer a sinusoid signal to a square wave signal, a differential opamp is preferred. For single ended signal, we can use a self biased inverter. The schematic is shown in Figure 4-14. Figure 4-14: Self biased inverter. To optimize the phase noise of this self biased inverter, very large sizes of the MOSs are chosen, at the expense of power consumption. Four inverters-based buffer is after this self biased inverter. This buffer is meant to enhance the driving ability, considering the input capacitance of the DTC is very large. DTC’s out of band phase noise also has an influence on the system’s performance. Thus, Figure 4-15 shows the phase noise from DTC along with the IO buffer and self biased inverter. Phase noise −136 −138 −140 −142 dBc/Hz −144 −146 −148 −150 −152 −154 −156 3 10 4 10 5 6 10 10 Relative frequency (Hz) 7 10 8 10 Figure 4-15: Phase noise of DTC. The phase noise at 100 KHz is -150.50 dBc/Hz, which is much better than the value mentioned Master of Science Thesis CONFIDENTIAL Peng Chen 56 Top Level Implementation in the previous chip, the value of which is -138.8 dBc/Hz. It is found that the new DTC indeed has better phase noise, even though the 12 dB improvement is mainly due to the IO buffer. Another component is the ESD protection circuit. ESD (Electrostatic discharge) is the sudden flow of the electricity between two electrically charged objects caused by contact, an electrical short, or dielectric breakdown. [33]. Emerging as a damaging effect in the integrated circuits, it usually lies in the interface between IC and the external world. Some circuit components are more easily damaged by discharges occurring within automated equipment. Others may be more readily damaged when handled by personnel. To characterize and classify the sensitivity of components to ESD, two primary models of ESD events are usually used, which can reproduce over 99% of all ESD field failure signatures. [34] One is human body model (HBM) which represents the discharge from the fingertip to the device. It is modeled by a 100 pF capacitor, a switching component and a 1.5 KΩ connected in serial. The voltage on the capacitor varies according to the environment and the individual condition. Another is the charged device model (CDM) where the discharge occurs from one device to another low potential object. In the test procedure, the device is placed on the field plate with its lead pointing up. Then it is charged and discharged to check whether the device is damaged. [35] introduces several on-chip ESD protection designs with very low parasitic capacitance, mainly for RF applications. In [36] a 2.5 KV HBM ESD robustness design is described for the 40 Gb/b application. In this chapter, the operation frequency is sub-GHz. So one simple ESD protection circuit is adopted from [29] as shown in Figure 4-16. Figure 4-16: Simple ESD protection circuit. With HBM model, the circuit can stand 2 KV at a peak current of 1.2 A flowing through the diodes. 4-6 Top Level Connection The top level connection of the layout is shown in Figure 4-17. It is fabricated with TSMC 40 nm technology. Except DTC, Charge pump and the comparator are two main analog Peng Chen CONFIDENTIAL Master of Science Thesis 4-6 Top Level Connection 57 blocks. Master of Science Thesis CONFIDENTIAL Peng Chen Top Level Implementation new DTC SPI Charge Pump RTL Old DTC Comparator 58 Figure 4-17: Top Level Layout of the Chip. Peng Chen CONFIDENTIAL Master of Science Thesis Chapter 5 Measurements This chapter describes the test PCB, measurement setup, measurement results, post-processing and finishes with a comparison of the results. 5-1 5-1-1 Measurement Setup Test PCB The test Printed Circuit Board (PCB) is given in Figure 5-1 below. The input current is generated with the help of the variable resistor. It connects to a NMOS current mirror. From the variable resistor, looking into the current mirror, the input impedance is 117 KΩ when the input current is 5 uA. To let the current be as low as 2.5 uA, the tunable resistor value is chosen to be 250 KΩ. "sn74avc4t245" and "sn74avc2t244" are chosen to level shift the voltage from 1.0 V to 3.3 V or vice versa. "TPS76201" is used to shift the voltage from 5.0 V to 3.3 V. SPI signals communicate with the computer by "teensy". "NL17SV16XV5T2" is a buffer to decrease the jitter. The input capacitance is only 2 pF, whose small value is the reason that it is chosen. 5-1-2 Measurement Setup The measurement setup is given in Figure 5-2. The signal generator provides a high frequency with low noise. If noise performance permitted, the higher the frequency, the smaller voltage swing on the capacitor after charge pump. Then the linearity will be better. There are two different ways to measure the DTC transfer function. One way is directly measuring DTC input signal and output signal and comparing the rising edge phase difference or duty cycle variance. Another way is to use the time-domain sigma-delta TDC. The output is connected to the PC by SPI. Power Supplier gives a voltage of 5 V. Master of Science Thesis CONFIDENTIAL Peng Chen 60 Measurements clock_in LDO chip FREF out Voltage Supply Teensy Figure 5-1: PCB Board. Python in PC Signal generator teensy Oscilloscope chip PCB Supply Figure 5-2: Measurement Setup. 5-2 5-2-1 Measurement Results Duty-cycle Measurement The are two ways to measure DTC transfer function off chip. One way is the direct measurement. Another is the duty-cycle measurement. Direct measurement means put a reference signal at the input port and let the DTC output be observed by the oscilloscope. By comparing the rising edges of the input signal and the output signal, DTC’s transfer function can be calculated. Duty-cycle measurement is to get the information from the duty cycle of the output signal, rather than comparing the rising edges. Those two methods are straightPeng Chen CONFIDENTIAL Master of Science Thesis 5-2 Measurement Results 61 forward and easy to operate. However, since the reference signal goes through DTC output buffer and the off-chip buffer, the supply voltage noise is very likely to be coupled into the signal. At the same time, the switches of the reference signal also influences the supply voltage. The on-chip output buffer shares the supply voltage with the DTC, whose performance is worsened. Thirdly, the on-chip buffer need to be very large to drive the off-chip buffer, whose input capacitance is very large. If not designed properly, the switching takes a long time, making the output signal very sensitive to the supply voltage variation. It should be mentioned that duty-cycle measurement is based on the architecture of this DTC. The falling edge of the output signal is synchronized with the input signal. Thus the longer the delay is, the smaller the duty cycle of the output signal will be. Let td denotes the delay time of the DTC; Du denotes the duty cycle of the output signal; Tr denotes the input reference signal’s period, then at two timestamps, td1 − td2 = (Du1 − Du2 ) ∗ Tr (5-1) Generally, we do not care about the constant offset in DTC. Therefore, there is no need to guarantee the input signal duty cycle to be 50%. Not considering the delay offset, the DTC delay can be written as td (k) = (Du (1) − Du (k)) ∗ Tr (5-2) Figure 5-3 shows the duty cycle and its corresponding delay of the previous DTC in board 1. Every four points, one measurement is done. That is due to the limitation of the equipment. To guarantee 1 ps accuracy, 1 THz sampling frequency is required by the oscilloscope, which is impossible for the current equipment in the lab. Actually, the sampling frequency of the oscilloscope is only 4 GHz. To model DTC delay, it can be written as td (k) = tconstant + k∆ + nonlinearity = tconstant + k∆ + IN L(k)∆ (5-3) (5-4) where ∆ is DTC resolution. The nonlinearity repeats every Tr /F CWf rac period. When all stages of DTC are used, then the nonlinearity is shown in the first figure in Figure 5-4. Do fft of this nonlinearity. The level of the first frequency determines the first fractional spur’s level. It is -21.09 dBc. The previous DTC is used in 2.4 GHz wireless transmission application. DCO output is divided by 2. Thus, the digital phase detection part works at a period of 833.3 ps. DTC resolution is 27 ps and only the first 30∼31 stages are used. In practical, only the first 30∼31 stages’ nonlinearity matters. Redo the fft of those stages and the result is shown in the second picture of Figure 5-4. The spur level is -20.75 dBc. It is the same for the new DTC, whose results are shown in Figure 5-5 and Figure 5-6. Do fft of the whole stages, resulting in a fractional spur level of -25.83 dBc. Do fft of the stages that are used, resulting in a fractional spur level of -36.90 dBc. The measurement results for board 2, the second board, are shown in Figure 5-7, Figure 5-8, Figure 5-9 and Figure 5-5 respectively. It can be found that compared with the whole stages’ nonlinearity, part of the stages’ nonlinearity can result in both a larger fractional spur and a smaller fractional spur. The absolute nonlinearity of the new DTC is better than the previous DTC. Considering new DTC is used in 900 MHz application. Tckv is roughly doubled. Thus, the fractional spur level will be 6 dB smaller in additional. Master of Science Thesis CONFIDENTIAL Peng Chen Measurements Duty cycle of FREFdly (%) 62 Duty Cycle Versus DTC Control Code (Old DTC) 32 30 28 26 0 10 20 30 40 50 DTC control code Delay Versus DTC Control Code (Old DTC) 60 Delay (ps) 2000 1000 0 0 10 20 30 40 DTC control code 50 60 Figure 5-3: Measured Duty Cycle and Delay versus DTC Control Code for "Old" DTC (Board 1). Old DTC Resolution: 27.12 ps; Spur Level: −15.07 dBc INL (ps) 50 0 −50 0 20 30 40 50 60 DTC control code Old DTC Resolution: 25.99 ps; Spur Level: −14.73 dBc (in practical) 50 INL (ps) 10 0 −50 0 5 10 15 20 DTC control code 25 30 Figure 5-4: Measured "Old" DTC INL (ps) using duty-cycle method (Board 1). 5-2-2 Sigma-Delta Measurement Sigma-Delta measurement is to use the first-order sigma-delta TDC to measure DTC’s transfer function. This is totally an on-chip measurement. The measurement results are stored in the registers. After measurement, the results can be output to the computer through SPI without interfering the measurement process. The on-chip measurement avoids the off-chip noise and the supply noise injection through the output buffers. Figure 5-11 (a) shows the DTC delay versus DTC control code. The red line denotes the previous DTC while the black line denotes the new DTC. It is obvious that the DNL of the new DTC is much better because the transfer function is much smoother. However, the fractional spur level relates with the INL. Thus Figure 5-11 (b) shows this kind of nonlinearity. The y-axis is the INL multiplying each DTC’s resolution. The INL variation is smaller for the new DTC from a general view of that figure. Peng Chen CONFIDENTIAL Master of Science Thesis 63 Duty cycle of FREFdly (%) 5-2 Measurement Results Duty Cycle Versus DTC Control Code (New DTC) 35 30 25 20 0 10 20 30 40 50 DTC control code Delay Versus DTC Control Code (New DTC) 60 Delay (ps) 3000 2000 1000 0 0 10 20 30 40 DTC control code 50 60 Figure 5-5: Measured Duty Cycle and Delay versus DTC Control Code for new DTC (Board 1). New DTC Resolution: 42.61 ps; Spur Level: −19.81 dBc INL (ps) 100 50 0 −50 0 20 30 40 50 60 DTC control code New DTC Resolution: 46.03 ps; Spur Level: −28.88 dBc (in practical) 20 INL (ps) 10 0 −20 0 5 10 15 DTC control code 20 25 Figure 5-6: Measured new DTC INL (ps) using duty-cycle method (Board 1). To quantitatively define the nonlinearity performance, do fft of the first stages’ nonlinearity that are used in practical. The results are shown in Figure 5-12. The fractional spur level caused by the new DTC in 0.9 GHz application should be 13.25 dB smaller than the previous one in 2.4 GHz application, even though among which 8.52 dB is due to the new application. The same analysis is also applied to board 2 and board 3. The results are shown in Figure 5-13, Figure 5-14, Figure 5-15 and Figure 5-16. At last, comparisons of the INL (ps) and DNL (ps) for the three boards are done. Each figure shows three boards’ results of one DTC. As Figure 5-17 shows, the INL (ps) of the same DTC has a common pattern. This pattern is largely due to the charge pump nonlinearity. A small portion of this patten is caused by the DTC nonlinearity. Right now, how large percent the charge pump nonlinearity dominates in the patten is unclear. Assuming that the DTC INLs are uncorrelated, the DTC nonlinearity will not contribute to the same pattern in its INL. Use 10th order polynomial function to fit each INL. Then average them to get the final Master of Science Thesis CONFIDENTIAL Peng Chen Measurements Duty cycle of FREFdly (%) 64 Duty Cycle Versus DTC Control Code (Old DTC) 30 28 26 24 0 10 20 30 40 50 DTC control code Delay Versus DTC Control Code (Old DTC) 60 Delay (ps) 1500 1000 500 0 0 10 20 30 40 DTC control code 50 60 Figure 5-7: Measured Duty Cycle and Delay versus DTC Control Code for "Old" DTC (Board 2). Old DTC Resolution: 20.45 ps; Spur Level: −20.41 dBc INL (ps) 50 0 −50 0 20 30 40 50 60 DTC control code Old DTC Resolution: 20.75 ps; Spur Level: −22.65 dBc (in practical) 50 INL (ps) 10 0 −50 0 10 20 DTC control code 30 40 Figure 5-8: Measured "Old" DTC INL (ps) using duty-cycle method (Board 2). polynomial function. This function is taken as the common pattern of the INLs. Subtract this common pattern, the new INL is shown in Figure 5-18. The new DTC is much better. Due to larger areas and proper layout, the new DTC’s DNL is much better. As shown in Figure 5-19, the data is not post-processed. 5-2-3 Post Processing for Measurement Data Back to Figure 5-11, Figure 5-13 and Figure 5-15, it can be found that there are peaks in the middle in the (INL*DTC resolution) curve. Take Figure 5-11 for example. The peak for new DTC locates at the place where DTC control word is 25. The previous DTC has a peak locating at the place where DTC control code is 33. In the left delay versus DTC control code figure, the peaks corresponding to a delay around 5000 ps. This phenomenon can be explained by the nonlinearity of the charge pump. Peng Chen CONFIDENTIAL Master of Science Thesis 65 Duty cycle of FREFdly (%) 5-2 Measurement Results Duty Cycle Versus DTC Control Code (New DTC) 30 25 20 0 10 20 30 40 50 DTC control code Delay Versus DTC Control Code (New DTC) 60 Delay (ps) 3000 2000 1000 0 0 10 20 30 40 DTC control code 50 60 Figure 5-9: Measured Duty Cycle and Delay versus DTC Control Code for new DTC (Board 2). New DTC Resolution: 34.3 ps; Spur Level: −37.1 dBc INL (ps) 50 0 −50 0 20 30 40 50 60 DTC control code New DTC Resolution: 33.65 ps; Spur Level: −33.34 dBc (in practical) 20 INL (ps) 10 0 −20 0 5 10 15 20 25 DTC control code 30 35 Figure 5-10: Measured new DTC INL (ps) using duty-cycle method (Board 2). Take a mathematical analysis. The measurement system consists of two other analog blocks: charge pump and comparator. Their non-ideal effects have been analyzed in chapter 3 and chapter 4. Among those non-ideal effects, the charging and discharging mismatch dominates. In the following model, only this effect is taken into consideration. Then the delay nonlinearity is a function of the DTC’s real delay. Let x represent DTC’s real delay; its corresponding nonlinearity due to charge pump is f (x); td represents the measurement delay; tc represents DTC’s constant offset; ∆ represents DTC’s resolution. Then td = x + f (x) x(k) = tc + k∆ + IN L(k)∆ (5-5) (5-6) where x(k) denotes the real delay when DTC control word is k. We want to extract f(x) and removes its effect. The relationship of td and k is known. If assuming two DTC’s nonlinearity is not correlated, the problem becomes solvable. The question is to find a f (x), making two INLs not related with each other. It is a problem of functional analysis. A stringent analysis Master of Science Thesis CONFIDENTIAL Peng Chen 66 Measurements Delay Versus DTC Control Code INL (ps) Versus DTC Control Code 7000 100 80 6500 new DTC Previous DTC 60 INL (ps) Delay (ps) 6000 5500 40 20 5000 0 4500 −20 new DTC Previous DTC 4000 0 10 20 30 40 DTC control code 50 60 −40 0 70 10 20 (a) Delay versus DTC Control Code 30 40 DTC control code 50 60 70 (b) INL (ps) Figure 5-11: Measured Results (Board 1) DTC Resolution: 39.47 ps; Spur Level: −30 dBc (in practical) DTC Resolution: 24.38 ps; Spur Level: −16.75 dBc (in practical) 20 40 15 30 20 10 INL (ps) INL (ps) 10 5 0 0 −10 −5 −20 −10 −15 0 −30 5 10 15 20 DTC control code 25 30 −40 0 (a) INL (ps) of New Chip 5 10 15 20 DTC control code 25 30 35 (b) INL (ps) of "Old" Chip Figure 5-12: Measured Results (Board 1) is beyond this thesis. A alternative method is to use the fitted curves. This method is only used for engineering reference. Figure 5-20 shows IN L ∗ DT Cresolution versus DTC control code before and after post processing. Before processing, a 3rd Fourier series fitting is applied on those data. The original IN L ∗ DT Cresolution curve minus the average of the two fitting curves. Then the new nonlinearity and the corresponding spur level can be got. Figure 5-21 and Figure 5-22 show the results of the second and third boards. The new DTC vibrates within a smaller range. And it is applied in a larger Tckv application. Its corresponding fractional spur is therefore smaller. Peng Chen CONFIDENTIAL Master of Science Thesis 5-2 Measurement Results 67 Delay Versus DTC Control Code INL (ps) Versus DTC Control Code 6500 100 80 6000 new DTC Previous DTC 60 40 INL (ps) Delay (ps) 5500 5000 4500 20 0 −20 new DTC Previous DTC −40 4000 −60 3500 0 10 20 30 40 DTC control code 50 60 −80 0 70 10 20 (a) Delay versus DTC Control Code 30 40 DTC control code 50 60 70 (b) INL (ps) Figure 5-13: Measured Results (Board 2) DTC Resolution: 37.51 ps; Spur Level: −27.18 dBc (in practical) DTC Resolution: 22.55 ps; Spur Level: −18.15 dBc (in practical) 30 50 25 40 20 30 20 10 INL (ps) INL (ps) 15 5 10 0 0 −10 −5 −10 −20 −15 −30 −20 0 5 10 15 20 DTC control code 25 30 −40 0 (a) INL (ps) of New Chip 5 10 15 20 25 DTC control code 30 35 40 (b) INL (ps) of the "Old" Chip Figure 5-14: Measured Results (Board 2) 5-2-4 Comparison of the Two Results The direct measurement method has a high demand on the equipment. And it needs a lot of data to average the noise. The sigma-delta TDC on-chip measurement is much less sensitive to the supply noise and the off-chip noise. It can give a very robust measurement result. Among all the boards, the nonlinearity of the new DTC has an obvious similar pattern. However, the design should be improved to self measure the sigma-delta TDC’s transfer function. Otherwise, the charge pump’s nonlinearity cannot be distinguished from DTC’s nonlinearity. Master of Science Thesis CONFIDENTIAL Peng Chen 68 Measurements Delay Versus DTC Control Code INL (ps) Versus DTC Control Code 6500 200 new DTC Previous DTC 6000 150 INL (ps) Delay (ps) 5500 5000 100 50 4500 new DTC Previous DTC 0 4000 3500 0 10 20 30 40 DTC control code 50 60 −50 0 70 10 20 (a) Delay versus DTC Control Code 30 40 DTC control code 50 60 70 (b) INL (ps) Figure 5-15: Measured Results (Board 3) DTC Resolution: 39.61 ps; Spur Level: −34.56 dBc (in practical) DTC Resolution: 24.32 ps; Spur Level: −21.62 dBc (in practical) 30 30 25 20 20 10 INL (ps) INL (ps) 15 10 5 0 −10 0 −20 −5 −10 0 5 10 15 20 DTC control code 25 30 −30 0 (a) INL (ps) of New Chip 5 10 15 20 DTC control code 25 30 35 (b) INL (ps) of the "Old" Chip Figure 5-16: Measured Results (Board 3) Peng Chen CONFIDENTIAL Master of Science Thesis 5-2 Measurement Results 69 New DTC INL (ps) Comparison of the Three Boards Old DTC INL (ps) Comparison of the Three Boards 40 60 Board 1 Board 2 Board 3 40 20 20 10 0 INL (ps) INL (ps) 30 0 −20 −10 −40 −20 −60 −30 0 10 20 30 40 DTC control code 50 60 −80 0 70 (a) INL (ps) of New Chip Board 1 Board 2 Board 3 10 20 30 40 DTC control code 50 60 70 (b) INL (ps) of the "Old" Chip Figure 5-17: Measured INL (ps) Comparison Spur Level after Fitting Process (new DTC) Spur Level after Fitting Process(Old DTC) 20 40 Spur Level for Board 1: −45.2378 dBc Spur Level for Board 2: −39.3697 dBc Spur Level for Board 3: −40.6781 dBc 10 5 0 −5 −10 −15 −20 0 Spur Level for Board 1: −23.4114 dBc Spur Level for Board 2: −24.632 dBc Spur Level for Board 3: −24.6419 dBc 30 INL after fitting process(ps) INL after fitting process(ps) 15 20 10 0 −10 −20 −30 10 20 30 40 DTC control code 50 60 70 −40 0 (a) New DTC Spur level 10 20 30 40 DTC control code 50 60 70 (b) Old DTC Spur level Figure 5-18: Spur level, based on the post-processed measurement data Master of Science Thesis CONFIDENTIAL Peng Chen 70 Measurements New DTC DNL (ps) Comparison of the Three Boards Old DTC DNL (ps) Comparison of the Three Boards 20 60 Board 1 Board 2 Board 3 10 40 20 DNL (ps) DNL (ps) 0 −10 0 −20 −20 −30 −40 −40 0 10 20 30 40 DTC control code 50 60 Board 1 Board 2 Board 3 −60 0 70 (a) DNL (ps) of New Chip 10 20 30 40 DTC control code 50 60 70 (b) DNL (ps) of the "Old" Chip Figure 5-19: Measured DNL (ps) Comparison Spur Level: −39.5 dBc (new DTC);−24.93 dBc (Previous DTC) 40 40 30 INL multiply DTC Resolution (ps) INL multiply DTC Resolution (ps) 30 20 10 0 −10 −20 20 10 0 −10 −20 −30 −40 0 10 20 30 40 50 60 DTC control code (not true for new DTC) (a) fitted curves of DTC nonlinearity 70 −30 0 10 20 30 40 50 60 DTC control code (not true for new DTC) 70 (b) Spur Level when DTC nonlinearity excluding Charge Pump nonlinearity Figure 5-20: Post-processing for Board 1 Peng Chen CONFIDENTIAL Master of Science Thesis 71 Spur Level: −40.28 dBc (new DTC);−23.55 dBc (Previous DTC) 60 40 40 30 INL multiply DTC Resolution (ps) INL multiply DTC Resolution (ps) 5-2 Measurement Results 20 0 −20 −40 −60 −80 0 20 10 0 −10 −20 −30 −40 10 20 30 40 50 60 DTC control code (not true for new DTC) (a) fitted curves of DTC nonlinearity −50 0 70 10 20 30 40 50 60 DTC control code (not true for new DTC) 70 (b) Spur Level when DTC nonlinearity excluding Charge Pump nonlinearity Figure 5-21: Post-processing for Board 2 Spur Level: −41.24 dBc (new DTC);−26.18 dBc (Previous DTC) 40 30 INL multiply DTC Resolution (ps) INL multiply DTC Resolution (ps) 30 20 10 0 −10 −20 −30 20 10 0 −10 −20 −40 −50 0 10 20 30 40 50 60 DTC control code (not true for new DTC) (a) fitted curves of DTC nonlinearity 70 −30 0 10 20 30 40 50 60 DTC control code (not true for new DTC) 70 (b) Spur Level when DTC nonlinearity excluding Charge Pump nonlinearity Figure 5-22: Post-processing for Board 3 Master of Science Thesis CONFIDENTIAL Peng Chen 72 Peng Chen Measurements CONFIDENTIAL Master of Science Thesis Chapter 6 Conclusions 6-1 Conclusions DTC-based fractional-N PLL is more power efficient than the one without DTC. The new architecture also relaxes the TDC design specification. The linearity requirement is shifted on DTC. DTC’s nonlinearity dominates the fractional spur. The complete-value LMS algorithm can correct the DTC gain. The algorithm can be improved to correct the DTC nonlinearity, such as pre-distortion. Due to the larger area, the new DTC has a much better DNL performance. INL (ps) peak to peak value is also smaller, even though not too much. In the further design, a different DTC architecture should be considered to reduce the INL variation. The "old" DTC used in the previous tape-out has a very bad performance on mismatch. It is one of the main reasons resulting in fractional spurs in the previous ADPLL tape-out. However, the new ADPLL tape-out still has a very large spur. This indicates that except from DTC nonlinearity, there are some problems in the RTL part. 6-2 Future Work Improved adaptive gain calibration algorithm is better to be implemented, to calibrate DTC nonlinearity. And the important phase information are better to be observable in the future tape-out. A different DTC architecture is desired to keep the INL small. Dithering is needed when generating DTC control code to randomize the TDC quantization noise. An extra signal is desired to be fed into the chip, to measure the first-order sigma-delta TDC’s transfer function, to exclude other analog blocks’ influence on the measurement results. Master of Science Thesis CONFIDENTIAL Peng Chen 74 Peng Chen Conclusions CONFIDENTIAL Master of Science Thesis Appendix A Fractional Spur Estimation To get an estimation of the fractional spur level mathematically, first FM (frequency modulation) should be discussed briefly. The following is divided into three parts: introducing FM, applying the results to DTC-based DPLL to estimate the fractional spur, and along with experimental validation improving the definition of the location of fractional spurs. A-1 Fractional Spur Level Theoretically Derivation In the DPLL after phase detection, the phase error, which is then filtered by and normalized, has a direct relationship with the tuning word applied on the DCO. This tuning word tunes DCO’s output frequency. Thus the periodic pattern of the phase noise can generate spurs in CKV’s spectrum. So FM is introduced. FM encodes the information in a carrier wave by varying the instantaneous frequency of wave. Assume the baseband signal is xm (t); the sinusoid carrier signal is xc (t) = Ac cos(2πfc t), in which Ac is the carrier’s amplitude and fc is the carrier’s base frequency. Then we can get, Z t y(t) = Ac cos(2πfc t + 2πK∆ xm (τ )dτ ) (A-1) 0 where K∆ is the gain from baseband signal’s amplitude to FM output signal’s frequency deviation, which is similar like voltage-to-frequency gain of a DCO. Taking a simple case into consideration, we define the baseband modulated signal as a sinusoid continuous wave: xm (t) = Am cos(2πfm t).Then, f∆ sin(2πfm t)) fm = Ac cos(2πfc t + βsin(2πfm t)) y(t) = Ac cos(2πfc t + = Ac y(f ) = Master of Science Thesis Ac 2 ∞ X (A-2) (A-3) Jn (β)cos(2π(fc + nfm )t) (A-4) [δ(f − fc − nfm ) + δ(f + fc + nfm )] (A-5) n=−∞ ∞ X n=−∞ CONFIDENTIAL Peng Chen 76 Fractional Spur Estimation where f∆ = K∆ Am represents the peak frequency deviation of the FM signal from the carrier ∆ represents the modulation index, which indicates how much the modulated frequency. β = ffm variable varies around its unmounted level. Jn (β) is n-th Bessel function of first kind. Another important thing should be mentioned is the Carson’s rule, which states that around 98 percent of the power of a frequency-modulated signal lies within a bandwidth BT = 2(∆f + fm ). In general, smaller modulation index is desired to generate smaller sidebands with smaller amplitude. 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