Transcript
DN06014/D
Design Note – DN06014/D
170 Vdc Output, Quasi-Resonant Supply Device NCP1308
Application
Input Voltage
TVs, Monitors
90 – 270 Vac
Output Power
Topology
I/O Isolation
100 W
QuasiResonant Flyback
Yes
Other Specifications Output Voltage Ripple Nominal Current Max Current Min Current
Output 1
Output 2
Output 3
Output 4
170 Vdc 400 mV max 600 mA 600 mA 0
12 Vdc 100 mV 100 ma 100 mA 10 mA
N/A N/A N/A N/A N/A
N/A N/A N/A N/A N/A
PFC (Yes/No)
No
Minimum Efficiency
80%
Inrush Limiting / Fuse
Yes
Operating Temp. Range Cooling Method/Supply Orientation
0 – 60C
Others
Convection
12 volt aux regulation: +/- 10% worst case (quasi regulated)
Circuit Description
Key Features
This Design Note presents an off-line, universal input quasi-resonant flyback power supply that provides a main output of 170 Vdc and an auxiliary output of 12 Vdc. The quasi-resonant design, utilizing ON Semiconductor’s NCP1308 controller, enhances efficiency with zero voltage switching (ZVS) and minimizes EMI for TV and monitor applications. A common and differential mode input EMI filter is included along with NTC thermistor inrush current limiting. The 170 volt output is regulated by a simple, yet effective TL431 and optocoupler feedback scheme. The 12 volt auxiliary output is quasi-regulated and provides and an additional voltage for logic level circuitry and interfacing.
September 2006, Rev. 0
• Quasi-resonant flyback design for high efficiency and low EMI. • Input EMI filter and inrush limiting • Over-current and over-voltage protection (inherent in NCP1308) • Quasi-regulated 12 volt output for logic level circuitry and interfacing • Low cost circuit components
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DN06014/D
Schematic F1
AC Input
5A 250Vac
0.22uF "X2"
T1
3
R2 150 3W
C5 270uF 400V
C2
D2
9
C6
BD1
L1
C1 0.22uF "X2"
1 nF 3 kV
MUR110 C11 14 470uF 25V D3
8
Q1
TH1 T
R1
4A 3.7 mH
10 ohm 3A Gnd Chassis Gnd
C3 C4
1Meg 0.5W R6 18K 0.5W
2.2nF "Y2" x2
R5 R4 4.7 10K
NCP1308 5
8
6
C7 1nF
4
R9 1K
3 C8 47uF 16V
2 15
170 V 600 mA C14 10nF 250V
6
2K
11
C9 100pF
NOTES:
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1. Crossed lines on schematic are NOT connected. 2. Q1 is Infineon SPA11N80C3 (11 amp, 800 volt) 3. U2 is Vishay H11A817A or equivalent optocoupler. 4. TH1 is NTC thermistor for inrush limiting. 5. L1 is Coilcraft CMT-1-3.7-4L (3.7mH, 4A) 6. R2 is a non-inductive resistor. 7. Q1 will need a small heatsink. 8. BD1 is an 4A (min), 600V bridge rectifier. 9. D1, D2, D3, D4, U1, U3 are ON Semiconductor components 10. R14 sets Vout (Vsense = 2.5 V) 11. See magnetics drawing for T1 details. 12. High current and/or low inductance traces in heavy black.
Com
C15 10nF "Y2"
R10
4
September 2006, Rev. 0
C12 0.1uF 50V
MUR1100 C13 100uF 200V
R7 120
R8 27K
U1 1 2
D1 1N4148
1 16
R3 0.22 1W
12V, 100 mA
R15 1K (pre-load)
U2
1
2
R11 1K C10 47nF
U3 TL-431
R13 160K 0.5W
R12 2.2K R14 2.4K
100 Watt, Dual Output Quasi-Resonant Power Supply ON Semiconductor Design Center
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DN06014/D 1
MAGNETICS DESIGN DATA SHEET Project: 100 watt, high voltage, dual output, universal input power supply Part Description: Flyback transformer, 45 kHz (QR), universal input, 170V/12V outputs Schematic ID: T1 Core Type: ETD-39, 3C90 or P material Core Gap: Gap for 400 uH nominal on primary Inductance: 390 - 410 uH on primary Bobbin Type: 16 pin horizontal pc mount (Ferroxcube PC1-38H or equivalent) Windings (in order): Winding # / type
Turns / Material / Gauge / Insulation Data
Secondary A (1 - 16)
27 turns of #24HN over 1 layer with 0.20" end margins. Selfleads to pins. Insulate for 3 kV to next winding with tape.
Vcc/Demag (6 - 11)
5 turns of #24HN spiral wound over Sec A with 0.20" end margins. Insulate for 1 kV to next winding with tape.
Primary (8 - 9)
40 turns of #24HN over 1 layer with 0.050" end margins. Insulate with tape for 3 kV to next winding.
12V Secondary (3 - 14)
4 turns of #24HN spiral wound over Primary with 0.20" end margins. Insulate for 1 kV to next winding with tape.
Secondary B (2 - 15)
27 turns of #24HN over 1 layer with 0.20" end margins. Insulate with final layer of tape.
Vacuum varnish final assembly.
Hipot: 3 kV from primary/Vcc to all secondary windings.
Schematic
Lead Breakout / Pinout (bottom view)
9
3
1 2 3 4 5 6 7 8 12V sec
Primary
14 1 Sec A
8 16 6
2
Vcc
16
14
12
11 10
Sec B 11
15
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© 2006 ON Semiconductor. Disclaimer: ON Semiconductor is providing this design note “AS IS” and does not assume any liability arising from its use; nor does ON Semiconductor convey any license to its or any third party’s intellectual property rights. This document is provided only to assist customers in evaluation of the referenced circuit implementation and the recipient assumes all liability and risk associated with its use, including, but not limited to, compliance with all regulatory standards. ON Semiconductor may change any of its products at any time, without notice.
Design note created by Frank Cathell, e-mail:
[email protected] September 2006, Rev. 0
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