Online Health Monitoring In Digitally Controlled Power Converters

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Online Health Monitoring in Digitally Controlled Power Converters Jeffrey Morroni, Arseny Dolgov, Mariko Shirazi, Regan Zane and Dragan Maksimovic Colorado Power Electronics Center University of Colorado at Boulder Boulder, CO (USA) Email: {morroni, arseny.dolgov, mariko.shirazi, zane, maksimov}@colorado.edu Abstract - Spacecraft power systems and other missioncritical applications require robust power delivery systems. This paper focuses on two aspects of power converter health monitoring: detecting and analyzing loss-related and frequency response-related changes. Two hardware-efficient algorithms are discussed that can be implemented without any additional sensing points other than those required for operation of the converter and with minimal additional digital hardware. It is shown that available converter operating information can be processed to detect a significant (e.g. 2x) change in the power MOSFET RON. In addition, a system identification-based approach with an additional digital pre-filter is used to extract an accurate and useful frequency response of the converter despite large quantization noise caused by a low-resolution A/D converter. It is shown that this information can be used to accurately monitor the stability margins of the converter. The techniques are verified experimentally on a 90 W 50 V-15 V forward converter with FPGA control. I. INTRODUCTION It is often important to ensure exceptional reliability in mission-critical power systems, such as those on spacecraft and satellites. The degradation of components over time as well as sudden failure can have catastrophic consequences on downstream devices and systems. Since it is impossible to ensure 100 % reliability of all critical power supply components, there is a need for real-time online converter “health” monitoring capable of measuring system performance and detecting faults or anomalies in the operation of the converter [1]. Traditionally, system monitoring and control is performed by a central power management and distribution (PMAD) unit coupled to a large number of voltage and current sensors attached to converter units and relays for over current protection and fault isolation [2-4]. Drawbacks to the traditional approach include the additional hardware required for sensing converter unit voltages and currents, the data network required for transmitting and receiving the significant amount of raw data, and the processing requirements on the central controller. Additionally, only limited information can be inferred about the health of the power electronic components from the externally available converter data. This limits the ability to make intelligent decisions on load and system management prior to system faults. With the increased Switching Power Converter A/D Converters Health Monitoring Sensing Points Digital Controller Programmable Compensator DPWM Health Monitoring Efficiency Monitoring Frequency Response Monitoring System Interface Figure 1. System architecture for health monitoring test-bed. Converter parameters are sensed using A/D converters and the data is sent to a digital controller for processing. A system interface then displays processed data concerning the converter health status. use, capability and availability of switching converters with digital controllers at their core [5, 6], new opportunities exist for the system to interact directly with the embedded digital controllers to share higher-level critical information. The purpose of this paper is to demonstrate the feasibility of monitoring converter health status using hardware-efficient algorithms requiring only sensing points already available in a typical power converter. The paper is organized as follows: Section II includes a description of the experimental test-bed, which consists of a 90 W 50 V-15 V digitally controlled forward converter switching at 100 kHz. The paper then addresses two important aspects of converter health monitoring: loss related changes and frequency response related changes. In Section III, detection of loss-related changes is presented with derivation of a hardware-efficient algorithm capable of monitoring changes in MOSFET RON. In Section IV, a system identification-based approach and hardware implementation for extracting converter stability margins from the frequency response are discussed. A complete system block diagram demonstrating both aspects of health monitoring addressed in this paper is shown in Fig. 1. II. EXPERIMENTAL SYSTEM The experimental prototype used as a test-bed to verify system health monitoring feasibility is a 90 W 50 V-15 V forward converter with damped input filter, as shown in Fig. 2a. The power stage and input filter parameters of Fig. 2a are as follows: fs=100 kHz, L=100 μH, C=330 μF, Lf=1.2 mH, Cf=66 μF, Cb=1.2 mF, Rb=0.5 Ω, transformer turns ratio of 1:1:1, Power MOSFET: FB31N20D and Power Diodes: 60EPU04. The converter is controlled by a digital control loop realized using a Xilinx Virtex-IV FPGA. The FPGA controller includes a 10-bit counter-based pulse width modulator and an on-line programmable discrete-time compensator. The output voltage is sampled once per switching cycle through a resistor divider (H1) using an A/D converter (TITHS1230) with a conversion resolution of 1.95 mV. The MOSFET current is measured through a sense resistor using a TI-THS1230 with an ADC resolution of 1.95 mV. The MOSFET current is sampled once per switching cycle at D/2 with a time resolution of 0.16 μs. Finally, the input voltage is sensed through a resistor divider (H2) using an AD7829 MUX/ADC with a conversion resolution of 7.8 mV. The system interface is realized using a MATLAB Graphical User Interface (GUI) communicating via an RS-232 serial link. The MATLAB GUI is capable of displaying all the converter health status information to the user. Specifically, the GUI displays real-time converter efficiency status while stability margin information is updated periodically. In addition to displaying converter health status, the GUI also controls the discrete time compensator parameters, converter switching frequency and output voltage regulation level. A picture of the laboratory hardware for this system is shown in Fig. 2b. III. LOSS-RELATED HEALTH MONITORING Decreases in expected converter efficiency are directly related to the health of the overall system. A decrease in efficiency can be indicative of any number of losses including stresses or degradation of semiconductor materials, bonding wires and interconnects [1]. Any of these types of degradations can prelude converter failure and potentially damage or disable critical downstream devices. Therefore, a robust algorithm capable of monitoring efficiency degradation in a power converter can potentially prevent catastrophic downstream system failures. Traditional approaches to efficiency monitoring rely on a large number of voltage and current sensing points throughout the converter. This raw data is then sent to a central controller where the data is processed in an attempt to extract useful information about the converter health status [2-4]. This approach inherently requires complicated and unnecessary Figure 2a. Experimental prototype forward converter. Converter parameters are sensed using A/D converters and the data is sent to the FPGA for processing. The FPGA communicates via RS-232 serial interface to a MATLAB GUI to display health data and control converter parameters. Figure 2b. Laboratory hardware used to implement health monitoring system extra hardware. An alternative approach is to extend the use of the digital controller to monitor efficiency-related losses using data already available to it from the converter. This method improves on the approaches of [2-4] by eliminating unnecessary sensing points and sending out higher-level data to the central controller. By utilizing a digital controller, it is possible to utilize the sensing points already present in the converter such as input voltage (necessary for over-voltage protection), MOSFET current (necessary for over-current protection), and output voltage (necessary to close the voltage feedback loop). These three sensing points plus duty cycle, which is available inside the digital controller, can be used to directly monitor the relative efficiency status of various system components. A subset of losses of particular interest is duty-cycle dependent losses. Monitoring duty-cycle dependent losses can give important information about changes in resistive loss elements associated with switching components inside the power converter. As an example, this paper specifically addresses monitoring of MOSFET on-resistance (RON) using an embedded digital controller. It is possible to monitor MOSFET RON directly by measuring the switch-node voltage and the MOSFET current. However, doing this requires sensing points normally unnecessary for operation of the power converter. To monitor MOSFET RON using sensing points inherently available in the converter, consider first the averaged model of the forward converter including the following losses: transformer winding resistance, MOSFET RON, sense resistor losses, diode forward voltage drops and inductor winding resistance [7]. Analysis of this model shows that the resistive conduction losses in the converter can be lumped into two resistive loss elements – one element is duty-cycle dependent (DRX) while the other is not (RY). The averaged circuit model including DRX and RY is shown in Fig. 3. Solving for RX in the averaged model of Fig. 3 yields RX = ⎤ 1 ⎡ DV g − V − VD − RY ⎥ . ⎢ D⎣ I LOAD ⎦ (1) In (1), D is the average duty cycle, Vg is the input voltage, VD is the diode forward voltage drop, V is the output voltage, and ILOAD is the load current. Sensing V and Vg is straightforward, requiring only a resistor divider and an A/D converter. ILOAD can be sensed in any number of ways including current sensing MOSFET’s, series resistors or methods utilizing component parasitics, such as inductor equivalent series resistance [8-10]. For this experiment, ILOAD is monitored by sampling the voltage across a sense resistor in series with the power MOSFET at exactly D/2. However, it should be noted that any of the above described methods would be suitable for this application. Rather than using the component expected values for RY and VD in (1), Fig. 3 can be used as the basis for an experimental curve fit with empirical values for RY and VD. By employing an experimental curve fit, non-duty cycle dependent losses and diode forward voltage drops are characterized more accurately than the averaged model predicts. Then, using the empirical values of RY and VD along with instantaneous samples of the voltages and current mentioned previously, the instantaneous value of RX can be monitored. Further, since RX is a measure of duty cycle dependent losses, its value includes MOSFET RON. Therefore, significant changes in RX can indicate changes in MOSFET RON. The advantage to monitoring changes in RON in this manner is the insensitivity of the algorithm to converter operating conditions. Specifically, the values of RY and RX in the averaged model are ideally independent of input voltage and RY + DVg -VD + – V IV. FREQUENCY RESPONSE HEALTH MONITORING The frequency response health monitoring method addressed in this paper builds on concepts presented in [1114]. In particular, it was recently shown that hardwareefficient system identification is possible for switching power converters containing a digital control loop [11]. A brief summary of system identification and its relevance to power converter health monitoring is given below in subsection A. An improved system identification method, suitable for measuring stability margins is given in subsection B along with experimental results. Finally, subsection C describes a hardware-efficient algorithm for finding the stability margins from the frequency response data for the purpose of detecting changes in converter health. RLOA D _ Measured Rx vs Input Voltage 1.06 1.01 Rx (Ohms) I LOAD DRX load current. Therefore, the characterization of RON using this method does not depend on particular values of either input voltage or load current. Further, implementing the algorithm for monitoring RX is hardware-efficient, requiring only one divider, no look up tables, and limited multiplications. Figure 4 shows experimental results obtained for the prototype shown in Fig. 2a. The calculated value of RX is shown over a wide range of input voltages and two different load currents. The blue lines correspond to normal MOSFET RON=41 mΩ while the red lines correspond to abnormally high MOSFET RON=82 mΩ. The orange line between the normal and abnormal MOSFET RON is a failure prediction threshold above which the algorithm detects unusually high MOSFET RON. Notice in Fig. 4 the relative insensitivity to a wide range of input voltages and load currents. As a final note, the effective quantization of (1) based on the quantization of the individual terms is of interest to determine the precision in monitoring RX. Assuming the model of Fig. 3 is ideal and that RY and VD are characterized perfectly, it is possible to look at the quantization of (1) based on the quantization of the individual terms sensed by A/D converters. For this example, based on the quantization intervals stated in Section II, the worst case precision in RX based on (1) is 1.5 mΩ. This effective quantization is better than the necessary precision required to accurately monitor RX. 0.96 0.91 Ron = 41mΩ I = 5A Ron = 82mΩ I = 5A Failure Threshold Ron = 41mΩ I = 6A Ron = 82mΩ I = 6A 0.86 0.81 42 Figure 3. Averaged circuit model of the forward converter shown in Fig. 2(a) including the lumped resistances RX and RY, input voltage Vg, diode voltage VD and load RLOAD. 47 52 Input Voltage (V) 57 Figure 4. Measured RX based on (1). The unfilled markers correspond to RON=41 mΩ for two Iload equal to 5A and 6A, while the filled markers correspond to RON=82 mΩ for the same two load currents. The dashed line between the two different MOSFET RON plots is a failure prediction threshold above which the algorithm detects abnormal RX. A. System identification through cross-correlation A digital power converter can be regarded as a discrete-time linear time-invariant system if the converter is in steady-state and the input disturbances are small. If white noise is chosen as the input disturbance, then the cross-correlation of the input signal u(k) and the output error signal y(k) is given by [15]: ∞ Ruy (m) = ∑ u (n) y (n + m) = h(m) , (2) n =1 where h(m) is the discrete-time system impulse response. The converter transfer function can then be found by applying the Discrete Fourier Transform (DFT) to h(m). From a hardware design standpoint, it is useful to approximate the white noise input with a pseudo-random binary sequence (PRBS). The PRBS is a deterministic sequence that can be easily generated in hardware using a simple shift register and XOR gate [13]. A 10-bit shift register can generate a non-repeating sequence length of m=1023, which provides an adequate approximation of white noise. Figure 5 shows the identification of the control-to-output transfer function for the experimental prototype described in Section II. In Fig. 5, the blue line is the identified result while the dashed-red line is the expected result based on the discrete-time model of [16], where the forward converter dynamics are assumed to match those of a buck converter. In the result shown in Fig. 5, the corresponding output voltage perturbation resulting from the PRBS injection is +/-150 mV or about +/-1.0 % of the output voltage regulation level. The experimental system identification results shown in Fig. 5 contain a large amount of noise at high identification frequencies. This noise is primarily due to A/D converter quantization effects. Specifically, the power converter acts as a low-pass filter such that a duty cycle injection of fixed Identified Frequency Response without Pre-Filter Magnitude [dB] 40 B. Input pre-filtering for better high frequency response In order to remove the effects of the quantization noise introduced at high frequencies, the PRBS injection can be digitally pre-filtered. The digital pre-filter is designed to have a high-pass characteristic in which the high frequency content of the PRBS signal is amplified relative to the low frequency content. The pre-filter takes the PRBS sequence as input and outputs a multi-level sequence based on the specific filter design. This multi-level signal is then used as the input perturbation to excite the system. The pre-filter must be designed to meet the following two criteria: the injection magnitude must be such that it does not cause duty cycle saturation and the output voltage perturbation caused by a pre-filtered injection must not exceed the perturbation without the pre-filter. These two criteria limit the pre-filter from achieving perfect system identification. To ensure that the duty cycle does not saturate, the maximum duty cycle perturbation must be within the saturation limits of the pulse-width modulator (PWM). Based on the convolution equation, it can be shown that the maximum duty cycle input is given by [17]: 20 0 -20 2 10 yt DT Model Experimental 3 4 10 10 5 10 where ht -50 -100 -150 -200 2 10 L1 ≤ ht L∞ ut L1 L∞ , (3) is the L1 norm of the pre-filter impulse response, is the L∞ norm of the PRBS injection and yt L is the L∞ ∞ norm of the PWM input. To ensure that the duty cycle does not saturate, the following equations must then be satisfied: ut 0 Phase [deg] amplitude perturbs the output of the system less at higher frequencies. Therefore, A/D quantization becomes an issue as the identified frequency increases. A compromise exists between the magnitude of the PRBS and the quantization level of the A/D converter. If the disturbance caused by the injected PRBS is desired to be small, then a high resolution A/D converter with a smaller quantization level is required to maintain the identification precision. However, a high resolution A/D converter is not required for normal converter operation. Thus, it is desirable to use the existing lower resolution output voltage A/D converter for both closed-loop regulation and system identification. If useful information is to be obtained from the frequency response there should be a close match to the ideal model at all frequencies. This is the primary motivation for input digital pre-filtering, which is described in subsection B. L∞ yt 3 4 10 10 5 10 Frequency [Hz] Figure 5. Identification of the control-to-output transfer function for the prototype described in Section II. The blue line is the identified result while the red line is the expected transfer function. The output perturbation required for the above identification is +/-150 mV. L∞ ≤ ht L1 ut L∞ < Dmax − D , (4) and yt L∞ ≤ ht L1 ut L∞ < D − Dmin , (5) where D is the steady state duty cycle, Dmax is the maximum duty cycle and Dmin is the minimum duty cycle. The L∞ norm is defined as: u L∞ = sup u (t ) , (6) t ≥0 and the L1 norm is defined as: ∞ u L1 = ∫ u(t ) dt . (7) 0 The intuition behind the requirement stated in (4) and (5) is that the least upper bound of y(t) and u(t) is defined as the L∞ norm for the scalar case. Therefore, in (4) and (5) the maximum value of the duty cycle perturbation, yt L , can be ∞ found by multiplication of the maximum value of the PRBS injection u t L and the L1 norm of the pre-filter impulse ∞ response. The second criterion states that the output perturbation with the pre-filter must not exceed the perturbation without the prefilter. In the case of a PRBS injection with no pre-filter, the output perturbation magnitude is primarily a function of the low frequency gain of the converter, since the converter control-to-output transfer function has a low-pass characteristic. Therefore, with a pre-filtered injection, all that is required is the pre-filter gain at a given frequency times the control-to-output gain at the same frequency not be greater than the maximum control-to-output gain. Ensuring this will guarantee the output perturbation with the pre-filter is not larger than without the pre-filter. It should be noted that introducing the pre-filter into the system identification loop will also require a post-filter to remove the pre-filter frequency response in the identified result. The digital post-filter must be an exact matched inverse of the pre-filter. The cross-correlation and Fast Fourier Transform (FFT) is then performed on the output of the post-filter. The complete system diagram for the system identification process including digital pre-filter and post-filter can be found in Fig. 6. For the experimental prototype, a fixed 2nd order digital prefilter was designed with the following transfer function: 1 − 0.4158z −1 + 0.0432z − 2 the PRBS injection will be amplified above frequencies where the quantization noise begins to take effect. Figure 8 shows experimental results for the system identification including the pre-filter shown in Fig. 7. Figure 8a is the output perturbation resulting from a PRBS injection with no pre-filter. Figure 8b is the output perturbation resulting from a pre-filtered duty cycle perturbation. Figure 8c is the resulting frequency response identification based on the pre-filtered injection. Comparison of Fig. 8a with Fig. 8b clearly shows the increased high frequency content of the output perturbation for the case of the pre-filtered injection. Also, there are significant improvements in the high frequency content of both the magnitude and the phase in the identified frequency response. The use of a pre-filter enables detection of system stability margins with greater accuracy than without the preBode Diagram 40 DT Model Experimental 30 Pre-Filter 20 , (8) Magnitude (dB) G filter ( z ) = 7 − 9.456 z −1 + 2.709 z −2 Figure 6. System identification subsystem including input pre-filter and output post-filter. A PRBS sequence is generated and passed through a high-pass filter which is injected as a duty cycle perturbation. The output voltage is then sensed and passed through a matched inverse of the pre-filter. The cross-correlation is preformed on the PRBS and the post-filtered output perturbation. 10 0 while the exact match inverse filter is described by: Ginv _ filter ( z ) = 1 − 0.4158z −1 + 0.0432z −2 7 − 9.456 z −1 + 2.709 z −2 . -10 (9) Figure 7 shows the pre-filter magnitude response overlaid with the identified result of subsection A. The plot shows that -20 2 10 3 4 10 10 5 10 Frequency (Hz) Figure 7. Bode diagram of the pre-filter used to shape the frequency content of the PRBS signal before it is injected into the converter duty cycle. The pre-filter response is overlaid with the system identification results presented in earlier sections. The loop gain of the system is given by: T = Gvd (z ) ⋅ H (z ) (10) where Gvd (z ) is the transfer function of the converter and H (z ) is the transfer function of the compensator and the other gains in the loop. The crossover occurs at the frequency where: Figure 8a. Output perturbation resulting from pure PRBS duty cycle perturbation. Figure 8b. Output perturbation resulting from pre-filtered duty cycle perturbation Magnitude [dB] 20 -20 2 10 (Re{G vd DT Model Experimental 3 4 10 10 5 10 Phase [deg] 0 -50 -100 -150 -200 2 10 3 4 10 10 (11) Rearranging (11) and writing it in terms of the complex frequency response data available from the system identification, the equation that must be satisfied is: Identified Frequency Response, w/ Prefilter 40 0 Gvd (z ) ⋅ H (z ) = 1 . 5 10 Frequency [Hz] Figure 8c. Magnitude and phase of the pre-filtered system identification results. The output voltage perturbation is +/-150 mV, or +/-1.0% of the regulated output voltage. filter over the entire system frequency range. A hardwareefficient algorithm for finding system stability margins is discussed in the next subsection. C. Stability Margin Detection After system identification has been performed with a prefilter, it is desirable to process the raw data directly on the digital controller of the converter to avoid sending large amounts of low-level data to a higher-level PMAD central controller. Thus, the raw complex frequency response data created by the system identification algorithm must be processed to extract useful information about the health of the converter. In particular, it is useful to find the converter stability margins using the identified results shown in Fig. 8c. The architecture and implementation of the system identification algorithm only yields the transfer function of the converter itself, not accounting for the compensator and scale factors present in the loop gain. Therefore, a hardwareefficient algorithm for finding the loop gain must be designed so that the stability margins can be extracted. For fixed compensator parameters, it is possible to store real and imaginary data in a look-up table (LUT) on the embedded controller. This data, along with the identified converter frequency response can then be used to compute the loop gain. }2 + Im{Gvd }2 )⋅ (Re{H }2 + Im{H }2 ) − 1 = 0 . (12) The left side of (12) is computed in hardware over the data set to produce an error value for each data point. The data point corresponding to the smallest error is output at the end of the search. To find the gain margin, a search is performed on the frequency data to determine the -180° point of the phase. Rather than directly computing the actual phase from the complex data at each point using an arctan function, it is possible to determine the -180° point by direct inspection of the signs of the real and imaginary data. Specifically, the -180° crossing occurs where the real part of the complex data is negative and the imaginary part changes sign from negative to positive. This approach is far more hardware-efficient than brute-force phase calculations at each point. A simple state machine for performing the stability margin search is illustrated in Fig. 9. The state machine works by searching through the FFT data in a linear fashion. The loop gain is computed from the complex frequency data and used in (12) to determine how close the current data is to the crossover frequency. The signs of the real and imaginary loop gain data are also checked to find the -180° crossing. At the end of the search, the frequency and corresponding complex Start Get FFT Data Compute T Compute Crossover Error LUT Check Re{T}, Im{T} Sign End of Data? NO YES Output PM Output GM Figure 9. Finite state machine used to process FFT data to find the loop stability margins. TABLE I IDENTIFIED VS DT MODEL[16] SYSTEM STABILITY MARGINS FOR TWO DIFFERENT OUTPUT FILTER CAPACITANCES C=330 μF Crossover [kHz] Phase Margin -180° Crossing [kHz] Gain Margin [dB] ACKNOWLEDGMENTS C=800 μF Without PF With PF DT Model Without PF With PF DT Model 5.96 8.60 8.81 4.79 4.79 4.83 39.4° 58.1° 54.7° 33.7° 61.1° 55.4° 21 49 50 20 49 50 26.03 12.34 12.23 27.32 19.66 18.3 loop data for the smallest computed errors are output. Using the above described algorithms, Table I shows the stability margin predictions versus experimentally obtained values using both pre-filtered and non-filtered system identification data. The expected values are based on the discrete-time model of [16] and a fixed compensator. Two separate cases are shown in Table I, one with an output filter capacitor of 330 μF while the other has an output filter capacitor of 800 μF. The results show that the stability margins are determined with far more precision when a prefilter is used to improve the frequency response data. The proposed system monitoring can be used to detect degradation of converter stability margins, leading to system failure. In this experiment, only output filter capacitance was varied to force changes in stability margins, possibly indicative of degradation or failure of capacitors on a voltage bus. The method also applies to other variations in the system leading to potential instabilities and can be used to provide early warning to local or system level controllers. The authors would like to acknowledge Mr. Robert Button of the NASA Glenn Research Center in Cleveland, Ohio who has sponsored this work. REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] V. CONCLUSIONS AND FUTURE WORK Intelligent, active health monitoring of power converters is essential for any system requiring robust operation. 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