Transcript
E8364A Overall Block Diagram
USB HUB
RS-232 PORT INTERFACE
DISPLAY PROCESSOR
FLASH
INVERTER POWER
A6 SIGNAL PROCESSING ADC MODULE (SPAM)
PROBE POWER
GPIB PORT INTERFACE
GPIB
A3 FRONT PANEL INTERFACE
MAIN CPU ROM
RAM
L
R
J4 R1
W26
61 kHz
J5
W27
61 kHz
R2/C
PCI BRIDGE
PCI BUS
VIDEO PROCESSOR
A4 POWER SUPPLY
LINE IN
VIDEO RAM
+ 15 dB
8.333 MHz
40 MHz
W21
90°
I
L
DSP
L
A IN
W69
RF
R
W60 A OUT
2nd LO b
W28
J6
To Phase Lock
B
0°
ADC
I
L
R
+ 15 dB
8.333 MHz
40 MHz
W22
41.667 kHz
IF
I
L
R1 IN
W70
RF
R
+ 15 dB
IF Calibration Signal
POWER BUS
LO
A28 R1 FIRST CONVERTER
A32 RECEIVER R1
B
61 kHz
A14 MOTHERBOARD
I
R
2nd LO a
A40 FLOPPY DISK DRIVE
RAM
A41 HARD DISK DRIVE
IF
+ 15 dB
ADC
VGA INTERFACE
VGA
I
41.667 kHz
LO
A27 A FIRST CONVERTER
ADC
10/100 BASE-T ETHERNET
LAN
0°
ADC
SPEAKER
B
A31 RECEIVER A
W25
J3 A
61 kHz
RAM EEPROM
PARALLEL PORT INTERFACE
PARALLEL
To Phase Lock
2nd LO a
USB INTERFACE
RS-232
MIXER BIAS
A35 RECEIVER MOTHERBOARD
PROBE CONNECTORS
USB
A15 CPU USB
A2 DISPLAY
A1 KEYPAD
REAR PANEL INTERCONNECTS
90°
I
L
W60
R R1 OUT
LOCAL DIGITAL BUS 2nd LO b
HIGH DENSITY DATA BUS
A10 FREQUENCY REFERENCE
LOCAL DIGITAL BUS
EXT REF IN 10 MHz
W33
200 Hz
211
0°
SERIAL TEST BUS NODES
To A8, A11, A16
B
I
L
R
+ 15 dB
8.333 MHz
40 MHz
W23
41.667 kHz
Bx = ACTIVE SOURCE BAND
IF
I
+ 15 dB
Φ
215
212
f
2
5
10 MHz HIGH STAB OCXO
12
Φ
20
99.50 MHz L
f
I
EXT REF OUT 10 MHz
W34
W29
J2
R2 OUT
4
200 Hz
W40
J4 To 2nd LO b x 4 216
213
To Phase Lock
2nd LO a
8.29167 MHz ∠90°
B
To Phase Lock 5 MHz W30
2
To Phase Lock
J50 MUX
J10
To Phase Lock To Phase Lock
20 MHz
0°
A
I
L
R
+ 15 dB
8.333 MHz
40 MHz
W24
41.667 kHz R1
IF
I
+ 15 dB 90°
R2
I
L
W14
LO
A30 B FIRST CONVERTER
A34 RECEIVER B
PHASE LOCK REF
20 MHz REF
W60
R
2nd LO b
2nd LO x4 33.1667 MHz
218 3
R
J3
5 MHz REF
L
R2 IN
W71
RF
R
To 2nd LO a x 4
214
217 10 MHz
I
L
8.29167 MHz ∠0°
100 MHz 500 kHz
DAC
90°
8.333 MHz
LO
A29 R2 FIRST CONVERTER
A33 RECEIVER R2
MIXED POWER AND CONTROL SIGNALS
10 MHz J2
To Phase Lock
2nd LO a
POWER BUS
L
B IN
W72
RF
R
W60
R B OUT
B 2nd LO b
J5 W31
FROM A16
FROM A16
W32 J5
A11 PHASE LOCK
A8 FRACTIONAL-N SYNTHESIZER
40 MHz COUNTER J6
20 MHz 15 MHz
B3-25
Φ
700 kHz 312
f
1.5 - 3.0 GHz VCO 413 412
LOCAL DIGITAL BUS
3 GHz
POWER BUS
Ramp Cal
315
317
2.5 GHz Offset 20 MHz Ref In
2
5 MHz REF
B1 J101
J105 2250 MHz 415 VCO 417
1V/GHz (TO A12, A16)
2.4 GHz
➊
Band
L.O. Harmonic A8 Frac-N Number Synthesizer (N) Frequency (GHz)
➋
➌
➍
➎
A17 LOMA 10 Frequency (GHz)
A20 LODA (L.O.) Frequency (GHz)
A12 Source 20 Frequency (GHz)
A21 SOMA 50 Frequency (GHz)
1
1
0.037 to 0.740 0.037 to 0.740 0.037 to 0.740 0.045 to 0.748 0.045 to 0.748
2
1
0.740 to 1.500 0.740 to 1.500 0.740 to 1.500 0.748 to 1.500 0.748 to 1.500
3
1
1.50 to 3.00
1.50 to 3.00
1.50 to 3.00
1.50 to 3.00
1.50 to 3.00
4
1
1.50 to 1.90
3.00 to 3.80
3.00 to 3.80
3.00 to 3.80
3.00 to 3.08
5
1
1.90 to 2.25
3.80 to 4.50
3.80 to 4.50
3.80 to 4.50
3.80 to 4.50
6
1
2.25 to 2.40
4.50 to 4.80
4.50 to 4.80
4.50 to 4.80
4.50 to 4.80
7
1
2.40 to 3.00
4.80 to 6.00
4.80 to 6.00
4.80 to 6.00
4.80 to 6.00
8
1
1.50 to 1.60
6.00 to 6.40
6.00 to 6.40
6.00 to 6.40
6.00 to 6.40
9
1
1.60 to 1.90
6.40 to 7.60
6.40 to 7.60
6.40 to 7.60
6.40 to 7.60
10
1
1.90 to 2.50
7.60 to 10.00
7.60 to 10.00
7.60 to 10.00
7.60 to 10.00
11
1
2.50 to 3.00
5.00 to 6.00 10.00 to 12.00 10.00 to 12.00 10.00 to 12.00
12
1
1.50 to 1.60
6.00 to 6.40 12.00 to 12.80 12.00 to 12.80 12.00 to 12.80
13
1
1.60 to 1.90
6.40 to 7.60 12.80 to 15.20 12.80 to 15.20 12.80 to 15.20
14
1
1.90 to 2.00
7.60 to 8.00 15.20 to 16.00 15.20 to 16.00 15.20 to 16.00
15
1
2.00 to 2.40
8.00 to 10.00 16.00 to 20.00 16.00 to 20.00 16.00 to 20.00
16
3
1.67 to 1.90
6.67 to 7.60
6.67 to 7.60 10.00 to 11.40 20.00 to 22.80
17
3
1.90 to 2.13
7.60 to 8.53
7.60 to 8.53 11.40 to 12.80 22.80 to 25.60
18
3
2.13 to 2.40
8.53 to 10.00
8.53 to 10.00 12.80 to 15.00 25.60 to 30.00
19
3
2.40 to 2.67
10.00 to 10.67 10.00 to 10.67 15.00 to 16.00 30.00 to 32.00
20
3
2.67 to 3.00
5.34 to 6.00 10.67 to 12.00 16.00 to 18.00 32.00 to 36.00
21
3
1.50 to 1.60
6.00 to 6.40 12.00 to 12.80 18.00 to 19.20 36.00 to 38.40
W20
3 - 3.8 GHz
B4-25
3
1.60 to 1.67
6.40 to 6.67 12.80 to 13.33 19.20 to 20.00 38.40 to 40.00
23
3
1.67 to 1.90
6.67 to 7.60 13.33 to 15.20 10.00 to 11.40 40.00 to 45.60
24
3
1.90 to 2.00
7.60 to 8.00 15.20 to 16.00 11.40 to 12.00 45.60 to 48.00
25
3
2.00 to 2.08
8.00 to 8.33 16.00 to 16.67 12.00 to 12.50 48.00 to 50.00
W14
12.8 - 16 GHz B4 - 7, 11, 20
X2
I
B
X2
3.8 - 4.8 GHz
16 - 20 GHz
6 - 7.6 GHz
FROM A16
B8 -10, 12 - 19, 21 - 25 4.8 - 6 GHz
ALC 414
W13
10-12.8 GHz R2
B1
418
X2 Level Adjust
7.6 - 10.0 GHz 516 517 518
511
-15V REF
FROM A16
FROM A16
+9V REF
A23 DETECTOR
W4
+15V REF
W65
W37
FROM A16
A24 DETECTOR
W5
W66
W38
SOURCE OUT
A21 SOURCE MODULATOR ASSY 50 (SOMA 50)
SOURCE 10
POWER BUS
5.25 GHz
11 GHz
W61
40-50 GHz
20-25.6 GHz
A25 TEST PORT COUPLER
W63
5
X2 B23-25
MODULATOR ASSY 20 (MA 20) FM
W60
A22 SWITCH SPLITTER
A16 TEST SET MOTHERBOARD
A12 SOURCE 20 LOCAL DIGITAL BUS
W2
COUPLER IN
PORT 1
8.0 GHz
YTO 3-10 GHz
4
11 GHz
B4-25 B4-25
23 GHz
B1-10
B1-3
117
B11-25
B1-3
45 GHz
25.6-32 GHz
B16-25
OPTION UNL
X2
W1
0.05-20 GHz
YTO TUNE
B1-15
15 GHz 10-12.8 GHz
A36 STEP ATTEN
32-40 GHz
To W60
W81
DC BIAS 1
W83
A38 BIAS TEE
W67 W55
W51
B16-22
3 GHz R
ALC
I L
113
112
12.8 - 16 GHz
Slope Compensation
PMYO 3.8 GHz
FROM A16
X2
3.8 GHz
118
SOURCE OUT
111
Temp Comp
W60
SOURCE ALC
(FROM A11)
DAC
0-60 dB
16 - 20 GHz
1V/GHz 114
Power DAC
22
R1
30-750 MHz
Analog Ramp FRAC-N LOGIC
W12
W17 W16
15 GHz
750 MHz R
W15 0.03-20 GHz
23 GHz
B11 - 15, 20 - 25
B1-3
B2-25
W11 A
B1-10, 16 - 19
W18
W19
L
PRETUNE: 30 kHz SWEEP: 100 Hz
Digital Pretune Ramp
MODULATOR ASSY 20 (MA 20)
2
3
A20 L.O. DISTRIBUTION ASSY (LODA)
A19 SPLITTER
11 GHz
J106
FRAC-N LOGIC
Delay Comp POWER BUS
LOMA10 11 GHz
B2-25
B1
AQUIRE: ON
A18 MODULATOR ASSY
416
1.5 GHz B2
BIAS/RF
1
ALC
314
316 LOCAL DIGITAL BUS
A17 L.O. MODULATOR ASSY 10 (LOMA 10)
115
611
R1
R1
612
W39
116 R2
R2
W62
613
614 1V/GHz
A26 TEST PORT COUPLER
W64
(FROM A11)
615 Temp Comp DAC
COUPLER IN
PORT 2
616 Slope Comp 618 Power DAC
TO A35, A17, A18, A20, A22, A36, A37
OPTION UNL FROM A16
A37 STEP ATTEN W52
To W60
W82
DC BIAS 2
W84
A39 BIAS TEE
W68 W56
LO ALC
OPTION UNL
512 Power DAC
REAR PANEL INTERCONNECT
PORT 1 BIAS INPUT
DC BIAS 1
PORT 2 BIAS INPUT
DC BIAS 2
TEST SET IO
TEST SET IO INTERFACE
AUX IO
AUX IO INTERFACE
HANDLER IO
FROM A16
513 1V/GHz
0-60 dB
TO A18
514
(FROM A11)
515 Slope Comp
HANDLER IO INTERFACE
LOCAL DIGITAL BUS POWER BUS
st502a
S1
E8364A Block Diagram (Option 014)/Service Guide E8364-90001
