Transcript
REAR PANEL INTERCONNECTS
N5230A Overall Block Diagram 2-Port Passive Measurement Configuration Service Guide: N5230-90014
FRONT PANEL INTERCONNECTS
USB
USB HUB
A15 CPU
ROM
VGA INTERFACE
VGA
15 MHz
PCI BRIDGE
VIDEO PROCESSOR
LINE IN
VIDEO RAM
I
C(R2)
15 MHz
B
J6 R
A14 SYSTEM MOTHERBOARD
D(B)
NC
I
I
J3
A10 FREQUENCY REFERENCE
215
10 MHz HIGH STAB OCXO
10
ƒ
2nd LO HB J4 P. LOCK REF J5
MIXED POWER AND CONTROL SIGNALS
N/C
L
W12
R
B
I
L
R
R
With spur avoidance ON, for frequencies below 40 MHz, the IF frequency is set to various values between 1 and 12 MHz to avoid generating spurs.
LOCAL DIGITAL BUS
100 MHz
R2
* With spur avoidance OFF.
HIGH DENSITY DATA BUS POWER BUS
J2
W10
R
20.0 MHz
TO A6, A7, A8, A9, A16
W25
L
20.0 MHz
7.66 MHz *
EXT REF IN 10 MHz
R1
DITHER NOISE
X8
5 MHz
211
W9
R
20.0 MHz
7.66 MHz * LOCAL DIGITAL BUS
200 Hz
L
R
POWER BUS
10 MHz
A
W24
J5
ADC
RAM
7.66 MHz *
USB INTERFACE
W11
R
DSP
A40 FLOPPY DISK DRIVE
15 MHz
USB x 4
L
20.0 MHz
7.66 MHz *
W23
R2
ADC
A41 HARD DISK DRIVE
I
A(R1)
J4
ADC
20.0 MHz
7.66 MHz *
W22
J2 R1
15 MHz
RAM
A4 POWER SUPPLY
B(A)
A
SPEAKER
PCI BUS
MAIN CPU
W21
J1
ADC
10/100 BASE-T ETHERNET
LAN
15 MHz
ADC
A3 FRONT PANEL INTERFACE
GPIB PORT INTERFACE
GPIB
A20 MIXER BRICK (QuintBrick)
EEPROM
PARALLEL PORT INTERFACE
PARALLEL
INVERTER POWER
A5 SIGNAL PROCESSING ADC MODULE (SPAM)
PROBE POWER
RAM
RS-232 PORT INTERFACE
RS-232
DISPLAY PROCESSOR
PROBE CONNECTORS
FLASH
USB INTERFACE
USB
A2 DISPLAY
A1 KEYPAD
SERIAL TEST BUS NODES
It is recommended that troubleshooting be done with spur avoidance OFF to ensure a fixed IF frequency.
Bx = ACTIVE SOURCE BAND
N/C
DAC 5 MHz REF
5 MHz
10 MHz
W26
EXT REF OUT 10 MHz
2
J3
W27
J12 W28
FROM A16
J10 W29 J11
Band
0 1 2
Mixer Brick L.O. Harmonic Number (N) 1 1 1
1
2
3
4
A7 Frac-N Synthesizer Frequency (GHz)
A6 Multiplier Frequency (GHz)
A9 Frac-N Synthesizer Frequency (GHz)
A8 Multiplier Frequency (GHz)
0.008 to 0.009
0.008 to 0.009
.0003 to 0.001
.0003 to 0.001
0.009 to 0.018 0.018 to 0.048
0.009 to 0.018 0.018 to 0.048
0.001 to 0.010 0.010 to 0.040
0.001 to 0.010 0.010 to 0.040
5 A19 SSLAM Frequency (GHz)
0.048 to 0.756
0.040 to 0.748
0.040 to 0.748
0.040 to 0.748
4
1
0.756 to 1.508
0.756 to 1.508
0.748 to 1.500
0.748 to 1.500
0.748 to 1.500
6 7 8 9
1 1 1 1
1.508 to 3.133 1.566 to 2.087 2.087 to 2.629 2.629 to 3.129 1.564 to 2.085
1.508 to 3.133 3.133 to 4.174 4.174 to 5.258 5.258 to 6.258 6.258 to 8.341
1.500 to 3.125 1.563 to 2.083 2.083 to 2.625 2.625 to 3.125 1.563 to 2.083
1.500 to 3.125 3.125 to 4.167 4.167 to 5.250 5.250 to 6.250 6.250 to 8.333
B4
B4-12
2
J105
2250 MHz VCO 417 415
1.500 to 3.125
W1
J100
516 1211
B0-5 B4-12
J106
FRAC-N LOGIC
B0-3
W2
B6-8, 11,12
1.5 GHz
J101
B0-3
J101
B9,10
2.083 to 2.625
8.333 to 10.500
11
3
1.751 to 2.085
3.503 to 4.169
2.625 to 3.125
5.250 to 6.250 10.500 to 12.500
12
3
2.085 to 2.251
4.169 to 4.503
1.563 to 1.688
6.250 to 6.750 12.500 to 13.510
2
811
W3
812 814
1217
B6-12
815
2.4 GHz
L
3.125 - 4.167 GHz
750 MHz
813
B6,9,11
I
4.167 - 5.25 GHz
ALC
818
FRAC-N LOGIC
411
Level Adjust
+5V REF
-10V REF
+10V REF -1.25V BIAS REF
BREAKPOINT 1
+5V REF
BREAKPOINT 2
LOCAL DIGITAL BUS
DET VOLTAGE OUT
712 714
617 611
612
717 J206
POWER BUS
615 616
PRELEVEL DAC
LOCAL DIGITAL BUS
711
OFFSET
PHASE LOCK IF DET
718
8.333 to 10.500
817
DRIVE
LOG AMP
B10
+15V REF
+1.78V BIAS REF
8.33 - 10.5 GHz B8
+9V REF
518
X2
5.25 - 6.25 GHz
-15V REF
517
+10V REF
B7,10,12
X2
418
414
B9
6.250 to 8.333
8.341 to 10.508
+5V REF
6.25 - 8.33 GHz
5.250 to 6.250
2.085 to 2.627
715
816 R
4.167 to 5.250
1
GND
B0-8,11,12
B0-5
3.125 to 4.167
10
A16 TEST SET MOTHERBOARD
1213
1214
416
B0-3
5 MHz REF
1215 POWER DAC
1
ALC 1.5 GHz
3.2 GHz
0.010 to 0.040
0.048 to 0.756
1
1.5 - 3.125 GHz VCO 412 413
0.001 to 0.010
1
5
B5-12
.0003 to 0.001
3
A6 MULTIPLIER
A7 FRACTIONAL-N SYNTHESIZER
618
R1
J204
R2
J205
716 TEMP COMP SLOPE COMP POWER DAC
POWER BUS W32
W30
W31
W9
W10
NOTE: ALL VALUES IN THE ABOVE TABLE ARE WITH THE SPUR AVOIDANCE FUNCTION OFF.
A8 MULTIPLIER
A9 FRACTIONAL-N SYNTHESIZER B5-12 1.5 - 3.125 GHz VCO 412 413
B4
B4-12
2
PORT 1 BIAS INPUT
A16 TEST SET MOTHERBOARD
5 MHz REF
J105
415
2250 MHz VCO 417
B0-3
2.4 GHz R
TRIGGER OUT
POWER BUS
TRIGGER OUT
TO A19, A20, A25
TRIGGER IN
LOCAL DIGITAL BUS
AUX IO
AUX IO INTERFACE
TEST SET IO
TEST SET IO INTERFACE
HANDLER IO
HANDLER IO INTERFACE
n5230ablk_2port_passive 2 September 2004
414
411
LOCAL DIGITAL BUS
B0-5 B4-12
W5
J101
L
B6-8,11
1.5 GHz B0-3
3.125 - 4.167 GHz
I
4.167 - 5.25 GHz
+5V REF
X2
418 Level Adjust
POWER BUS
B0-10
50
50
50
1117
A21 TEST PORT COUPLER
PORT 1
B11-12
50
50
X2
6.25 - 8.33 GHz B9,12
W11
18 dB
10.5 - 13.5 GHz
B7,10
W7
50
B6,9,12
50 50
8.33 - 10.5 GHz B8,11
5
W6
B9,10,12
R2
50
50
4
+5V REF
X2
5.25 - 6.25 GHz
R1
18 dB
GND
B6-12
750 MHz
J1
J2
J3
50
B0-8,11
B0-5
ALC
FRAC-N LOGIC
DC BIAS 2
J100
J101
DC BIAS 1 PORT 2 BIAS INPUT
W4
J106
FRAC-N LOGIC
1111 1114
416
B0-3
1113
POWER DAC
3
ALC 1.5 GHz
3.2 GHz
1115
A19 SWITCH/SPLITTER/LEVELER/ AMPLIFIER/MULTIPLIER (SSLAM)
50
W8
A22 TEST PORT COUPLER
PORT 2
B10
W12 LOCAL DIGITAL BUS
POWER BUS
FROM A16
