Transcript
Data Sheet PT7C4701 PLL Multi-Clock Generator |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Features
Product Description
• 27-MHz Master Clock Input
The PT7C4701 family is low cost, multi-clock generator
• Zero PPM Error Output Clocks
Phase Lock Loop (PLL). It can generate four systems
• Low Jitter Output
clocks from a 27MHz reference input frequency.
• Generated Audio System Clock: SCKO0
768fS
SCKO1
256fS
SCKO2
384fS
SCKO3
768fS, 384fS
The device gives customers both cost and space savings by eliminating external components and enables customers to achieve the very low jitter performance needed for high performance audio digital-to-analog converters (DAC) and/or analog-to-digital converters (ADC). The
• Multiple Sampling Frequencies: SCKO0
44.1
SCKO1
32, 44.1, 48, 64, 88.2, 96
SCKO2
32, 44.1, 48, 64, 88.2, 96
SCKO3
32, 44.1, 48 (for 768f S), 64, 88.2, 96 (for
PT7C4701 is ideal for MPEG-2 applications which use a 27MHz master clock such as DVD players, DVD addon cards for multimedia PCs, digital HDTV systems, and set-top boxes.
384fS) • Supply Voltage: Dual power: +5V for PLL and
Ordering Information
+3.3V or single power: +3.3V • Control Mode: serial (software) and parallel
Part Number
(hardware)
PT7C4701H PT7C4701HE
PT0198(04/05)
1
Package 20-Pin 20-Pin
SSOP
SSOP Lead free
Ver:2
Data Sheet PT7C4701 PLL Multi-Clock Generator |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Block Diagram
ML/
MD/ MC/
SR0
FS0 FS1
VDDP GNDP VDDB GNDB VDD GND
Mode Control I/F RST
Power Supply
VDD3 (only for 4701)
Reset
PLL2 XT1 OSC XT2
PLL1
SCKO0
PT0198(04/05)
2
Counter Q
Counter P
SCKO1
SCKO2
SCKO3
Ver:2
Data Sheet PT7C4701 PLL Multi-Clock Generator |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Pin Assignment PT7C4701 ML/SR0
１
２０
MC/FS1
MODE
２
１９
MD/FS0
VD D
３
１８
RST
GND
４
XTO
５
XTI
１７
SCKO2
１６
VDDO
６
１５
GND0
GNDP
７
１４
SCKO1
VDDP
８
１３
SCKO3
VDD3
９
１２
SCKO0
１０
１１
MON
MO
SSOP 20
Pin Description Pin
Name
Type
1
ML/SR0
I
2
MODE
I
19
MD/FS0
I
20
MC/FS1
I
18
RST
I
5
XTO
O
27MHz Crystal. left open when using external 27MHz clock
6 10 11 12 13 14 17 3 4 7 8 15 16 9
XTI MO MON SCKO0 SCKO3 SCKO1 SCKO2 VDD GND GNDP VDDP GNDO VDDO VDD3
I O O O O O O P P P P P P P
27MHz Oscillator Input / External 27MHz Input. 27 MHz fixed-frequency output 27 MHz fixed-frequency output (inverted) 33.8688 MHz fixed-frequency output 768fs output 256fs output 384fs output 5 V or 3.3V supply (Digital block) Ground (Digital block) Ground (PLL block) 5 V or 3.3V supply (PLL block) Ground (output buffer) 3.3 V supply (output buffer) 3.3 V supply (output buffer)
PT0198(04/05)
Description Control signal input. (Schmitt trigger input with pull-down resistor) In serial mode: latch enable signal (ML). When MODE = 0, ML is select. In parallel mode: sampling rate select signal. Mode select signal. (Schmitt trigger input with pull-down resistor) LOW: serial mode. HIGH: parallel mode Control signal input. (Schmitt trigger input with pull-down resistor) In serial mode: control data input signal. When MODE = 0, MD is select. In parallel mode: sampling frequency select signal Control signal input. (Schmitt trigger input with pull-down resistor) In serial mode: clock signal. When MODE = 0, MC is select. In parallel mode: sampling frequency select signal LOW-level reset input. (Schmitt trigger input with pull-up resistor)
3
Ver:2
Data Sheet PT7C4701 PLL Multi-Clock Generator |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Function Description Master Clock The PT7C4701 consists of a dual PLL clock and master clock generator which generates four system clocks and two buffered 27MHz clocks from a 27MHz master clock. The PLL is designed to accept a 27MHz master clock or crystal oscillator. The master clock can be either a crystal oscillator placed between XTI and XTO, or an external input to XTI. If an external master clock is used, XTO should be open. Fig 1. PT7C4701 Master Clock Generator Connection Diagram.
MCKO
MCKO Buffer
Buffer MCKO MCKO
MCKO MCKO Buffer
Buffer C1
XTI
C2
XTO
C1.C2 = 10pF to 33pF
Crystal OSC Circuit
27MHz Internal External Clock Master Clock
XTI Crystal OSC Circuit
XTO
PT7C4701
27MHz Internal Master Clock
PT7C4701
Crystal Resonator Connection
External Clock Input
Fig 2. PT7C4701 External Master Clock Timing Requirement.
tXT1H 2.0V XT1 0.8V
Description System clock pulse width HIGH System clock pulse width LOW
Sym. Min Typ Max Unit t XT1H 15 ns t XT1L 15 ns
tXT1L
PT0198(04/05)
4
Ver:2
Data Sheet PT7C4701 PLL Multi-Clock Generator |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
System Clock Output The PT7C4701 provides a low jitter, high accuracy clock. SCKO0 is a fixed frequency clock which is 33.8688MHz (768 x 44.1kHz) for a CD-DA DSP. The output frequency of the remaining clocks is determined by the sampling frequency (fS) by software or hardware control. SCKO1 and SCKO2 output 256fS and 384fS systems clocks, respectively. SCKO3 output is 768fS if the sampling frequency is 32kHz, 44.1kHz, 48kHz, or the output is 384fS if the sampling frequency is 64kHz, 88.2kHz, or 96kHz. Table 1 shows PT7C4701 sampling frequency and output clock frequency. Table 1. Sampling Frequencies and Master Clock Output Frequencies Sampling Rate Sampling Frequency (kHz) Output clock frequency (MHz) Standard
Double
SCKO0 (MHz)
SCKO1 (MHz)
SCKO2 (MHz)
SCKO3 (MHz)
33.8688
8.192
12.288
24.576
44.1
33.8688
11.2896
16.9344
33.8688
48
33.8688
12.288
18.4320
36.8640
64
33.8688
16.384
24.576
24.576
88.2
33.8688
22.5792
33.8688
33.8688
96
33.8688
24.576
36.8640
36.8640
32
Response time from power-on (or applying the clock to XTI) to SCKO settling time is typically 15ms. Delay time from sampling frequency change to SCKO settling time is 40ms (max) for PT7C4701. External buffers are recommended on all output clocks in order to avoid degrading the jitter performance of the PT7C4701. Fig 3. System Clock Transient Timing Chart. ML 3 Clocks of MCKO SCKO2 SCKO3 SCKO4
SCKO1
PT0198(04/05)
Stable
tS Clock Transistion Region
Stable
33.86888MHz
5
Ver:2
Data Sheet PT7C4701 PLL Multi-Clock Generator |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Reset The PT7C4701have an internal power-on reset circuit, and have an external forced reset (RST, pin 18). The mode register default settings for software mode are initialized by reset. Throughout the reset period, all clock outputs are enabled with the default settings. Initialization for the internal power-on reset is done automatically during 1024 master clocks at VDD > 2.2V (1.8V to 2.6V). When using the internal power-on reset, RST should be HIGH. Power-on reset timing is shown in Fig 4. RST (pin 18) accepts an external forced reset by RST = L. Initialization (reset) is done when RST = L and 1024 master clocks after RST = H. External reset timing is shown in Fig 5 and 6. Fig 4. power-on reset timing
2.6V VDD 2.2V 1.8V Reset Reset Removal Internal Reset 1024 System Clock Periods Master Clock
Fig 5. external Reset Timing
RST
tRST Reset Reset Removal
Internal Reset 1024 System Clock Periods Master Clock
Fig 6. reset pulse timing requirement
１．４Ｖ
ＲＳＴ ｔＲＳＴ System Clock Pulse Width Low
PT0198(04/05)
t RST
6
20ns
(min)
Ver:2
Data Sheet PT7C4701 PLL Multi-Clock Generator |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Function Control The built-in function of the PT7C4701 can be controlled in the software mode (serial mode), which uses a three-wire interface by ML (pin 1), MC (pin 20), and MD (pin 19), when MODE (pin 2) = L. They can also be controlled in the hardware mode (parallel mode) which uses SR0 (pin 1), FS1 (pin 20) and FS0 (pin 19), when MODE (pin 2) = H. The selectable functions are shown in Table 2. Table 2. selectable Functions. Item
•
Function
Hardware mode (MODE = H) Software mode (MODE = L)
1
Sampling Frequency Select (32kHz, 44.1kHz, 48kHz)
Y
Y
2
Sampling Rate Select (Standard/Double)
Y
Y
3
Each Clock Output Enable/Disable
N
Y
Hardware Mode (MODE = H)
Sampling Group Select FS1 (Pin 20)
FS0 (Pin 19)
SAMPLING GROUP
L
L
48kHz
L
H
44.1kHz
H
L
32kHz
H
H
Reserved
Sampling Rate Select
•
SR0 (Pin 1)
Sampling rate select
L
Standard
H
Double
Software Mode (MODE = L)
The built-in functions of the PT7C4701 is controlled through a 16-bit program register. This register is loaded using MD. After the 16 data bits are clocked in using the rising edge of MC, ML is used to latch the data into the register. The software mode control format is shown in Fig 7. Fig 7. Software Mode Control Format.
ML (pin 1) MC (pin 20) MD (pin 19)
PT0198(04/05)
7
Ver:2
Data Sheet PT7C4701 PLL Multi-Clock Generator |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Table 3. PT7C4701 Register Mapping. Bit
Bit name
Description
D15
Address
0
D14
1
D13
1
D12
1
D11
0
D10
0
D9
CE6
MON output 1 enable (default) / disable
D8
CE5
MO output 1 enable (default) / disable
D7
CE4
SCKO3 output 1 enable (default) / disable
D6
CE3
SCKO2 output 1 enable (default) / disable
D5
CE2
SCKO1 output 1 enable (default) / disable
D4
CE1
SCKO0 output 1 enable (default) / disable
D3
RSV
Fixed as LOW
D2
R2
D1
R1
D0
R0
Sampling frequency select (see Table 3.2)
Table 3.2. PT7C4701 sampling frequency select
Table 3.1. PT7C4701 sampling rate select R2
Sampling rate
R1
R0
Sampling group
0
Standard (default)
0
0
48 kHz (default)
1
Double
0
1
44.1 kHz
1
0
32 kHz
1
1
Reserved
PT0198(04/05)
8
Ver:2
Data Sheet PT7C4701 PLL Multi-Clock Generator |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Application Information +5V or +3.3V 22uF - 47uF (1)
C1
C2
22uF - 47uF (1)
+3.3V
PT7C4701 Mode Control
MC/FS1 MODE 0.1uF and 10uF(1) VDD
MD/FS0 RST
C3 (2)
GND
SCKO2
XTO
VDDO
XTI
GNDO
C5
C4 0.1uF and 10uF(1)
GNDP
SCKO1
VDDP
SCKO3
VDD3
SCKO0
MO
0.1uF and 10uF (1)
Clock Output(3)
MON
NOTES: (1) 0.1uF ceramic and 10uF tantalum capacitor typical, depending on quality of power supply and pattern layout. (2) 27MHz quartz crystal and 18pF through two 30pF ceramic capacitors. (3) To achieve best possible jitter performance, it is recommended to minimize the load capacitance on the clock output.
PT0198(04/05)
9
Ver:2
Data Sheet PT7C4701 PLL Multi-Clock Generator |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Maximum Ratings Storage temperature ................................................................. -55 to 150OC Ambient Operating Temperature .............................................. -10 to 85OC Supply Voltage to Ground Potential (VCC) ............................. -0.3 to +6.5V Supply Voltage Differences ................................................................. +0.1V GND Voltage Differences ..................................................................... +0.1V Digital Input Voltage .......................................................... -0.3 to Vcc+0.3V Digital Output Voltage .....................................................-0.3 to VccB+0.3V Input Current (any pins except supplies ........................................ +10mA Power Dissipation ..............................................................................300mW
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics PT7C4701 All specifications at TA = +25OC, VDD = VDDP = 4.5 to 5.5V, VDDO = VDD3 = 2.7 to 3.6V, 27MHz external clock input and fS = 48kHz, unless otherwise noted. Description Test Conditions Min Typ Max Unit Power Supply Requirement Voltage range:
VDD, VDDP
4.5
5
5.5
V
VDDO, VDD3
2.7
3.3
3.6
V
32
45
mA
Supply current: IDD
VDD = VDDP = 5V, VDDO = VDD3 = +3.3V, external 27MHz master clock, fS = 48kHz, no load
Input/Output Input threshold: VIH1
2.0
VIL1
Input current:
0.8 0.7 VDD
V
VIH2
XTI
VIL2
XTI
0.3VDD
V
IIH1 (1)
VIN = VDD
150
uA
IIL1
(1)
VIN = 0V
-1
uA
IIH2
(2)
RST, VIN = VDD
1
uA
IIL2
(2)
V
RST, VIN = 0V
-150
uA
IIH3
XTI, VIN = VDD
40
uA
IIL3
XTI, VIN = 0V
-40
uA
Output driving: VOH
IOH = -2mA
VDDO-0.4
VOL IOL = 4mA NOTES: (1) ML, MC, MD, MODE (Schmitt-trigger input with internal pull-down resistor). (2) RST. Schmitt trigger input, internal pull-up.
PT0198(04/05)
V
10
V 0.4
V
Ver:2
Data Sheet PT7C4701 PLL Multi-Clock Generator |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
All specifications at TA = +25OC, VDD = VDDP = VDDO = VDD3 = 3.0 to 3.6V, 27MHz external clock input and fS = 48kHz, unless otherwise noted. Description Test Conditions Min Typ Max Unit Power Supply Requirement Voltage range:
VDD, VDDP
3.0
Supply current: IDD
VDD = VDDP = 5V, VDDO = VDD3 = +3.3V, external 27MHz master clock, fS = 48kHz, no load
3.3
3.6
V
10
30
mA
Input/Output Input threshold: VIH1
2.0
V
VIL1
Input current:
0.8
V
VIH2
XTI
0.7 VDD
V
VIL2
XTI
0.3VDD
V
IIH1 (1)
VIN = VDD
100
uA
IIL1
(1)
VIN = 0V
-1
uA
IIH2
(2)
RSTN, VIN = VDD
1
uA
IIL2
(2)
RSTN, VIN = 0V
-100
uA
IIH3
XTI, VIN = VDD
40
uA
IIL3
XTI, VIN = 0V
-40
uA
Output driving: VOH
IOH = -2mA
VDDO-0.4
V
VOL IOL = 4mA NOTES: (1) ML, MC, MD, MODE (Schmitt-trigger input with internal pull-down resistor). (2) RST Schmitt trigger input, internal pull-up.
0.4
V
AC Characteristics Fig 8. PT7C4701 software control timing ｔＭＨＨ
ｔＭＬＬ ＭＬ（Ｐｉｎ １）
１．４Ｖ ｔＭＬＳ
ｔＭＣＨ
ｔＭＣＬ
ｔＭＬＨ
ＭＣ （Ｐｉｎ ２０）
ｔＭＬＳ １．４Ｖ
ｔＭＣＹ １．４Ｖ
ＭＤ （Ｐｉｎ １９） ＭＳＢ
PT0198(04/05)
ｔＭＤＳ
ｔＭＤＨ
11
ＬＳＢ
Ver:2
Data Sheet PT7C4701 PLL Multi-Clock Generator |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
PT7C4701 All specifications at TA = +25oC, VDD = VDDP = +5V, VDDO = +3.3V, 27MHz crystal, unless otherwise noted. Description Test Conditions Min Typ
Max
Unit
Sampling Frequency (fS) Standard fS
32
44.1
48
kHz
Double fS
64
88.2
96
kHz
26.73
27
27.27
MHz
Master Clock (MKO, MON) Master clock frequency Clock jitter (4)
300
Clock duty cycle (crystal) Clock duty cycle (external)
ps
MO
40
49
60
%
MON
40
56
60
%
MO
40
%
MON
60
%
Phase Lock Loop (PLL) Generated system clock frequency: SCKO1
Fixed
SCKO2
256fS
8.192
24.576
MHz
SCKO3
384fS
12.288
36.864
MHz
768fS, 384fS
24.576
36.864
MHz
SCKO4 Generated Clock Rise Time
(3)
33.8688
MHz
20% to 80% VDDO
5
ns
Generated Clock Fall Time (3)
80% to 20% VDDO
5
ns
Generated Clock Duty Cycle
SCKO1, SCKO3, SCKO4
40
50
60
%
SCKO2 (standard)
40
50
60
%
(5)
25
33
40
%
SCKO2 (double) Generated Clock Jitter (4)
Settling Time
(refer for design)
Power-Up Time (refer for design)
SCKO1,SCKO4
300
ps
SCKO3
650
ps
SCKO2
550
ps
To Programmed Frequency (Fig 3) To Programmed Frequency
15
Software Control Timing (Fig 8)
20
ms
30
ms MC
Pulse Cycle Time - t MCY
100
ns
MC Pulse Width LOW - t MCL
40
ns
MC Pulse Width HIGH - t MCH
40
ns
MD Hold Time - t MDH
40
ns
MD Set-Up Time - t MDS
40
ns
ML Low Level Time - t MLL
16xt MCY
ns
ML High Level Time- t MHH
200
ns
40
ns
ML Hold Time
(6)
- t MLH (7)
ML Set-Up Time - t MLS 40 ns Note: (3) MO, MON, SCKO3, SCKO2, SCKO1, and SCKO0. (4) Jitter performance is specified as standard deviation of jitter under 27MHz crystal oscillation. (5) When SCKO2 is set to double rate clock output, its duty cycle is 33%. (6) MC rising edge for LSB to ML rising edge. (7) ML rising edge to the next MC rising edge. If the MC Clock is stopped after the LSB, any ML rising time is accepted. PT0198(04/05)
12
Ver:2
Data Sheet PT7C4701 PLL Multi-Clock Generator |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
PT7C4701 All specifications at TA = +25oC, VDD = VDDP = VDDO = +3.3V, 27MHz crystal, unless otherwise noted. Description Test Conditions Min Typ
Max
Unit
Sampling Frequency (fS) Standard fS
32
44.1
48
kHz
Double fS
64
88.2
96
kHz
26.73
27
27.27
MHz
Master Clock (MKO, MON) Master clock frequency Clock jitter
(4)
300
Clock duty cycle (crystal) MO MON
ps
40
46
60
%
40
55
60
%
Phase Lock Loop (PLL) Generated system clock frequency: SCKO1
Fixed
SCKO2
256fS
8.192
24.576
MHz
SCKO3
384fS
12.288
36.864
MHz
768fS, 384fS
24.576
36.864
MHz
SCKO4 Generated Clock Rise Time Generated Clock Fall Time
(3)
(3)
Generated Clock Duty Cycle
20% to 80% VDDO
Generated Clock Jitter
Settling Time
(refer for design)
Power-Up Time
(refer for design)
MHz
2.8
80% to 20% VDDO
ns
2.8
ns
SCKO1, SCKO3, SCKO4
40
50
60
%
SCKO2 (standard)
40
50
60
%
(5)
25
33
40
%
SCKO2 (double) (4)
33.8688
SCKO1, SCKO4
350
ps
SCKO2(standard)
650
ps
SCKO2 (double),SCKO3
850
ps
To Programmed Frequency (Fig 3) To Programmed Frequency
15
20
ms
30
ms
Software Control Timing (Fig 8) MC Pulse Cycle Time - t MCY
100
ns
MC Pulse Width LOW - t MCL
40
ns
MC Pulse Width HIGH - t MCH
40
ns
MD Hold Time - t MDH
40
ns
MD Set-Up Time - t MDS
40
ns
ML Low Level Time - t MLL
16xt MCY
ns
ML High Level Time- t MHH
200
ns
ML Hold Time (6) - t MLH
40
ns
(7)
ML Set-Up Time - t MLS 40 ns Note: (3) MO, MON, SCKO3, SCKO2, SCKO1, and SCKO0. (4) Jitter performance is specified as standard deviation of jitter under 27MHz crystal oscillation. (5) When SCKO2 is set to double rate clock output, its duty cycle is 33%. (6) MC rising edge for LSB to ML rising edge. (7) ML rising edge to the next MC rising edge. If the MC Clock is stopped after the LSB, any ML rising time is accepted. PT0198(04/05)
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Ver:2
Data Sheet PT7C4701 PLL Multi-Clock Generator |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Mechanical Information H/HE (20-Pin SSOP)
20
.197 .220
5.00 5.60
.004 .009
0.55 0.95
1 .272 .295 6.90 7.50
.078 2.00
0.09 0.25
.022 .037
.291 .322 7.40 8.20
Max SEATING PLANE
.002 .0256 BSC 0.65
X.XX X.XX
.0098 Max
0.050
Min
0.25
DENOTES DIMENSIONS IN MILLIMETERS
Note:
1) Controlling dimensions in millimeters. 2) Ref: JEDEC MO - 150AE
PT0198(04/05)
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Ver:2
Data Sheet PT7C4701 PLL Multi-Clock Generator |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Notes
Pericom Technology Inc. Email:
[email protected]
Web Site: www.pti.com.cn, www.pti-ic.com
China:
No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181
Asia Pacific:
Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 Fax: (852)- 2243 3667
U.S.A.:
3545 North First Street, San Jose, California 95134, USA Tel: (1)-408-435 0800 Fax: (1)-408-435 1100
Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation. PT0198(04/05)
15
Ver:2
