Transcript
Output Parallel-to-Serial Logic Resources (OSERDESE2)
Output Parallel-to-Serial Logic Resources (OSERDESE2) The OSERDESE2 in 7 series devices is a dedicated parallel-to-serial converter with specific clocking and logic resources designed to facilitate the implementation of high-speed source-synchronous interfaces. Every OSERDESE2 module includes a dedicated serializer for data and 3-state control. Both data and 3-state serializers can be configured in SDR and DDR mode. Data serialization can be up to 8:1 (10:1 and 14:1 if using OSERDESE2 Width Expansion). 3-state serialization can be up to 14:1. There is a dedicated DDR3 mode to support high-speed memory applications. Figure 3-13 shows a block diagram of the OSERDESE2, highlighting all the major components and features of the block. X-Ref Target - Figure 3-13
3-State Parallel-to-Serial Converter
TCE TBYTEIN T1-T4
TFB TBYTEOUT TQ
CLK CLKDIV RST
OCE D1 D2 D3 D4 D5 D6 D7 D8
OQ
Data Parallel-to-Serial Convert OFB UG471_c3_13_111011
Figure 3-13:
OSERDESE2 Block Diagram
Data Parallel-to-Serial Converter The data parallel-to-serial converter in one OSERDESE2 blocks receives two to eight bits of parallel data from the fabric (14 bits if using OSERDESE2 Width Expansion), serializes the data, and presents it to the IOB via the OQ outputs. Parallel data is serialized from lowest order data input pin to highest (i.e., data on the D1 input pin is the first bit transmitted at the OQ pins). The data parallel-to-serial converter is available in two modes: single-data rate (SDR) and double-data rate (DDR). The OSERDESE2 uses two clocks, CLK and CLKDIV, for data rate conversion. CLK is the high-speed serial clock, CLKDIV is the divided parallel clock. CLK and CLKDIV must be phase aligned. See OSERDESE2 Clocking Methods. Prior to use, a reset must be applied to the OSERDESE2. The OSERDESE2 contains an internal counter that controls dataflow. Failure to synchronize the reset deassertion with the CLKDIV will produce an unexpected output.
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Chapter 3: Advanced SelectIO Logic Resources
3-State Parallel-to-Serial Conversion In addition to parallel-to-serial conversion of data, an OSERDESE2 module also contains a parallel-to-serial converter for 3-state control of the IOB. Unlike data conversion, the 3-state converter can only serialize up to four bits of parallel 3-state signals. The 3-state converter cannot be cascaded.
OSERDESE2 Primitive The OSERDESE2 primitive is shown in Figure 3-14. X-Ref Target - Figure 3-14
OQ
CLK
OFB
CLKDIV
TQ
D1
TFB D2 TBYTEOUT D3 SHIFTOUT1 D4
SHIFTOUT2
D5
OSERDESE2 Primitive
D6 D7 D8 T1 T2 T3 T4
TCE OCE TBYTEIN RST SHIFTIN1 SHIFTIN2 UG471_c3_14_041712
Figure 3-14:
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OSERDESE2 Primitive
7 Series FPGAs SelectIO Resources User Guide UG471 (v1.3) October 31, 2012
Output Parallel-to-Serial Logic Resources (OSERDESE2)
OSERDESE2 Ports Table 3-6 lists the available ports in the OSERDESE2 primitive. Table 3-6:
OSERDESE2 Port List and Definitions
Port Name
Type
Width
Description
OQ
Output
1
Data path output to IOB only. See Data Path Output - OQ.
OFB
Output
1
Data path output feedback to ISERDESE2 or connection to ODELAYE2. See Output Feedback.
TQ
Output
1
3-state control output to IOB. See 3-state Control Output - TQ.
TFB
Output
SHIFTOUT1
Output
1
Carry output for data width expansion. Connect to SHIFTOUT1 of slave OSERDESE2. See OSERDESE2 Width Expansion.
SHIFTOUT2
Output
1
Carry output for data width expansion. Connect to SHIFTOUT2 of slave OSERDESE2. See OSERDESE2 Width Expansion.
CLK
Input
1
High-speed clock input. See High-Speed Clock Input - CLK.
CLKDIV
Input
1
Divided clock input. Clocks delay element, deserialized data, Bitslip submodule, and CE unit. See Divided Clock Input - CLKDIV.
D1 to D8
Input
TCE
Input
1
3-state clock enable. See 3-state Signal Clock Enable - TCE.
OCE
Input
1
Output data clock enable. See Output Data Clock Enable - OCE.
TBYTEIN
Input
1
Byte group 3-state input.
TBYTEOUT
Input
1
Byte group 3-state output.
RST
Input
1
Active High reset.
SHIFTIN1
Input
1
Carry input for data width expansion. Connect to SHIFTIN1 of master OSERDESE2. See OSERDESE2 Width Expansion.
SHIFTIN2
Input
1
Carry input for data width expansion. Connect to SHIFTIN2 of master OSERDESE2. See OSERDESE2 Width Expansion.
T1 to T4
Input
3-state control output to fabric. See 3-state Control Output - TFB.
1 (each) Parallel data inputs. See Parallel Data Inputs - D1 to D8.
1 (each) Parallel 3-state inputs. See Parallel 3-state Inputs - T1 to T4.
Data Path Output - OQ The OQ port is the data output port of the OSERDESE2 module. Data at the input port D1 will appear first at OQ. This port connects the output of the data parallel-to-serial converter to the data input of the IOB. This port can not drive the ODELAYE2; the OFB pin must be used.
Output Feedback from OSERDESE2 - OFB The output feedback port (OFB) is the serial (high-speed) data output port of the OSERDESE2 for use with the ODELAYE2 primitive, or the OFB port can be used to send out serial data to the ISERDESE2. See Output Feedback.
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