Parker Block Diagram - Alltechies Support Area

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A B C D E Battery Charger ISL88731 Parker Block Diagram Clock Generator ICS 951463 4 Intel Mobile CPU Yonah / Merom ULV FSB:533Mhz 4 5,6 HOST BUS 200-PIN DDR2 SODIMM FSB 533MHz INPUTS OUTPUTS +PWR_SRC +PBATT CPU DC/DC ADP3207 4 INPUTS OUTPUTS +PWR_SRC +VCC_CORE System DC/DC DDRII 533/667MHz RS600ME ISL6236/MAX8778 ON-BOARD RAM 1G CELL X 8 12,13,14 +3.3V_RTC_LDO INTEGRATED GRAPHICS DDRII 533/667MHz PCI-EXPRESS(4) UNBUFFERED DDR2 SODIMM Socket 15 Power Switch31 RGB CRT +1.8V_SUS Express Card PORT6 Slot 54mm PCIE3 16 +1.8V_SUS V_DDR_NB_REF Mini-Card PCIE2 32 802.11a/g/n ATI 33 SB600 SD card 8 in1 26 TI 7402 ATA 66/ 100/133 LPC I/F AZALIA SPI MAX9789A SPI RJ45 CONN28 27 EC SMSC MEC5025 36 30 1 Touch Pad 37 KBC SMSC ECE1077 Int. KB 03/22/2007 37 37 2 L1:TOP L2:Signal L3:GND L4:Signal L5:GND L6:VCC L7:Signal L8:GND L9:Signal L10:BOTTON SIO Expander SMSC ECE5021 35 SMBus INT.SPKR BCM5756ME Giga LAN LPC TPM 1.2 PCIE0 SPI FLASH 33 2MB Speaker AMP. Headphone AMP. +1.2V_SUS PCB LAYER Digi Tizer PORT3 17 BIOS Digital MIC Array LINE OUT 18,19,20,21,22 SPI Azalia CODEC STAC 9205 29 +PWR_SRC USB*2 PORT0.1 P-USB*1 PORT2 34 ACPI 2.0 2 46 +NB_VCORE Bluetooth PORT7 31 USB2.0 (10) SATA2 (4) 1394 2 port 24,25 PCI/PCI BRIDGE MIC IN ISL6236/MAX8778 High Definition Audio PCI BUS Card reader +1.05V_VCCP System DC/DC Biometric PORT5 17 USB 2.0/1.1 ports (10) 1394 CONN26 1394 45 +1.8V_SUS +PWR_SRC IDE 3 ISL6236/MAX8778 SIM CONN 32 23 PATA HDD 44 +0.9V_DDR_VTT System DC/DC Mini-Card PORT9 PCIE1 32 WWAN ALINK x4 44 +1.5V_RUN LDO TPS51100 31 7,8,9,10,11 CRT EMC4001 +3.3V_ALW LDO MAX8794 PCI Express (4) Thermal Sensor +5V_ALW +PWR_SRC LVDS 3 43 OUTPUTS INPUTS DUAL DDR2 CHANNEL SDVO CRT Port 42 Support Aero Glass LVDS 12.1WXGA 17 Project code:91.4S701.001 PCB P/N :48.4S701.0SC REVISION :06240-SC 39,40 1 Wistron Corporation DVI CRT 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. SMBus S/PDIF USB 2.0 RJ45 Title PORT8 Media-Slice BLOCK DIAGRAM 38 Size A3 Document Number Rev A B C D SC Parker Date: Thursday, March 22, 2007 Sheet E 1 of 53 A B C CLK-GEN ICS951463 EXT CLK FREQUENCY SELECT TABLE(MHZ) FSC FSB FSA CPU SRC PCI 1 0 1 100 100 33 14.31 0 0 1 133 100 33 14.31 0 1 1 166 100 33 14.31 0 1 0 200 100 33 14.31 0 0 0 266 100 33 14.31 1 0 0 333 100 33 14.31 1 1 0 400 100 33 14.31 1 1 1 Resv 100 33 14.31 4 NB ALINK EXPRESS CARD SB ALINK WLAN LOM CLKSRC 0 WWAN ATIGCLK 1 NB-PCIEX16 ATIGCLK 2 NO -USED CLKREQC# P01-BLOCK DIAGRAM P19-SB600-IDE&SATA$SPI(2/5) P02-Table Content P20-SB600-USB&AZALIA&GPIO(3/5) P38-MEDIA SLICE P21-SB600-Power(4/5) P39-DCIN/BATT CONN. P04-CLK GEN(ICS951463) P22-SB600-Strapping Pin(5/5) P40-Charger P05-CPU-01-FSB P23-FAN, EMC4001 P41-BATTERY SELECT P06-CPU-02-POWER P24-PCI7402-1 P42-ADP3207A_CPU_Core P07-RS600ME-AGTL(1/5) P25-PCI7402-2 P43-ISL6236_MAX8778_5V/3D3V P08-RS600ME-ALINK/PCIE-2(2/5) P26-SD/1394 P44-MAX8794_1D5V/TPS51100_0D9V P09-RS600ME-MEMORY I/F (3/5) P27-LAN BCM5756ME P45-ISL6236_MAX8778_1D8V/1D05V P10-RS600ME-LVDS/CRT/CLK4(4/5) P28-LAN Connector P46-ISL6236_MAX8778_1D2V/NB_Core P11-RS600ME-5(5/5) P29-CODEC STAC 9205 P47-POWER ENABLE P13-ON BOARD MEMORY ATI NB-RS600ME STRAP PIN LOW 0 MOBILE GRAPHICS DEVICE ★ NB_VSYNC(DAC_VSYNC: STRAP_MOBILE_GFX) DESKTOP GRAPHICS DEVICE 3 NB_HSYNC(DAC_HSYNC: STRP_INTGFX_DISABLE) ENABLE NB_SDVO_CTRLDATA ★ (STRP_DATA: STRP_MEMSTRAPS) STRP_DATA SELECT MEMORY CHA A AS DEBUG BUS DDR2 ★ NORMAL MODE ★ P33-PATA HDD/BIOS/Pen P51-EMI/HOLE P16-CRT P34-P-USB/USB P52-HISTORY P17-LVDS P35-KBC MEC5025 P18-SB600-CPU&LPC&PCI&PCIE(1/5) P36-SIO ECE5021 SMBUS TABLE SOURCE SIGNAL NAME NB RS600ME I2C_CLK/DAC_SDA CRT/SLICE CRT I2C_CLK/I2C_DATA LVDS I2C_CLK/DDC_SDA DVI SB600 SCL1/SDA1 LAN / WLAN / WWAN / EXPRESS CARD/SO-DIMM MEC5025 AB1A_CLK/AB1A_DATA SLICE CONN. AB1B_CLK/AB1B_DATA INVERTER / LIGHT SENSOR USB TABLE AB1C_CLK/AB1C_DATA BATTERY CONN. AB1D_CLK/AB1D_DATA BATTERY-SLICE CONN. USB0 Ext Side 1 AB1E_CLK/AB1E_DATA P-USB / CHARGER / THERMAL USB1 Ext Side 2 AB1H_CLK/AB1H_DATA CLK-GEN USB2 POWER USB IMCLK/IMDAA TOUCH PAD USB3 Digi Tizer PCIE 2 MINI WLAN PCIE 3 EXPRESS CARD ATI SB-SB600 STRAP PIN Strap name LOW 0 HIGH 1 AC_SDOUT SB_AC_SDOUT IGNORE DEBUG STRAPS ★ DEBUG STRAPS RTC_CLK SB_RTCCLK EXTERNAL RTC PCI_CLK4CLK_SB_PCI4 EXTERNAL 48MHZ PCI_CLK0 CLK_SB_PCI0 Default 1 ★ INTERNAL PLL48 ★ AMD CPU USB4 Default ROM TYPE 0 1 0 1 USB5 Biometric USB6 Express Card IDSEL INT USB7 BLUETOOTH D1 OTP USB8 Media Slice D2 CPU edge diode USB9 MiniCard WWAN D3 Bottom SoDIMM D4 D5 skin temp sensor at the bottom of the MB located within the triangle of MCH/CPU/ DRAM RS600ME VCP1 Pwr Mon VCP2 WWAN AD17 G H PCI-CLK route REQ GNT PCICLK 2 MEC5025 1 1 PCICLK 5 BCM5756ME PCICLK 6 TI7402 LINKED DEVICES 2 EMC4001 Thermal sensor mapping FWH LPCDefault SPI PCI PCI ROUTING 1394/ MEDIACARD ★ Default PCI_CLK1 0 0 1 1 INTERNAL RTC Default CLK_SB_PCI1 P50-POWER ON TIMING P15-DDR-B PCIE 1 MINI WWAN PCI_CLK6CLK_SB_PCI6 P49-POWER ON SEQUENCE SMBUS TABLE PCIE 0 LOM BCM5756ME INTEL CPU P48-POWER ON LOGIC 3 SR600ME PCIE route 2 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Table Contsnt Size A3 Document Number Rev B C D SC Parker Date: Wednesday, March 21, 2007 A 4 DISABLE DDR3 (DDC_DATA: STRAP_MEMVMODE) P31-EXPRESS CARD/BT/SNIFFER P14-ON-BOARD MEMORY TERMINATIONP32-WLAN/WWAN HIGH 1 P37-ECE1077/TP/KBC P03-ITP Debug P12-ON BOARD MEMORY RESISTORS P30-AUDIO AMP Strap name E TABLE OF CONTENTS CLKREQA# B# C# MAP CLKSRC 7 CLKREQA# CLKSRC 5 CLKSRC 6 CLKSRC 2 CLKREQB# CLKSRC 4 REF D Sheet E 2 of 53 A B C D E SSID = CPU 4 4 CPU ITP Conn. TCK(PIN 5) TCK(PIN AC5) FBO(PIN 11) 3 3 5 ITP_TDI 1 1 R558 39D2R2F-L-GP 5 ITP_TCK 5,7,51 H_RESET# 5 ITP_BPM#5 ITP_TDO CLK_CPU_ITP# CLK_CPU_ITP 1 R561 XDP_TDO_FELX 2 22D6R2F-L1-GP H_RESET# ITP_BPM#5 1 R550 CPURST_FLEX# 2 22D6R2F-L1-GP ITP_BPM#4 5 ITP_BPM#4 ITP_BPM#3 5 ITP_BPM#3 ITP_BPM#2 5 ITP_BPM#2 ITP_BPM#1 5 ITP_BPM#1 ITP_BPM#0 5 ITP_BPM#0 ITP_DBRESET# 1 R559 R560 680R2J-3-GP 27D4R2F-L1-GP +1.05V_VCCP 29 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 H_CPURST# use pull-up Resistor close ITP connector 500 mil ( max ) DY 2 30 SCD1U10V2KX-4GP 2 2 C605 1 1 4,5,20,36 ITP_DBRESET# 2 ITP1 1 ITP_TCK 5 ITP_TDO 4 CLK_CPU_ITP# 4 CLK_CPU_ITP R557 150R2F-1-GP 2 51R2F-2-GP ITP_TMS ITP_TRST# 5 ITP_TMS 5 ITP_TRST# 2 R551 51R2F-2-GP 2 ITP_TDI R541 2 2 R552 150R2F-1-GP 1 +1.05V_VCCP 1 1 +3.3V_SUS 2 clk-gen may have leakage ,if use +3.3V_SUS +1.05VRUN use Decoupling Capacitor close ITP connector 100 mil ( max ) MLX-CON28-3-GP 20.K0116.028 ITP Debug Conn. 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title ITP Debug Size A3 Document Number Rev A B C D SC Parker Date: Wednesday, March 21, 2007 Sheet E 3 of 53 C D E CLK-GEN XTAL 200mA CLOSE TO PIN 14,23,26,33,36,48 CLOSE TO PIN 4 2CLK_XTAL1_R 1 R241 0R2J-2-GP 1 2 X4 XTAL-14D318M-2GP CLOSE TO PIN2 ,3 CLK_VDD48 CLK_VDDREF 4 1 48 VDD48 VDDREF VDDCPU 48MHZ_0 48MHZ_1 5 6 CLK_48M_0 CLK_48M_1 1 R226 1 R221 14 23 26 36 VDDSRC VDDSRC VDDSRC VDDSRC ATIGCLKC1 ATIGCLKT1 34 35 CLK_ATIC1 CLK_ATIT1 2 1 39 38 24 25 20 21 18 19 16 17 12 13 SRCCLKT0 SRCCLKC0 SRCCLKT2 SRCCLKC2 SRCCLKT4 SRCCLKC4 SRCCLKT5 SRCCLKC5 SRCCLKT6 SRCCLKC6 SRCCLKT7 SRCCLKC7 ATIGCLKC2 ATIGCLKT2 30 31 1 2 RN13 4 3 RN9 11 28 29 CLKREQA# CLKREQB# CLKREQC# CLK_SDATA 2 CLK_SCLK 1 SRN2K2J-1-GP 10 9 SMBDAT SMBCLK CLK_IREF CLK_EN#_R 2 2 0R2J-2-GP CLK_CPU_STOP# 0R2J-2-GP C633 SC33P50V2JN-3GP 40 8 51 52 SRN33J-5-GP-U SRN33J-5-GP-U SRN33J-5-GP-U 31 CARD_CLK_REQ# 32 MINI1CLK_REQ# 32 MINI2CLK_REQ# CLKREQA# B# C# INTERNAL 120K ohm PU +3.3V_RUN 3 4 RN77 CLOSE TO PIN 40 1 Layout swap 1 R572 1 R592 42,51 CLK_ENABLE# 18 H_CPU_STP# R535 475R2F-L1-GP DY 55 54 53 GNDSRC GNDSRC GNDSRC GNDSRC 15 22 27 37 GNDCPU GNDREF GND48 47 56 7 GNDATIG GNDA 32 41 RN14 RN11 CLK_REF0 CLK_REF1 CLK_REF2 CLK_CPU_BCLK# CLK_CPU_BCLK SRN22-3-GP CLK_NB_FSB# 3 CLK_NB_FSB 4 SRN33J-5-GP-U CLK_CPU_ITP# 3 CLK_CPU_ITP 4 SRN33J-5-GP-U CLK_SB_14M 2 2 33R2J-2-GP CLK_NB_14M CLK_SIO_14M 2 15R2J-GP 33R2J-2-GP 2 1 3 4 2 1 2 1 1 R593 1 R595 1 R594 CLK_NBLINK C609 SC3D3P50V2CN-GP CLK_NBLINK# 3 1 ITP DY 1 2 CLK_SBLINK C604 SC3D3P50V2CN-GP CLK_SBLINK# CLK_RESET_IN# RB751V-40-1-GP DY CLK_PCIE_MINI2 C595 SC3D3P50V2CN-GP CLK_PCIE_MINI2# 2N7002DW-7F-GP 2 DY 2 1 R607 1KR2J-1-GP 1 R610 1KR2J-1-GP 2 DY 100 100 33 14.31 1 R605 1 R609 1 R608 2 0 0 1 133 100 33 14.31 2 0 1 1 166 100 33 14.31 0 1 0 200 100 33 14.31 CLK_SB_14M 8K2R2J-3-GP CLK_NB_14M 8K2R2J-3-GP 2 CLK_SIO_14M 8K2R2J-3-GP X01 0 0 0 266 100 33 14.31 1 0 0 333 100 33 14.31 1 1 0 400 100 33 14.31 1 1 1 Resv 100 33 14.31 1 2 CLK_CPU_BCLK# C622 SC3D3P50V2CN-GP CLK_CPU_BCLK 1 1 CLKREQA# B# C# MAP CLKSRC 7 CLKREQA# CLKSRC 5 CLKSRC 6 CLKSRC 2 CLKREQB# CLKSRC 4 CLKREQC# NB ALINK EXPRESS CARD SB ALINK WLAN LOM CLKSRC 0 WWAN ATIGCLK 1 NB-PCIEX16 ATIGCLK 2 NO -USED DY 2 0 DY CLK_NBSRC# C585 SC3D3P50V2CN-GP CLK_NBSRC 1 1 DY CLK_NBLINK CLK_NBLINK# 2 1 RN74 SRN49D9F-GP CLK_PCIE_MINI1# 1 CLK_PCIE_MINI1 2 RN57 SRN49D9F-GP CLK_PCIE_LOM 2 CLK_PCIE_LOM# 1 RN60 SRN49D9F-GP CLK_PCIE_EXPCARD 2 CLK_PCIE_EXPCARD# 1 RN67 SRN49D9F-GP CLK_SBLINK 2 CLK_SBLINK# 1 RN71 SRN49D9F-GP CLK_PCIE_MINI2 1 CLK_PCIE_MINI2# 2 RN66 SRN49D9F-GP CLK_NB_FSB# 2 CLK_NB_FSB 1 RN73 SRN49D9F-GP CLK_CPU_ITP# 2 CLK_CPU_ITP 1 RN70 SRN49D9F-GP CLK_CPU_BCLK# 2 CLK_CPU_BCLK 1 RN75 SRN49D9F-GP CLK_NBSRC# 2 CLK_NBSRC 1 RN59 SRN49D9F-GP B D 4 3 3 4 2 3 4 3 4 4 3 3 4 3 4 3 4 3 4 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Clock Generator Size Document Number Custom C 3 4 Rev SC Parker Date: Wednesday, March 21, 2007 A 3 DY 2 2 1 R616 1KR2J-1-GP 1 R617 1KR2J-1-GP CPU_BSEL0_R 0R2J-2-GP CPU_BSEL1_R 0R2J-2-GP 2 CPU_BSEL2_R 0R2J-2-GP REF DY 2 2 5 CPU_BSEL2 1 R613 1 R618 1 R615 1 R606 1KR2J-1-GP 5 CPU_BSEL1 2 5 CPU_BSEL0 1 DY 2 2 1 R614 1KR2J-1-GP EXT CLK FREQUENCY SELECT TABLE(MHZ) DY CLK_CPU_ITP# C606 SC3D3P50V2CN-GP CLK_CPU_ITP 1 +1.05V_VCCP CLK_NB_FSB# C611 SC3D3P50V2CN-GP CLK_NB_FSB 2 35 CKG_SMBCLK PCI DY placed CAP closed CLK-GEN within 20 mm (80mil) DY SRC C635 SC3D3P50V2CN-GP ECE5032 TP176 TPAD28 DY CPU DY CLK_NB_14M CLK_SB_14M 20 CLK_NB_14M 10 CLK_PCIE_EXPCARD C592 SC3D3P50V2CN-GP CLK_PCIE_EXPCARD# FSC FSB FSA 2 CLK_CPU_ITP# 3 CLK_CPU_ITP 3 1 2 4 C634 SC3D3P50V2CN-GP DY 2 5 1 CLK_SB_14M NB FSB 2 4 3 1 2 CLK_SCLK 2 3,5,20,36 ITP_DBRESET# CPU CLK_NB_FSB# 10 CLK_NB_FSB 10 CLK_PCIE_LOM C582 SC3D3P50V2CN-GP CLK_PCIE_LOM# D11 CLK_SDATA 1 CLK_CPU_BCLK# 5 CLK_CPU_BCLK 5 CLK_PCIE_MINI1 C570 SC3D3P50V2CN-GP CLK_PCIE_MINI1# R229 4K7R2J-2-GP 6 35 CKG_SMBDAT CLK_USB_48M X01 +3.3V_RUN U47 DY 2 CLK_CPUC0 CLK_CPUT0 CLK_CPUC1 CLK_CPUT1 CLK_CPUC2 CLK_CPUT2 RN8 FSLA/REF0 FSLB/REF1 FSLC/REF2 NB PCIEX16 C615 SC3D3P50V2CN-GP +3.3V_RUN RN19 SRN2K2J-1-GP 2 IREF VTT_PWRGD#/PD CPU_STOP# RESET_IN# 49 50 45 46 43 44 CLK_NBSRC# 8 CLK_NBSRC 8 X01 ICS951463BGLFT-GP 2 2 +3.3V_ALW CARD_CLK_REQ# MINI1CLK_REQ# MINI2CLK_REQ# CPUCLKC0 CPUCLKT0 CPUCLKC1 CPUCLKT1 CPUCLKC2 CPUCLKT2 CLK_NBSRC# 3 CLK_NBSRC 4 SRN33J-5-GP-U 2 4 3 SRN33J-5-GP-U C623 SC3D3P50V2CN-GP CLK_SMCARD_48M 25 CLK_USB_48M 20 SB USB 2 1 2 RN7 CLK_SRCT0 CLK_SRCC0 CLK_SRCT2 CLK_SRCC2 CLK_SRCT4 CLK_SRCC4 CLK_SRCT5 CLK_SRCC5 CLK_SRCT6 CLK_SRCC6 CLK_SRCT7 CLK_SRCC7 SRN33J-5-GP-U RN4 CLK_SMCARD_48M CLK_USB_48M 1 4 3 SRN33J-5-GP-U 2 2 33R2J-2-GP 15R2J-GP 2 4 3 CLK_SMCARD_48M X01 1 1 2 1 2 CLK_SBLINK CLK_SBLINK# CLK_NBLINK CLK_NBLINK# 3 4 4 3 RN5 8 CLK_NBLINK 8 CLK_NBLINK# NB ALINK 2 1 1 2 CLK_PCIE_EXPCARD CLK_PCIE_EXPCARD# 18 CLK_SBLINK 18 CLK_SBLINK# SB ALINK CLK_XTAL0 CLK_XTAL1 2 CLK_PCIE_LOM CLK_PCIE_LOM# EXPRESS CARD 31 CLK_PCIE_EXPCARD 31 CLK_PCIE_EXPCARD# 3 2 3 1 RN3 27 CLK_PCIE_LOM 27 CLK_PCIE_LOM# LOM X1 X2 1 RN6 CLK_PCIE_MINI1 CLK_PCIE_MINI1# 32 CLK_PCIE_MINI1 32 CLK_PCIE_MINI1# WLAN VDDA VDDATIG 2 32 CLK_PCIE_MINI2 32 CLK_PCIE_MINI2# WWAN 42 33 1 CLK_PCIE_MINI2 CLK_PCIE_MINI2# 4 placed CAP closed CLK-GEN within 20 mm (80mil) CLK_VDDA +3.3V_RUN_CLK C327 SC27P50V2JN-2-GP CLOSE TO PIN 1 U36 SSID = CLOCK 2 CLK_XTAL1 2 1 C328 SC27P50V2JN-2-GP DY 1 R242 1MR2F-GP 2 1 2 1 C331 SC4D7U6D3V3KX-GP 1 2 CLK_VDDREF L33 BLM18BB221SN1D-GP 2 1 2 2 CLOSE TO PIN 42 +3.3V_RUN C322 SCD01U16V2KX-3GP 1 1 2 CLK_VDD48 L32 BLM18BB221SN1D-GP C330 SC4D7U6D3V3KX-GP C597 SCD01U16V2KX-3GP 1 +3.3V_RUN 2 C248 SC10U10V5KX-2GP 1 CLK_VDDA 1 2 L25 BLM18BB221SN1D-GP 2 C572 SCD1U10V2KX-4GP C603 SCD1U10V2KX-4GP 2 1 C578 SCD1U10V2KX-4GP 2 1 +3.3V_RUN C584 SCD1U10V2KX-4GP 2 1 C612 SCD1U10V2KX-4GP 2 1 C580 SCD1U10V2KX-4GP 2 1 1 2 4 C246 SC10U10V5KX-2GP 2 1 +3.3V_RUN_CLK 1 2 L26 BLM18PG181SN-3GP C329 SCD01U16V2KX-3GP CLK_XTAL0 +3.3V_RUN 1 200mA 1 200mA 1 1500mA 1 B 1 A Sheet E 4 of 53 A B C D E +1.05V_VCCP IC CPU YONAH U1500 1.33G BGA--P/N:UP954 IC CPU MEROM U7500 1.06G BGA--P/N:JW602 IC CPU YONAH U1400 1.2G BGA--P/N:FW289 H_A#[31..3] H_D#[63..0] 7 H_A#[31..3] 7 R546 4K7R2J-2-GP 2 H_D#[63..0] 1 R545 42 H_DPRSTP# H_REQ#[4..0] 7 2 H_DPRSTP#_2 0R2J-2-GP 3 H_REQ#[4..0] H_RS#[2..0] H_RS#[2..0] 7 2 4 1 SSID = CPU U87A A20M# FERR# IGNNE# H_STPCLK# H_INTR# H_NMI# H_SMI# H_STPCLK# H_INTR# H_NMI# H_SMI# D5 C6 B4 A3 STPCLK# LINT0 LINT1 SMI# TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 2 TP42 TP28 TP35 TP141 TP27 TP25 TP143 TP31 TP43 TP37 CPU_RSVD01 CPU_RSVD02 CPU_RSVD03 CPU_RSVD04 CPU_RSVD05 CPU_RSVD06 CPU_RSVD07 CPU_RSVD08 CPU_RSVD09 CPU_RSVD10 AA1 AA4 AB2 AA3 M4 N5 T2 V3 B2 C3 RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10] CPU_RSVD11 B25 RSVD[11] H_IERR# H_INIT# LOCK# H4 H_LOCK# RESET# RS[0]# RS[1]# RS[2]# TRDY# B1 F3 F4 G3 G2 H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY# HIT# HITM# G6 E4 H_HIT# H_HITM# CONTROL XDP/ITP SIGNALS THERM BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# THERMTRIP# BCLK[0] BCLK[1] 1 H_INIT# 18 H_THERMTRIP# U87B H_LOCK# 7 H_RESET# 3,7,51 H_TRDY# 7 H_HIT# 7 H_HITM# 7 ITP_BPM#0 3 ITP_BPM#1 3 ITP_BPM#2 3 ITP_BPM#3 3 ITP_BPM#4 3 ITP_BPM#5 3 ITP_TCK 3 ITP_TDI 3 ITP_TDO 3 ITP_TMS 3 ITP_TRST# 3 ITP_DBRESET# 3,4,20,36 7 H_DSTBN#0 7 H_DSTBP#0 7 H_DINV#0 and H_THERMDC routing Trace width and Spacing use 10 / 10 mil CPU_GTLREF0 close to Pin AD26 500 mil ( max ) H_THERMTRIP# 23 A22 CLK_CPU_BCLK A21 CLK_CPU_BCLK# CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4 RSVD[12] T22 CPU_RSVD12 TP7 TPAD28 RSVD[13] RSVD[14] RSVD[15] RSVD[16] RSVD[17] RSVD[18] RSVD[19] RSVD[20] D2 F6 D3 C1 AF1 D22 C23 C24 CPU_RSVD13 CPU_RSVD14 CPU_RSVD15 CPU_RSVD16 CPU_RSVD17 CPU_RSVD18 CPU_RSVD19 CPU_RSVD20 TP44 TP26 TP34 TP48 TP41 TP9 TP4 TP1 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 +1.05V_VCCP R57 1KR2F-3-GP 7 H_DSTBN#1 7 H_DSTBP#1 7 H_DINV#1 1 R378 1 R379 Change R846 to 51 ohm and Populate R843 for Yonah B0 Forward +1.05V_VCCP A B D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1 N22 K25 P26 R23 L25 L22 L23 M23 P25 P22 P23 T24 R24 L26 T25 N24 M24 N25 M26 D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# AD26 GTLREF TEST1 2 1KR2J-1-GP TEST2 2 51R2F-2-GP C26 TEST1 D25 TEST2 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 B22 B23 C21 BSEL[0] BSEL[1] BSEL[2] DY CPU_SEL MISC D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 W24 Y25 V23 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2 D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 AD23 AE24 AC20 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3 COMP[0] COMP[1] COMP[2] COMP[3] R26 U26 U1 V1 COMP0 COMP1 COMP2 COMP3 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# E5 B5 D24 D6 D7 AE6 H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# H_PSI# H_SEL0 H_SEL1 H_SEL2 133 0 0 1 166 0 1 1 Parker will use B0 version or later version C610 SC22P50V2JN-4GP DY C599 SC22P50V2JN-4GP 2 1 DY C581 SC22P50V2JN-4GP 2 1 DY C569 SC22P50V2JN-4GP 2 1 DY C550 SC22P50V2JN-4GP 2 1 H_CPUSLP# 7,18 DY C557 SC22P50V2JN-4GP 2 1 H_CPUSLP# 200R2F-L-GP DY C529 SC22P50V2JN-4GP 2 1 2 1 DY H_STPCLK# H_CPUSLP# H_IGNNE# H_INIT# H_NMI# H_SMI# H_INTR# H_A20M# C531 SC22P50V2JN-4GP 2 1 1 R547 DY THESE CAPS PLACE WITHIN 1.5" FROM CPU place cap close cpu pin 2 1 H_PWRGOOD 200R2F-L-GP H_THERMTRIP# 56R2J-4-GP 2 CPU_PROCHOT# 56R2J-4-GP 2 H_RESET# 54D9R2F-L1-GP 2 H_FERR# 56R2J-4-GP 2 ITP_BPM#4 54D9R2F-L1-GP 2 H_DPSLP# H_DPSLP# 18 470R2J-2-GP 2 E22 F24 E26 H22 F23 G25 E25 E23 K24 G24 J24 J23 H26 F26 K22 H25 H23 G22 J26 Yonah support DY 2 DY 4 CPU_BSEL0 4 CPU_BSEL1 4 CPU_BSEL2 H_THERMDC 1 2 H_THERMDA C461 SC2200P50V2KX-2GP DY H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0 V_CPU_GTLREF R54 2KR2F-3-GP C126 close to Pin A24 and Pin A25 1 R568 1 R476 1 R80 1 R512 1 R486 1 R182 1 R483 H_DPRSTP#_R 18 56R2J-4-GP D21 CPU_PROCHOT# CPU_PROCHOT# 35 H_THERMDA A24 H_THERMDC H_THERMDA 23 A25 H_THERMDA H_THERMDC 23 C7 1 0R2J-2-GP R92 H_BR0# 7 ITP_BPM#0 AD4 ITP_BPM#1 AD3 ITP_BPM#2 AD1 ITP_BPM#3 AC4 ITP_BPM#4 AC2 ITP_BPM#5 AC1 ITP_TCK AC5 ITP_TDI AA6 ITP_TDO AB3 ITP_TMS AB5 ITP_TRST# AB6 C20 ITP_DBRESET# 4 2 H_DEFER# 7 H_DRDY# 7 H_DBSY# 7 1 TPAD28 TP2 D20 B3 PROCHOT# THERMDA THERMDC H CLK 18 18 18 18 IERR# INIT# DY DATA GRP 2 A6 A5 C4 H_BR0# 2 DATA GRP 3 H_A20M# H_FERR# H_IGNNE# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# ADDR GROUP 1 18 H_A20M# 18 H_FERR# 18 H_IGNNE# F1 BR0# R544 2 A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# ADSTB[1]# H_DEFER# H_DRDY# H_DBSY# H_DPRSLPVR 18,42 +1.05V_VCCP 1 Y2 U5 R3 W6 U4 Y5 U2 R4 T5 T3 W3 W5 Y4 W2 Y1 V4 H5 F21 E1 DEFER# DRDY# DBSY# H_ADS# 7,51 H_BNR# 7 H_BPRI# 7 2 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_ADSTB#1 H_ADS# H_BNR# H_BPRI# DATA GRP 1 K3 H2 K2 J3 L5 H1 E2 G5 ADS# BNR# BPRI# DATA GRP 0 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 3 7 H_ADSTB#1 A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# RESERVED J4 L4 M3 K5 M1 N2 J1 N3 P5 P2 L1 P4 P1 R1 L2 ADDR GROUP 0 7 H_ADSTB#0 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0 1H_DPRSLPVR_1 1 2 Q57 R566 MMBT3904-7-F-GP 470R2J-2-GP 3 H_DSTBN#2 7 H_DSTBP#2 7 H_DINV#2 7 2 H_DSTBN#3 7 H_DSTBP#3 7 H_DINV#3 7 1 R49 1 R51 1 R540 1 R539 2 2 27D4R2F-L1-GP 2 54D9R2F-L1-GP 2 27D4R2F-L1-GP 54D9R2F-L1-GP H_DPRSTP# 42 H_DPSLP# 18 H_DPWR# 7 H_PWRGOOD 18,51 H_CPUSLP# 7,18 H_PSI# 42 Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal.Trace should be No Longer than 500 mils 1 Wistron Corporation This resistor is needed for Yonah but not for Meorm. 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title DY CPU - 01 - Yonah - FSB Size A3 Document Number Date: Wednesday, March 21, 2007 C D Rev SC Parker Sheet E 5 of 53 A B C D E SSID = CPU 4 4 +VCC_CORE +VCC_CORE U87D 1 VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] V6 G21 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 VCCA B26 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] AD6 AF5 AE5 AF4 AE3 AF2 AE2 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 VCCSENSE AF7 VCCSENSE VSSSENSE AE7 VSSSENSE +1.05V_VCCP 2 C437 SC10U4V3MX-GP 42 2 H_VID[6..0] 1 +1.5V_RUN 1 Please these inside socket cavity on L8 ( North side Secondary ) 1 3 VCCSENSE 42 Place VSSSENSE 42 VCCSENSE 1 2 R473 100R2F-L1-GP-U VSSSENSE 1 2 R475 100R2F-L1-GP-U TC7 SE220U2VDM-8GP 2 C63 SCD1U10V2KX-4GP 1 2 1 C75 SCD1U10V2KX-4GP 2 1 C67 SCD1U10V2KX-4GP 2 1 2 C235 SCD1U10V2KX-4GP 1 C236 SCD1U10V2KX-4GP 2 1 +1.05V_VCCP VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] C438 SCD01U16V2KX-3GP 22uF 0805 X5R -> 85 degree C , Or better such As X6S and X7R A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 2 1 C169 SC10U4V3MX-GP 2 1 C208 SC10U4V3MX-GP 2 1 C142 SC10U4V3MX-GP 2 1 C144 SC10U4V3MX-GP 2 1 C191 SC10U4V3MX-GP 2 1 C166 SC10U4V3MX-GP 2 1 2 C186 SC10U4V3MX-GP 1 2 C84 SC10U4V3MX-GP 1 2 C117 SC10U4V3MX-GP C211 SC10U4V3MX-GP 1 C132 SC10U4V3MX-GP 2 1 C123 SC10U4V3MX-GP 2 1 2 C83 SC10U4V3MX-GP 1 2 C216 SC10U4V3MX-GP 1 C127 SC10U4V3MX-GP 2 1 C91 SC10U4V3MX-GP 2 1 C170 2 1 2 1 C104 SC10U4V3MX-GP 2 1 C105 SC10U4V3MX-GP 2 1 C165 SC10U4V3MX-GP 2 1 C93 SC10U4V3MX-GP 2 1 C190 SC10U4V3MX-GP 2 1 2 C82 SC10U4V3MX-GP 1 2 1 C193 SC10U4V3MX-GP 2 1 C94 SC10U4V3MX-GP 2 C92 SC10U4V3MX-GP U87C P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 AF3 AF6 AF8 AF11 AF13 AF16 AF19 AF21 AF24 C232 SCD1U10V2KX-4GP 2 VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] 2 3 VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] SC10U4V3MX-GP A4 A8 A11 A14 A16 A19 A23 A26 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 R50 and R51 near CPU Routing VCC_SENSE and VSS_SENSE at 27.4 ohms,50 mils spacing,1 inch. +VCC_CORE 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CPU - 02 - Yonah - POWER Size A3 Document Number Date: Wednesday, March 21, 2007 A B C D Rev SC Parker Sheet E 6 of 53 C H_A#[31..3] H_A#[31..3] 5 1 H_REQ#[4..0] 5 2 H_REQ#[4..0] 4 Place close pin AA35 +1.2V_RUN_NB_IOPLLVDD12 5 H_ADSTB#0 200mA +1.2V_RUN_NB_IOPLLVDD12 2 L13 BLM18BB221SN1D-GP C133 SC2D2U6D3V3MX-1-GP 2 1 1 +1.2V_RUN Place close pin V35 +1.05V_VCCP_NB_CPU_VREF 3 TPAD28 TP20 TPAD28 TP21 +1.05V_VCCP H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_ADSTB#1 AC39 W43 V44 V36 AA40 AC43 V38 AA42 AA38 AC42 AD36 AD38 AA36 AD42 AD40 AD44 AD43 AA44 U46 H_ADS# H_BNR# H_BPRI# H_DEFER# H_DRDY# H_DBSY# H_LOCK# H_RESET# H_RS#2 H_RS#1 H_RS#0 H_BR0# H_TRDY# H_HIT# H_HITM# H_DPWR# R46 M47 H44 K46 P45 M46 M45 K25 L45 R47 L47 T45 R45 K47 P46 T47 CPU_ADS CPU_BNR CPU_BPRI CPU_DEFER CPU_DRDY CPU_DBSY CPU_LOCK CPU_CPURST CPU_RS2 CPU_RS1 CPU_RS0 CPU_BR0 CPU_TRDY CPU_HIT CPU_HITM CPU_DPWR PM_SUS_STAT# PLTRST#_NB NB_POWERGOOD AT9 D10 F10 SUS_STAT# SYSRESET# POWERGOOD B32 CPU_COMP_P 1 5 H_ADSTB#1 M42 K42 M44 T39 M38 P42 T43 P38 P44 P36 W39 V40 W42 V42 P39 M39 K44 H42 K40 T42 width/space: 10/10 2 H_ADS# H_BNR# H_BPRI# H_DEFER# H_DRDY# H_DBSY# H_LOCK# H_RESET# +1.8V_SUS 5 5 5 5 5 2 1 2 2 2 C44 SC220P50V2JN-3GP 1 1 R76 127R2F-GP 5,51 5 5 5 5 5 5 3,5,51 +1.05V_VCCP_NB_CPU_VREF C43 SC1U10V2KX-1GP R84 61D9R2F-GP R170 DY4K7R2J-2-GP 1 Place close pin A32 H_BR0# H_TRDY# H_HIT# H_HITM# H_DPWR# S Q18 2N7002-7F-GP G R96 1KR2J-1-GP 1 R99 DY 2 2 0R2J-2-GP +1.05V_VCCP +3.3V_RUN_NB 1 0R2J-2-GP NB_CPU_COMP_P 53D6R3F-2-GP 2 NB_CPU_COMP_N 21R3F-GP NB_THERMDP 23 NB_THERMDP 1 R81 1 R65 +1.05V_VCCP NB_TEST_MODE 2 1 NB_H_CPUSLP#_2 R93 2K2R2J-2-GP NB_THERMDN A31 CPU_COMP_N AT5 THERMALDIODE_P AT4 THERMALDIODE_N AA35 IOPLLVDD18 +1.2V_RUN_NB_IOPLLVDD12 V35 IOPLLVDD12 NB_H_CPUSLP# +1.05V_VCCP_NB_CPU_VREF NB_TEST_MODE Q10 MMBT3904-7-F-GP CPU_A17 CPU_A18 CPU_A19 CPU_A20 CPU_A21 CPU_A22 CPU_A23 CPU_A24 CPU_A25 CPU_A26 CPU_A27 CPU_A28 CPU_A29 CPU_A30 CPU_A31 CPU_A32 CPU_A33 CPU_ADSTB1 CPU_RESERVED +1.8V_RUN_NB_IOPLLVDD18 20KR2J-L2-GP 2 1 3 R82 Q11 MMBT3904-7-F-GP 3 2 1 NB_H_CPUSLP#_1 R108 4K7R2J-2-GP 2 5,18 H_CPUSLP# 2 1 +1.05V_VCCP 2 23 NB_THERMDN 1 35,48,51 NB_PWRGD R405 2 2 PLTRST# 1 D +1.8V_RUN 20 PM_SUS_STAT# 18,27,31,32,35,45,46,51 CPU_A3 CPU_A4 CPU_A5 CPU_A6 CPU_A7 CPU_A8 CPU_A9 CPU_A10 CPU_A11 CPU_A12 CPU_A13 CPU_A14 CPU_A15 CPU_A16 CPU_REQ0 CPU_REQ1 CPU_REQ2 CPU_REQ3 CPU_REQ4 CPU_ADSTB0# ADDR GROUP 1 200mA 1 2 +1.8V_RUN_NB_IOPLLVDD18 L20 BLM18BB221SN1D-GP C168 SC2D2U6D3V3MX-1-GP +1.8V_RUN SSID = N.B 1 OF 7 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_ADSTB#0 W35 IOPLLVSS C17 A32 A20 CPU_SLP# CPU_VREF TESTMODE DATA GROUP 0 5 DATA GROUP 1 H_D#[63..0] DATA GROUP 2 5 E DATA GROUP 3 H_RS#[2..0] U91A H_D#[63..0] ADDR GROUP 0 H_RS#[2..0] P-4 AGTL+I/F +1.8V_RUN_NB_IOPLLVDD18 D CONTROL B MISC A CPU_D0 CPU_D1 CPU_D2 CPU_D3 CPU_D4 CPU_D5 CPU_D6 CPU_D7 CPU_D8 CPU_D9 CPU_D10 CPU_D11 CPU_D12 CPU_D13 CPU_D14 CPU_D15 CPU_DBI0 CPU_DSTB0N CPU_DSTB0P H46 G47 K45 G45 H45 G46 F45 F47 C46 A44 D46 C45 D47 B44 A43 B45 E47 E46 E45 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DINV#0 H_DSTBN#0 H_DSTBP#0 CPU_D16 CPU_D17 CPU_D18 CPU_D19 CPU_D20 CPU_D21 CPU_D22 CPU_D23 CPU_D24 CPU_D25 CPU_D26 CPU_D27 CPU_D28 CPU_D29 CPU_D30 CPU_D31 CPU_DBI1 CPU_DSTB1N CPU_DSTB1P E40 F44 E42 F40 H40 D44 D42 D40 E38 F36 E36 J34 F34 H38 D32 E34 K36 J38 J36 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DINV#1 H_DSTBN#1 H_DSTBP#1 CPU_D32 CPU_D33 CPU_D34 CPU_D35 CPU_D36 CPU_D37 CPU_D38 CPU_D39 CPU_D40 CPU_D41 CPU_D42 CPU_D43 CPU_D44 CPU_D45 CPU_D46 CPU_D47 CPU_DBI2 CPU_DSTB2N CPU_DSTB2P J32 F32 K32 D29 M29 K30 F30 E30 M27 F27 K27 D25 E27 J27 J25 F25 J30 H29 F29 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DINV#2 H_DSTBN#2 H_DSTBP#2 CPU_D48 CPU_D49 CPU_D50 CPU_D51 CPU_D52 CPU_D53 CPU_D54 CPU_D55 CPU_D56 CPU_D57 CPU_D58 CPU_D59 CPU_D60 CPU_D61 CPU_D62 CPU_D63 CPU_DBI3 CPU_DSTB3N CPU_DSTB3P C37 B40 B43 C42 C43 A42 B38 A41 C40 A38 C36 B36 A37 C38 B34 C34 A36 B41 C41 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DINV#3 H_DSTBN#3 H_DSTBP#3 4 H_DINV#0 5 H_DSTBN#0 5 H_DSTBP#0 5 H_DINV#1 5 H_DSTBN#1 5 H_DSTBP#1 5 3 H_DINV#2 5 H_DSTBN#2 5 H_DSTBP#2 5 2 H_DINV#3 5 H_DSTBN#3 5 H_DSTBP#3 5 RS600ME-GP NB THERMAL DIODE +3.3V_RUN_NB 1 1 DY4K7R2J-2-GP 2 R56 1 4K7R2J-2-GP NB_TEST_MODE CAP close to NB pin 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. NB_THERMDP 1 2 R52 RS600MODE HIGH TEST MODE LOW NORMAL MODE C239 SC2200P50V2KX-2GP NB_THERMDN Title DY RS600ME-AGTL(1/5) 2 TESTMODE Size A3 Document Number Rev A B C D SC Parker Date: Wednesday, March 21, 2007 Sheet E 7 of 53 A B C D E SSID = N.B 4 4 U91B 2 OF 7 SDVO_INT+ SDVO_INT- 3 PCIE 0 LOM BCM5756ME PCIE 1 MINI WWAN 2 PCIE 2 MINI WLAN PCIE 3 EXPRESS CARD 27 27 32 32 32 32 31 31 PCIE_RX0+ PCIE_RX0PCIE_RX1+ PCIE_RX1PCIE_RX2+ PCIE_RX2PCIE_RX3+ PCIE_RX3- 18 18 18 18 PCIE_SB_OUT3 PCIE_SB_OUT#3 PCIE_SB_OUT2 PCIE_SB_OUT#2 18 18 18 18 PCIE_SB_OUT1 PCIE_SB_OUT#1 PCIE_SB_OUT0 PCIE_SB_OUT#0 PCIE_RX0+ PCIE_RX0PCIE_RX1+ PCIE_RX1PCIE_RX2+ PCIE_RX2PCIE_RX3+ PCIE_RX3- AK6 AK5 AM2 AM1 AJ2 AJ1 AG5 AG6 GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P GFX_RX4N GFX_RX5P GFX_RX5N GFX_RX6P GFX_RX6N GFX_RX7P GFX_RX7N GFX_RX8P GFX_RX8N GFX_RX9P GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N AK9 AK10 AM5 AM6 SB_RX3P/GPP_RX5P SB_RX3N/GPP_RX5N SB_RX2P/GPP_RX4P SB_RX2N/GPP_RX4N PCIE_SB_OUT1 PCIE_SB_OUT#1 PCIE_SB_OUT0 PCIE_SB_OUT#0 AM9 AM10 AU3 AV3 SB_RX1P SB_RX1N SB_RX0P SB_RX0N 4 CLK_NBSRC 4 CLK_NBSRC# 4 CLK_NBLINK 4 CLK_NBLINK# D2 E1 F2 F1 G2 G1 H2 K1 L2 L1 M2 M1 P2 R1 T2 T1 U2 U1 V2 W1 Y2 Y1 AA2 AA1 AB2 AC1 AD2 AD1 AE2 AE1 AF2 AG1 GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N AG9 AG10 AK2 AL1 AH2 AH1 AE9 AE10 PCIE_TX0+_C PCIE_TX0-_C PCIE_TX1+_C PCIE_TX1-_C PCIE_TX2+_C PCIE_TX2-_C PCIE_TX3+_C PCIE_TX3-_C SB_TX3P/GPP_TX5P SB_TX3N/GPP_TX5N SB_TX2P/GPP_TX4P SB_TX2N/GPP_TX4N AN2 AN1 AP2 AT1 PCIE_NB_OUT3_C PCIE_NB_OUT#3_C PCIE_NB_OUT2_C PCIE_NB_OUT#2_C SB_TX1P SB_TX1N SB_TX0P SB_TX0N AU2 AU1 AV1 AV2 PCIE_NB_OUT1_C PCIE_NB_OUT#1_C PCIE_NB_OUT0_C PCIE_NB_OUT#0_C PCE_CALI BA3 NB_PCIE_CALI PCE_CALRN BA2 NB_PCIE_CALRN PCE_CALRP BA1 NB_PCIE_CALRP GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N PCIE_SB_OUT3 PCIE_SB_OUT#3 PCIE_SB_OUT2 PCIE_SB_OUT#2 CLK_NBSRC A5 GFX_REFCLKP CLK_NBSRC# B4 GFX_REFCLKN CLK_NBLINK A6 GPPSB_REFCLKP CLK_NBLINK# B6 SDVO_R+_C SDVO_R-_C SDVO_G+_C SDVO_G-_C SDVO_B+_C SDVO_B-_C SDVO_CLK+_C SDVO_CLK-_C GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N PCIE/F 38 SDVO_INT+ 38 SDVO_INT- C3 C2 H5 H4 K8 K6 M8 M6 M5 M4 P9 P8 P4 P5 T6 T5 T9 T10 V5 V6 V9 V10 AA6 AA5 AA9 AA10 AC5 AC6 AC9 AC10 AE6 AE5 PCIE CLK GPPSB_REFCLKN C467 C472 C477 C484 C490 C493 C503 C509 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SDVO_R+ SDVO_RSDVO_G+ SDVO_GSDVO_B+ SDVO_BSDVO_CLK+ SDVO_CLK- SDVO_R+ 38 SDVO_R- 38 SDVO_G+ 38 SDVO_G- 38 SDVO_B+ 38 SDVO_B- 38 SDVO_CLK+ 38 SDVO_CLK- 38 3 X01 C197 C205 C542 C545 C188 C187 C185 C184 R189 R180 R184 1 1 1 1 1 1 1 1 1 C543 1 C549 1 C238 1 C244 1 C259 1 C253 1 C568 1 C556 1 2 2 2 2 2 2 2 2 SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP 2 2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP SCD1U10V2KX-4GP 2 2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP SCD1U10V2KX-4GP PCIE_TX0+ PCIE_TX0PCIE_TX1+ PCIE_TX1PCIE_TX2+ PCIE_TX2PCIE_TX3+ PCIE_TX3PCIE_NB_OUT3 PCIE_NB_OUT#3 PCIE_NB_OUT2 PCIE_NB_OUT#2 PCIE_NB_OUT1 PCIE_NB_OUT#1 PCIE_NB_OUT0 PCIE_NB_OUT#0 PCIE_TX0+ PCIE_TX0PCIE_TX1+ PCIE_TX1PCIE_TX2+ PCIE_TX2PCIE_TX3+ PCIE_TX3- 27 27 32 32 32 32 31 31 2 PCIE_NB_OUT3 PCIE_NB_OUT#3 PCIE_NB_OUT2 PCIE_NB_OUT#2 18 18 18 18 PCIE_NB_OUT1 PCIE_NB_OUT#1 PCIE_NB_OUT0 PCIE_NB_OUT#0 18 18 18 18 2 1K47R2F-GP 1 2 2KR2F-3-GP 1 2 562R2F-GP +1.2V_RUN RS600ME-GP 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title RS600ME-ALINK/PCIE-2(2/5) Size A3 Document Number Rev A B C D SC Parker Date: Wednesday, March 21, 2007 Sheet E 8 of 53 A B C D E SSID = N.B 12 DDR_A_DM[0..7] 12 DDR_A_DQS[0..7] 12 12 12 12 2 MEMA_A0 MEMA_A1 MEMA_A2 MEMA_A3 MEMA_A4 MEMA_A5 MEMA_A6 MEMA_A7 MEMA_A8 MEMA_A9 MEMA_A10 MEMA_A11 MEMA_A12 MEMA_A13 MEMA_A14 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 BD46 BD47 BE30 MEMA_BA0 MEMA_BA1 MEMA_BA2 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 BD2 BE6 BG12 BE17 AN45 AH47 AD45 W45 MEMA_DM0 MEMA_DM1 MEMA_DM2 MEMA_DM3 MEMA_DM4 MEMA_DM5 MEMA_DM6 MEMA_DM7 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 BE2 BF7 BE12 BE18 AM46 AG47 AC46 W46 MEMA_DQS0P MEMA_DQS1P MEMA_DQS2P MEMA_DQS3P MEMA_DQS4P MEMA_DQS5P MEMA_DQS6P MEMA_DQS7P DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 BD3 BG7 BF12 BF18 AM47 AH46 AC47 W47 MEMA_DQS0N MEMA_DQS1N MEMA_DQS2N MEMA_DQS3N MEMA_DQS4N MEMA_DQS5N MEMA_DQS6N MEMA_DQS7N DDR_A_DM[0..7] DDR_A_DQS[0..7] 3 12 DDR_A_DQS#[0..7] BE42 BF36 BG36 BE34 BF34 BE33 BF33 BE32 BG33 BG32 BE46 BE31 BF31 AV45 BF30 DDR_A_DQS#[0..7] DDR_A_CLK_DDR#1 DDR_A_CLK_DDR1 DDR_A_CLK_DDR#0 DDR_A_CLK_DDR0 TPAD28 TP32 TPAD28 TP33 TPAD28 TP53 TPAD28 TP58 TPAD28 TP39 TPAD28 TP38 TPAD28 TP40 TPAD28 TP45 DDR_A_CLK_DDR#1 BB29 DDR_A_CLK_DDR1 BB30 DDR_A_CLK_DDR#0 AY10 DDR_A_CLK_DDR0 AY8 M_A_CLK_DDR#2 AV44 M_A_CLK_DDR2 AV43 M_A_CLK_DDR#3 BD29 M_A_CLK_DDR3 BD30 M_A_CLK_DDR#4 AY12 M_A_CLK_DDR4 AW12 M_A_CLK_DDR#5 AY43 M_A_CLK_DDR5 AY44 MEMA_CK0N MEMA_CK0P MEMA_CK1N MEMA_CK1P MEMA_CK2N MEMA_CK2P MEMA_CK3N MEMA_CK3P MEMA_CK4N MEMA_CK4P MEMA_CK5N MEMA_CK5P 12,14 DDR_A_CKE0 TPAD28 TP165 TPAD28 TP161 TPAD28 TP55 DDR_A_CKE0 DDR_A_CKE1 DDR_A_CKE2 DDR_A_CKE3 BF29 BG28 BG29 BE28 MEMA_CKE0 MEMA_CKE1 MEMA_CKE2 MEMA_CKE3 12,14 DDR_A_CS#0 TPAD28 TP130 TPAD28 TP135 TPAD28 TP123 DDR_A_CS#0 DDR_A_CS#1 DDR_A_CS#2 DDR_A_CS#3 BA46 AV46 BA47 AU45 MEMA_CS0# MEMA_CS1# MEMA_CS2# MEMA_CS3# 12,14 DDR_A_ODT0 TPAD28 TP124 TPAD28 TP131 TPAD28 TP122 DDR_A_ODT0 DDR_A_ODT1 DDR_A_ODT2 DDR_A_ODT3 AY45 AU47 AV47 AT47 MEMA_ODT0 MEMA_ODT1 MEMA_ODT2 MEMA_ODT3 MEMA_DQ0 MEMA_DQ1 MEMA_DQ2 MEMA_DQ3 MEMA_DQ4 MEMA_DQ5 MEMA_DQ6 MEMA_DQ7 MEMA_DQ8 MEMA_DQ9 MEMA_DQ10 MEMA_DQ11 MEMA_DQ12 MEMA_DQ13 MEMA_DQ14 MEMA_DQ15 MEMA_DQ16 MEMA_DQ17 MEMA_DQ18 MEMA_DQ19 MEMA_DQ20 MEMA_DQ21 MEMA_DQ22 MEMA_DQ23 MEMA_DQ24 MEMA_DQ25 MEMA_DQ26 MEMA_DQ27 MEMA_DQ28 MEMA_DQ29 MEMA_DQ30 MEMA_DQ31 MEMA_DQ32 MEMA_DQ33 MEMA_DQ34 MEMA_DQ35 MEMA_DQ36 MEMA_DQ37 MEMA_DQ38 MEMA_DQ39 MEMA_DQ40 MEMA_DQ41 MEMA_DQ42 MEMA_DQ43 MEMA_DQ44 MEMA_DQ45 MEMA_DQ46 MEMA_DQ47 MEMA_DQ48 MEMA_DQ49 MEMA_DQ50 MEMA_DQ51 MEMA_DQ52 MEMA_DQ53 MEMA_DQ54 MEMA_DQ55 MEMA_DQ56 MEMA_DQ57 MEMA_DQ58 MEMA_DQ59 MEMA_DQ60 MEMA_DQ61 MEMA_DQ62 MEMA_DQ63 BC3 BD1 BF4 BE4 BC2 BC1 BE3 BF3 BF5 BG6 BE8 BG10 BG5 BE5 BE7 BF8 BE10 BE11 BF15 BE15 BF10 BG11 BE14 BG15 BG17 BF17 BF19 BE20 BG16 BE16 BG19 BE19 AP45 AN46 AL45 AK46 AP46 AN47 AL47 AL46 AJ46 AJ45 AG45 AF45 AK45 AJ47 AG46 AF46 AE46 AD47 AB45 AA47 AE47 AE45 AC45 AB46 AA45 Y46 V46 U47 AA46 Y47 V45 U45 DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 MEMA_WE# BA45 DDR_A_WE# MEMA_CAS# AY46 DDR_A_CAS# MEMA_RAS# BC47 DDR_A_RAS# MEM_VREF BG44 DDR_A_D[0..63] 12 4 U91D 4 OF 7 15 DDR_B_MA[0..14] 15 DDR_B_BS[0..2] 15 DDR_B_DM[0..7] 15 DDR_B_DQS[0..7] 15 DDR_B_DQS#[0..7] DDR_A_WE# 12,14 DDR_A_CAS# 12,14 DDR_A_RAS# 12,14 15 DDR_B_CKE[0..1] DDR_B_MA[0..14] 2 RS600ME-GP 15 DDR_B_CS#[0..1] 15 DDR_B_ODT[0..1] BE36 BG31 BE29 BE27 BF27 BG27 BE26 BE25 BF26 BF25 BG37 BG25 BE24 BG42 BE23 MEMB_A0 MEMB_A1 MEMB_A2 MEMB_A3 MEMB_A4 MEMB_A5 MEMB_A6 MEMB_A7 MEMB_A8 MEMB_A9 MEMB_A10 MEMB_A11 MEMB_A12 MEMB_A13 MEMB_A14 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 BG38 BE37 BG24 MEMB_BA0 MEMB_BA1 MEMB_BA2 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 AY4 AV14 BB19 AT24 BB32 AW38 AT38 AM42 MEMB_DM0 MEMB_DM1 MEMB_DM2 MEMB_DM3 MEMB_DM4 MEMB_DM5 MEMB_DM6 MEMB_DM7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 AY6 AW16 BD19 AW27 BD32 BC38 AP44 AK40 MEMB_DQS0P MEMB_DQS1P MEMB_DQS2P MEMB_DQS3P MEMB_DQS4P MEMB_DQS5P MEMB_DQS6P MEMB_DQS7P DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 AY5 AV16 BD21 AW25 BD34 BD40 AT44 AK42 MEMB_DQS0N MEMB_DQS1N MEMB_DQS2N MEMB_DQS3N MEMB_DQS4N MEMB_DQS5N MEMB_DQS6N MEMB_DQS7N M_B_CLK_DDR#1 M_B_CLK_DDR1 M_B_CLK_DDR#0 M_B_CLK_DDR0 M_B_CLK_DDR#2 M_B_CLK_DDR2 M_B_CLK_DDR#3 M_B_CLK_DDR3 M_B_CLK_DDR#4 M_B_CLK_DDR4 M_B_CLK_DDR#5 M_B_CLK_DDR5 AV29 AT30 BC10 BD10 BB43 BB44 AT25 AV25 BC8 BD8 BD44 BE44 MEMB_CK0N MEMB_CK0P MEMB_CK1N MEMB_CK1P MEMB_CK2N MEMB_CK2P MEMB_CK3N MEMB_CK3P MEMB_CK4N MEMB_CK4P MEMB_CK5N MEMB_CK5P DDR_B_CKE0 DDR_B_CKE1 DDR_B_CKE2 DDR_B_CKE3 BF23 BG23 BE22 BF22 MEMB_CKE0 MEMB_CKE1 MEMB_CKE2 MEMB_CKE3 DDR_B_CS#0 DDR_B_CS#1 DDR_B_CS#2 DDR_B_CS#3 BF40 BF41 BE38 BF45 MEMB_CS0# MEMB_CS1# MEMB_CS2# MEMB_CS3# DDR_B_ODT0 DDR_B_ODT1 DDR_B_ODT2 DDR_B_ODT3 BC46 BC45 BB47 BB45 DDR_B_BS[0..2] DDR_B_DM[0..7] DDR_B_DQS[0..7] DDR_B_DQS#[0..7] 15 M_B_CLK_DDR#1 15 M_B_CLK_DDR1 15 M_B_CLK_DDR#0 15 M_B_CLK_DDR0 TPAD28 TP54 TPAD28 TP52 TPAD28 TP36 TPAD28 TP47 TPAD28 TP50 TPAD28 TP51 TPAD28 TP59 TPAD28 TP156 DDR_B_CKE[0..1] V_DDR_NB_REF C616 SCD1U10V2KX-4GP DDR_B_D[0..63] DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 TPAD28 TP164 TPAD28 TP157 DDR_B_CS#[0..1] TPAD28 TP60 TPAD28 TP158 DDR_B_ODT[0..1] TPAD28 TP134 TPAD28 TP138 MEMB_ODT0 MEMB_ODT1 MEMB_ODT2 MEMB_ODT3 MEM_B I/F 12,14 DDR_A_MA13 TPAD28 TP155 DDR_A_BS[0..2] 12,14 DDR_A_BS[0..2] DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 1 4 DDR_A_D[0..63] U91C 3 OF 7 MEM_A I/F 12,14 DDR_A_MA[0..12] DDR_A_MA[0..12] MEMB_DQ0 MEMB_DQ1 MEMB_DQ2 MEMB_DQ3 MEMB_DQ4 MEMB_DQ5 MEMB_DQ6 MEMB_DQ7 MEMB_DQ8 MEMB_DQ9 MEMB_DQ10 MEMB_DQ11 MEMB_DQ12 MEMB_DQ13 MEMB_DQ14 MEMB_DQ15 MEMB_DQ16 MEMB_DQ17 MEMB_DQ18 MEMB_DQ19 MEMB_DQ20 MEMB_DQ21 MEMB_DQ22 MEMB_DQ23 MEMB_DQ24 MEMB_DQ25 MEMB_DQ26 MEMB_DQ27 MEMB_DQ28 MEMB_DQ29 MEMB_DQ30 MEMB_DQ31 MEMB_DQ32 MEMB_DQ33 MEMB_DQ34 MEMB_DQ35 MEMB_DQ36 MEMB_DQ37 MEMB_DQ38 MEMB_DQ39 MEMB_DQ40 MEMB_DQ41 MEMB_DQ42 MEMB_DQ43 MEMB_DQ44 MEMB_DQ45 MEMB_DQ46 MEMB_DQ47 MEMB_DQ48 MEMB_DQ49 MEMB_DQ50 MEMB_DQ51 MEMB_DQ52 MEMB_DQ53 MEMB_DQ54 MEMB_DQ55 MEMB_DQ56 MEMB_DQ57 MEMB_DQ58 MEMB_DQ59 MEMB_DQ60 MEMB_DQ61 MEMB_DQ62 MEMB_DQ63 AV5 AV6 BC6 BD6 AT8 AV4 BB4 AV9 BC14 AY14 BD18 BC16 BB14 BD12 BB16 BB18 AT18 AW19 AW23 AY24 AY18 AV19 BB21 AY21 BB23 AV23 BD27 BB25 BC23 BD24 BC25 BB27 AW30 AV32 AW34 BB36 AY29 AT32 BB34 AY32 BD38 AY36 AY38 BC40 BB38 BC36 BB40 BD42 AV40 AT40 AP40 AT39 AY40 AV39 AT42 AP42 AM38 AK44 AJ42 AG44 AK36 AM43 AM39 AJ43 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 MEMB_WE# BE40 DDR_B_WE# MEMB_CAS# BG41 DDR_B_CAS# MEMB_RAS# BF38 DDR_B_RAS# MEM_COMPN AT45 DDR_COMPN MEM_COMPP AT46 DDR_COMPP DDR_B_D[0..63] 15 3 2 DDR_B_WE# 15 DDR_B_CAS# 15 DDR_B_RAS# 15 R492 R485 1 2 1 2 40D2R2F-GP +1.8V_SUS 40D2R2F-GP RS600ME-GP 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title RS600ME-MEMORY I/F (3/5) Size A3 Document Number Rev A B C D SC Parker Date: Wednesday, March 21, 2007 Sheet E 9 of 53 A B SSID = N.B C E LCD_A0- +3.3V_RUN_NB_VDDR33 200mA 1 2 200mA 2 R83 1 0R2J-2-GP 1 2 R742 10KR2J-3-GP 2 R31 C57 16 NB_VSYNC SCD01U16V2KX-3GP 16 NB_HSYNC 4 CLK_NB_14M 4 CLK_NB_FSB 4 CLK_NB_FSB# R109 150R2F-1-GP R102 150R2F-1-GP 2 1 1 2 R94 150R2F-1-GP 2 1 16,38 NB_RED 16,38 NB_GREEN 16,38 NB_BLUE 2 CLK_NB_14M CLK_NB_FSB CLK_NB_FSB# J23 H23 +3.3V_RUN_NB_VDDLT33 VDDLT18_1 VDDLT18_2 H24 J24 +1.8V_RUN_NB_VDDLT18 VSSPLL_PCIE_1 VSSPLL_PCIE_2 VSSPLL_PCIE_3 VSSLT_1 VSSLT_2 VSSLT_3 VSSLT_4 PLLVDD18 PLLVDD12 A11 PLLVSS B26 B12 TMDS_HPD DDC_DATA B23 B24 DAC_VSYNC DAC_HSYNC A25 DAC_RSET D19 F19 J19 RED GREEN BLUE B11 A7 B7 OSCIN CPU_CLKP CPU_CLKN 1 2 C36 SC3D3P50V2CN-GP LCD_A2+ use 24 bit or 18bit DY LCD_A2+ 17 LCD_ACLK- 1 LCD_ACLK- 17 C37 TP10 TPAD28 TP11 TPAD28 SC8P250V2CC-GP LCD_ACLK+ DY LCD_ACLK+ 17 TP102 TPAD28 TP103 TPAD28 C107 SCD1U10V2KX-4GP 1500mA C96 A30 SCD1U10V2KX-4GP A26 C29 F24 B21 LTPVSS18 A21 D3 C4 C5 C_PR J18 Y F18 1 1500mA LTPVDD18 LVDS_DIGON LVDS_BLON LVDS_ENA_BL 1 VDDLT33_1 VDDLT33_2 2 LCD_BCLKLCD_BCLK+ LCD_ACLKLCD_ACLK+ LCD_A2- 17 1 E21 F21 A27 B27 4 LCD_A1+ 17 LCD_A2- 2 TXCLK_UN TXCLK_UP TXCLK_LN TXCLK_LP DY 2 LCD_A0LCD_A0+ LCD_A1LCD_A1+ LCD_A2LCD_A2+ LCD_A3LCD_A3+ SC3D3P50V2CN-GP LCD_A1+ 2 VDDPLL_PCIE_1 VDDPLL_PCIE_2 VDDPLL_PCIE_3 C55 SC2D2U6D3V3MX-1-GP NB_DAC_RSET 2 715R3-GP NB_RED NB_GREEN NB_BLUE 1 R85 X01 M10 P13 P12 V12 T12 T13 NB_TMDS_HPD_R NB_SDVO_CTRLDATA 0R2J-2-GP 1 2 1 AVSSDI +1.8V_RUN_NB_PLLVDD18 A14 +1.2V_RUN_NB_PLLVDD12 A12 2 2 BLM18BB221SN1D-GP BLM18BB221SN1D-GP C35 SC2D2U6D3V3MX-1-GP 1 1 L3 1 L8 +1.8V_RUN +1.2V_RUN hot-plug detect. need used it or detect by KBC A19 2 FROM DVI CONN. AVDDDI B28 A28 C30 B30 B29 A29 C28 C27 LCD_A1- 17 C41 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 1 2 L15 C129 BLM18PG181SN-3GP SC4D7U6D3V3KX-GP +1.8V_RUN 1 2 +3.3V_RUN_NB L11 C130 BLM18PG181SN-3GP SC4D7U6D3V3KX-GP 3 200mA +1.8V_RUN_NB_LTPVDD18 1 1 C124 SC4D7U6D3V3KX-GP 2 3 B19 C88 SC2D2U6D3V3MX-1-GP +1.2V_RUN_NB_VDDPLL_PCIE 2 L14 BLM18PG181SN-3GP LVDS I/F 1 2 1500mA 1 +1.2V_RUN +1.8V_RUN_NB_AVDDDI AVSSQ TXOUT_L0N TXOUT_L0P TXOUT_L1N TXOUT_L1P TXOUT_L2N TXOUT_L2P TXOUT_L3N TXOUT_L3P SVID A24 200mA 1 2 L12 BLM18BB221SN1D-GP AVDDQ DAC 1 A23 C49 SC2D2U6D3V3MX-1-GP 2 1 2 L4 BLM18BB221SN1D-GP +1.8V_RUN_NB_AVDDQ AVSSN_1 AVSSN_2 TP109 TP108 TP106 TP107 TP101 TP100 TP104 TP105 1 200mA M23 N23 LCD_B0LCD_B0+ LCD_B1LCD_B1+ LCD_B2LCD_B2+ LCD_B3LCD_B3+ C39 SCD1U10V2KX-4GP ENVDD 17 TP3 TPAD28 PANEL_BKEN 36 ENVDD LVDS_BLON PANEL_BKEN COMP_PB D18 DAC_SDA A22 NB_DDCDATA_R I2C_CLK C21 NB_I2C_CLK I2C_DATA B22 NB_LDDC_DATA_R STRP_DATA B14 STRP_DATA CRT +1.8V_RUN AVDD_1 AVDD_2 C24 C25 D24 E24 H21 J21 E23 F23 R44 R16 R15 R17 R24 R66 2 2 2 2 2 2 1 2 +1.8V_RUN L5 BLM18BB221SN1D-GP 1 C65 SC2D2U6D3V3MX-1-GP 2 1 L9 BLM18PG181SN-3GP A17 B17 TXOUT_U0N TXOUT_U0P TXOUT_U1N TXOUT_U1P TXOUT_U2N TXOUT_U2P TXOUT_U3N TXOUT_U3P 2 +3.3V_RUN_NB_AVDD 2 CLK 1 VDDR3_1 VDDR3_2 2 1500mA LCD_A0+ 17 LCD_A1- 1 4 DY SC3D3P50V2CN-GP LCD_A0+ 2 A18 B18 LCD_A0- 17 C40 5 OF 7 1 U91E C66 SC2D2U6D3V3MX-1-GP 2 1 L10 BLM18PG181SN-3GP 2 2 2 1500mA 1 placed CAP closed NB within 20 mm (80mil) PUT AT LEAST TWO VIAS CLOSE TO VDDR3 TWO BALLS FOR POWER DELIVERY NB 3.3V are independent +3.3V_RUN_NB 38 NB_TMDS_HPD 38 SDVO_CTRLDATA D C21 SC2D2U6D3V3MX-1-GP +3.3V_RUN_NB NB_I2C_CLK 1 4 NB_LDDC_DATA 2 3 RN2 SRN4K7J-8-GP NB_DDCDATA 1 2 R45 4K7R2J-2-GP 1 1 0R2J-2-GP 1 0R2J-2-GP 1 0R2J-2-GP 0R2J-2-GP 1 0R2J-2-GP 1 0R2J-2-GP NB_DDCDATA 16 CRT NB_DDCCLK 16 NB_LDDC_CLK 17 SDVO_CTRLCLK 38 NB_LDDC_DATA 17 NB_VCORE_CNTRL LVDS 20,46 2 RS600ME-GP Use to control NB core power 1~1.2V Place close to NB ONLY FOR NB 3.3V POWER 2 R30 4K7R2J-2-GP 1 STRP_DATA Title RS600ME-4(4/5) Size A3 Document Number Rev B C D SC Parker Date: Thursday, March 22, 2007 A 1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. DYR64 4K7R2J-2-GP 1 1 R48 4K7R2J-2-GP SDVO_CTRLDATA Wistron Corporation 2 NB_HSYNC R77 4K7R2J-2-GP 1 2 2 1 NB_VSYNC 2 1 2 DYR38 4K7R2J-2-GP DYR40 4K7R2J-2-GP S Q14 MMBT3904-7-F-GP R39 4K7R2J-2-GP DDC_DATA: STRAP_MEMVMODE DEFAULT: 1 0: DDR3 +3.3V_RUN_NB 1: DDR2 +3.3V_RUN_NB 2 2NB_POWER_ON1 1 2K2R2J-2-GP +3.3V_RUN_NB STRP_DATA: STRP_MEMSTRAPS DEFAULT: 1 0: SELECT MEMORY CHA A AS DEBUG BUS 1: NORMAL MODE 2N7002-7F-GP 3 +1.8V_RUN +3.3V_RUN_NB DAC_HSYNC: STRP_INTGFX_DISABLE DEFAULT: 0 0: ENABLE 1: DISABLE 1 2 Q13 NB_POWER_ON2G C113 SC470P50V2KX-3GP 2 R100 100KR2J-1-GP D 1 1 SI3456BDV-T1-GP +3.3V_RUN_NB NB_POWER_ON3 1 BAT54CW-1-GP D 6 D 5 S 4 C99 SC4D7U6D3V3KX-GP +3.3V_ALW2 R119 100KR2J-1-GP 2 2 1 R126 U22 1 D 2 D 3 G 1 1 3 2 D5 DAC_VSYNC: STRAP_MOBILE_GFX DEFAULT: 1 0: DESKTOP GRAPHICS DEVICE 1: MOBILE GRAPHICS DEVICE 1 +3.3V_RUN_NB +3.3V_ALW 2 +15V_ALW +1.8V_RUN Sheet E 10 of 53 7 OF 7 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315 VSS316 VSS317 VSS318 VSS319 VSS320 VSS321 VSS322 VSS323 VSS324 VSS325 VSS326 AK26 AK29 AK39 AK43 AK47 AM40 AM44 AM45 AP39 AP43 AP47 AT6 AT10 AT12 AT43 AU46 AV8 AV12 AV42 AW10 AW14 AW18 AW21 AW24 AW29 AW32 AW36 AY16 AY19 AY23 AY25 AY27 AY30 AY34 AY42 AY47 B5 B31 B37 B42 B46 BB8 BB10 BB12 BB24 BB46 BC12 BC18 BC19 BC21 BC24 BC29 BC30 BC32 BC34 BD4 BD14 BD16 BD23 BD25 BC27 BD36 BE1 BE21 BE41 BE43 BE47 BF2 BF6 BF11 BF14 BF16 BF20 BF21 BF28 BF32 BF37 BF42 BF44 BF43 BG3 BG4 BG8 BG14 BG18 BG20 BG21 BF24 BG43 C6 C11 C12 C14 C19 C20 C22 C23 C26 C44 C47 D4 D6 D12 D21 D23 D27 D30 D34 D36 D38 D45 E10 E12 E18 E19 E25 E29 E32 F5 F12 F38 F46 H12 H18 H19 H25 H27 H34 H36 H43 H47 J12 K18 K19 K21 K23 K24 K34 K39 K43 L46 M18 M19 M21 M24 M25 M36 M40 M43 N18 N19 N21 P40 P43 T38 T40 T44 T46 V19 V22 V25 V28 V30 2 1 DY DY 1 A DY 1 X01 1 DY DY B 1 DY DY DY DY 1 2 1 C 1 2 1 GROUND D 2 DY 1 2 DY DY 1 DY 1 DY VSS327 VSS328 VSS329 VSS330 VSS331 VSS332 VSS333 VSS334 VSS335 VSS336 VSS337 VSS338 VSS339 VSS340 VSS341 VSS342 1 DY Size A2 Date: DY 1 2 1 2 1 1 1 1 1 2 1 1 2 DY C174 SC1U10V2KX-1GP 1 C175 SC1U10V2KX-1GP 2 C210 SC1U10V2KX-1GP 2 C180 SC1U10V2KX-1GP 1 C157 SC1U10V2KX-1GP 2 C222 SC10U4V3MX-GP 2 C150 SC22U6D3V5MX-2GP 2 C240 SCD1U10V2KX-4GP 2 C147 SC1U10V2KX-1GP DY C257 SC1U10V2KX-1GP 2 1 C76 SC1U10V2KX-1GP DY C201 SC1U10V2KX-1GP 2 2 DY C192 SC1U10V2KX-1GP 2 +1.8V_SUS C226 SC1U10V2KX-1GP 150mA(15 mil) 2 +1.2V_RUN_NB_VPCIE 1 C196 SC22U6D3V5MX-2GP 2 C254 SC10U4V3MX-GP 60mA(10 mil) 2 1 C58 SC4D7U6D3V3KX-GP DY 1 C252 SC10U4V3MX-GP 2 C217 SC4D7U6D3V3KX-GP POWER 1V~1.2V 1 C213 SC10U4V3MX-GP 1 C C223 SC10U4V3MX-GP NB-VDD_CPU DE-COUPLING 2 2 C143 SC4D7U6D3V3KX-GP +1.2V_RUN_NB_VPCIE C251 SC10U4V3MX-GP CPU I/F PWR C241 SC10U4V3MX-GP PCIE PWR VDD_MEM64 VDD_MEM63 VDD_MEM62 VDD_MEM61 VDD_MEM60 VDD_MEM59 VDD_MEM58 VDD_MEM57 VDD_MEM56 VDD_MEM55 VDD_MEM54 VDD_MEM53 VDD_MEM52 VDD_MEM51 VDD_MEM50 VDD_MEM49 VDD_MEM48 VDD_MEM47 VDD_MEM46 VDD_MEM45 VDD_MEM44 VDD_MEM43 VDD_MEM42 VDD_MEM41 VDD_MEM40 VDD_MEM39 VDD_MEM38 VDD_MEM37 VDD_MEM36 VDD_MEM35 VDD_MEM34 VDD_MEM33 VDD_MEM32 VDD_MEM31 VDD_MEM30 VDD_MEM29 VDD_MEM28 VDD_MEM27 VDD_MEM26 VDD_MEM25 VDD_MEM24 VDD_MEM23 VDD_MEM22 VDD_MEM21 VDD_MEM20 VDD_MEM19 VDD_MEM18 VDD_MEM17 VDD_MEM16 VDD_MEM15 VDD_MEM14 VDD_MEM13 VDD_MEM12 VDD_MEM11 VDD_MEM10 VDD_MEM9 VDD_MEM8 VDD_MEM7 VDD_MEM6 VDD_MEM5 VDD_MEM4 VDD_MEM3 VDD_MEM2 VDD_MEM1 Y29 Y26 Y23 Y20 Y18 W31 W30 W28 W25 W22 W19 W17 V31 V29 V26 V23 V20 V18 V17 U31 U30 U29 U19 U18 U17 J16 H16 F16 E16 D16 C16 B16 AL31 AL30 AL29 AL19 AL18 AL17 AK31 AK30 AK28 AK25 AK22 AK19 AK17 AJ31 AJ29 AJ26 AJ23 AJ20 AJ18 AJ17 AH30 AH28 AH25 AH22 AH19 AF29 AF26 AF23 AF20 AF18 AE30 AE28 AE25 AE22 AE19 AC29 AC26 AC23 AC20 AC18 AB30 AB28 AB25 AB22 AB19 A16 1 B BG40 BG34 BG30 BG26 BG22 BG45 BF46 BE45 BD45 AV36 AV34 AV30 AV27 AV24 AV21 AV18 AT36 AT34 AT29 AT27 AT23 AT21 AT19 AT16 AT14 AR34 AR32 AR30 AR29 AR25 AR24 AR23 AR21 AR19 AR18 AR16 AR14 AP38 AP36 AP35 AN33 AN32 AN31 AN30 AN29 AN19 AN18 AN17 AM36 AM35 AL33 AK38 AK35 AK33 AJ36 AJ35 AJ33 AG39 AG38 AG36 AG35 AE38 AE36 AE35 VDDC78 VDDC77 VDDC76 VDDC75 VDDC74 VDDC73 VDDC72 VDDC71 VDDC70 VDDC69 VDDC68 VDDC67 VDDC66 VDDC65 VDDC64 VDDC63 VDDC62 VDDC61 VDDC60 VDDC59 VDDC58 VDDC57 VDDC56 VDDC55 VDDC54 VDDC53 VDDC52 VDDC51 VDDC50 VDDC49 VDDC48 VDDC47 VDDC46 VDDC45 VDDC44 VDDC43 VDDC42 VDDC41 VDDC40 VDDC39 VDDC38 VDDC37 VDDC36 VDDC35 VDDC34 VDDC33 VDDC32 VDDC31 VDDC30 VDDC29 VDDC28 VDDC27 VDDC26 VDDC25 VDDC24 VDDC23 VDDC22 VDDC21 VDDC20 VDDC19 VDDC18 VDDC17 VDDC16 VDDC15 VDDC14 VDDC13 VDDC12 VDDC11 VDDC10 VDDC9 VDDC8 VDDC7 VDDC6 VDDC5 VDDC4 VDDC3 VDDC2 VDDC1 2 C179 SC22U6D3V5MX-2GP DY C86 SCD1U10V2KX-4GP 2 +1.8V_RUN_NB_VDD18MEM 2 MEM TRANS PWR C73 SCD1U10V2KX-4GP VDD_CPU_PACK VDD_CPU33 VDD_CPU32 VDD_CPU31 VDD_CPU30 VDD_CPU29 VDD_CPU28 VDD_CPU27 VDD_CPU26 VDD_CPU25 VDD_CPU24 VDD_CPU23 VDD_CPU22 VDD_CPU21 VDD_CPU20 VDD_CPU19 VDD_CPU18 VDD_CPU17 VDD_CPU16 VDD_CPU15 VDD_CPU14 VDD_CPU13 VDD_CPU12 VDD_CPU11 VDD_CPU10 VDD_CPU9 VDD_CPU8 VDD_CPU7 VDD_CPU6 VDD_CPU5 VDD_CPU4 VDD_CPU3 VDD_CPU2 VDD_CPU1 1 DY 1 C100 SCD1U10V2KX-4GP +1.05V_VCCP 1 P47 W38 W36 W33 V33 U33 T36 T35 T33 R33 R32 R31 R30 R29 P35 N34 N32 N30 N29 N27 M34 M32 M30 K29 J29 H32 H30 C33 C32 C31 B33 AC36 AC35 A33 2 C81 SC1U10V2KX-1GP 250mA(15 mil) 2 +1.8V_RUN_NB_VDD18MEM 2 NB-VDD18_MEN DE-COUPLING C103 SC10U4V3MX-GP X01 1 +1.8V_RUN_NB_VDD18CPU 2 1 DY C90 SC10U4V3MX-GP 2 C139 SC1U10V2KX-1GP DY C153 SC10U4V3MX-GP CPU TRANS PWR 1 2 L19 BLM21PG600SN1-GP 1 1 +1.2V_RUN 2 2 50mA(10mil) 2 3 W15 W13 W12 V15 V13 V3 V1 U15 T15 R15 N14 M14 M12 K14 K12 K9 J10 H10 H8 F8 E8 D8 C10 C8 C7 B10 B8 AP13 AP12 AP3 AP1 AN15 AM15 AM13 AM12 AL15 AK15 AK13 AJ15 AJ13 AG13 AE13 AD13 AC13 AA13 AA12 A10 A8 1 C72 SC1U10V2KX-1GP DY VDD_PCIE48 VDD_PCIE47 VDD_PCIE46 VDD_PCIE45 VDD_PCIE44 VDD_PCIE43 VDD_PCIE42 VDD_PCIE41 VDD_PCIE40 VDD_PCIE39 VDD_PCIE38 VDD_PCIE37 VDD_PCIE36 VDD_PCIE35 VDD_PCIE34 VDD_PCIE33 VDD_PCIE32 VDD_PCIE31 VDD_PCIE30 VDD_PCIE29 VDD_PCIE28 VDD_PCIE27 VDD_PCIE26 VDD_PCIE25 VDD_PCIE24 VDD_PCIE23 VDD_PCIE22 VDD_PCIE21 VDD_PCIE20 VDD_PCIE19 VDD_PCIE18 VDD_PCIE17 VDD_PCIE16 VDD_PCIE15 VDD_PCIE14 VDD_PCIE13 VDD_PCIE12 VDD_PCIE11 VDD_PCIE10 VDD_PCIE9 VDD_PCIE8 VDD_PCIE7 VDD_PCIE6 VDD_PCIE5 VDD_PCIE4 VDD_PCIE3 VDD_PCIE2 VDD_PCIE1 R18 R17 N25 N24 K16 H14 E14 C15 A15 2 C116 SC1U10V2KX-1GP +1.8V_RUN_NB_VDD18CPU VDD18_MEM_29 VDD18_MEM_28 VDD18_MEM_27 VDD18_MEM_26 VDD18_MEM_25 VDD18_MEM_24 VDD18_MEM_23 VDD18_MEM_22 VDD18_MEM_21 VDD18_MEM_20 VDD18_MEM_19 VDD18_MEM_18 VDD18_MEM_17 VDD18_MEM_16 VDD18_MEM_15 VDD18_MEM_14 VDD18_MEM_13 VDD18_MEM_12 VDD18_MEM_11 VDD18_MEM_10 VDD18_MEM_9 VDD18_MEM_8 VDD18_MEM_7 VDD18_MEM_6 VDD18_MEM_5 VDD18_MEM_4 VDD18_MEM_3 VDD18_MEM_2 VDD18_MEM_1 VDD18_CPU_9 VDD18_CPU_8 VDD18_CPU_7 VDD18_CPU_6 VDD18_CPU_5 VDD18_CPU_4 VDD18_CPU_3 VDD18_CPU_2 VDD18_CPU_1 1 2 NB-VDD18_CPU DE-COUPLING C102 SC22U6D3V5MX-2GP 6 OF 7 2 C125 SC10U4V3MX-GP 1 1500mA VDD18_CPU_20 VDD18_CPU_19 VDD18_CPU_18 VDD18_CPU_17 VDD18_CPU_16 VDD18_CPU_15 VDD18_CPU_14 VDD18_CPU_13 VDD18_CPU_12 VDD18_CPU_11 VDD18_CPU_10 1 R127 0R3-0-U-GP W16 V16 U16 T16 R16 N16 M16 J14 F14 D14 B15 AR27 AN16 AM33 AM32 AM31 AM30 AM29 AM19 AM18 AM17 AM16 AL32 AL16 AK32 AK16 AJ32 AJ16 AD35 W32 V32 U32 T32 T31 T30 T29 T19 T18 T17 R19 2 C115 SC22U6D3V5MX-2GP DY C87 SC1U10V2KX-1GP 2 2 DY C176 SC1U10V2KX-1GP 2 R107 0R3-0-U-GP 1 C231 SC1U10V2KX-1GP 2 1 C234 SC10U4V3MX-GP 2 1 C126 SC10U4V3MX-GP 1 DY VSS_PCIE1 VSS_PCIE2 VSS_PCIE3 VSS_PCIE4 VSS_PCIE5 VSS_PCIE6 VSS_PCIE7 VSS_PCIE8 VSS_PCIE9 VSS_PCIE10 VSS_PCIE11 VSS_PCIE12 VSS_PCIE13 VSS_PCIE14 VSS_PCIE15 VSS_PCIE16 VSS_PCIE17 VSS_PCIE18 VSS_PCIE19 VSS_PCIE20 VSS_PCIE21 VSS_PCIE22 VSS_PCIE23 VSS_PCIE24 VSS_PCIE25 VSS_PCIE26 VSS_PCIE27 VSS_PCIE28 VSS_PCIE29 VSS_PCIE30 VSS_PCIE31 VSS_PCIE32 VSS_PCIE33 VSS_PCIE34 VSS_PCIE35 VSS_PCIE36 VSS_PCIE37 VSS_PCIE38 VSS_PCIE39 VSS_PCIE40 VSS_PCIE41 VSS_PCIE42 VSS_PCIE43 VSS_PCIE44 VSS_PCIE45 VSS_PCIE46 VSS_PCIE47 VSS_PCIE48 VSS_PCIE49 VSS_PCIE50 VSS_PCIE51 VSS_PCIE52 VSS_PCIE53 VSS_PCIE54 VSS_PCIE55 VSS_PCIE56 VSS_PCIE57 VSS_PCIE58 VSS_PCIE59 VSS_PCIE60 VSS_PCIE61 VSS_PCIE62 VSS_PCIE63 VSS_PCIE64 VSS_PCIE65 VSS_PCIE66 VSS_PCIE67 VSS_PCIE68 VSS_PCIE69 VSS_PCIE70 VSS_PCIE71 VSS_PCIE72 VSS_PCIE73 VSS_PCIE74 VSS_PCIE75 VSS_PCIE76 VSS_PCIE77 VSS_PCIE78 VSS_PCIE79 VSS_PCIE80 VSS_PCIE81 VSS_PCIE82 VSS_PCIE83 VSS_PCIE84 VSS_PCIE85 VSS_PCIE86 VSS_PCIE87 VSS_PCIE88 VSS_PCIE89 VSS_PCIE90 VSS_PCIE91 VSS_PCIE92 VSS_PCIE93 VSS_PCIE94 VSS_PCIE95 VSS_PCIE96 VSS_PCIE97 VSS_PCIE98 VSS_PCIE99 VSS_PCIE100 VSS_PCIE101 VSS_PCIE102 VSS_PCIE103 VSS_PCIE104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 1 4 A3 AA3 AA4 AA8 AB1 AB3 AC2 AC3 AC4 AC8 AC12 AD3 AD4 AD5 AD6 AD8 AD9 AD10 AD12 AE3 AE4 AE8 AE12 AF1 AF3 AG2 AG3 AG4 AG8 AG12 AH3 AJ3 AJ4 AJ5 AJ6 AJ8 AJ9 AJ10 AJ12 AK1 AK3 AK4 AK8 AK12 AL2 AL3 AM3 AM4 AM8 AN3 AP4 AP5 AP6 AP8 AP9 AP10 AT2 AT3 AY1 AY2 AY3 B2 B3 BB1 BB2 BB3 C1 D1 E2 E3 F3 F4 G3 H1 H3 H6 K2 K3 K4 K5 L3 M3 M9 P1 P3 P6 P10 R2 R3 T3 T4 T8 U3 V4 V8 W2 W3 W4 W5 W6 W8 W9 W10 Y3 A4 A34 A40 A45 AA39 AA43 AB18 AB20 AB23 AB26 AB29 AB47 AC19 AC22 AC25 AC28 AC30 AC38 AC40 AC44 AD39 AD46 AE18 AE20 AE23 AE26 AE29 AE39 AE40 AE42 AE43 AE44 AF19 AF22 AF25 AF28 AF30 AF47 AG40 AG42 AG43 AH18 AH20 AH23 AH26 AH29 AH45 AJ19 AJ22 AJ25 AJ28 AJ30 AJ38 AJ39 AJ40 AJ44 AK18 AK20 AK23 2 DY C228 SC22U6D3V5MX-2GP A D E +1.8V_RUN NB-VDD_PCIE DE-COUPLING NB-VDDC DE-COUPLING +NB_VCORE 6A(240 mil) 4 SSID = N.B +NB_VCORE U91F RS600ME-GP CORE POWER MEM I/F PWR +1.8V_SUS 3 +1.05V_VCCP +1.8V_RUN NB-VDD_MEN DE-COUPLING 2.5A(100 mil) THE CAPS HAVE TO BE PLACED UNDER NB. ALL CAPS' GND USE COPPER FLOOD TOGETHER, AND POWER ALSO LIKE THIS WAY. 2 2 V39 V43 V47 W18 W20 W23 W26 W29 W40 W44 Y19 Y22 Y25 Y28 Y30 Y45 U91G RS600ME-GP 1 Wistron Corporation Title 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Wednesday, March 21, 2007 Document Number RS600ME-5(5/5) Parker E Sheet 11 of 53 Rev SC A B C D E FROM NB 4 DDR_A_D11 1 DDR_A_D15 2 DDR_A_D16 3 DDR_A_D20 4 RN42 SRN22J-3-GP-U 8 7 6 5 M_R_DQ11 M_R_DQ15 M_R_DQ16 M_R_DQ20 DDR_A_D17 1 DDR_A_D21 2 DDR_A_DQS2 3 DDR_A_DQS#2 4 RN41 SRN22J-3-GP-U 8 7 6 5 DDR_A_D13 1 DDR_A_DM1 2 DDR_A_D8 3 DDR_A_D10 4 RN44 SRN22J-3-GP-U 8 7 6 5 M_R_DQ13 M_R_DM1 M_R_DQ8 M_R_DQ10 DDR_A_D6 1 DDR_A_D2 2 DDR_A_D7 3 DDR_A_D14 4 RN45 SRN22J-3-GP-U 8 7 6 5 DDR_A_D44 1 DDR_A_D42 2 DDR_A_D40 3 DDR_A_D45 4 RN33 SRN22J-3-GP-U DDR_A_D48 1 DDR_A_DM6 2 DDR_A_D49 3 DDR_A_DQS6 4 RN30 SRN22J-3-GP-U 8 7 6 5 M_R_DQ48 M_R_DM6 M_R_DQ49 M_R_DQS6 M_R_DQ6 M_R_DQ2 M_R_DQ7 M_R_DQ14 DDR_A_DQS#6 1 DDR_A_D54 2 DDR_A_D55 3 DDR_A_D50 4 RN29 SRN22J-3-GP-U 8 7 6 5 M_R_DQS#6 M_R_DQ54 M_R_DQ55 M_R_DQ50 8 7 6 5 M_R_DQ44 M_R_DQ42 M_R_DQ40 M_R_DQ45 DDR_A_D0 DDR_A_D4 DDR_A_D3 DDR_A_D5 8 7 6 5 M_R_DQ0 M_R_DQ4 M_R_DQ3 M_R_DQ5 DDR_A_D23 1 DDR_A_D29 2 DDR_A_D28 3 DDR_A_D25 4 RN39 SRN22J-3-GP-U 8 7 6 5 M_R_DQ23 M_R_DQ29 M_R_DQ28 M_R_DQ25 8 7 6 5 M_R_DQ35 M_R_DQ39 M_R_DQ38 M_R_DQ41 1 2 3 4 RN47 SRN22J-3-GP-U DDR_A_D35 1 DDR_A_D39 2 DDR_A_D38 3 DDR_A_D41 4 RN34 SRN22J-3-GP-U M_R_DQ17 M_R_DQ21 M_R_DQS2 M_R_DQS#2 DDR_A_DQS#5 1 DDR_A_DQS5 2 DDR_A_DM5 3 DDR_A_D46 4 RN32 SRN22J-3-GP-U 8 7 6 5 M_R_DQS#5 M_R_DQS5 M_R_DM5 M_R_DQ46 DDR_A_D43 1 DDR_A_D47 2 DDR_A_D53 3 DDR_A_D52 4 RN31 SRN22J-3-GP-U 8 7 6 5 M_R_DQ43 M_R_DQ47 M_R_DQ53 M_R_DQ52 DDR_A_D24 1 DDR_A_DM3 2 DDR_A_DQS#3 3 DDR_A_DQS3 4 RN38 SRN22J-3-GP-U 8 7 6 5 M_R_DQ24 M_R_DM3 M_R_DQS#3 M_R_DQS3 DDR_A_D30 1 DDR_A_D26 2 DDR_A_D31 3 DDR_A_D27 4 RN37 SRN22J-3-GP-U 8 7 6 5 M_R_DQ30 M_R_DQ26 M_R_DQ31 M_R_DQ27 DDR_A_D61 1 DDR_A_DM7 2 DDR_A_DQS#7 3 DDR_A_DQS7 4 RN27 SRN22J-3-GP-U 8 7 6 5 DDR_A_D[0..63] M_R_DQ61 M_R_DM7 M_R_DQS#7 M_R_DQS7 DDR_A_DM[0..7] DDR_A_DQS[0..7] 8 7 6 5 DDR_A_BS[0..2] DDR_A_BS[0..2] DDR_A_CS#0 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# DDR_A_CKE0 DDR_A_ODT0 DDR_A_MA13 9 9,14 4 9,14 9,14 9,14 9,14 9,14 9,14 9,14 DDR_A_MA13 9,14 DDR_A_CLK_DDR#1 DDR_A_CLK_DDR1 DDR_A_CLK_DDR#0 DDR_A_CLK_DDR0 ohm 9 DDR_A_MA[0..12] DDR_A_CS#0 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# DDR_A_CKE0 DDR_A_ODT0 series resistor 22 9 DDR_A_DQS#[0..7] DDR_A_MA[0..12] M_R_DQ58 M_R_DQ62 M_R_DQ59 M_R_DQ63 9 DDR_A_DM[0..7] DDR_A_DQS[0..7] DDR_A_DQS#[0..7] DDR_A_D58 1 DDR_A_D62 2 DDR_A_D59 3 DDR_A_D63 4 RN26 SRN22J-3-GP-U DDR_A_D[0..63] DDR_A_CLK_DDR#1 9 DDR_A_CLK_DDR1 9 DDR_A_CLK_DDR#0 9 DDR_A_CLK_DDR0 9 CHANNEL A DATA TO DIMM M_R_DQ[63..0] 3 DDR_A_DM0 1 DDR_A_D1 2 DDR_A_DQS#0 3 DDR_A_DQS0 4 RN46 SRN22J-3-GP-U 8 7 6 5 M_R_DM0 M_R_DQ1 M_R_DQS#0 M_R_DQS0 DDR_A_D12 1 DDR_A_DQS#1 2 DDR_A_DQS1 3 DDR_A_D9 4 RN43 SRN22J-3-GP-U 8 7 6 5 M_R_DQ12 M_R_DQS#1 M_R_DQS1 M_R_DQ9 DDR_A_DM2 1 DDR_A_D22 2 DDR_A_D19 3 DDR_A_D18 4 RN40 SRN22J-3-GP-U 8 7 6 5 M_R_DQ[63..0] M_R_DM[7..0] M_R_DM2 M_R_DQ22 M_R_DQ19 M_R_DQ18 M_R_DQS[7..0] M_R_DQS[7..0] M_R_DQS#[7..0] M_R_DQ51 M_R_DQ60 M_R_DQ56 M_R_DQ57 DDR_A_DM4 1 DDR_A_D33 2 DDR_A_D32 3 DDR_A_D36 4 RN36 SRN22J-3-GP-U 8 7 6 5 M_R_DM4 M_R_DQ33 M_R_DQ32 M_R_DQ36 DDR_A_D37 1 DDR_A_DQS4 2 DDR_A_DQS#4 3 DDR_A_D34 4 RN35 SRN22J-3-GP-U CHANNEL A DATA-MASK series resistor 22 ohm M_R_DQ37 M_R_DQS4 M_R_DQS#4 M_R_DQ34 8 7 6 5 M_R_A13 M_R_A8 M_R_A4 M_R_A0 DDR_A_BS1 1 DDR_A_WE# 2 DDR_A_BS0 3 DDR_A_MA12 4 RN22 SRN3J-4-GP 8 7 6 5 DDR_A_RAS# 1 DDR_A_MA9 2 DDR_A_MA5 3 DDR_A_MA1 4 RN20 SRN3J-4-GP 8 7 6 5 8 7 6 5 M_R_A11 M_R_A6 M_R_A2 M_R_CAS# DDR_A_CLK_DDR#1 1 DDR_A_MA13 1 DDR_A_MA8 2 DDR_A_MA4 3 DDR_A_MA0 4 RN17 SRN3J-4-GP M_R_A10 M_R_BS#2 DDR_A_MA11 1 DDR_A_MA6 2 DDR_A_MA2 3 DDR_A_CAS# 4 RN18 SRN3J-4-GP C664 SC5D6P50V2CN-1GP 1 R632 DDR_A_CLK_DDR1 13 13 13 13 2 2 M_A_CLK_DDR#1 0R2J-2-GP 1 R633 2 M_A_CLK_DDR1 0R2J-2-GP R736,R737 only use in Mircon 1 1 C659 SC5D6P50V2CN-1GP 1 R630 2 M_A_CLK_DDR#0 0R2J-2-GP R737 100R2J-2-GP DY DDR_A_CLK_DDR0 2 2 M_R_BS#1 M_R_WE# M_R_BS#0 M_R_A12 1 R629 2 M_A_CLK_DDR0 0R2J-2-GP SSID = MEMORY DDR_A_CKE0 1 2 RN25 SRN3J-2-GP 4 3 M_R_CKE0 4 3 M_R_ODT0 M_R_CS#0 1 Wistron Corporation DDR_A_ODT0 1 DDR_A_CS#0 2 RN16 SRN3J-2-GP ohm series resistor 3 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 ohm CHANNEL A RESISTORS Document Number Date: Wednesday, March 21, 2007 A M_A_CLK_DDR#1 M_A_CLK_DDR1 M_A_CLK_DDR#0 M_A_CLK_DDR0 R736 100R2J-2-GP DY DDR_A_CLK_DDR#0 M_R_RAS# M_R_A9 M_R_A5 M_R_A1 M_A_CLK_DDR#1 M_A_CLK_DDR1 M_A_CLK_DDR#0 M_A_CLK_DDR0 2 M_R_A7 M_R_A3 M_R_A13 13 CHANNEL A DATA-STROBE X01 CHANNEL A BANK SELECT 1 8 7 6 5 ohm 2 DDR_A_MA7 1 DDR_A_MA3 2 DDR_A_MA10 3 DDR_A_BS2 4 RN24 SRN3J-4-GP series resistor 3 M_R_CS#0 13 M_R_CAS# 13 M_R_RAS# 13 M_R_ODT0 13 M_R_CKE0 13 M_R_WE# 13 M_R_A13 Layout swap 1 M_R_BS#[2..0] 13 M_R_CS#0 M_R_CAS# M_R_RAS# M_R_ODT0 M_R_CKE0 M_R_WE# series resistor 22 CHANNEL A COMMAND RAM CELL ADDRESS 13 CHANNEL A ADDRESS 2 8 7 6 5 13 M_R_A[12..0] 13 M_R_BS#[2..0] 8 7 6 5 13 M_R_DQS#[7..0] M_R_A[12..0] DDR_A_D51 1 DDR_A_D60 2 DDR_A_D56 3 DDR_A_D57 4 RN28 SRN22J-3-GP-U 3 13 M_R_DM[7..0] 13 B C D Rev SC Parker Sheet E 12 of 53 A B C On-board DDR2 Memory D E samsung M_R_DQ[63..0] +1.8V_SUS U58 +1.8V_SUS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 C8 C2 D7 D3 D1 D9 B1 B9 M_R_DQ0 M_R_DQ1 M_R_DQ2 M_R_DQ3 M_R_DQ4 M_R_DQ5 M_R_DQ6 M_R_DQ7 NU/RDQS# DM/RDQS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 M_R_A0 M_R_A1 M_R_A2 M_R_A3 M_R_A4 M_R_A5 M_R_A6 M_R_A7 M_R_A8 M_R_A9 M_R_A10 M_R_A11 M_R_A12 M_R_A13 A8 B7 DQS# DQS NC#L7 NC#L3 L7 L3 F7 G7 RAS# CAS# VSSDL E7 CK# CK CKE VSSQ VSSQ VSSQ VSSQ VSSQ A7 B2 B8 D2 D8 BA0 BA1 BA2 VSS VSS VSS VSS A3 E3 J1 K9 A1 E9 H9 L1 VDD VDD VDD VDD A9 C1 C3 C7 C9 VDDQ VDDQ VDDQ VDDQ VDDQ E1 VDDL E2 VREF M_R_WE# M_R_CS#0 M_R_ODT0 F3 G8 F9 WE# CS# ODT M_R_DM0 A2 B3 M_R_DQS#0 M_R_DQS0 M_R_RAS# M_R_CAS# 4 V_DDR_NB_REF M_A_CLK_DDR#0 F8 M_A_CLK_DDR0 E8 M_R_CKE0 F2 3 M_R_BS#0 M_R_BS#1 M_R_BS#2 G2 G3 G1 U46 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 C8 C2 D7 D3 D1 D9 B1 B9 M_R_DQ8 M_R_DQ9 M_R_DQ10 M_R_DQ11 M_R_DQ12 M_R_DQ13 M_R_DQ14 M_R_DQ15 NU/RDQS# DM/RDQS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 M_R_A0 M_R_A1 M_R_A2 M_R_A3 M_R_A4 M_R_A5 M_R_A6 M_R_A7 M_R_A8 M_R_A9 M_R_A10 M_R_A11 M_R_A12 M_R_A13 A8 B7 DQS# DQS NC#L7 NC#L3 L7 L3 F7 G7 RAS# CAS# VSSDL E7 CK# CK CKE VSSQ VSSQ VSSQ VSSQ VSSQ A7 B2 B8 D2 D8 BA0 BA1 BA2 VSS VSS VSS VSS A3 E3 J1 K9 A1 E9 H9 L1 VDD VDD VDD VDD A9 C1 C3 C7 C9 VDDQ VDDQ VDDQ VDDQ VDDQ E1 VDDL E2 VREF M_R_WE# M_R_CS#0 M_R_ODT0 F3 G8 F9 WE# CS# ODT M_R_DM1 A2 B3 M_R_DQS#1 M_R_DQS1 M_R_RAS# M_R_CAS# V_DDR_NB_REF M_A_CLK_DDR#0 F8 M_A_CLK_DDR0 E8 M_R_CKE0 F2 M_R_BS#0 M_R_BS#1 M_R_BS#2 +1.8V_SUS G2 G3 G1 K4T1G084QC-ZCE6-GP-U U57 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 C8 C2 D7 D3 D1 D9 B1 B9 M_R_DQ16 M_R_DQ17 M_R_DQ18 M_R_DQ19 M_R_DQ20 M_R_DQ21 M_R_DQ22 M_R_DQ23 NU/RDQS# DM/RDQS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 M_R_A0 M_R_A1 M_R_A2 M_R_A3 M_R_A4 M_R_A5 M_R_A6 M_R_A7 M_R_A8 M_R_A9 M_R_A10 M_R_A11 M_R_A12 M_R_A13 A8 B7 DQS# DQS NC#L7 NC#L3 L7 L3 F7 G7 RAS# CAS# VSSDL E7 CK# CK CKE VSSQ VSSQ VSSQ VSSQ VSSQ A7 B2 B8 D2 D8 BA0 BA1 BA2 VSS VSS VSS VSS A3 E3 J1 K9 A1 E9 H9 L1 VDD VDD VDD VDD A9 C1 C3 C7 C9 VDDQ VDDQ VDDQ VDDQ VDDQ E1 VDDL E2 VREF M_R_WE# M_R_CS#0 M_R_ODT0 F3 G8 F9 WE# CS# ODT M_R_DM2 A2 B3 M_R_DQS#2 M_R_DQS2 M_R_RAS# M_R_CAS# V_DDR_NB_REF M_A_CLK_DDR#0 F8 M_A_CLK_DDR0 E8 M_R_CKE0 F2 M_R_BS#0 M_R_BS#1 M_R_BS#2 +1.8V_SUS G2 G3 G1 K4T1G084QC-ZCE6-GP-U U45 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 C8 C2 D7 D3 D1 D9 B1 B9 M_R_DQ24 M_R_DQ25 M_R_DQ26 M_R_DQ27 M_R_DQ28 M_R_DQ29 M_R_DQ30 M_R_DQ31 NU/RDQS# DM/RDQS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 M_R_A0 M_R_A1 M_R_A2 M_R_A3 M_R_A4 M_R_A5 M_R_A6 M_R_A7 M_R_A8 M_R_A9 M_R_A10 M_R_A11 M_R_A12 M_R_A13 A8 B7 DQS# DQS NC#L7 NC#L3 L7 L3 F7 G7 RAS# CAS# VSSDL E7 CK# CK CKE VSSQ VSSQ VSSQ VSSQ VSSQ A7 B2 B8 D2 D8 BA0 BA1 BA2 VSS VSS VSS VSS A3 E3 J1 K9 A1 E9 H9 L1 VDD VDD VDD VDD A9 C1 C3 C7 C9 VDDQ VDDQ VDDQ VDDQ VDDQ E1 VDDL E2 VREF M_R_WE# M_R_CS#0 M_R_ODT0 F3 G8 F9 WE# CS# ODT M_R_DM3 A2 B3 M_R_DQS#3 M_R_DQS3 M_R_RAS# M_R_CAS# V_DDR_NB_REF M_A_CLK_DDR#0 F8 M_A_CLK_DDR0 E8 M_R_CKE0 F2 M_R_BS#0 M_R_BS#1 M_R_BS#2 G2 G3 G1 K4T1G084QC-ZCE6-GP-U M_R_DQ[63..0] 12 M_R_DM[7..0] M_R_DM[7..0] 12 M_R_DQS[7..0] M_R_DQS[7..0] 12 M_R_DQS#[7..0] M_R_DQS#[7..0] 12 M_R_A[12..0] 4 M_R_A[12..0] 12 M_R_BS#[2..0] M_R_BS#[2..0] 12 M_R_A13 M_R_A13 12 M_R_CS#0 M_R_CAS# M_R_RAS# M_R_ODT0 M_R_CKE0 M_R_WE# M_R_CS#0 12 M_R_CAS# 12 M_R_RAS# 12 M_R_ODT0 12 M_R_CKE0 12 M_R_WE# 12 M_A_CLK_DDR#1 M_A_CLK_DDR1 M_A_CLK_DDR#0 M_A_CLK_DDR0 M_A_CLK_DDR#1 M_A_CLK_DDR1 M_A_CLK_DDR#0 M_A_CLK_DDR0 12 12 12 12 3 K4T1G084QC-ZCE6-GP-U SSID = MEMORY V_DDR_NB_REF A2 B3 NU/RDQS# DM/RDQS NU/RDQS# DM/RDQS A8 B7 DQS# DQS NC#L7 NC#L3 L7 L3 F7 G7 RAS# CAS# VSSDL E7 CK# CK CKE VSSQ VSSQ VSSQ VSSQ VSSQ A7 B2 B8 D2 D8 BA0 BA1 BA2 VSS VSS VSS VSS A3 E3 J1 K9 E2 VREF M_R_WE# M_R_CS#0 M_R_ODT0 F3 G8 F9 WE# CS# ODT M_R_DM7 A2 B3 L7 L3 M_R_DQS#7 M_R_DQS7 M_R_RAS# M_R_CAS# +1.8V_SUS 2 1 A8 B7 DQS# DQS NC#L7 NC#L3 M_R_RAS# M_R_CAS# F7 G7 RAS# CAS# M_A_CLK_DDR#1 F8 M_A_CLK_DDR1 E8 M_R_CKE0 F2 M_R_BS#0 M_R_BS#1 M_R_BS#2 G2 G3 G1 CK# CK CKE BA0 BA1 BA2 L7 L3 M_R_DQS#5 M_R_DQS5 A8 B7 DQS# DQS NC#L7 NC#L3 VSSDL E7 M_R_RAS# M_R_CAS# F7 G7 A7 B2 B8 D2 D8 RAS# CAS# VSSQ VSSQ VSSQ VSSQ VSSQ VSS VSS VSS VSS A3 E3 J1 K9 K4T1G084QC-ZCE6-GP-U M_A_CLK_DDR#1 F8 M_A_CLK_DDR1 E8 M_R_CKE0 F2 M_R_BS#0 M_R_BS#1 M_R_BS#2 G2 G3 G1 CK# CK CKE BA0 BA1 BA2 L7 L3 M_R_DQS#6 M_R_DQS6 A8 B7 DQS# DQS NC#L7 NC#L3 VSSDL E7 M_R_RAS# M_R_CAS# F7 G7 VSSDL E7 A7 B2 B8 D2 D8 RAS# CAS# VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ A7 B2 B8 D2 D8 VSS VSS VSS VSS A3 E3 J1 K9 VSS VSS VSS VSS A3 E3 J1 K9 K4T1G084QC-ZCE6-GP-U M_A_CLK_DDR#1 F8 M_A_CLK_DDR1 E8 M_R_CKE0 F2 M_R_BS#0 M_R_BS#1 M_R_BS#2 G2 G3 G1 CK# CK CKE BA0 BA1 BA2 M_A_CLK_DDR#1 F8 M_A_CLK_DDR1 E8 M_R_CKE0 F2 M_R_BS#0 M_R_BS#1 M_R_BS#2 K4T1G084QC-ZCE6-GP-U G2 G3 G1 2 M_R_DQS#4 M_R_DQS4 C688 SC1U10V2KX-1GP M_R_DM6 M_R_A0 M_R_A1 M_R_A2 M_R_A3 M_R_A4 M_R_A5 M_R_A6 M_R_A7 M_R_A8 M_R_A9 M_R_A10 M_R_A11 M_R_A12 M_R_A13 VDDL C714 SCD1U10V2KX-4GP 2 1 WE# CS# ODT H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 E1 V_DDR_NB_REF C642 SC10U4V3MX-GP F3 G8 F9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 VDDQ VDDQ VDDQ VDDQ VDDQ C644 SCD1U10V2KX-4GP 2 1 NU/RDQS# DM/RDQS M_R_WE# M_R_CS#0 M_R_ODT0 M_R_A0 M_R_A1 M_R_A2 M_R_A3 M_R_A4 M_R_A5 M_R_A6 M_R_A7 M_R_A8 M_R_A9 M_R_A10 M_R_A11 M_R_A12 M_R_A13 A9 C1 C3 C7 C9 C648 SCD1U10V2KX-4GP 2 1 A2 B3 VREF H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 M_R_DQ56 M_R_DQ57 M_R_DQ58 M_R_DQ59 M_R_DQ60 M_R_DQ61 M_R_DQ62 M_R_DQ63 C663 SCD1U10V2KX-4GP 2 1 M_R_DM5 E2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 C8 C2 D7 D3 D1 D9 B1 B9 VDD VDD VDD VDD C681 SCD1U10V2KX-4GP WE# CS# ODT VDDL DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 A1 E9 H9 L1 C691 SCD1U10V2KX-4GP 2 1 F3 G8 F9 E1 V_DDR_NB_REF M_R_DQ48 M_R_DQ49 M_R_DQ50 M_R_DQ51 M_R_DQ52 M_R_DQ53 M_R_DQ54 M_R_DQ55 C637 SCD1U10V2KX-4GP 2 1 NU/RDQS# DM/RDQS M_R_WE# M_R_CS#0 M_R_ODT0 M_R_A0 M_R_A1 M_R_A2 M_R_A3 M_R_A4 M_R_A5 M_R_A6 M_R_A7 M_R_A8 M_R_A9 M_R_A10 M_R_A11 M_R_A12 M_R_A13 VDDQ VDDQ VDDQ VDDQ VDDQ C8 C2 D7 D3 D1 D9 B1 B9 C660 SCD1U10V2KX-4GP 2 1 A2 B3 VREF H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 A9 C1 C3 C7 C9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 C690 SCD1U10V2KX-4GP 2 1 M_R_DM4 E2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 VDD VDD VDD VDD C675 SCD1U10V2KX-4GP 2 1 WE# CS# ODT VDDL A1 E9 H9 L1 C666 SCD1U10V2KX-4GP 2 1 F3 G8 F9 E1 V_DDR_NB_REF M_R_DQ40 M_R_DQ41 M_R_DQ42 M_R_DQ43 M_R_DQ44 M_R_DQ45 M_R_DQ46 M_R_DQ47 C696 SCD1U10V2KX-4GP 2 1 M_R_WE# M_R_CS#0 M_R_ODT0 M_R_A0 M_R_A1 M_R_A2 M_R_A3 M_R_A4 M_R_A5 M_R_A6 M_R_A7 M_R_A8 M_R_A9 M_R_A10 M_R_A11 M_R_A12 M_R_A13 VDDQ VDDQ VDDQ VDDQ VDDQ C8 C2 D7 D3 D1 D9 B1 B9 C626 SCD1U10V2KX-4GP 2 1 VREF H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 A9 C1 C3 C7 C9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 C661 SCD1U10V2KX-4GP 2 1 E2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 VDD VDD VDD VDD C695 SCD1U10V2KX-4GP 2 1 VDDL A1 E9 H9 L1 C647 SCD1U10V2KX-4GP 2 1 E1 V_DDR_NB_REF 2 M_R_DQ32 M_R_DQ33 M_R_DQ34 M_R_DQ35 M_R_DQ36 M_R_DQ37 M_R_DQ38 M_R_DQ39 2 VDDQ VDDQ VDDQ VDDQ VDDQ C8 C2 D7 D3 D1 D9 B1 B9 1 A9 C1 C3 C7 C9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 2 VDD VDD VDD VDD C631 SCD1U10V2KX-4GP 2 1 A1 E9 H9 L1 C689 SCD1U10V2KX-4GP 2 1 U43 C646 SCD1U10V2KX-4GP 2 1 +1.8V_SUS C645 SCD1U10V2KX-4GP 2 1 U55 1 +1.8V_SUS C649 SCD1U10V2KX-4GP 2 1 U56 C650 SCD1U10V2KX-4GP 2 1 +1.8V_SUS C662 SCD1U10V2KX-4GP 2 1 U44 C630 SCD1U10V2KX-4GP 2 1 +1.8V_SUS K4T1G084QC-ZCE6-GP-U 1 1 Place around the DDR2 chips Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title ON BOARD MEMORY Size Document Number Custom A B C D Rev SC Parker Date: Wednesday, March 21, 2007 Sheet E 13 of 53 A B C D E SSID = MEMORY DDR_A_BS[0..2] 4 DDR_A_MA[0..12] DDR_A_MA13 DDR_A_BS[0..2] DDR_A_MA[0..12] 4 9,12 9,12 DDR_A_MA13 9,12 ON-BOARD MEMORY TERMINATION +0.9V_DDR_VTT 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 DIMMA-DDR +0.9V_DDR_VTT DE-COUPLINGPleace +0.9V_DDR_VTT use One Capacitor close to every Two pull-up Resistors 1 2 C748 SC4D7U6D3V3KX-GP 1 C750 SC4D7U6D3V3KX-GP 2 1 C740 SCD1U10V2KX-4GP 2 1 2 C636 SCD1U10V2KX-4GP 1 2 C643 SCD1U10V2KX-4GP 1 C653 SCD1U10V2KX-4GP 2 1 C632 SCD1U10V2KX-4GP 2 1 2 C651 SCD1U10V2KX-4GP 1 C627 SCD1U10V2KX-4GP 2 1 C745 SCD1U10V2KX-4GP 2 1 2 C694 SCD1U10V2KX-4GP 1 C693 SCD1U10V2KX-4GP 2 1 C741 SCD1U10V2KX-4GP 2 1 2 C744 SCD1U10V2KX-4GP 1 2 C692 SCD1U10V2KX-4GP 3 DDR_A_BS0 DDR_A_MA12 DDR_A_MA7 DDR_A_MA3 RN82 SRN56J-5-GP DDR_A_MA4 DDR_A_MA0 DDR_A_MA11 DDR_A_MA6 RN79 SRN56J-5-GP DDR_A_MA2 DDR_A_CAS# DDR_A_RAS# DDR_A_MA9 RN80 SRN56J-5-GP DDR_A_MA10 DDR_A_BS2 DDR_A_CKE0 RN86 SRN56J-5-GP DDR_A_ODT0 DDR_A_CS#0 DDR_A_MA13 DDR_A_MA8 RN76 SRN56J-5-GP DDR_A_MA5 DDR_A_MA1 DDR_A_BS1 DDR_A_WE# RN81 SRN56J-5-GP Layout swap DDR_A_CAS# 9,12 DDR_A_RAS# 9,12 3 Layout swap DDR_A_CKE0 9,12 DDR_A_ODT0 9,12 DDR_A_CS#0 9,12 Layout swap DDR_A_WE# 9,12 2 2 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 ON-BOARD MEMORY TERMINATION Document Number Date: Wednesday, March 21, 2007 A B C D Rev SC Parker Sheet E 14 of 53 1 1 A 1 1 1 1 B 1 1 1 1 1 1 1 1 1 1 1 1 1 C382 SC10U4V3MX-GP 2 C381 SC10U4V3MX-GP 2 C384 SC2D2U6D3V3MX-1-GP 2 C375 SCD1U10V2KX-4GP 2 C378 SC2D2U6D3V3MX-1-GP 2 C373 SCD1U10V2KX-4GP 2 C383 SC2D2U6D3V3MX-1-GP 2 11 29 49 68 129 146 167 186 13 31 51 70 131 148 169 188 114 119 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_ODT0 DDR_B_ODT1 DIMMB-DDR +1.8V_SUS DE-COUPLING 2 +1.8V_SUS DIMMB-DDR +0.9V_DDR_VTT DE-COUPLING Pleace close to the DIMM Slot Pleace use One Capacitor close to every Two pull-up Resistors 1 C 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 DDR_B_WE# DDR_B_CAS# DDR_B_CS#1 DDR_B_ODT1 RN95 SRN56J-5-GP DDR_B_MA14 DDR_B_CKE1 DDR_B_MA7 DDR_B_MA11 RN89 SRN56J-5-GP DDR_B_ODT0 DDR_B_MA13 DDR_B_CKE0 DDR_B_BS2 RN92 SRN56J-5-GP DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 RN93 SRN56J-5-GP DDR_B_MA0 DDR_B_BS1 DDR_B_RAS# DDR_B_CS#0 RN91 SRN56J-5-GP DDR_B_MA3 DDR_B_MA1 DDR_B_MA10 DDR_B_BS0 RN94 SRN56J-5-GP DDR_B_MA6 DDR_B_MA2 DDR_B_MA4 RN90 SRN56J-5-GP D Size A3 201 DDR_B_CS#[0..1] DDR_B_DQS[0..7] DDR_B_DQS#[0..7] DDR_B_CKE[0..1] DDR_B_ODT[0..1] GND DDR_B_BS[0..2] GND 1 C719 SC2D2U6D3V3MX-1-GP 2 DDR_B_DM[0..7] C712 SC2D2U6D3V3MX-1-GP 202 1 DDR_B_MA[0..14] 1 2 C717 SCD1U10V2KX-4GP DDR_B_D[0..63] 2 VREF VSS ODT0 ODT1 DDR_SEL_B0 DDR_SEL_B1 +3.3V_RUN 1 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196 81 82 87 88 95 96 103 104 111 112 117 118 50 69 83 120 163 198 200 199 195 197 SSID = MEMORY DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD NC#50 NC#69 NC#83 NC#120 NC#163/TEST SA0 SA1 VDDSPD SDA SCL 10 26 52 67 130 147 170 185 164 166 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 DDR_B_CKE0 DDR_B_CKE1 79 80 +1.8V_SUS /DQS0 /DQS1 /DQS2 /DQS3 /DQS4 /DQS5 /DQS6 /DQS7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DDR_B_CS#0 DDR_B_CS#1 110 115 30 32 DDR_B_RAS# DDR_B_WE# DDR_B_CAS# 108 109 113 C 1 2 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 BA0 BA1 CK1 /CK1 CK0 /CK0 CKE0 CKE1 /CS0 /CS1 /RAS /WE /CAS B C715 SCD1U10V2KX-4GP 2 107 106 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 2 C718 SC4D7U6D3V3KX-GP 1 C374 SCD1U10V2KX-4GP 2 102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 2 2 C749 SC4D7U6D3V3KX-GP 2 C747 SCD1U10V2KX-4GP 2 C724 SCD1U10V2KX-4GP 1 1 C376 SC2D2U6D3V3MX-1-GP 2 1 R311 0R2J-2-GP 1 R307 0R2J-2-GP 2 C739 SCD1U10V2KX-4GP 2 1 C372 SCD1U10V2KX-4GP 2 MEN_SCLK MEN_SDAT M_B_CLK_DDR#1 M_B_CLK_DDR1 M_B_CLK_DDR#0 M_B_CLK_DDR0 C726 SCD1U10V2KX-4GP 2 C725 SCD1U10V2KX-4GP 2 +0.9V_DDR_VTT C716 SCD1U10V2KX-4GP 2 C742 SCD1U10V2KX-4GP 2 C743 SCD1U10V2KX-4GP 2 C723 SCD1U10V2KX-4GP 1 1 20 MEN_SCLK 20 MEN_SDAT 9 M_B_CLK_DDR#1 9 M_B_CLK_DDR1 9 M_B_CLK_DDR#0 9 M_B_CLK_DDR0 2 C746 SCD1U10V2KX-4GP 1 2 C380 SC2D2U6D3V3MX-1-GP 3 2 C721 SCD1U10V2KX-4GP 2 C738 SCD1U10V2KX-4GP 4 2 C722 SCD1U10V2KX-4GP 2 A D E DDR_B_D[0..63] DDR_B_MA[0..14] DDR_B_DM[0..7] 9 DDR_B_BS[0..2] 9 Date: Wednesday, March 21, 2007 9 DDR_B_CS#[0..1] 9 DDR_B_DQS[0..7] DDR_B_DQS#[0..7] 9 DDR_B_CKE[0..1] 9 DDR_B_ODT[0..1] 9 9 9 4 DDR1 DDR2-200P-8-GP-U1 62.10017.861 3 V_DDR_NB_REF +0.9V_DDR_VTT DDR_B_WE# 9 DDR_B_CAS# 9 2 DDR_B_RAS# 9 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Document Number DDR-B Parker Sheet E 15 of 53 Rev SC A B C D E SSID = VIDEO A +5V_RUN D17 RB500V-40TE-GP K 5V_CRT_S0 4 CRT1 R1 6K8R2J-GP 16 1 D_DDC_DATA 38 D_DDC_CLK C423 SC27P50V3JN-GP 20.20720.015 DY DY 2 17 VIDEO-15-77-GP 2 2 D_DDC_CLK 1 DY VSYNC_CRT 15 2 DY 14 C424 SC27P50V3JN-GP 2 DY X01 5V_CRT_S0 HSYNC_CRT 1 BLM18BA100SN1DGP D_DDC_DATA 13 C2 SC100P50V2JN-3GP CRT_B 12 2 2 7 2 8 3 9 4 10 5 1 1 CRT_G BLM18BA100SN1DGP 11 C1 SC100P50V2JN-3GP 2 6 1 2 1 CRT_R BLM18BA100SN1DGP C420 SC3P50V2CN-1-GP L37 R354 150R2F-1-GP R352 150R2F-1-GP 2 1 1 2 2 DY R353 150R2F-1-GP 2 1 1 C429 SC6P50V2CN-1GP 1 DY 2 2 DY C430 SC6P50V2CN-1GP 1 10,38 NB_BLUE C431 SC6P50V2CN-1GP L38 2 C421 SC3P50V2CN-1-GP 2 1 10,38 NB_GREEN 1 1 L39 C422 SC3P50V2CN-1-GP 2 1 10,38 NB_RED R2 6K8R2J-GP 2 For NB and DOCK C426 SCD01U50V2KX-1GP 1 1 1 4 38 DOCK 3 3 DOCKED SYSTEM DOCKED 36,38 +5V_RUN 3 GND Y 4 U72 74AHCT1G125GW-1-GP K A D1 RB500V-40TE-GP HSYNC_5 2 DY 1 R355 39R2J-L-GP 10 NB_VSYNC 2 NB_VSYNC_1 1 OE# 2 A VCC 5 3 GND Y 4 U71 74AHCT1G125GW-1-GP VSYNC_5 1 2 2 DY DOCK_DET# C3 SCD1U10V2KX-4GP RN1 SRN1KJ-7-GP 5V_CRT_S0 1 2 L41 BLM18BA100SN1DGP HSYNC_CRT 5 CRT_R 6 7 VSYNC_CRT 1 2 L40 BLM18BA100SN1DGP 4 4 CRT_G 3 DY 8 U1 PACDN009 5 2 DY 2 1 D_DDC_CLK 3 D_DDC_DATA 6 CRT_B 2 1 D2 BAV99DPT-GP X01 +3.3V_RUN TO DOCK DOCK_DET# 38 1 OE# 2 A VCC 1 OE# 2 A VCC NB_DDCCLK 5 3 GND Y 4 U2 74AHCT1G125GW-1-GP 1 5V_CRT_S0 4 3 5 1 2 VCC 1 A 2 OE# 2 1 1 C428 SC22P50V2JN-4GP NB_HSYNC_1 C427 SC22P50V2JN-4GP 1 2 R356 39R2J-L-GP 10 NB_HSYNC D_HSYNC_5 R3 1 2 33R2J-2-GP D_HSYNC D_DDC_DATA 38 3 5 2 6 1 D_DDC_CLK NB_DDCDATA 10 U4 2N7002DW-7F-GP 5 3 GND Y 4 U3 74AHCT1G125GW-1-GP 4 10 D_VSYNC_5 R4 1 2 33R2J-2-GP D_VSYNC 1 Wistron Corporation 38 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CRT Size A3 Document Number Rev A B C D SC Parker Date: Wednesday, March 21, 2007 Sheet E 16 of 53 A B 5 2 6 1 DY 1 R750 +3.3V_RUN 1 R751 1 2 0R3-0-U-GP DY +3.3V_BIOMET 2 0R3-0-U-GP C54 2 0R3-0-U-GP DY +3.3V_RUN C53 SCD1U10V2KX-4GP 2 2 C19 SC1KP50V2KX-1GP USBP3_DUSBP3_D+ USBP5_DUSBP5_D+ LCD_TST 36 LCD_TST 1 1 2 1 C28 SCD1U10V2KX-4GP 2 S_PWR_SRC 2 LCDVDD C30 SCD1U10V2KX-4GP 2 X01 1 1 2 C34 SC1KP50V2KX-1GP SCD1U10V2KX-4GP 1 R748 C64 SCD1U10V2KX-4GP 1 +3.3V_SUS C31 SCD1U10V2KX-4GP 2 100KR2J-1-GP 1 2 3 U10 SI3457BDV-T1-1GP C23 SC4D7U25V5KX-GP 2 1 1 1 2 2 G R42 200KR2J-L1-GP D D G C24 SC4D7U25V5KX-GP 2 1 6 D 5 D 4 S +PWR_SRC C_PWR_SRC 1 D Q4 R55 2N7002-7F-GP 1 +3.3V_ALW AUD_DMIC_IN0 AUD_DMIC_CLK_G BT_LED LED_WLAN_OUT BAT1_LED BAT2_LED HDD_LED BREATH_PWRLED POWER_SW# KSO18 KSI7 KSI3 KSI2 KSI1 KSI0 KSI6 KSI5 KSI4 +3.3V_DIGITIZER U13 2N7002DW-7F-GP FPVCC_CTL3 GFX_PWR_SRC NB_LDDC_DATA NB_LDDC_CLK 10 NB_LDDC_DATA 10 NB_LDDC_CLK C56 SCD1U10V2KX-4GP DY LCD_A0+ LCD_A0- 2 10 LCD_A0+ 10 LCD_A0- LCD_A1+ LCD_A1- 10 LCD_A1+ 10 LCD_A1- 3 LCD_A2+ LCD_A2- 3 PIN LCD_ACLK+ LCD_ACLK- 2 LVDS 3 INVERTER POWER 61 FOX-CON60-GP-U C563 SC1U10V2KX-1GP 1 Biometric NP2 10 PIN 20.F1015.060 User-Programmable Botton Toggle Switch Battery status LED. 1 IN 37 KSI5 KSI3 37 KSI3 KSI5 2 35 BAT2_LED# R1 Screen Rotation Botton KSI1 R Q6 DTA114YKA-1-GP L KSI6 37 KSI6 2 USBP3_D- +3.3V_ALW 1 Forward Botton G 2 37 KSI7 R118 4K7R2J-2-GP 2 S 35 BAT1_LED# +5V_ALW Q16 2N7002-7F-GP R2 EL1 DLW21SN900SQ2LUGP BAT1_LED#_1 D 1 IN KSI7 2 R1 KSO18 37 KSO18 DY BAT2_LED 3 OUT 1 2 R75 0R2J-2-GP KSI4 37 KSI4 Mobility Center Botton Amber KSI2 37 KSI2 R2 KSI0 37 KSI0 37 KSI1 1 Digi Tizer +3.3V_ALW 2 PIN Q7 DTA114YKA-1-GP Power & Suspend LED. blue BAT1_LED 3 +3.3V_ALW 2 3 4 Botton function 10KR2J-3-GP Ctrl+Del+Alt Botton maybe use the same SMBUS 20 SB600_USBP3- 4 LED's POWER_SW# 2 2 PIN Digi Tizer +3.3V_RUN PLANE 2 1 1 1 R511 35,51 MAIN_PWR_SW# LCD_SMBCLK LCD_SMBDAT SW1 PUSH-SW31-U2-GP 23 POWER_SW# 2 AUD_DMIC_CLK_G AUD_DMIC_IN0 Light Sensor +3.3V_RUN PLANE 2 10 LCD_ACLK+ 10 LCD_ACLK- 5 GFX_PWR_SRC R504 100KR2J-1-GP 35 LCD_SMBCLK 35 LCD_SMBDAT 6 +RTC_CELL +3.3V_RUN PLANE 29 AUD_DMIC_CLK_G 29 AUD_DMIC_IN0 CLOSED CONNECT PIN Power Botton Digi MICs GND 750uA GND Digi MICs 4 3 10 LCD_A2+ 10 LCD_A2- INVERTER OUT S 2 DY 1 2 R53 4K7R2J-2-GP 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 LCD_SMBCLK_LCD LCD_SMBDAT_LCD 2 2 0R2J-2-GP 0R2J-2-GP 2 FPVCC_CTL2 1 3 OUT 2 R1 IN 1 GND R2 Q3 DDTC144EUA-7F-GP 35,47,48,51 RUN_ON 1 1 R46 R50 C32 SCD1U10V2KX-4GP 3 LCD_SMBCLK LCD_SMBDAT 2 4 1 1 D4 BAT54CW-1-GP C29 C42 SCD1U10V2KX-4GP 2 1 FPVCC_CTL1 DY FPVCC_CTL4 +5V_ALW SC1KP50V2KX-1GP 1 2 R35 100KR2J-1-GP 35 LCDVCC_TST_EN 1 R47 150R2F-1-GP 4 3 X01 1 INVERTER_CBL_DET# 37 INVERTER_CBL_DET# C27 SC10U10V5KX-2GP NP1 LCD_CBL_DET# 36 LCD_CBL_DET# 2 U11 SI3456BDV-T1-GP 62 LCDVDD D 6 D 5 S 4 1 1 2 1 D 2 D 3 G 1 2 C33 SCD1U25V2ZY-1GP 2 E LVDS1 1 2 R37 100KR2J-1-GP +15V_ALW D SSID = INVERTER C38 SCD1U10V2KX-4GP 10 ENVDD C +3.3V_ALW Choose the Transistors Type and Rating base on the LCD Panel Power requirements for each system +5V_SUS 2 +5V_RUN G G R116 100KR2J-1-GP Q17 2N7002-7F-GP 1 1 32 LED_WLAN_OUT# S LED_WLAN_OUT#_1 D R2 IN R1 2 Q66 DTA114YKA-1-GP 2 Q8 DTA114YKA-1-GP 1 3 LED_WLAN_OUT_1 1 R101 2 LED_WLAN_OUT 220R2J-L2-GP 3 HDD_LED_1 1 R701 2 HDD_LED 220R2J-L2-GP 6 PIN 1 3 DY 1 2 1LED_WLAN_OUT#_2 D6 RB751V-40-1-GP GND 2 +5V_RUN OUT 1 +3.3V_WLAN HDD activity LED. 33 PATA_ACT# 4 BREATH_PWRLED IN EL2 DLW21SN900SQ2LUGP 3 R1 USBP5_D- WLAN LED. R2 1 2 R73 0R2J-2-GP 1 GND IN R1 2 PIN 20 SB600_USBP5- 1 BREATH_LED#_1 D 2 Q15 Q5 2N7002-7F-GP DTA114YKA-1-GP S 35 BREATH_LED# Biometric +3.3V_RUN PLANE R2 USBP3_D+ 2 0R2J-2-GP 1 GND R74 OUT 20 SB600_USBP3+ OUT R117 100KR2J-1-GP Bluetooth LED. USBP5_D+ 2 0R2J-2-GP +5V_RUN Wistron Corporation Q9 R2 IN 2 R1 31 BT_ACTIVE# 1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. BT_LED_1 3 2 DTA114YKA-1-GP 1 1 GND R72 OUT 20 SB600_USBP5+ 2 BT_LED 680R2J-3-GP 1 R98 C74 SC2200P50V2KX-2GP Title LVDS Size Document Number Custom Date: A B C D Rev SC Parker Wednesday, March 21, 2007 Sheet E 17 of 53 B C 1 PCIE_CALI U29 PCIE_PVDD U28 PCIE_PVSS F27 F28 F29 G26 G27 G28 G29 J27 J29 L25 L26 L29 N29 PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR 1 C562 SCD1U10V2KX-4GP 1 2 1 C583 SC1U10V2KX-1GP 2 1 C588 SC1U10V2KX-1GP 2 2 +3.3V_ALW +5V_ALW DY 2 1 R439 10KR2J-3-GP 35 CPU_PWRGD R413 10KR2J-3-GP 1 D DY DY G H_PWRGOOD_1 3 S Q51 2N7002-7F-GP 1 DYQ44 MMBT3904-7-F-GP 2 2 SB_XTAL0 1 DYR406 2 D2 X1 C1 X2 INTE#/GPIO33 INTF#/GPIO34 INTG#/GPIO35 INTH#/GPIO36 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_C_BE#0 PCI_C_BE#1 PCI_C_BE#2 PCI_C_BE#3 PCI_FRAME# PCI_DEVSEL# PCI_IRDY# PCI_TRDY# PCI_PAR PCI_STOP# PCI_PERR# PCI_SERR# PCI_REQ#0 PCI_REQ#1 PCI_REQ#2 PCI_REQ#3 PCI_REQ#4 PCI_GNT#0 PCI_GNT#1 PCI_GNT#2 PCI_GNT#3 PCI_GNT#4 CLKRUN# PCI_LOCK# AD3 AF1 AF4 AF3 PCI_INTE# PCI_INTF# PCI_INTG# PCI_INTH# AG24 AG25 AH24 AH25 AF24 AJ24 AH26 W22 AF23 LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_FRAME# LPC_DRQ0# LPC_DRQ1# PCI_REQ#5 IRQ_SERIRQ CLK_PCI_5025 CLK_PCI_TPM CLK_PCI_PCCARD 2 2 SB_XTAL2_1 1 R159 0R2J-2-GP 2 5,42 H_DPRSLPVR 5 H_DPRSTP#_R 1394/ MediaCard PCI_C_BE#0 25 PCI_C_BE#1 25 PCI_C_BE#2 25 PCI_C_BE#3 25 PCI_FRAME# 25 PCI_DEVSEL# 25 PCI_IRDY# 25 PCI_TRDY# 25 PCI_PAR 25 PCI_STOP# 25 PCI_PERR# 25 PCI_SERR# 25 TP68 TPAD28 RTCCLK RTC_IRQ#/GPIO69 D3 F5 VBAT RTC_GND E1 D1 SB600-GP REQ GNT AD17 1 1 G H +3.3V_RUN CLKRUN# IRQ_SERIRQ 1 R588 1 R600 2 210KR2J-3-GP 10KR2J-3-GP PCI_REQ#1 25 TP172TPAD28 TP69 TPAD28 TP66 TPAD28 TP171TPAD28 PCI_REQ#5 R578 DY 1 1 C207 SC18P50V2JN-1-GP SB_A_RST# 2 1 2 C243 SC18P50V2JN-1-GP +3.3V_SUS PCI_GNT#1 25 CLKRUN# 25,35 TP173TPAD28 2 TP170TPAD28 TP174TPAD28 PCI_INTG# 25 PCI_INTH# 25 LPC_LAD0 27,35 LPC_LAD1 27,35 LPC_LAD2 27,35 LPC_LAD3 27,35 LPC_FRAME# 27,35 TP63 TPAD28 TP64 TPAD28 TP154TPAD28 IRQ_SERIRQ 25,27,35 SB_RTCCLK SB_ACPWR_STRAPSB_RTCCLK 22 SB_RTC R434 0R2J-2-GP +RTC_CELL 1 TP117 TPAD28 +RTC_CELL +3.3V_RTC_LDO +3.3V_RTC_LDO_1 RTC1 4 1 3 D25 BAT54CW-1-GP 2 VBAT 1 19 RTC_BAT_DET# 2 VBAT_R R435 1KR2J-1-GP MLX-CON3-7-GP 2 A VCC 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 5 Title SB600-CPU&LPC&PCI&PCIE(1/5) PLTRST#_S 2 1 R664 22R2J-2-GP PLTRST# 7,27,31,32,35,45,46,51 Size Document Number Custom Rev C D SC Parker Date: Wednesday, March 21, 2007 B 1 20.F0693.003 +3.3V_SUS 3 GND Y 4 U97 74AHC1G08GW-GP-U Place Close to pin D2,C1 A B 2 3 5 Wistron Corporation AND Gate 1 2 10KR2J-3-GP TP67 TPAD28 TP163TPAD28 TP65 TPAD28 2 DY 1 2 X2 X-32D768KHZ-43GP 3 IDSEL INT 1 LPC SB_XTAL2 R167 20MR3-GP 1 22,25 PCI Interface Routing C258 SCD1U10V2KX-4GP 1 1 R154 20MR3-GP 5 H_DPSLP# 2 SB_XTAL0 H_IGNNE# H_A20M# H_FERR# H_STPCLK# H_CPU_STP# 1 1 R480 0R2J-2-GP SB_Xtal 5 5 5 5 4 CPU_PG/LDT_PG INTR/LINT0 NMI/LINT1 INIT# SMI# SLP#/LDT_STP# IGNNE#/SIC A20M#/SID FERR# STPCLK#/ALLOW_LDTSTP CPU_STP#/DPSLP_3V# DPSLP_OD#/GPIO37 DPRSLPVR LDT_RST#/DPRSTP#/PROCHOT# C266 SC1U10V2KX-1GP 2 1 2 H_INTR# H_NMI# H_INIT# H_SMI# LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ0# LDRQ1#/GNT5#/GPIO68 BMREQ#/REQ5#/GPIO65 SERIRQ RTC 5,7 H_CPUSLP# 1 R581 0R2J-2-GP 5 5 5 5 PCI_AD[0..31] SSID =RBATT CPU OD need pull high NB level shift AC26 W26 W24 W25 AA24 AA23 AA22 AA26 Y27 AA25 AH9 B24 W23 AC25 XTAL 5,51 H_PWRGOOD H_PWRGOOD H_INTR# H_NMI# H_INIT# H_SMI# H_CPUSLP#_R H_IGNNE# H_A20M# H_FERR# H_STPCLK# H_CPU_STP# H_DPSLP#_R H_DPRSLPVR H_DPRSTP#_R 4 PCI_AD[0..31] 10KR2J-3-GP SB_XTAL2 22,25 1 PCIE_CALRP PCIE_CALRN E27 W7 Y1 W8 W5 AA5 Y3 AA6 AC5 AA7 AC3 AC7 AJ7 AD4 AB11 AE6 AC9 AA3 AJ4 AB1 AH4 AB2 AJ3 AB3 AH3 AC1 AH2 AC2 AH1 AD2 AG2 AD1 AG1 AB9 AF9 AJ5 AG3 AA2 AH6 AG5 AA1 AF7 Y2 AG8 AC11 AJ8 AE2 AG9 AH8 AH5 AD11 AF2 AH7 AB12 AG4 AG7 AF6 CLK_SB_PCI0 22 22R2J-2-GP CLK_SB_PCI1 22 22R2J-2-GP CLK_SB_PCI3 CLK_PCI_5025 35 22R2J-2-GP TP62 TPAD28 22R2J-2-GP CLK_SB_PCI4 22 22R2J-2-GP CLK_PCI_TPM 27 22R2J-2-GP CLK_PCI_PCCARD 22R2J-2-GP GPIO TP57 TPAD28 PCI_RST# 2 PCI_RST# 25,51 2 22R2J-2-GP 8K2R2J-3-GP 2 E29 E28 PCIE_CALI AD0/ROMA18 AD1/ROMA17 AD2/ROMA16 AD3/ROMA15 AD4/ROMA14 AD5/ROMA13 AD6/ROMA12 AD7/ROMA11 AD8/ROMA9 AD9/ROMA8 AD10/ROMA7 AD11/ROMA6 AD12/ROMA5 AD13/ROMA4 AD14/ROMA3 AD15/ROMA2 AD16/ROMD0 AD17/ROMD1 AD18/ROMD2 AD19/ROMD3 AD20/ROMD4 AD21/ROMD5 AD22/ROMD6 AD23/ROMD7 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 CBE0#/ROMA10 CBE1#/ROMA1 CBE2#/ROMWE# CBE3# FRAME# DEVSEL#/ROMA0 IRDY# TRDY#/ROMOE# PAR/ROMA19 STOP# PERR# SERR# REQ0# REQ1# REQ2# REQ3#/GPIO70 REQ4#/GPIO71 GNT0# GNT1# GNT2# GNT3#/GPIO72 GNT4#/GPIO73 CLKRUN# LOCK# 1 R621 1 R620 2 2 2 2 2 2 2 C320 SC10P50V2JN-4GP PCIE_CALRP PCIE_CALRN 2 2 562R2F-GP 2K05R2F-GP 2 0R2J-2-GP PCI_RST#_R 1 1 1 1 1 1 1 1 PCIE_RX0P PCIE_RX0N PCIE_RX1P PCIE_RX1N PCIE_RX2P PCIE_RX2N PCIE_RX3P PCIE_RX3N PCIRST# AJ9 R213 R201 R216 R243 R601 R239 R554 2 T25 T26 T22 T23 M25 M26 M22 M23 2 1 2 1 2 3 PCIE_NB_OUT0 PCIE_NB_OUT#0 PCIE_NB_OUT1 PCIE_NB_OUT#1 PCIE_NB_OUT2 PCIE_NB_OUT#2 PCIE_NB_OUT3 PCIE_NB_OUT#3 VCC_SB_VDDR C245 SC22U6D3V5MX-2GP 1500mA 1 2 L24 BLM18PG181SN-3GP VCC_RUN_SB PCIE_TX0P PCIE_TX0N PCIE_TX1P PCIE_TX1N PCIE_TX2P PCIE_TX2N PCIE_TX3P PCIE_TX3N C306 SC1U10V2KX-1GP C596 SC1U10V2KX-1GP 2 1 C315 SC10U4V3MX-GP 1 2 L31 BLM18PG181SN-3GP VCC_RUN_SB P29 P28 M29 M28 K29 K28 H29 H28 PCIE_NB_OUT0 PCIE_NB_OUT#0 PCIE_NB_OUT1 PCIE_NB_OUT#1 PCIE_NB_OUT2 PCIE_NB_OUT#2 PCIE_NB_OUT3 PCIE_NB_OUT#3 1 R502 1 R510 1 R496 VCC_SB_VDDR VCC_SB_PVDD PCIE_SB_OUT0_S PCIE_SB_OUT#0_S PCIE_SB_OUT1_S PCIE_SB_OUT#1_S PCIE_SB_OUT2_S PCIE_SB_OUT#2_S PCIE_SB_OUT3_S PCIE_SB_OUT#3_S CLK_SB_PCI0_R CLK_SB_PCI1_R CLK_SB_PCI2_R CLK_SB_PCI3_R CLK_SB_PCI4_R CLK_SB_PCI5_R CLK_SB_PCI6_R SB_SPDIFOUT C326 SC10P50V2JN-4GP 8 8 8 8 8 8 8 8 Place R160,R155,R156 Close to pin E29,E28,E27<100 mil 1500mA SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP U2 T2 U1 V2 W3 U3 V1 T1 2 2 2 2 2 2 2 2 2 PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 SPDIF_OUT/PCICLK7/GPIO41 1 1 1 1 1 1 1 1 1 PCIE_RCLKP PCIE_RCLKN 2 C288 C299 C277 C279 C267 C273 C256 C262 2 4 PCIE_SB_OUT0 PCIE_SB_OUT#0 PCIE_SB_OUT1 PCIE_SB_OUT#1 PCIE_SB_OUT2 PCIE_SB_OUT#2 PCIE_SB_OUT3 PCIE_SB_OUT#3 PCIE_SB_OUT0 PCIE_SB_OUT#0 PCIE_SB_OUT1 PCIE_SB_OUT#1 PCIE_SB_OUT2 PCIE_SB_OUT#2 PCIE_SB_OUT3 PCIE_SB_OUT#3 C579 SCD1U10V2KX-4GP 8 8 8 8 8 8 8 8 A_RST# C607 SC10P50V2JN-4GP SB_A_RST# 2 AG10 8K2R2J-3-GP CLK_SBLINK J24 CLK_SBLINK# J25 1 4 CLK_SBLINK 4 CLK_SBLINK# PCI INTERFACE R619 E 1 of 4 U35A PCI CLKS SSID = S.B D PCI EXPRESS INTERFACE A Sheet E 18 of 53 A B C D E SSID = S.B U35B 2 of 4 AD16 SATA_X1 SATA_XTAL2 AD18 SATA_X2 AC12 SATA_ACT#/GPIO67 AD14 AJ10 PLLVDD_SATA PLLVDD_SATA AC16 XTLVDD_SATA AE14 AE16 AE18 AE19 AF19 AF21 AG22 AG23 AH22 AH23 AJ12 AJ14 AJ19 AJ22 AJ23 AVDD_SATA AVDD_SATA AVDD_SATA AVDD_SATA AVDD_SATA AVDD_SATA AVDD_SATA AVDD_SATA AVDD_SATA AVDD_SATA AVDD_SATA AVDD_SATA AVDD_SATA AVDD_SATA AVDD_SATA DY 1 1 2 L35 BLM18BB221SN1D-GP 1 VCC_RUN_SB C628 SC1U10V2KX-1GP 200mA R738 0R2J-2-GP VCC_SATA_XTL 200mA 1 2 L34 BLM18BB221SN1D-GP DY 1 +3.3V_RUN 2 2 DY 2 R739 0R2J-2-GP 2 2 R740 0R2J-2-GP 1 1 DY 2 1 DY C640 SC1U10V2KX-1GP 2 DY 2 DY 1 1 2 L36 BLM18PG181SN-3GP C334 SC22U6D3V5MX-2GP VCC_RUN_SB C638 SC1U10V2KX-1GP VCC_SATA_SB 1500mA AB14 AB16 AB18 AC14 AC18 AC19 AD12 AD19 AD21 AE12 AE21 AF11 AF14 AF16 AF18 AG11 AG12 AG13 AG14 AG16 AG17 AG18 AG19 AG20 AG21 AH10 AH19 SATA_Xtal R484 1KR2J-1-GP 1 2 X3 XTAL-25MHZ-72GP SB_SPI_CS# C323 SC10P50V2JN-4GP FANOUT0/GPIO3 FANOUT1/GPIO48 FANOUT2/GPIO49 M4 T3 V4 FANIN0/GPIO50 FANIN1/GPIO51 FANIN2/GPIO52 N3 P2 W4 TEMP_COMM TEMPIN0/GPIO61 TEMPIN1/GPIO62 TEMPIN2/GPIO63 TEMPIN3/TALERT#/GPIO64 P5 P7 P8 T8 T7 VIN0/GPIO53 VIN1/GPIO54 VIN2/GPIO55 VIN3/GPIO56 VIN4/GPIO57 VIN5/GPIO58 VIN6/GPIO59 VIN7/GPIO60 V5 L7 M8 V6 M6 P4 M7 V7 AVDD N1 AVSS M1 DY 0R2J-2-GP 47R2J-2-GP 47R2J-2-GP 0R2J-2-GP SB_EC_SPI_DIN SB_EC_SPI_DO SB_EC_SPI_CLK SB_SPI_HOLD# 35 35 35 33 TP126 TPAD28 TP132 TPAD28 PCIE_WLAN_DET# USB_WLAN_DET# PCIE_WWAN_DET# USB_WWAN_DET# SB_TEMP_COMM PCIE_WLAN_DET# 32 USB_WLAN_DET# 32 WLAN PCIE_WWAN_DET# 32 USB_WWAN_DET# 32 WWAN TP151 TPAD28 X01 AUD_SPK_DET AUD_SPK_DET 30 RTC_BAT_DET# 18 1 R543 MINI3_CLK_REQ# NC_GPIO56 LBF_ID0 LBF_ID1 LBF_ID2 ALT_TP_DET# 2 2 2 2 2 10KR2J-3-GP +3.3V_RUN SB_WWAN_PCIE_RST# 32 SB_WLAN_PCIE_RST# 32 SB_LOM_PCIE_RST# 27 TP147 TPAD28 TP148 TPAD28 TP145 TPAD28 1 2 R563 +3.3V_RUN_HW 10KR2J-3-GP +3.3V_RUN 35 SIO_SPI_CS# 1 B 2 A 3 GND VCC 200mA 1 2 +3.3V_RUN L27 BLM18BB221SN1D-GP 1 2 R186 0R3-0-U-GP BIOS should not enable the internal GPIO pull up resistor HWM AGND trace at least 10 mil wide 1 2 47R2J-2-GP 1 X01 Wistron Corporation +3.3V_ALW 5 1 2 C499 SCD1U10V2KX-4GP 4 SPI_CS#_R 1 R436 DY Y U84 74AHC1G08GW-GP-U 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. DY DY Title 2 15R2J-GP SB600-IDE&SATA$SPI(2/5) SPI_CS# 33 Size A3 Document Number Rev B C D SC Parker Date: Wednesday, March 21, 2007 A 2 Place R175 close to SB600 AND Gate 2 DY 2 DY 1 1 DY C332 SC10P50V2JN-4GP SB_LAN_RST# SB_ROM_RST# 1 1 1 1 HW_AGND R445 1 DY LAN_RST#/GPIO13 ROM_RST#/GPIO14 C23 G5 3 X01 R518 R529 R514 R509 +3.3V_SUS SATA_XTAL2 1 2 R244 10MR2J-L-GP 1 SB_EC_SPI_DIN_R SB_EC_SPI_DO_R SB_EC_SPI_CLK_R SB_SPI_HOLD#_R SB_SPI_CS# SB600-GP 2SATA_XTAL1 0R2J-2-GP DY J3 J6 G3 G2 G6 2 SATA_XTAL3 1 R247 AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA AVSS_SATA SPI_DI/GPIO12 SPI_DO/GPIO11 SPI_CLK/GPIO47 SPI_HOLD#/GPIO31 SPI_CS#/GPIO32 1 VCC_SATA_PLL 3 DY R589 20KR2J-L2-GP SATA_XTAL1 X01 2 X01 1 SATA_CAL C776 SC22P50V2JN-4GP AF12 SB_EC_SPI_DIN_R 2 SATA_CAL SPI ROM 2 1KR2F-3-GP HW MONITOR DY SERIAL ATA POWER 1 R602 33 R522 20KR2J-L2-GP 2 1 SATA_RX3SATA_RX3+ IDE_D[0..15] R533 20KR2J-L2-GP 2 1 AH12 AJ13 IDE_D0 IDE_D1 IDE_D2 IDE_D3 IDE_D4 IDE_D5 IDE_D6 IDE_D7 IDE_D8 IDE_D9 IDE_D10 IDE_D11 IDE_D12 IDE_D13 IDE_D14 IDE_D15 1 SATA_TX3+ SATA_TX3- AD28 AD26 AE29 AF27 AG29 AH28 AJ28 AJ27 AH27 AG27 AG28 AF28 AF29 AE28 AD25 AD29 R585 20KR2J-L2-GP 2 1 SATA_RX2SATA_RX2+ AJ11 AH11 IDE_D0/GPIO15 IDE_D1/GPIO16 IDE_D2/GPIO17 IDE_D3/GPIO18 IDE_D4/GPIO19 IDE_D5/GPIO20 IDE_D6/GPIO21 IDE_D7/GPIO22 IDE_D8/GPIO23 IDE_D9/GPIO24 IDE_D10/GPIO25 IDE_D11/GPIO26 IDE_D12/GPIO27 IDE_D13/GPIO28 IDE_D14/GPIO29 IDE_D15/GPIO30 4 2 SATA_TX2+ SATA_TX2- AH16 AJ16 1 SATA_RX1SATA_RX1+ AH13 AH14 IDE_IORDY 33 INT_IRQ14 33 IDE_A0 33 IDE_A1 33 IDE_A2 33 IDE_DACK# 33 IDE_DREQ 33 IDE_IOR# 33 IDE_IOW# 33 IDE_CS1# 33 IDE_CS3# 33 C275 SC2D2U6D3V3MX-1-GP SATA_TX1+ SATA_TX1- AH17 AJ17 AB29 AA28 AA29 AB27 Y28 AB28 AC27 AC29 AC28 W28 W27 2 AH18 AJ18 If SATA I/F no used SATA_X1 directly to GND AVDD_SATA directly to GND PLLVDD_SATA directly to GND XTLVDD_SATA directly to GND IDE_IORDY IDE_IRQ IDE_A0 IDE_A1 IDE_A2 IDE_DACK# IDE_DRQ IDE_IOR# IDE_IOW# IDE_CS1# IDE_CS3# C276 SCD1U10V2KX-4GP SATA_RX0SATA_RX0+ ATA 66/100 SATA_TX0+ SATA_TX0- AH20 AJ20 SERIAL ATA AH21 AJ21 4 Sheet E 19 of 53 A B C D E U35D 4 of 4 SB_SMB_CLK1 SB_SMB_DATA1 FOR EXPRESS CARD,WLAN,WWAN,LOM 29 SB_AZ_CODEC_BITCLK 29 SB_AZ_CODEC_SDOUT 29 SB_AZ_CODEC_SDIN3 29 SB_AZ_CODEC_SYNC 29 SB_AZ_CODEC_RST# 2 1 CLK_SB_14M 2 SB_AZ_CODEC_BITCLK SB_AZ_CODEC_SDOUT SB_AZ_CODEC_SDIN3 SB_AZ_CODEC_SYNC SB_AZ_CODEC_RST# 1 R556 10KR2J-3-GP AZ_BITCLK_SB N2 2 AZ_DOUT_SB M2 2 33R2J-2-GP 33R2J-2-GP K2 AZ_SYNC_SB L3 2 33R2J-2-GP AZ_RST#_SB K3 2 33R2J-2-GP SB_AC_BITCLK TPAD28 TP49 L1 SB_AC_SDOUT L2 22 SB_AC_SDOUT ICH_AZ_CODEC_SDIN0 L4 ICH_AZ_MDC_SDIN1 TPAD28 TP140 J2 ICH_AZ_SDIN2 TPAD28 TP137 J4 SB_AC_SYNC TPAD28 TP136 M3 IDE_RST_MOD TPAD28 TP46 L5 33 IDE_RST_MOD 1 R596 1 R591 1 R587 1 R565 AZ_BITCLK AZ_SDOUT AZ_SDIN3/GPIO46 AZ_SYNC AZ_RST# AC_BITCLK/GPIO38 AC_SDOUT/GPIO39 ACZ_SDIN0/GPIO42 ACZ_SDIN1/GPIO43 ACZ_SDIN2/GPIO44 AC_SYNC/GPIO40 AC_RST#/GPIO45 R479 DY33R2J-2-GP NC#E23 NC#AC21 NC#AD7 NC#AE7 NC#AA4 NC#T4 NC#D4 NC#AB19 1 CLK_SB_14M_E 2 E23 AC21 AD7 AE7 AA4 T4 D4 AB19 2 DY C533 SC22P50V2JN-4GP EMI D16 E16 SB600_USBP5+ 17 SB600_USBP5- 17 USB_HSDP4+ USB_HSDM4- D18 E18 USB_HSDP3+ USB_HSDM3- G16 H16 SB600_USBP3+ 17 SB600_USBP3- 17 USB_HSDP2+ USB_HSDM2- G18 H18 SB600_USBP2+ 34 SB600_USBP2- 34 USB_HSDP1+ USB_HSDM1- D19 E19 USB_HSDP0+ USB_HSDM0- G19 H19 SB600_USBP4+ SB600_USBP4- Biometric TP128 TPAD28 TP127 TPAD28 Ext Side 1 USB1 Ext Side 2 USB2 POWER USB USB3 Digi Tizer Digi Tizer USB5 Biometric USB6 Express Card USB7 BLUETOOTH USB8 Media Slice USB9 MiniCard WWAN SB600_USBP1+ 34 SB600_USBP1- 34 SB600_USBP0+ SB600_USBP0- X01 SB600_USBP0+ 34 SB600_USBP0- 34 +3.3V_SB_USB_TX AVDDC A12 AVSSC A13 AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB AVSS_USB A16 C9 C10 C11 C12 C13 C14 C16 C17 C18 C19 C20 D11 D21 E11 E21 F11 F12 F14 F16 F18 F19 F21 G11 G21 H11 H21 J11 J12 J14 J16 J18 J19 2 B9 B11 B13 B16 B18 A9 B10 B12 B14 B17 1 AVDDTX AVDDTX AVDDTX AVDDTX AVDDTX AVDDRX AVDDRX AVDDRX AVDDRX AVDDRX 1 2A 2 USB_OC9#/SLP_S2/GPM9# USB_OC8#/AZ_DOCK_RST#/GPM8# USB_OC7#/GEVENT7# USB_OC6#/GEVENT6# USB_OC5#/DDR3_RST#/GPM5# USB_OC4#/GPM4# USB_OC3#/GPM3# USB_OC2#/GPM2# USB_OC1#/GPM1# USB_OC0#/GPM0# USB_HSDP5+ USB_HSDM5- USB0 USB4 C183 C156 SC10U10V5KX-2GP SC10U10V5KX-2GP 3 4 SB600_USBP6+ 31 SB600_USBP6- 31 C539 SC1U10V2KX-1GP 2 1 RN58 SRN2K2J-1-GP G14 H14 slice USB HUB C541 SC1U10V2KX-1GP 2 1 USB_OC9# C6 USB_OC8# C5 USB_OC7# C4 USB_OC6# B4 USB_OC5# B6 EXP_CARD_SB_WAKE#A6 35 EXP_CARD_SB_WAKE# USB_OC3# C8 USB_OC2# C7 34 USB_OC2# B8 USB_OC0_1# A8 34 USB_OC0_1# +3.3V_SUS SB600_USBP7+ 31 SB600_USBP7- 31 USB_HSDP6+ USB_HSDM6- C547 SCD1U10V2KX-4GP 2 1 SB_SHUTDOWN# SB_SATA_IS E14 D14 1 2 L18 BLM21PG221SN1D-1GP 3 +3.3V_SUS +3.3V_SB_AVDDC 200mA 1 C135 SC22U6D3V5MX-2GP 1 4 3 15 15 27,31,32 27,31,32 USB_HSDP7+ USB_HSDM7- Place R186 near pin A14. Route it with 10 mils trace width and 25mils spacing to any signals in x, y, z directions 4 2 1 2 RN52 SRN10KJ-5-GP X01 SB_DDCCLK1 SB_DDCDATA1 SATA_IS0#/GPIO10 ROM_CS#/GPIO1 GHI#/SATA_IS1#/GPIO6 WD_PWRGD/GPIO7 SMARTVOLT/SATA_IS2#/GPIO4 SHUTDOWN#/GPIO5 SPKR/GPIO2 SCL0/GPOC0# RUN PLANE SDA0/GPOC1# SCL1/GPOC2# SUS PLANE SDA1/GPOC3# DDC1_SCL/GPIO9 RUN PLANE DDC1_SDA/GPIO8 SSMUXSEL/SATA_IS3#/GPIO0 LLB#/GPIO66 SB600_USBP8+ 38 SB600_USBP8- 38 1 FOR MEMORY DY OSC / RST E12 D12 2 3 4 1 R139 1 R481 1 R487 10,46 NB_VCORE_CNTRL 14M_OSC C28 A26 B29 A23 B27 D23 B26 C27 B28 C3 F3 D26 C26 A27 A4 USB_HSDP8+ USB_HSDM8- C546 SC1U10V2KX-1GP 2 1 RN55 SRN2K2J-1-GP X01 MEN_SDAT MEN_SCLK RSMRST# SB600_USBP9+ 32 SB600_USBP9- 32 CLK_USB_48M 4 2 11K8R3F-GP TP113 TPAD28 TP112 TPAD28 C538 SCD1U10V2KX-4GP 2 1 3 4 SB_SATA_IS SB_ROM_CS# TPAD28 TP22 PWM_CTRL 2 2 10KR2J-3-GP WD_PWRGD 2 10KR2J-3-GP SMARTVOLT 10KR2J-3-GP SB_SHUTDOWN# SPKR 29 SPKR MEN_SCLK MEN_SCLK MEN_SDAT MEN_SDAT SB_SMB_CLK1 SB_SMB_CLK1 SB_SMB_DATA1 SB_SMB_DATA1 SB_DDCCLK1 SB_DDCDATA1 SB_SSMUXSEL TPAD28 TP23 PATA_DET# 33 PATA_DET# E2 B23 H12 G12 1 3 2 1 RN88 SRN2K2J-1-GP CLK_SB_14M USB_HSDP9+ USB_HSDM9- 2 +3.3V_RUN SB_RSMRST#_R A11 A10 C537 SCD1U10V2KX-4GP 4 CLK_SB_14M USB_ATEST1 USB_ATEST0 SB_USB_RCOMP 1 R137 SB_USB_ATEST1 SB_USB_ATEST0 1 DY 2 2 0R2J-2-GP 0R2J-2-GP CLK_USB_48M 2 1 R531 1 R519 35,51 SB_RSMRST# 23,35,48,51 SUSPWROK A17 A14 1 2 EMI R534 USBCLK USB_RCOMP 2 TPAD28 3,4,5,36 ITP_DBRESET# 36 SB_PCIE_WAKE# 35 SIO_EXT_SMI# USB INTERFACE DYC535 SC22P50V2JN-4GP PCI_PME#/GEVENT4# RI#/EXTEVNT0# SLP_S3# SLP_S5# PWR_BTN# PWR_GOOD SUS_STAT# TEST2 TEST1 TEST0 GA20IN KBRST# LPC_PME#/GEVENT3# LPC_SMI#/EXTEVNT1# S3_STATE/GEVENT5# SYS_RESET#/GPM7# WAKE#/GEVENT8# BLINK/GPM6# SMBALERT#/THRMTRIP#/GEVENT2# USB PWR 35 SIO_A20GATE 35 SIO_RCIN# 35 SIO_EXT_SCI# 2 0R2J-2-GP GPIO R494 R482 R516 SB_PCI_PME# A3 SIO_EXT_WAKE# B2 SIO_SLP_S3# F7 SIO_SLP_S5# A5 SIO_PWRBTN# E3 SB_PWRGD B5 PM_SUS_STAT# B3 SB_TEST2 F9 1 2 E9 1 2 2K2R2J-2-GP SB_TEST1 G9 1 2 2K2R2J-2-GP SB_TEST0 2K2R2J-2-GP AF26 AG26 D7 SB_EXTEVNT1# C25 TP18 SB_S3_STATE D9 ITP_DBRESET#_R F4 1 2 SB_PCIE_WAKE# E7 0R2J-2-GP C2 SMB_ALERT# TPAD28 TP125 G7 1 USB OC 2 CLK_USB_48M_E R140 1 4 SB_PME# AZALIA 36 SB_PME# 36 SIO_EXT_WAKE# 35,51 SIO_SLP_S3# 35,51 SIO_SLP_S5# 35,51 SIO_PWRBTN# 23,48,51 SB_PWRGD 7 PM_SUS_STAT# AC97 R478 DY33R2J-2-GP ACPI / WAKE UP EVENTS 1 CLK_USB_48M 2 +3.3V_SUS L17 BLM18BB221SN1D-GP C140 SCD1U10V2KX-4GP 2 +3.3V_SUS SB_PCIE_WAKE# 1 4 SIO_EXT_SMI# 2 3 RN69 SRN10KJ-5-GP SMB_ALERT# 1 4 SIO_EXT_WAKE# 2 3 RN56 SRN10KJ-5-GP PATA_DET# 1 4 SB_S3_STATE 2 3 RN53 SRN10KJ-5-GP SB_PME# 1 2 R141 10KR2J-3-GP DY DY SB600-GP DY USB OC# PULL HIGH R249 +3.3V_SUS 1 USB_OC7# USB_OC8# USB_OC6# USB_OC9# +3.3V_SUS 1 2 3 4 5 10 9 8 7 6 RP1 SRN10KJ-L3-GP 1 SIO_EXT_SCI# 2 DY10KR2J-3-GP 1 USB_OC5# USB_OC2# USB_OC3# USB_OC0_1# Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title SSID = S.B SB600-USB&AZALIA&GPIO(3/5) Size Document Number Custom Rev SC Parker Date: Wednesday, March 21, 2007 A B C D Sheet E 20 of 53 A B C D E SSID = S.B 1 2 C608 SC1U10V2KX-1GP C573 SCD1U10V2KX-4GP 1 2 C601 SC1U10V2KX-1GP C577 SCD1U10V2KX-4GP 2 1 1 C602 SC1U10V2KX-1GP 2 C560 SCD1U10V2KX-4GP 2 1 1 1 2 S5_1.2V S5_1.2V S5_1.2V S5_1.2V A18 A19 B19 B20 B21 1 C617 SCD1U10V2KX-4GP 2 C194 SCD1U10V2KX-4GP 1 DY 2 1 C181 SC2D2U6D3V3MX-1-GP C536 SC1U10V2KX-1GP C534 SC1U10V2KX-1GP 2 1 C554 SC1U10V2KX-1GP 2 1 C544 SC1U10V2KX-1GP 2 1 C548 SC1U10V2KX-1GP 2 1 1 G4 H1 H2 H3 SB_5V_REF AE11 SB_AVDDCK1.2V VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD S5_3.3V S5_3.3V S5_3.3V S5_3.3V S5_3.3V S5_3.3V SB_AVDDCK3.3V 1 2 L21 BLM18BB221SN1D-GP VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ A2 A7 F1 J5 J7 K1 AA27 200mA VCC_RUN_SB M13 M17 N12 N15 N18 R13 R17 U12 U15 U18 V13 V17 +1.05V_VCCP 2 2 DY 2 1 2 L22 BLM18BB221SN1D-GP 1 +3.3V_RUN C195 SCD1U10V2KX-4GP 200mA 2 C182 SC2D2U6D3V3MX-1-GP 2 1 +1.2V_SUS C587 SC1U10V2KX-1GP 2 1 2 +1.2V_SUS C561 SCD1U10V2KX-4GP 2 1 1 C576 SC1U10V2KX-1GP 2 1 2 C555 SC1U10V2KX-1GP 2 1 +3.3V_SUS C137 SC22U6D3V5MX-2GP 3 C316 SC22U6D3V5MX-2GP 1 2 +1.2V_RUN TC11 ST220U6D3VDM-17GP VCC_RUN_SB 1 2 L30 BLM21PG221SN-1GP A25 A28 C29 D24 L9 L21 M5 P3 P9 T5 V9 W2 W6 W21 W29 AA12 AA16 AA19 AC4 AC23 AD27 AE1 AE9 AE23 AH29 AJ2 AJ6 AJ26 USB_PHY_1.2V USB_PHY_1.2V USB_PHY_1.2V USB_PHY_1.2V USB_PHY_1.2V CPU_PWR V5_VREF A24 AVDDCK_3.3V A22 AVDDCK_1.2V B22 AVSSCK V29 V28 V27 V26 V25 V24 V23 V22 U27 T29 T28 T27 T24 T21 P27 PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS POWER 1 C589 SC1U10V2KX-1GP 2 1 2 C641 SC1U10V2KX-1GP 1 C621 SC1U10V2KX-1GP 2 1 2 C639 SC1U10V2KX-1GP 1 C540 SC1U10V2KX-1GP 2 2 1 C629 SC1U10V2KX-1GP 1 2 4 TC12 ST220U6D3VDM-17GP U35C 3 of 4 +3.3V_RUN VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS A1 A20 A21 A29 B1 B7 B25 C21 C22 C24 D6 E24 F2 F23 G1 J1 J8 L6 L8 M9 M12 M15 M18 N13 N17 P1 P6 P21 R12 R15 R18 T6 T9 U13 U17 V3 V8 V12 V15 V18 V21 W1 W9 Y29 AA11 AA14 AA18 AC6 AC24 AD9 AD23 AE3 AE27 AG6 AJ1 AJ25 AJ29 4 3 D27 D28 D29 F26 G23 G24 G25 H27 J23 J26 J28 K27 L22 L23 L24 L27 L28 M21 M24 M27 N27 N28 P22 P23 P24 P25 P26 2 SB600-GP 1 1 R584 +5V_RUN 2 SB_5V_REF 1KR2J-1-GP 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. C620 SC1U10V2KX-1GP Title 1 1 2 D12 RB751V-40-1-GP SB600-Power(4/5) Size A3 2 +3.3V_RUN Document Number Rev A B C D SC Parker Date: Wednesday, March 21, 2007 Sheet E 21 of 53 A B C DY R597 10KR2J-3-GP DY 1 R577 2K2R2J-2-GP DY +3.3V_RUN 1 R217 10KR2J-3-GP +3.3V_RUN 1 R488 10KR2J-3-GP 4 2 DY R202 10KR2J-3-GP 2 DY 1 1 1 R579 2K2R2J-2-GP +3.3V_RUN 2 DY +3.3V_RUN 2 R612 10KR2J-3-GP +3.3V_ALW 2 DY 1 1 R246 10KR2J-3-GP +3.3V_RUN 2 DY +3.3V_RUN 2 R627 10KR2J-3-GP +3.3V_RUN 2 DY 1 1 +3.3V_RUN 2 1 R598 10KR2J-3-GP DY R214 10KR2J-3-GP R569 10KR2J-3-GP R209 10KR2J-3-GP DY 2 R493 2K2R2J-2-GP 2 DY 1 1 1 R570 10KR2J-3-GP 2 DY 2 R611 2K2R2J-2-GP 2 DY 1 1 R245 2K2R2J-2-GP 2 DY 2 R623 2K2R2J-2-GP 2 DY 1 1 R250 2K2R2J-2-GP 2 DY 2 R624 2K2R2J-2-GP 2 DY 2 R603 2K2R2J-2-GP 1 CLK_SB_PCI0 18 CLK_SB_PCI1 18 1 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 SB_AC_SDOUT SB_RTCCLK R248 10KR2J-3-GP 1 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 SB_AC_SDOUT SB_RTCCLK CLK_SB_PCI4 CLK_PCI_PCCARD DY 1 18,25 18,25 18,25 18,25 18,25 18,25 20 18 18 18,25 R628 10KR2J-3-GP 2 DY 2 R599 10KR2J-3-GP +3.3V_RUN 2 1 +3.3V_RUN 1 +3.3V_RUN E Standard Straps Debug Straps SSID = S.B 4 D 3 3 CLK_SB_PCI4 PCI_AD28 HIGH LOW PCI_AD27 LONG RESET PCI PLL SHORT RESET BYPASS PCI PLL PCI_AD26 ACPI BCLK PCI_AD25 PCI_AD24 IDE PLL DEFAULT PCIE STRAPS BYPASS IDE PLL EEPROM PCIE STRAPS Default Default Default Default Default BYPASS ACPI BCLK PCI_AD23 AC_SDOUT BOOTFAIL TIMER DISABLED DEBUG STRAPS BOOTFAIL TIMER ENABLED IGNORE DEBUG STRAPS Default Default RTC_CLK INTERNAL RTC Default EXTERNAL RTC PCI_CLK4 CLK_SB_PCI0 PCI_CLK6 PCI_CLK0 PCI_CLK1 ROM TYPE INTERNAL PLL48 AMD CPU 0 0 FWH 0 1 LPC EXTERNAL 48MHZ INTEL CPU 1 0 SPI CLK_PCI_PCCARD 1 1 PCI Default Default Default CLK_SB_PCI1 2 2 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title SB600-Strapping Pin(5/5) Size A3 Document Number Rev A B C D SC Parker Date: Wednesday, March 21, 2007 Sheet E 22 of 53 A B C D E +5V_SUS 1 Placement should be near the WWAN minicard connector just under the inserted minicard. R656 2K2R2F-GP DP4 DN4 48 47 REM_DIODE4_P REM_DIODE4_N 35 3V_SUS DP5 DN5 2 1 NB_THERMDP NB_THERMDN 21 RTC_PWR3V 23 16 VSUS_PWRGD 3V_PWROK# D 1 2 S 2 2 1 EMC4001-HZH-1GP REM_DIODE3_P1 Q56 MMBT3904-7-F-GP DY REM_DIODE3_N1 7 NB_THERMDP REM_DIODE3_N Locate C352 near Guardian REM_DIODE4_P 2 1 2 1 R549 0R2J-2-GP Thermal sensor mapping C614 SC2200P50V2KX-2GP REM_DIODE4_N 1 R136 100KR2J-1-GP +3.3V_SUS Bottom SoDIMM D4 D5 skin temp sensor at the bottom of the MB located within the triangle of MCH/CPU/ DRAM RS600ME VCP1 Pwr Mon VCP2 WWAN Wistron Corporation G THERM_B1 1 2 1 R477 2K2R2J-2-GP Q53 MMBT3904-7-F-GP H_THERMTRIP# 5 H_THERMTRIP# 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 1 THERMTRIP1# 2 20,48,51 SB_PWRGD +1.05V_VCCP 3 Q24 2N7002-7F-GP 2 D 20.F0693.004 CPU edge diode D3 1 C526 SCD1U10V2KX-4GP 2 DY 1 2 3 4 OTP D2 R567 8K2R2J-3-GP S C728 SC1KP50V2KX-1GP 1 FAN1_TACH 2 1 C720 SC22U6D3V5MX-2GP 2 D28 RB751V-40-1-GP 1 2 FAN1_OUT SB_PWRGD# JFAN1 MLX-CON4-15-GP 6 35 FAN1_TACH D1 1 2 2 1 Title FAN, EMC4001 Size Document Number Custom 36 FAN1_DET# Rev SC Parker Date: Wednesday, March 21, 2007 A B 2 Reserve area near NB for a cap between DP4/DN4 5 R670 10KR2J-3-GP C624 SC470P50V2KX-3GP CPU THERMALTRIP +3.3V_SUS 1 2 1 R538 0R2J-2-GP 3 REM_DIODE4_N1 3V_PWROK# +3.3V_RUN Q55 MMBT3904-7-F-GP NB_THERMDN Locate C355 near Guardian 2 H_THERMDC 5 H_THERMDC FAN DY 2 1 C590 SC2200P50V2KX-2GP 2 C586 SC470P50V2KX-3GP REM_DIODE4_P1 H_THERMDA 5 H_THERMDA 1 H_THERMDA and H_THERMDC routing Trace width and Spacing use 10 / 10 mil REM_DIODE4_N and REM_DIODE4_P routing Trace width and Spacing use 10 / 10 mil 7 NB_THERMDN D4 Thermal sensor for skin temp NB_THERMDP 1 Thermal sensor for CPU DIODE D2 2 Locate C368 near Guardian Please near the bottom SODIMM CONN 2 1 2 C600 SC2200P50V2KX-2GP 1 2 R536 0R2J-2-GP REM_DIODE1_N D5 NB_THERMDA and NB_THERMDC routing Trace width and Spacing use 10 / 10 mil REM_DIODE3_P 1 C558 SCD1U10V2KX-4GP Thermal sensor for RS600ME Locate C351 near Guardian 1 2 R555 0R2J-2-GP 3 1 C594 SC2200P50V2KX-2GP C564 SCD1U10V2KX-4GP D3 1 REM_DIODE1_P +5V_RUN 2 +3.3V_RUN 0R5J-5-GP 2 1 5 6 49 VDD_5V VDD_5V THERM_GND 1 R491 C552 SC10U10V5KX-2GP 2 1 9 VDD_3V 1 1 THERMAL_LDO_IN REM_DIODE3_N and REM_DIODE3_P routing Trace width and Spacing use 10 / 10 mil C575 SC2200P50V2KX-2GP 1 R498 1KR2F-3-GP +3.3V_RUN GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6/FAN_DAC2 DY +2.5V_RUN 2 10 13 14 15 22 36 4 5V_CAL_SIO1# R499 31K6R2F-GP 48,51 C553 SC1U10V2KX-1GP FAN_DAC1 2.5V_RUN_PWRGD THERM_LDO_SET 2 39 2 LDO_IN LDO_IN 30 29 1 32 31 G Q60 2N7002-7F-GP +2.5V_RUN 2 1 LDO_OUT LDO_OUT R542 10KR2J-3-GP R443 = R526*((VOUT/1.22)-1) VOUT=1.5V,R443=0.229*R526 +3.3V_SUS 1 FAN_OUT FAN_OUT 2 3 2 1 2 1 DY Q25 MMBT3904-7-F-GP 7 8 Locate C350 near Guardian place on the backside of the motherboard under CPU 28 Thermal sensor for SODIMM D1 REM_DIODE1_N and REM_DIODE1_P routing Trace width and Spacing use 10 / 10 mil LDO_SET 2 7K5R2F-1-GP C317 SC10U10V5KX-2GP EMC4001's GPIO1-6 are 3.3V tolerant only LDO_POK 1 R500 2 TP168 30 AUD_AVDD_ON Thermal sensor for CPU C189 SC2200P50V2KX-2GP MDC_DISABLE# SIO_GFX_PWR 5V_CAL_SIO1# 5V_CAL_SIO2# TP166 TP167 THERM_LDO_SHDN# 1 2 VSET = (Tp - 70) / 21 3.3 * (R411/ R406 + R411) = (Tp - 70) / 21 Where Tp = 70 to 101 degrees C Tp set at 88 degrees C Guardian temp tolerance = +/- 3 degrees C 27 33 R517 DY10KR2J-3-GP THERM_STP# 43 1 DY DY 2 2 10KR2J-3-GP 10KR2J-3-GP LDO_SHDN#/ADDR VSET XEN VSS R655 10KR2J-3-GP C698 SC2200P50V2KX-2GP TP133 2 42 26 34 FAN1_OUT 1 R582 1 R580 THERMTRIP1# THERMTRIP2# THERMTRIP3# +3.3V_SUS ATF_INT# 36 POWER_SW# 17 ACAV_IN 35,40,41 C307 SCD1U10V2KX-4GP THERM_VSET THERM_XEN 17 18 19 1 2 1KR2J-1-GP THERMTRIP1# THERMTRIP2# THERMTRIP3# ATF_INT# POWER_SW# ACAV_IN THERMTRIP_SIO THERM_STP# 2 2 2 8K2R2J-3-GP 8K2R2J-3-GP R513 10KR2J-3-GP 20 3 4 25 24 ATF_INT# POWER_SW# ACAVAIL_CLR THERMTRIP_SIO SYS_SHDN# +RTC_CELL 1 DP2 DN2 +3.3V_ALW 1 41 40 2 2 1 1 1 R501 Note : 3 REM_DIODE3_P REM_DIODE3_N 2 1 R562 1 R553 +3.3V_SUS +3.3V_SUS R537 118KR2F-1-GP +3.3V_SUS 2 SC2200P50V2KX-2GP 45 44 1 R530 332KR2F-GP 2 C593 SCD1U10V2KX-4GP C598 THERM_PWRGD 2 2 1KR2J-1-GP +3V_PWROK 1KR2J-1-GP 1 SB_PWRGD# R526 1 R576 DP3 DN3 2 20,35,48,51 SUSPWROK DP1 DN1 3 +3.3V_SUS C591 SC1U10V2KX-1GP 1 1 2 +3.3V_SUS 38 37 +3.3V_SUS 1 2VCP2_1 R653 NTC-10K-19-GP PWR_MON 42 2 +RTC_CELL H_THERMDA H_THERMDC 1 2 C551 SCD1U10V2KX-4GP +3VSUS_THRM 1 2 R495 49D9R2F-GP VCP2 C318 SC10U10V5KX-2GP 4 43 46 1 REM_DIODE1_P REM_DIODE1_N VCP1 VCP2 C618 SCD1U10V2KX-4GP SSID = THERMAL SMDATA SMBCLK 2 VCP2 11 12 Thermistor 2 U95 34,35,40 THRM_SMBDAT 34,35,40 THRM_SMBCLK C D Sheet E 23 of 53 A B PCI7402_AVDD_33 D SSID = 1394 1 C346 SCD01U16V2KX-3GP 2 1 2 C345 SCD01U16V2KX-3GP 2 1 C354 SCD1U10V2KX-4GP 1 C355 SC1U6D3V2KX-GP 2 1 4 4 +3.3V_PCI7402_AVDD P14 P13 U15 AVDD_33 AVDD_33 AVDD_33 +3.3V_PCI7402 F6 F9 F12 F14 J6 J14 L6 L14 P6 P8 P10 G6 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC +3.3V_PCI7402_VCCP P1 W8 VCCP VCCP PCI7402_VR_PORT P15 VDDPLL_15 +3.3V_PCI7402_VDDPLL33 U19 VDDPLL_33 +3.3V_PCI7402 1 C713 SC1KP50V2KX-1GP 2 C730 SC10U6D3V5MX-3GP 1 2 C707 SCD1U10V2KX-4GP 1 +3.3V_PCI7402_VDDPLL33 2 1 2 R673 0R3-0-U-GP 1 C658 K2 1 POWER VR_EN# K19 K1 VR_PORT VR_PORT P9 P7 N6 K14 M14 K6 H6 G14 F13 F10 F7 GND GND GND GND GND GND GND GND GND GND GND R14 U14 U13 AGND AGND AGND U12 V12 W12 E5 NC#U12 NC#V12 NC#W12 NC#E5 SCD1U10V2KX-4GP 2 PCI7402_VDDPLL33 2 +3.3V_RUN 2 PCI7402_VR_PORT_R 2 2 1 DY R668 C657 0R3-0-U-GP SCD1U10V2KX-4GP C655 SCD01U16V2KX-3GP 2 C656 SC1U6D3V2KX-GP 1 2 C678 SCD1U10V2KX-4GP 1 +3.3V_PCI7402_VCCP 2 1 2 R639 0R3-0-U-GP PCI7402_VR_EN# 1 1 +3.3V_PCI7402 C700 SC1U6D3V2KX-GP 1 PCI7402_VCCP 2 3 C703 SC10U6D3V5MX-3GP 1 C671 SCD01U16V2KX-3GP 2 1 2 C672 SCD01U16V2KX-3GP 2 1 C674 SCD1U10V2KX-4GP 1 1 2 2 2 C679 SC1U6D3V2KX-GP +3.3V_PCI7402 C364 SC10U6D3V5MX-3GP 1 R648 0R3-0-U-GP 1 of 2 U63A PCI7402_VCC +3.3V_RUN E +3.3V_PCI7402_AVDD 2 C348 SC10U6D3V5MX-3GP 1 R284 0R3-0-U-GP 2 +3.3V_RUN C PCI7402_VR_EN# RSVD#P19 RSVD#N18 RSVD#N17 RSVD#M15 RSVD#N19 RSVD#M18 RSVD#M17 RSVD#L19 RSVD#L18 RSVD#L15 RSVD#K18 RSVD#K17 RSVD#K15 RSVD#J18 RSVD#J15 RSVD#J17 RSVD#H19 RSVD#F15 RSVD#F17 RSVD#D19 RSVD#A16 RSVD#E14 RSVD#B15 RSVD#B14 RSVD#A14 RSVD#C13 RSVD#B13 RSVD#C11 RSVD#E11 RSVD#F11 RSVD#A10 RSVD#C10 RSVD#B12 RSVD#H15 RSVD#N15 RSVD#B11 RSVD#E19 RSVD#F19 RSVD#G17 RSVD#E12 RSVD#E17 RSVD#G19 RSVD#C14 RSVD#C12 RSVD#G18 RSVD#A12 RSVD#G15 RSVD#H14 RSVD#A13 RSVD#B16 RSVD#L17 RSVD#H18 RSVD#E18 RSVD#E10 RSVD#B10 RSVD#F5 RSVD#G5 RSVD#E3 RSVD#F3 RSVD#F2 RSVD#E2 RSVD#D1 RSVD#E1 RSVD#H17 RSVD#F18 RSVD#M19 RSVD#J19 RSVD#C15 RSVD#A15 RSVD#E13 RSVD#A11 P19 N18 N17 M15 N19 M18 M17 L19 L18 L15 K18 K17 K15 J18 J15 J17 H19 F15 F17 D19 A16 E14 B15 B14 A14 C13 B13 C11 E11 F11 A10 C10 B12 H15 N15 B11 E19 F19 G17 E12 E17 G19 C14 C12 G18 A12 G15 H14 A13 B16 L17 H18 E18 E10 B10 F5 G5 E3 F3 F2 E2 D1 E1 H17 F18 M19 J19 C15 A15 E13 A11 3 2 PCI7402ZHK-GP-U 2 +3.3V_PCI7402 R635 0R2J-2-GP 1 DY Wistron Corporation PCI7402_VR_EN# 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 2 1 1 R634 0R2J-2-GP Title 1 PCI7402-1 Size A3 Document Number Rev A B C D SC Parker Date: Wednesday, March 21, 2007 Sheet E 24 of 53 B C PCI_C_BE#0 PCI_C_BE#1 PCI_C_BE#2 PCI_C_BE#3 18,22 CLK_PCI_PCCARD 18,51 PCI_RST# 1 2 100KR2J-1-GP 1394 CARD READER 18 PCI_INTG# 18 PCI_INTH# 2 R622 0R2J-2-GP 2 R625 0R2J-2-GP DY W10 V7 U5 P2 C/BE0# C/BE1# C/BE2# C/BE3# CLK_PCI_PCCARD L1 PCI_RST# K3 GBSRST# K5 PCLK PRST# GRST# 1 2 C337 SC1U10V2KX-1GP 18,27,35 IRQ_SERIRQ 18,35 CLKRUN# PCI_C_BE#0 PCI_C_BE#1 PCI_C_BE#2 PCI_C_BE#3 1 1 PCI_INTG# PCI_INTH# MFUNC2 MFUNC4 MFUNC5 MFUNC6 TPB0P TPB0N TPB1P TPB1N TPB0P 26 TPB0N 26 TPBIAS0 TPBIAS1 R13 W17 TPBIAS0 TPBIAS1 XO XI R18 R19 1394_X1 1394_X3 SD_CLK/SM_RE#/SC_GPIO1 SD_CMD/SM_ALE/SC_GPIO2 SD_DAT0/SM_D4/SC_GPIO6 SD_DAT1/SM_D5/SC_GPIO5 SD_DAT2/SM_D6/SC_GPIO4 SD_DAT3/SM_D7/SC_GPIO3 A4 C5 C6 A5 B5 E6 PCI7402_SC_GPIO1 PCI7402_SC_GPIO2 PCI7402_SC_GPIO6 PCI7402_SC_GPIO5 PCI7402_SC_GPIO4 PCI7402_SC_GPIO3 MFUNC0 MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6 2 PCI-CLK EMI E7 C8 F8 MS_CLK/SD_CLK/SM_EL_WP# MS_BS/SD_CMD/SM_WE# MS_SDIO(DATA0)/SD_DAT0/SM_D0 MS_DATA1/SD_DAT1/SM_D1 MS_DATA2/SD_DAT2/SM_D2 MS_DATA3/SD_DAT3/SM_D3 A7 E8 B7 C7 A6 B6 SD_CD# MS_CD# SM_CD# E9 A8 B8 PCI7402_MS_CD# PCI7402_SM_CD# SM_CLE/SC_GPIO0 XD_CD#/SM_PHYS_WP# B4 A3 PCI7402_XD_CD# CLOSE TO PIN L1 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 1 R631 33R2J-2-GP DY 2 TP74 TP71 TP78 TP77 TP76 TP73 CLK_PCI_PCCARD SD_WP 26 MC_PWR_CTRL_0 26 PCI7402_MC_PWR_CTRL_1 1 TP83 TPAD28 C654 SC22P50V2JN-4GP EMI SD_CD# 26 CLK 48M EMI TP79 TPAD28 TP81 TPAD28 TP72 TPAD28 CLOSE TO PIN F1 CLK_SMCARD_48M R636 33R2J-2-GP CLK_48 SCL SDA SPKROUT PHY_TEST_MA RI_OUT#/PME# SUSPEND# TEST0 F1 CLK_SMCARD_48M G2 G3 H3 P17 L5 J5 P12 PCI7402_SPKROUT PCI7402_PHY_TEST_MA PME#_1394 PCI7402_SUSPEND# DY CLK_SMCARD_48M 4 TP70 TPAD28 2 DY 2 R256 10KR2J-3-GP A9 B9 C9 C4 SYS_PME# 1 SYS_PME# 36 R257 0R2J-2-GP 1 +3.3V_PCI7402 C667 SC22P50V2JN-4GP EMI R259 1 1 2 1 1 1 38 38 38 38 DY R671 330R2J-3-GP CLOSE TO PIN P17 1 TPA1P TPA1N TPB1P TPB1N R315 56R2J-4-GP PCI7402_PHY_TEST_MA 2 2 56R2J-4-GP 2 PHY_TEST_MA R674 330R2J-3-GP R323 1 CLOSE TO PIN V16,W16,V15,W15 PCI7402_SUSPEND# R324 56R2J-4-GP 1 TPA1P TPA1N TPB1P TPB1N MFUNC2 MFUNC4 MFUNC5 +3.3V_PCI7402 SCD01U16V2KX-3GP +3.3V_PCI7402 C370 1 2 2 SCD33U10V3KX-3GP 1 TPBIAS1 C625 2 2 47KR2J-2-GP 2 47KR2J-2-GP 47KR2J-2-GP 2 47KR2J-2-GP 2 DY MEDIA SLICE 1394 1 1 1 3 DY 2 SD_CLK 26 SD_CMD 26 SD_DATA0 26 SD_DATA1 26 SD_DATA2 26 SD_DATA3 26 PCI7402ZHK-GP-U R255 R253 R254 4 SC12P50V2JN-3GP PCLK_CBUS_E SD_WP/SM_CE# CLOCK/VD1/VCCD0# DATA/VD2/VPPD1 LATCH/VD3/VPPD0 RSVD#C4/VD0/VCCD1# X01 SC12P50V2JN-3GP X01 C385 TPBIAS0 26 MC_PWR_CTRL_0 MC_PWR_CTRL_1/SM_R/B# Miscellaneous G1 H5 H2 H1 J1 J2 J3 1394_X3 1 2 1394_X2 1 2 R326 X5 0R2J-2-GP X-24D576MHZ-46GP C386 1 TPB0P TPB0N TPB1P TPB1N V13 W13 V15 W15 if want to use internal 1.5V regulator, must be use 0.1uF cap placed between pin T18 and R17 2 TPA0P 26 TPA0N 26 1394_X1 1 TPA0P TPA0N TPA1P TPA1N 1 V14 W14 V16 W16 C734 SCD1U10V2KX-4GP R17 TPA0P TPA0N TPA1P TPA1N 6K34R2F-GP 1 18 18 18 18 VSSPLL 2 0R2J-2-GP CLK_CARD_48M_E 2 3 GNT# REQ# IDSEL FRAME# IRDY# DEVSEL# TRDY# SERR# STOP# PERR# PAR 2 R12 T18 T19 1 2 18 PCI_FRAME# 18 PCI_IRDY# 18 PCI_DEVSEL# 18 PCI_TRDY# 18 PCI_SERR# 18 PCI_STOP# 18 PCI_PERR# 18 PCI_PAR L2 L3 N5 R6 V5 U6 W5 W6 V6 R7 U7 1394_CPS 1 1394_R0 R289 1394_R1 1 R678 CPS R0 R1 2 PCI_AD17 1 R251 100R2J-2-GP PCI_GNT#1 PCI_REQ#1 PCI_IDSEL PCI_FRAME# PCI_IRDY# PCI_DEVSEL# PCI_TRDY# PCI_SERR# PCI_STOP# PCI_PERR# PCI_PAR AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PCI 18 PCI_GNT#1 18 PCI_REQ#1 R11 P11 U11 V11 W11 R10 U10 V10 R9 U9 V9 W9 V8 U8 R8 W7 W4 T2 T1 R3 P5 R2 R1 P3 N3 N2 N1 M5 M6 M3 M2 M1 IEEE 1394 4 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 SD/MMC/MS/MS-PRO/SM/XD SSID = 1394 2 1394 Xtal 2 of 2 U63B R258 E PCI_AD[0..31] 18,22 PCI_AD[0..31] +3.3V_PCI7402 D 2 A R322 TO MEDIA SLICE 1 Wistron Corporation 2 D_TPB_EMI 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 2 1 2 56R2J-4-GP PCI7402-2 2 CHOCK put on MEDIA SLICE side Title 5K11R2F-L1-GP 1 C368 SC270P50V2JN-2GP R310 Size A3 Document Number Rev A B C D SC Parker Date: Wednesday, March 21, 2007 Sheet E 25 of 53 A B C SSID = 1394 SD POWER-SWITCH D E M/B 1394 TPA0+ 2 0R2J-2-GP 1 R67 R68 TPB0P TPB0N 3 1 2 1 2 R69 0R2J-2-GP TPB0+ 2 L7 DLW21HN900SQ2LGP 2 TPA0+ TPA0- 2 1 TPB0+ TPB0- GND GND GND 5 6 7 22.10218.S11 DY 1 2 56R2J-4-GP TPB_EMI 4 3 SKT1394 SKT-1394-4P-21-GP-U R292 56R2J-4-GP R285 2 2 1 5K11R2F-L1-GP 1 C349 SC270P50V2JN-2GP TPA00R2J-2-GP 3 R296 SD SOCKET 4 R306 56R2J-4-GP TPA0P TPA0N 1 25 TPB0P 25 TPB0N 2 1 25 TPA0P 25 TPA0N R301 56R2J-4-GP 4 SCD33U10V3KX-3GP 4 DY 1 C357 2 TPBIAS0 1 25 TPBIAS0 L6 DLW21HN900SQ2LGP 1 2 TPS2051BDBVR-GP 2 SC1U10V2KX-1GP SD_CMD_R SC1KP50V2KX-1GP SD_DATA0_R SC1KP50V2KX-1GP SD_DATA1_R SC1KP50V2KX-1GP SD_DATA2_R SC1KP50V2KX-1GP SD_DATA3_R SC1KP50V2KX-1GP 2 EN# 1 2 3 1 4 OUT GND OC# C763 SC1U10V2KX-1GP 2 C755 IN 1 MC_PWR_CTRL_0 25 MC_PWR_CTRL_0 5 DY2 DY2 DY2 DY2 DY2 1 +3.3V_RUN_CARD U106 DY 1 C344 1 C360 1 C366 1 C340 1 C342 C363 SCD01U16V2KX-3GP TPS2051_OC# 100KR2J-1-GP 2 2 1 1 R685 2 C766 SC1U10V2KX-1GP 4 1 +3.3V_ALW SD_CMD SD_CLK SD_WP SD_CD# 1 R277 1 R291 1 R312 X01 SDIO1 4 POWER 2 5 11 12 SD_CMD SD_CLK SD_WP# SD_CD# X01 25 25 25 25 TPB02 0R2J-2-GP 1 R70 C350 SCD1U10V2KX-4GP 1 3 2 2 1 C347 SC1U10V2KX-1GP +3.3V_RUN_CARD 3 2 2 0R2J-2-GP 2 56R2J-4-GP 0R2J-2-GP SD_CMD_R SD_CLK_R SD_WP_R NP1 NP2 NP1 NP2 SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3 GND GND GND GND GND SD_DATA0_R SD_DATA1_R SD_DATA2_R SD_DATA3_R 7 8 9 1 R294 R305 R260 R265 2 2 2 2 1 1 200R2J-L1-GP 1 200R2J-L1-GP 1 200R2J-L1-GP 200R2J-L1-GP SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3 25 25 25 25 3 6 10 13 14 CARDBUS12P-GP-U2 2 2 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title SMART CARD/SD/1394(3/3) Size A3 Document Number Rev A B C D SC Parker Date: Wednesday, March 21, 2007 Sheet E 26 of 53 B C C3 F3 H10 K12 K11 DOCK_LOM_TRD3- 38 DOCK_LOM_TRD3+ 38 DK_TRD2DK_TRD2+ J12 J11 DOCK_LOM_TRD2- 38 DOCK_LOM_TRD2+ 38 DK_TRD1DK_TRD1+ H12 H11 DOCK_LOM_TRD1- 38 DOCK_LOM_TRD1+ 38 DK_TRD0DK_TRD0+ G12 G11 DOCK_LOM_TRD0- 38 DOCK_LOM_TRD0+ 38 NV_STRAP1 NV_STRAP0 L1 J1 LOM_NV_STRAP0 SCLK SI SO CS# A8 C8 B8 B9 LOM_SCLK LOM_SI LOM_SO LOM_CS# GPIO0 GPIO1 GPIO2 M7 L7 B4 LOM_SMB_ALERT# DY 2 1 DY DY DY 2 1 4 5 1 R129 1 R124 +3.3V_LAN 4K7R2J-2-GP 4 3 2 1 LOM_SCLK LOM_SO 2 2 4K7R2J-2-GP 4K7R2J-2-GP S# RESET# C D W# VCC VSS Q 1 5 6 7 8 X01 LOM_REGCTL12_PNP 0 1 1 2 C177 SCD1U10V2KX-4GP +3.3V_LAN +3.3V_LAN LOM_SI CLKREQ# SUPER_LOW_PWR +3.3V_LAN_R DY C121 SCD1U10V2KX-4GP C128 SC4D7U6D3V3KX-GP Q12 MMJT9435T1G-GPU +2.5V_LOM C62 SC10U10V5KX-2GP 2 C60 SCD1U10V2KX-4GP C160 SC4D7U6D3V3KX-GP Q19 MMJT9435T1G-GPU B C +1.2V_LOM +2.5V_LOM VDDIOPower Decoupling +3.3V_LAN C108 SCD1U10V2KX-4GP C146 SCD1U10V2KX-4GP C171 SCD1U10V2KX-4GP C161 SC4D7U6D3V3KX-GP VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A3 A9 C5 D4 D8 E5 E6 E7 E8 F4 F5 F6 F7 F8 F9 G3 G4 G5 G6 G9 H4 J4 K5 L3 L5 M5 place C937 near U91 pin L11 BCM5756MEKFBG-GP Core Power Decoupling +1.2V_LOM VDDP Power Decoupling C111 SC4D7U6D3V3KX-GP M9 L9 J5 H6 H5 G2 F1 D5 2 NC#M9 NC#L9 NC#J5 NC#H6 NC#H5 NC#G2 NC#F1 NC#D5 C492 SC10U4V3MX-GP C148 SCD1U10V2KX-4GP 2 1 E_SWITCH_CONTROL ENERGYDET LOM_CABLE_DETECT goes to an input on a system microcontroller that can poll this signal periodically and can de-assert the LOM_LOM_PWR when LOM_CABLE_DETECT signal is high. Connect to an EC GPIO defined by th GPIO mapping. C136 SCD1U10V2KX-4GP C167 SC4D7U6D3V3KX-GP 2 1 TRST# TCK TDI TDO TMS C530 SCD1U10V2KX-4GP 2 1 0R2J-2-GP 1 C488 SC4D7U6D3V3KX-GP 2 1 LOM_CABLE_DET 2 E3 B3 0 1 DY B2 B5 F2 C4 E1 5 6 7 8 +3.3V_LAN 1 2 1 DY 1 R423 39KR2J-GP Logic High Voltage must be 0.7V to 2.75V R458 B1 J10 0 2 SUPER_LOW_PWR 2 X01 38 LOM_E_SWITCH 36 LOM_CABLE_DETECT L10 L11 Atmel AT45BCM021B B 2 DY 1 R422 20KR2J-L2-GP 36 LOM_SUPER_IDDQ DOCKED SEL 0:RJ45. SEL 1:Dock. REGCTL12 0 1 LOM_REGCTL25_PNP M10 REGSEN12 0 0 AT45BCM021B-GP 1 1 R465 X01 LOMCLKREQ# 2 470R2J-2-GP 0 0 +3.3V_LAN LOM_SI C78 SCD047U10V2KX-2GP REGSUP12 0 1 2 NB_RDAC DK_RDAC M11 M12 WP# VCC GND SO DY +3.3V_LAN 1 E12 F12 REGCTL25 REGSEN25 2 2 4K7R2J-2-GP 4K7R2J-2-GP 0 1 2 XTALO XTALI L12 DY DY 1 M8 L8 REGSUP25 LOM_SERIAL_DI 1 LOM_SERIAL_DO R467 1 R472 1 C510 SC33P50V2JN-3GP NB_LOM_RDAC DOCK_LOM_RDAC 2 2 1K24R2F-GP 1K18R2F-GP SMB_CLK SMB_DATA H2 K2 CS# RESET# SCK SI 2 1 R419 1 R420 D7 B6 SERIAL_DI SERIAL_DO LOM_SCLK LOM_SO 2 LOM_XTALO LOM_XTALI VAUXPRSNT VMAINPRSNT LOW_PWR 4 3 2 1 C152 SCD1U10V2KX-4GP 20,31,32 SB_SMB_CLK1 20,31,32 SB_SMB_DATA1 A5 G10 H1 LOM_CS# +3.3V_LAN 1 VAUX_PRSNT VMAIN_PRSNT 0 0 U15 LOM_SMB_ALERT# 35 1 36 2 2 1KR2J-1-GP 1KR2J-1-GP LOM_LOW_PWR 2 +3.3V_LAN 4K7R2J-2-GP R134 1R2512J-1-GP 1 R455 1 R421 SCLK 2 +3.3V_LAN +3.3V_RUN CS# Ato-Sense Mode E TPM_GPIO2/TPM_STATUS TPM_GPIO1 TPM_GPIO0 SI ST M45PE20 1 1 R466 2 H8 J7 J8 R503 470KR2J-2-GP 2 +3.3V_LAN 4K7R2J-2-GP SO U14 LOM_CS# R123 2 1 1 R468 38 NVSTRAP0 E TPM_GPIO2 TPM_GPIO1 TPM_GPIO0 2 1 2 2 DOCK_LOM_ACTLED_YEL# 1 DY DY DY 2 2 10KR2J-3-GP 2 10KR2J-3-GP 10KR2J-3-GP 2 200R2F-L-GP 1 2 X6 XTAL-25MHZ-72GP C516 SC27P50V2JN-2-GP 1 DOCK_LOM_SPD10LED_GRN# 38 DOCK_LOM_SPD100LED_ORG# 38 1 LOM_XTAL1 1 R452 Atmel part is available in standard package size, where as ST-Micro part is available in narrow package size. Ensure that pads are laid out for bath footprints. Recommendation: Pads for pins 1 (reference) through 4 can be standard and identically located for both packages. Pads for pins 5-8 need to be larger to accommodate both packages. 1 TPM_EN# D2 D1 C2 E2 3 NV_STRAP1 Important Layout Note for Dual footprint design: 2 LOM_TPM_EN_R# K1 DK_LINKLED# DK_SPD100LED# DK_SPD1000LED# DK_TRAFFICLED# 28 1 LAD3 LAD2 LAD1 LAD0 LFRAME# LRESET# LCLK SERIRQ NB_LOM_ACTLED_YEL# 2 H9 J9 H7 K8 K10 K7 G7 K9 Place resister as close as possible to the ASIC. Pad is needed to measure 125MHz clock for debugging. NB_LOM_SPD10LED_GRN# 28 NB_LOM_SPD100LED_ORG# 28 2 REFCLK_SEL A7 B7 C7 C6 2 R471 4K7R2J-2-GP 2 6 2 A2 NB_LINKLED# NB_SPD100LED# NB_SPD1000LED# NB_TRAFFICLED# C571 DYSC4700P50V2KX-1GP 35 AUX_ON 1 1 R426 1 R424 1 R425 Place crystal less than 0.75" (~1.9cm) from LAN Controller 1 2N7002DW-7F-GP PCIE_TXDP PCIE_TXDN PCIE_RXDP PCIE_RXDN WAKE# PERST# REFCLK+ REFCLK- +3.3V_LAN_EN2 U94 M45PE20-VMN6TP-GP 2 1 1 R470 0R2J-2-GP 36 LOM_TPM_EN# 1 DK_TRD3DK_TRD3+ +3.3V_LAN D 6 1 D D 5 2 D S 4 3 G U93 SI3456BDV-T1-GP 1 C 2 18 CLK_PCI_TPM 18,25,35 IRQ_SERIRQ NB_LOM_TRD0- 28 NB_LOM_TRD0+ 28 1 DY R469 100KR2J-1-GP LPC_LAD3 LPC_LAD2 LPC_LAD1 LPC_LAD0 LPC_FRAME# PLTRST# CLK_PCI_TPM IRQ_SERIRQ LPC_LAD3 LPC_LAD2 LPC_LAD1 LPC_LAD0 LPC_FRAME# D12 D11 2 18,35 18,35 18,35 18,35 18,35 +3.3V_LAN LOM_REFCLK_SEL 2 4K7R2J-2-GP NB_TRD0NB_TRD0+ 2 DY 1 R459 Populate resister for debug NB_LOM_TRD1- 28 NB_LOM_TRD1+ 28 C178 SCD1U10V2KX-4GP 2 1 0R2J-2-GP C12 C11 2 R461 4 CLK_PCIE_LOM 4 CLK_PCIE_LOM# 2 NB_TRD1NB_TRD1+ +3.3V_ALW R528 100KR2J-1-GP 1 0R2J-2-GP DY 1 NB_LOM_TRD2- 28 NB_LOM_TRD2+ 28 +3.3V_LAN_EN1 3 PCIE_SDSVDD M2 L2 M6 L6 A4 LOM_PCIE_RST# A1 M4 L4 31,32,36 PCIE_WAKE# 2 R463 B12 B11 +15V_ALW 100KR2J-1-GP 1 1 PLTRST# 19 SB_LOM_PCIE_RST# R515 2 PCIE_PLLVDD M3 1 2 1 2 C138 C151 SC4D7U6D3V3KX-GP SC47P50V2JN-3GP GLAN_RXP_C 1 2 C158 1 2 SCD1U10V2KX-4GP GLAN_RXN_C C159 SCD1U10V2KX-4GP PCIE_RX0+ PCIE_RX0PCIE_TX0+ PCIE_TX0- NB_LOM_TRD3- 28 NB_LOM_TRD3+ 28 NB_TRD2NB_TRD2+ GPHY_PLLVDD K4 1 2 1 2 C523 C521 SC4D7U6D3V3KX-GP SC47P50V2JN-3GP +1.2V_PCIE_SDSVDD 1 2 L16 BK1608LM182-T-1GP 7,18,31,32,35,45,46,51 F11 1 2 1 2 C480 C485 SC4D7U6D3V3KX-GP SC47P50V2JN-3GP +1.2V_PCIE_PLLVDD 1 2 L61 BK1608LM182-T-1GP 3 1 2 C500 SCD1U10V2KX-4GP +1.2V_GPHY_PLLVDD 1 2 L52 BK1608LM182-T-1GP 8 8 8 8 1 2 C514 SC4D7U6D3V3KX-GP A12 A11 1 1 2 C501 SCD1U10V2KX-4GP NB_TRD3NB_TRD3+ AVDDL AVDDL AVDDL C110 SCD047U10V2KX-2GP 1 2 C502 SC47P50V2JN-3GP B10 C10 D10 C122 SCD1U10V2KX-4GP +3.3V_ALW2 1 GPHY_TVCOI 4 1 2 L59 BK1608LM182-T-1GP C515 SC47P50V2JN-3GP 2 +1.2V_AVDDL 1 2 L55 BK1608LM182-T-1GP 1 2 L53 BK2125LM182-T-GP 1 2 1 2 C494 C495 SC47P50V2JN-3GP SCD1U10V2KX-4GP +2.5V_AVDD C9 D9 E10 2 E9 +1.2V_LOM 1 2 L51 BK1608LM182-T-1GP 1 2 C482 SCD1U10V2KX-4GP 2 AVDD AVDD AVDD 1 2 C481 SC47P50V2JN-3GP +2.5V_XTALVDD 1 2 LOM_GPHY_TVCOI 0R2J-2-GP DY K6 C119 SCD1U10V2KX-4GP 1 R433 XTALVDD +2.5V_BIASVDD 1 Monitor GPHY PLL Clk VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC E11 2 VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO D3 D6 E4 G8 H3 J3 J6 K3 E +2.5V_LOM BIASVDD 2 4 U86 D Place filters close to the power pins - 0.1uF should be closest to the power pin. Minimize the loop path from pin to cap to power feed via. The length of the path from the ground side of the cap to the ground via should also be minimized. +2.5V_LOM C120 SCD1U10V2KX-4GP Closed to pin E4, J3, D6, G8 Place filters close to the power pins - 0.1uF should be closest to the power pin. Minimize the loop path from pin to cap to power feed via. The length of the path from the ground side of the cap to the ground via should also be minimized. A6 A10 C1 F10 G1 J2 M1 C163 SC47P50V2JN-3GP C154 SC47P50V2JN-3GP 2 1 2 1 C131 SC47P50V2JN-3GP 2 1 SSID = LOM +3.3V_LAN C141 SC47P50V2JN-3GP 2 1 +1.2V_LOM VDDP VDDP VDDP A C527 SC22P50V2JN-4GP 1 2 SCD1U10V2KX-4GP C483 1 2 C149 SCD1U10V2KX-4GP 1 2 C476 SCD1U10V2KX-4GP 1 2 C164 SCD1U10V2KX-4GP 1 2 1 2 C528 SCD1U10V2KX-4GP 1 2 C475 SCD1U10V2KX-4GP 1 C162 SCD1U10V2KX-4GP Place high-freqency decoupling cpas close to the power pin. Minimize the loop path from pin to cap to power feed via. The length of the path from the ground side ofthe cap to the ground via should also be minimized. 2 DY 2 2 1 1 CLK_PCIGLAN 2 DYR462 33R2J-2-GP C95 SCD1U10V2KX-4GP 1 1 CLK_PCI_TPM C101 SC4D7U6D3V3KX-GP 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title LAN BCM5756ME Size Document Number Custom Reserve for EMI Date: A B C D Rev SC Parker Wednesday, March 21, 2007 Sheet E 27 of 53 A B C D E SSID = LOM 10/100/1000M Lan Transformer +2.5V_LOM XF1 1 C445 1 C444 1 C443 1 C442 2 2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP SCD1U10V2KX-4GP 3 4 9 10 TDCT#3 TDCT#4 TDCT#9 TDCT#10 24 23 20 19 18 17 14 13 RJ45_LOM_TRD0+ RJ45_LOM_TRD0RJ45_LOM_TRD1+ RJ45_LOM_TRD1RJ45_LOM_TRD2+ RJ45_LOM_TRD2RJ45_LOM_TRD3+ RJ45_LOM_TRD3- TXCT#16 TXCT#15 TXCT#21 TXCT#22 16 15 21 22 XFR_MCT3 XFR_MCT4 XFR_MCT2 XFR_MCT1 4 XFORM-248-GP Pulse H5020NL 2 LAN CONN R361 75R2F-2-GP NB_LOM_TCT TX+#24 TX-#23 TX+#20 TX-#19 TX+#18 TX-#17 TX+#14 TX-#13 R362 75R2F-2-GP 2 1 2 2 BK2125LM152-T-GP TD+#1 TD-#2 TD+#5 TD-#6 TD+#7 TD-#8 TD+#11 TD-#12 R363 75R2F-2-GP 2 1 L45 DY 0R3-0-U-GP 1 2 5 6 7 8 11 12 1 R383 4 NB_LOM_TRD0+ NB_LOM_TRD0NB_LOM_TRD1+ NB_LOM_TRD1NB_LOM_TRD2+ NB_LOM_TRD2NB_LOM_TRD3+ NB_LOM_TRD3- NB_LOM_TRD0+ NB_LOM_TRD0NB_LOM_TRD1+ NB_LOM_TRD1NB_LOM_TRD2+ NB_LOM_TRD2NB_LOM_TRD3+ NB_LOM_TRD3- R364 75R2F-2-GP 2 1 1 1 27 27 27 27 27 27 27 27 EC17 SC1KP3KV8KX-GP 2 1 LAN_TERMINAL 3 3 RJ1 2 1 RJ45_0RJ45_0+ B1 RJ45_2+ RJ45_2- 4 5 RJ45_LOM_TRD2+ RJ45_LOM_TRD2- B3 6 3 RJ45_1RJ45_1+ RJ45_3RJ45_3+ 8 7 RJ45_LOM_TRD3RJ45_LOM_TRD3+ A1 A2 A3 B2 NC#B2 GND GND 1 R358 1 R394 1 R395 9 10 EC16 SC1KP50V2KX-1GP LOM_ACTLED_YEL# LOM_SPD100LED_ORG# LOM_SPD10LED_GRN# 1 B3 A1 A3 EC20 SC1KP50V2KX-1GP 2 1 RJ45_LOM_TRD1RJ45_LOM_TRD1+ TX/RX#/YELLOW SPEED100#/AMBER SPEED10#/GREEN 2 RJ45_LOM_TRD0RJ45_LOM_TRD0+ POWER POWER EC21 SC1KP50V2KX-1GP 2 1 B1 A2 +3.3V_LAN 2 2 150R2F-1-GP 2 150R2F-1-GP 150R2F-1-GP NB_LOM_ACTLED_YEL# 27 NB_LOM_SPD100LED_ORG# 27 NB_LOM_SPD10LED_GRN# 27 Yellow LED:TX/RX Amber LED:Speed 100 Green LED:Speed 10 RJ45-126-GP 22.10277.031 1.route on bottom as differential pairs. 2.Tx+/Tx- are pairs. Rx+/Rx- are pairs. 3.No vias, No 90 degree bends. 4.pairs must be equal lengths. 5.6mil trace width,12mil separation. 6.36mil between pairs and any other trace. 7.Must not cross ground moat,except RJ-45 moat. 2 2 The blowout from the LAN magnetics to the RJ45 connector maintining the distance between the two to be within 1 inch. Hipot layout guide line update space > 50mil Rj11 layout guide line update > 100mil 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title LAN Connector Size A3 Document Number Rev A B C D SC Parker Date: Wednesday, March 21, 2007 Sheet E 28 of 53 A B C SSID = AUDIO E POP C255,C258 and DEPOP R317 FOR AD1984 AUD_EXT_MIC_L 30 AUD_EXT_MIC_R 30 AUD_VREFOUT_B 30 PORT_C_L PORT_C_R VREFOUT_C 23 24 29 Y DY DY PORT_D_L PORT_D_R 35 36 AUD_LINE_OUT_L 30 AUD_LINE_OUT_R 30 PORT_E_L PORT_E_R GPIO4/VREFOUT_E 14 15 31 DOCK_HP_MUTE# 36 PORT_F_L PORT_F_R GPIO3/VREFOUT_F 16 17 30 SPDIF_SHDN CD_L CD_GND CD_R 18 19 20 2 74LVC1G125DC-GP 3 R457 2 AUD_DMIC_CLK AUD_DMIC_IN0 1 0R2J-2-GP 17 AUD_DMIC_IN0 X01 46 2 4 DMIC_CLK DMIC0/VOL_UP/GPIO1 DMIC1/VOL_DN/GPIO2 Pop R315 for AD1984 +3.3V_RUN 1 R172 2 DY10KR2J-3-GP 47 48 30 AUD_EAPD# 38 AUD_SPDIF_OUT SPDIF_IN/EAPD/GPIO0 SPDIF_OUT PC_BEEP 12 MONO_OUT 32 CAP2 VREFFILT 33 27 AVSS AVSS 26 42 To SPDIF and media slice NC#43 NC#44 NC#45 7 49 DVSS GND 3 From EC To SPDIF & EC 36 AUD_PC_BEEP CAP2 CODEC_VREF 2 1 43 44 45 RN10 SRN10KJ-5-GP TO Audio OP STAC9205X5NBEB2XR-GP 2 1 +VDDA R222 10KR2J-3-GP DY DY +VDDA Change R352 to 2.67K 1% for AD1984 2 1 HDA_RST# AUD_DMIC_OE# 1 R453 10KR2J-3-GP +VDDA 3 4 AUD_DMIC_CLK_G 4 1 2 3 OE# A GND 1 21 22 28 1 VCC 1 PORT_B_L PORT_B_R VREFOUT_B U89 5 2 AUD_HP_OUT_L 30 AUD_HP_OUT_R 30 1 2 R208 100KR2J-1-GP 2 11 C285 SC1U10V2KX-1GP 1 PORT_A_L PORT_A_R VREFOUT_A 39 41 37 AUD_SENSE_A AUD_SENSE_B 2 1 HDA_SDO 20 SB_AZ_CODEC_RST# 2 1 HDA_SDI_CODEC 5 HDA_SYNC 4 +VDDA 8 10 C295 SCD1U10V2KX-4GP 13 34 HDA_BITCLK 20 SB_AZ_CODEC_SYNC +3.3V_RUN SENSE_A SENSE_B C293 SCD1U10V2KX-4GP SB_AZ_CODEC_SDIN3_R 2 33R2J-2-GP 25 38 1 1 R149 20 SB_AZ_CODEC_SDIN3 20 SB_AZ_CODEC_SDOUT 2 2 6 20 SB_AZ_CODEC_BITCLK AVDD AVDD DVDD_CORE DVDD_CORE DVDD_CORE DVDD_IO 2 1 2 C215 SCD1U10V2KX-4GP 1 2 R185 CODEC_DVDD_CORE_PIN40 100KR2J-1-GP C300 DYSC10U10V5KX-2GP C304 SC10U10V5KX-2GP 1 2 C270 SC1000P50V3JN-GP C301 SC10U10V5KX-2GP +3.3V_RUN +VDDA DY U31 1 9 40 3 C212 SC4D7U6D3V3KX-GP DY 2 1 CODEC_DVDD_CORE C218 SCD1U10V2KX-4GP 1 1 2 R148 0R2J-2-GP DY 2 1 2 C260 SC1U10V2KX-1GP 1 C227 SCD1U10V2KX-4GP 2 4 C519 SC10U10V5KX-2GP +3.3V_RUN Close to pin9 17 AUD_DMIC_CLK_G D 2 R166 If SENSE_A total length > 6" change C to 0.1uF 5K1R2F-2-GP 1 1 R173 39D2R2F-L-GP 30,36 HP_NB_SENSE 1 1 PC BEEP 3 U33 2N7002DW-7F-GP 1 30,36 AUD_MIC_SWITCH 20 SPKR 35 BEEP From EC 1 2 3 B A GND VCC 5 Y 4 U90 74AHC1G86GW-GP 1 2 R454 20KR2J-L2-GP AUD_BEEP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. AUD_PC_BEEP 1 2 C214 SCD1U10V2KX-4GP Title R456 XOR gate C198 SCD1U10V2KX-4GP 1 Wistron Corporation AUD_SYS_BEEP 1 From SB C522 SCD1U10V2KX-4GP DY10KR2J-3-GP CODEC STAC 9205 Size A3 2 DY Document Number Rev B C D SC Parker Date: Wednesday, March 21, 2007 A 1 +VDDA 2 2 1 DY 2 2 2 C199 SCD1U10V2KX-4GP 1 SB_AZ_CODEC_SDOUT1 1 DY SB_AZ_CODEC_BITCLK1 DY 6 R150 47R2J-2-GP R151 47R2J-2-GP 2 SB_AZ_CODEC_BITCLK HP_NB_SENSE_1 SB_AZ_CODEC_SDOUT MIC_SWITCH 4 Azalia I/F EMI 5 Azalia I/F EMI 2 R177 20KR2J-L2-GP 2 2 C242 SC1KP50V2KX-1GP 1 AUD_SENSE_A 2 Change C470 to 1UF and pop R157,C253 for AD1984 Sheet E 29 of 53 A B 2 C478 SC10U10V5KX-2GP DY 5 2 EC9 SC100P50V2JN-3GP 20.F0693.004 4 6 C229 SCD1U10V2KX-4GP 2 1 C292 SC1U10V2KX-1GP SPK1 MLX-CON4-15-GP 1 2 3 4 2 2 2 1 2 30 17 VDD +VDDA 2 1 2 1 2 POP R292 and CHANGE R366 TO 1.3K FOR AD1984 for TPA6040A4 R746,C219,C220, Depop R152,R153,R210, Change C203,C204,C294 to 0.47UF for MAX9789A R152,R153,R210, Depop R746,C219,C220, Change C203,C204,C294 to 0.033UF EC22 SC100P50V2JN-3GP SPKR_L+1 2 BLM18BD601SN1D-GP SPKR_R+1 2 BLM18BD601SN1D-GP 1 1 L56 L54 Close to pin13,14 LOUT1 29,36 HP_NB_SENSE AUD_HP_JACK_L AUD_HP_JACK_R C272 SC1U10V2KX-1GP 1 U32 Pop U32 Pop R442 100KR2J-1-GP EC23 SC100P50V2JN-3GP 2 1 1 2 X01 3 +3.3V_RUN 2 1 2 1 R191 2K2R2J-2-GP C219 SCD47U10V2KX-GP AUD_CPVSS LINE OUT DY DY 2 DY 2 TPA6040A4-GP 1 1 2 R152 0R2J-2-GP PVSS 14 13 11 28 33 21 5 AUD_BIAS AUD_SET DY AUD_LINE_OUT_R 29 AUD_LINE_OUT_L 29 C268 SC1U10V2KX-1GP AUD_SPK_ENABLE# AMP_MUTE# AUD_HP_EN AMP_REGEN 1 2 C204 1 2 SCD47U25V5KX-2GP C203 SCD47U25V5KX-2GP C224 SC47P50V2JN-3GP 1 23 25 22 4 29 24 1 X01 2 SC1U10V2KX-1GP 2 SPKR_EN# MUTE# HP_EN REGEN VOUT BIAS SET 1 C263 1 AUD_LIN_R AUD_LIN_L 2 2 DY DY GND GND C290 SC47P50V2JN-3GP CPGND GAIN1 GAIN2 CPVSS 31 32 PGND PGND C287 SC47P50V2JN-3GP SPKR_INR SPKR_INL 2 3 C274 SC1U10V2KX-1GP HP_INR HP_INL AMP_C1P AMP_C1N 2 26 27 10 12 C1P C1N C294 SCD47U10V2KX-GP HPR HPL AUD_HP_R 1 2 C311 1 2 SC1U25V6KX-2GP AUD_HP_L C312 SC1U25V6KX-2GP AUD_AMP_GAIN1 AUD_AMP_GAIN2 U32 C225 SC47P50V2JN-3GP 2 1 15 16 HPVDD AUD_HP_JACK_R AUD_HP_JACK_L CPVDD OUTL+ OUTLOUTROUTR+ AUD_SPK_L- 9 8 18 PVDD PVDD 2 C249 SC1U10V2KX-1GP 1 1 2 C305 SC10U10V5KX-2GP 2 1 C230 SC1U10V2KX-1GP AUD_SPK_R+ 6 7 19 20 1 29 AUD_HP_OUT_R 29 AUD_HP_OUT_L C291 SC1U10V2KX-1GP EC7 SC100P50V2JN-3GP AUD_SPK_DET Close to pin17,18 1 3 C520 SC10U10V5KX-2GP 2 1 Close to pin8 1 C265 SC1U10V2KX-1GP 1 Close to pin30 +5V_SPK_AMP Close to pin9 AUD_SPK_L- 19 AUD_SPK_DET AUD_SPK_R+ 1 4 1 3A,60ohm@100MHz DCR:0.025ohm 1 L50 BLM21PG600SN1-GP E Speaker SSID = AUDIO +5V_SPK_AMP 1 D 2 +5V_RUN C 1 2 6 3 4 5 G1 G2 AUDIO-JK51-GP 22.10088.A31 2 +3.3V_RUN 0 1 10dB 1 0 15.6dB 1 1 21.6dB 36 NB_MUTE# AUD_SPK_ENABLE# From EC AND Gate X01 2 4 3 5 2 6 1 AUD_EAPD# 29 NB_MUTE 1 2 MIC1 DY From CODEC NB_MUTE# 1 B HP_NB_SENSE 2 A VCC 5 3 GND Y 4 U42 74AHC1G08GW-GP-U U41 2N7002DW-7F-GP B C 1 MIC_IN_R_C 1 2 6 3 4 5 G1 G2 AUDIO-JK51-GP 22.10088.A31 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. +3.3V_RUN 1 2 C319 SCD1U10V2KX-4GP Title AUDIO AMP Size A3 AUD_HP_EN Document Number Rev D SC Parker Date: Thursday, March 22, 2007 A MIC_IN_L_C EC18 SC100P50V2JN-3GP 1 6dB 1 R389 1 R385 R230 100KR2J-1-GP GAIN 0 R380 4K7R2J-2-GP 2 1 1 DY +5V_SPK_AMP 2 GAIN2 X01 1 +5V_SPK_AMP R227 100KR2J-1-GP 0 2 C453 MIC_IN_L_2 SC1U25V3KX-GP 2 C446 MIC_IN_R_2 SC1U25V3KX-GP 29,36 AUD_MIC_SWITCH L47 2 MIC_IN_L_3 1 2 0R2J-2-GP BLM18BD601SN1D-GP 2 MIC_IN_R_3 1 2 0R2J-2-GP L46 BLM18BD601SN1D-GP EC19 SC100P50V2JN-3GP 2 1 Signal inverter for speaker shutdown 2 DY R165 100KR2J-1-GP 1 GAIN1 MIC_IN_L_1 1 5D1R2J-1-GP 2 MIC_IN_R_1 1 5D1R2J-1-GP 2 R376 100KR2J-1-GP 2 29 AUD_EXT_MIC_R AUD_AMP_GAIN2 1 R390 1 R382 2 R176 100KR2J-1-GP 2 DY 29 AUD_EXT_MIC_L 1 1 AUD_AMP_GAIN1 MIC IN DY C462 SC10U10V5KX-2GP R381 20KR2J-L2-GP R162 100KR2J-1-GP 2 2 R171 100KR2J-1-GP 2 1 1 DY X01 R398 4K7R2J-2-GP 2 1 AMP_MUTE# 1 2 R210 100KR2J-1-GP 2 1 1 2 R142 R746 100KR2J-1-GP 0R2J-2-GP 1 2 AMP_REGEN1 2 23 AUD_AVDD_ON R153 C220 0R2J-2-GP SCD47U10V2KX-GP From EMC4001 DY +5V_SPK_AMP AUD_VREFOUT 2 1 GAIN SETTING 1 R403 0R2J-2-GP 29 AUD_VREFOUT_B R393 20KR2J-L2-GP 2 1 +5V_SPK_AMP Sheet E 30 of 53 A B EXPRESS CARD POWER SWITCH C SSID = ExpressCard D 1 R657 20 SB600_USBP6+ E EXPRESS CARD Geometry : 1759714-1 USBP6D+ 2 0R2J-2-GP USB-PORT6 ERPSKT1 1 1 EL7 DLW21SN900SQ2LUGP 21 19 18 1 36 PCIE_TX3+ PCIE_TX3- 8 PCIE_TX3+ 8 PCIE_TX3- SHDN# PERST# CPUSB# CPPE# SYSRST# +1.5VVIN +1.5VOUT +3VOUT +3VIN SHDN# CARD_RESET# CPUSB# EXPRCRD_PWREN# NRST R704 1 1 R705 1 R702 1 R680 2 100KR2J-1-GP 2 2 100KR2J-1-GP 2 100KR2J-1-GP 0R2J-2-GP +3.3V_SUS PCIE_RX3+ PCIE_RX3- PLTRST# PLTRST# 7,18,27,32,35,45,46,51 +3.3V_CARD 27,32,36 PCIE_WAKE# TPS2231RGP-GP +3.3V_CARDSUS CLK_PCIE_EXPCARD CLK_PCIE_EXPCARD# EXPRCRD_PWREN# CARD_CLK_REQ# 4 CLK_PCIE_EXPCARD 4 CLK_PCIE_EXPCARD# 36 EXPRCRD_PWREN# 4 CARD_CLK_REQ# PCIE_WAKE# 1 R649 2 0R2J-2-GP CARD_RESET# +3.3V_CARDSUS PCIE_WAKE#_C +1.5V_CARD SB_SMB_DATA1 SB_SMB_CLK1 20,27,32 SB_SMB_DATA1 20,27,32 SB_SMB_CLK1 CPUSB# USBP6D+ USBP6D- +3.3V_RUN +3.3V_SUS +3.3V_CARD +3.3V_CARD+1.5V_CARD +1.5V_CARD 1 C697 SC10U10V5KX-2GP C680 SCD1U10V2KX-4GP 2 1 C665 SCD1U10V2KX-4GP 2 2 C668 SC10U10V5KX-2GP 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 EXPRESS PIN 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 27 +1.5V_RUN 1 +1.5V_CARD +3.3V_CARD 1 Use Card and No Card USBP6D- 2 0R2J-2-GP 8 PCIE_RX3+ 8 PCIE_RX3- 20 8 9 10 6 4 ERP1 2 Test circuit 3 EXPRCRD_STDBY# For Newcard socket EC5018 AUXOUT AUXIN 1.5VOUT 1.5VIN 3.3VOUT 3.3VIN NC#16 NC#14 NC#13 NC#5 NC#4 15 17 11 12 3 2 +1.5V_RUN +1.5V_CARD +3.3V_CARD +3.3V_RUN DY 2EXPRCRD_STDBY# 0R2J-2-GP +1.5V_CARD Max. 650mA, Average 500mA. +3.3V_CARD Max. 1300mA, Average 1000mA +3.3V_CARDAUX Max. 275mA U65 THERMAL_PAD OC# RCLKEN STBY# 7 GND 16 14 13 5 4 1 R703 CARDBUS-SKT92-GP-U2 3 1 R658 20 SB600_USBP6STBY# 2 Close EPR1 DY C765 SCD1U10V2KX-4GP 4 C390 SCD1U10V2KX-4GP 2 C403 SCD1U10V2KX-4GP 2 2 C402 SCD1U10V2KX-4GP +1.5V_CARD 1 1 +3.3V_CARD 1 1 2 C391 SCD1U10V2KX-4GP +3.3V_CARDSUS 2 1 C762 SCD1U10V2KX-4GP +1.5V_RUN 1 +3.3V_RUN 2 4 +3.3V_SUS 2 NP1 Please Near the U32 GND PCIE_TXP4 PCIE_TXN4 GND PCIE_RXP4 PCIE_RXN4 GND CLK_PCIE_NEW CLK_PCIE_NEW# CPPE# CONN_CLKREQ# +3VRUN_NEW +3VRUN_NEW PERST# +3VAUX_NEW PCIE_WAKE# +1.5VRUN_NEW +1.5VRUN_NEW SMB_DATA SMB_CLK TP1 TP2 CPUSTB# USB+ USBGND 3 CARDBUS26P-9GP-U 62.10024.891 Please Near the EPR1 SSID = User.interface SSID = User.interface Bluetooth Module conn. Sniffer LED. 1 1 2 2 G 1 D SNIFFER_BLUE#_1 2 blue Q33 DTA114YKA-1-GP 36 SNIFFER_DET# 3 1 2 SNIFFER_B 1 2 R308 R309 220R2J-L2-GP 220R2J-L2-GP 8 2 2 1 DY 1 2 SNIFFER1 0R2J-2-GP C367 SC1U10V2KX-1GP SNIFFER2 1 1 R317 100KR2J-1-GP 1 BT_ACTIVITY Q64 MMBT3904-7-F-GP Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 2 Q65 2N7002-7F-GP 1 2 R697 0R2J-2-GP DY 20.K0267.006 +RTC_CELL BT_ACTIVITY_1# 3 S 2 2 D HRS-CON6-3-GP R707 10KR2J-3-GP G 2 35 SNIFFER_PWR_SW# DY 1 17 BT_ACTIVE# BT_ACTIVE# 1 R318 36 WIRELESS_ON/OFF# +5V_RUN BT_ACTIVITY_1# 32 1 2 3 4 5 6 R313 100KR2J-1-GP Note:Place R310 near CN13. 33,36 LED_MASK# 1 RSNIFFER_Y RSNIFFER_B Sniffer Switch 1 20.D0183.110 This circuit is only needed if the platform has the SNIFFER SNIFFER_DET# +3.3V_RUN MLX-CON10-7-GP 2 1 S 1 R319 2 0R2J-2-GP Title EXPRESS CARD/BT/SNIFFER C371 SC1U10V2KX-1GP Size A3 Document Number Rev B C D SC Parker Date: Wednesday, March 21, 2007 A SNIFFER1 7 +5V_SUS 1 IN 35 SNIFFER_BLUE# 2 SNIFFER_Y 3 Q34 2N7002-7F-GP R1 C756 SCD1U10V2KX-4GP R297 100KR2J-1-GP R2 2 Q35 DTA114YKA-1-GP OUT 2 35 SNIFFER_YELLOW# GND IN +3.3V_SUS R1 BT_ACTIVITY C760 SC4D7U6D3V3KX-GP R679 10KR2J-3-GP 1 OUT 32 COEX1_BT_ACTIVE 36 BT_RADIO_DIS# 32 COEX2_WLAN_ACTIVE +3.3V_RUN R2 20 SB600_USBP7+ 20 SB600_USBP7- 2 +3.3V_SUS yellow BT1 1 2 3 4 5 6 7 8 9 10 11 12 GND USB-PORT7 Sheet E 31 of 53 C D E USB-PORT9 +1.5V_RUN MiniCard WWAN connector 1 PERN0 PERP0 23 25 PCIE_RX1PCIE_RX1+ PETN0 PETP0 31 33 PCIE_TX1PCIE_TX1+ USB_DUSB_D+ 36 38 MINI_USBP9MINI_USBP9+ SMB_CLK SMB_DATA 30 32 SB_SMB_CLK1 SB_SMB_DATA1 WAKE# CLKREQ# PERST# 1 7 22 PCIE_WAKE# PCIE_WAKE# 27,31,36 MINI2CLK_REQ# SB_WWAN_PCIE_RST#_R 2 1 R645 0R2J-2-GP 2 1 R646 0R2J-2-GP 52 +3.3V 24 +3.3VAUX UIM_RESET C377 SC100P50V2JN-3GP 1 C369 SC100P50V2JN-3GP 2 1 2 DY VCC VPP C2 C3 C7 RST CLK I/O UIM_PWR UIM_DATA UIM_CLK UIM_RESET UIM_VPP 7 8 9 C5 GND GND GND GND 3 5 8 10 12 14 16 17 19 20 37 39 41 43 45 47 49 51 RESERVED#3 RESERVED#5 RESERVED#8 RESERVED#10 RESERVED#12 RESERVED#14 RESERVED#16 RESERVED#17 RESERVED#19 RESERVED#20 RESERVED#37 RESERVED#39 RESERVED#41 RESERVED#43 RESERVED#45 RESERVED#47 RESERVED#49 RESERVED#51 CARDBUS6P-GP 62.10024.841 DY 36 WWAN_RADIO_DIS# WWAN_RADIO_DIS# PCIE_WWAN_DET# X01 3 42 44 46 LED_WWAN# LED_WLAN# LED_WPAN# UIM_VPP 4 TP182 TPAD28 2 EC3 SC33P50V2JN-3GP 2 1LED_WWAN_OUT# UIM_PWR 5 GND GND GND GND GND GND GND GND GND GND GND GND GND GND 4 9 15 18 21 26 27 29 34 35 40 50 53 54 3 PCIE_RX1- 8 PCIE_RX1+ 8 SB_SMB_CLK1 20,27,31 SB_SMB_DATA1 20,27,31 DY 2 0R2J-2-GP SB600_USBP9+ 20 Layout Note: Place resistors close to choke as possible to minimize stubs. MINI2CLK_REQ# 4 PLTRST# 7,18,27,31,35,45,46,51 SB_WWAN_PCIE_RST# 19 RN87 SRN100KJ-6-GP WWANSKT1 NP1 NP1 NP2 NP2 GND 1 GND 2 GND 3 GND 4 NP1 NP2 1 1 R278 USB_WWAN_DET# 62.10043.481 EC4 SC33P50V2JN-3GP PCIE_WWAN_DET# USB_WWAN_DET# 19 PCIE_WWAN_DET# 19 USB_WWAN_DET# 3 MINDIN4-42-GP 2 2 1 2 EC5 SC33P50V2JN-3GP 2 EC2 SC33P50V2JN-3GP EC6 SC1U10V2KX-1GP UIM_DATA 6 1 UIM_CLK 1 ESD1 SRV05-2-GP MINI_USBP9+ 4 Close MINICARD2(WWAN) +3.3V_RUN SKT-MINI52P-14-GP 3 EL3 DLW21SN900SQ2LUGP DY PCIE_TX1- 8 PCIE_TX1+ 8 4 3 +1.5V +1.5V SB600_USBP9- 20 CLK_PCIE_MINI2 4 CLK_PCIE_MINI2# 4 2 28 48 1 2 R279 0R2J-2-GP 1 2 2 REFCLK+ REFCLK- 1 3.3V CLK_PCIE_MINI2 CLK_PCIE_MINI2# 2 1 C704 SCD047U10V2KX-2GP 2 2 C685 SCD047U10V2KX-2GP 1.5V 2 13 11 NP1 NP2 2 C1 C6 UIM_RESET UIM_CLK UIM_DATA Place caps closest to the SIM connector 1 MINI_USBP9- WWAN1 6 SIM1 UIM_PWR UIM_VPP C676 SCD1U10V2KX-4GP C593 Please Near the MINICARD2/Pin24 1 1 1 1 +3.3V_RUN C670 SC33P50V2JN-3GP 2 1 C702 SC33P50V2JN-3GP 2 TC19 ST330U6D3VDM-18GP-U 2 4 1 +3.3V_RUN TC20 ST330U6D3VDM-18GP-U C677 SCD047U10V2KX-2GP 2 C669 SC33P50V2JN-3GP 1 SSID = WWAN 4 B 1 A 62.10043.491 EC Pin 71 19 8051_TX 82 42 8051_RX 81 +3.3V_WLAN 1 For Debug card used only. DY 2 0R2J-2-GP WLAN_RADIO_OFF# PCIE_WLAN_DET# 1 D27 RB751V-40-1-GP 1 G89 +5V_RUN +5V_DBG_RUN 2 GAP-OPEN-PWR +3.3V_ALW +3.3V_DBG_ALW 2 GAP-OPEN-PWR 1 G90 LED_WLAN_OUT# R652 1 DY 2 BT_ACTIVITY_WLAN# 0R2J-2-GP 2 2 X01 3.3V 28 48 +1.5V +1.5V 52 +3.3V 24 +3.3VAUX 3 5 8 10 12 14 16 17 19 20 37 39 41 43 45 47 49 51 RESERVED#3 RESERVED#5 RESERVED#8 RESERVED#10 RESERVED#12 RESERVED#14 RESERVED#16 RESERVED#17 RESERVED#19 RESERVED#20 RESERVED#37 RESERVED#39 RESERVED#41 RESERVED#43 RESERVED#45 RESERVED#47 RESERVED#49 RESERVED#51 42 44 46 LED_WWAN# LED_WLAN# LED_WPAN# REFCLK+ REFCLK- 13 11 CLK_PCIE_MINI1 CLK_PCIE_MINI1# PERN0 PERP0 23 25 PCIE_RX2PCIE_RX2+ PETN0 PETP0 31 33 PCIE_TX2PCIE_TX2+ USB_DUSB_D+ 36 38 MINI_USBP4MINI_USBP4+ SMB_CLK SMB_DATA 30 32 WLAN_SCLK WLAN_SDATA WAKE# CLKREQ# PERST# 1 7 22 GND GND GND GND GND GND GND GND GND GND GND GND GND GND 4 9 15 18 21 26 27 29 34 35 40 50 53 54 PCIE_WAKE# MINI1CLK_REQ# SB_WLAN_PCIE_RST#_R 2 R651 2 R650 SKT-MINI52P-14-GP 62.10043.481 CLK_PCIE_MINI1 4 CLK_PCIE_MINI1# 4 35 WLAN_3V_ENABLE PCIE_RX2- 8 PCIE_RX2+ 8 R663 100KR2J-1-GP +3.3V_WLAN PCIE_TX2- 8 PCIE_TX2+ 8 TP179 TPAD28 TP181 TPAD28 1 2 RN85 SRN2K2J-1-GP 4 3 +3.3V_RUN TP178 TPAD28 TP180 TPAD28 4 3 1.5V 2 1 2 1 C706 SCD047U10V2KX-2GP 2 C705 SCD047U10V2KX-2GP 1 2 1 C683 SCD1U10V2KX-4GP 2 2 6 DY 1 0R2J-2-GP 1 0R2J-2-GP RN83 SRN100KJ-6-GP MINI1CLK_REQ# 4 PLTRST# 7,18,27,31,35,45,46,51 SB_WLAN_PCIE_RST# 19 19 PCIE_WLAN_DET# 19 USB_WLAN_DET# B 1 USB_WLAN_DET# WLANSKT1 NP1 NP1 NP2 NP2 GND 1 GND 2 GND 3 GND 4 MINDIN4-42-GP 62.10043.491 C PCIE_WLAN_DET# USB_WLAN_DET# Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title WLAN/WWAN Size Document Number Custom Rev D SC Parker Date: Wednesday, March 21, 2007 A D 6 D 5 S 4 SCD1U10V2KX-4GP 1 2 1 COEX2_WLAN_ACTIVE_1 2 2 0R2J-2-GP COEX1_BT_ACTIVE_1 0R2J-2-GP U98 SI3424DV-T1-GP WLAN1 NP1 NP2 2 1 R662 1 35 8051_RX 17 LED_WLAN_OUT# 31 BT_ACTIVITY_1# 2 WLAN_RADIO_DIS# Prevent backdrive when WoW is enabled. MiniCard WLAN connector NP1 NP2 35 HOST_DEBUG_TX 35 HOST_DEBUG_RX 35 8051_TX 36 WLAN_RADIO_DIS# C682 SCD1U10V2KX-4GP 1 2 1 COEX2_WLAN_ACTIVE 1 COEX1_BT_ACTIVE R665 1 R666 31 COEX2_WLAN_ACTIVE 31 COEX1_BT_ACTIVE C587 Please Near the MINICARD1/Pin24 C701 SC4D7U6D3V3KX-GP +3.3V_WLAN +3.3V_WLAN C684 SCD047U10V2KX-2GP 2 C687 SCD047U10V2KX-2GP C711 D D G 2 1 1 2 1 2 3 WLAN_3V_ENABLE_2 U99 2N7002DW-7F-GP +1.5V_RUN C686 SCD1U10V2KX-4GP +3.3V_ALW 1 HOST_DEBUG_RX R669 100KR2J-1-GP 2 17 1 2WLAN_3V_ENABLE_1 R667 100KR2J-1-GP 4 70 5 HOST_DEBUG_TX 3 16 6 Debug Pin Name +3.3V_ALW2 2 JMINI Pin SSID = WLAN 1 +15V_ALW DEBUG PINS Sheet E 32 of 53 A B C D E PATA HDD conn. SSID = PATA SSID = PATA IDE_D[0..15] 19 IDE_D[0..15] 4 +3.3V_RUN_HDD +3.3V_ALW2 +15V_ALW PATA1 1 2 C395 SC10U10V5KX-2GP 1 C397 SC10U10V5KX-2GP 2 2 IDE_D8 IDE_D9 IDE_D10 IDE_D11 IDE_D12 IDE_D13 IDE_D14 IDE_D15 IDE_DREQ IDE_IOW# DY +3.3V_RUN_HDD 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 IDE_DREQ 19 IDE_IOW# 19 INT_IRQ14 IDE_DIAG# IDE_A2 IDE_CS3# R333 10KR2J-3-GP INT_IRQ14 19 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 DY IDE_A2 19 IDE_CS3# 19 +3.3V_RUN_HDD 1 2 4 2 MLX-CONN40D-7GP R334 DY 2K7R2J-GP 3 20.F0091.040 1 +3.3V_RUN 1 IDE_IORDY 4K7R2J-2-GP IDE_DREQ 5K6R2J-1-GP 2 IDE_D7 10KR2J-3-GP 2 INT_IRQ14 8K2R2J-3-GP 2 DY 2 1 1 2 1 +3.3V_RUN_HDD 3 This circuit is only needed if the platform has the SNIFFER IDE_IOR# IDE_IORDY IDE_DACK# IDE_A1 IDE_A0 IDE_CS1# HDD_LED# 19 IDE_IOR# 19 IDE_IORDY 19 IDE_DACK# 19 IDE_A1 19 IDE_A0 19 IDE_CS1# C735 ST100U6D3VBM-13GP 2 2 R691 100KR2J-1-GP C708 SC4D7U6D3V3KX-GP 1 C731 SCD1U10V2KX-4GP R676 100KR2J-1-GP 1 +3.3V_RUN_HDD SI3456BDV-T1-GP D 6 D 5 S 4 1 2 1 1 D D G 2 HDDC_EN 36 HDDC_EN IDE_RST_MOD_R IDE_D7 IDE_D6 IDE_D5 IDE_D4 IDE_D3 IDE_D2 IDE_D1 IDE_D0 1 C751 SCD1U10V2KX-4GP 2 R688 0R2J-2-GP 20 IDE_RST_MOD +3.3V_ALW R686 10KR2J-3-GP U100 1 2 HDDC_EN_2 3 3 2 1 U103 2N7002DW-7F-GP PATA_DET# 20 PATA_DET# R692 100KR2J-1-GP 2 4 5 6 2 1 2HDDC_EN_1 R672 100KR2J-1-GP 1 R690 1 R340 1 R689 1 R335 31,36 LED_MASK# 2 G R715 10KR2J-3-GP D 17 PATA_ACT# HDD_LED#_1 S Q69 2N7002-7F-GP 1 R716 2 DY 2 R714 0R2J-2-GP 1 HDD_LED# 0R2J-2-GP SSID = User.interface JUST SUPPORT S3 WAKE UP,CHANGE TO SUS POWER 2 SPI BIOS :SST FEROM 25VF016B P/N:72.25016.A01 SPI BIOS socket :62.10076.011 PEN 1 +3.3V_ALW R19 100KR2J-1-GP 35 +3.3V_SUS PEN_SW# R532 10KR2J-3-GP 2 C613 SCD1U10V2KX-4GP 36 PEN_DET# 2 1 1 SPI ROM 1 2 R18 10KR2J-3-GP C9 SC1U10V2KX-1GP +3.3V_ALW 2 SPI1 1 R548 1 R573 2 2 0R2J-2-GP 0R2J-2-GP 36 PEN_LED# S D PEN_LED#_1 1 2 Q1 DTA114YKA-1-GP 62.10076.011 1 PEN_LED#_2 3 1 Wistron Corporation C774 SC22P50V2JN-4GP DY 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. DY 2 1 C773 SC22P50V2JN-4GP 2 DY 2 1 C772 SC22P50V2JN-4GP SPI_CS# SPI_CLK0 SPI_SI0 Title HDD/SPI ROM/PEN Size A3 Document Number Rev B C D SC Parker Date: Wednesday, March 21, 2007 A MLX-CON6-15-GP 1 G Q2 2N7002-7F-GP SKT-G6179-GP 1 R13 220R2J-L2-GP +5V_SUS SB_SPI_HOLD# 19 EC_FLASH_SPI_CLK 35 EC_FLASH_SPI_DO 35 IN SB_SPI_HOLD# SPI_CLK0 SPI_SI0 R1 8 7 6 5 PEN_CABLE_DET# PEN_SW# PEN_DET# PEN_LED#3 NC#5 GND GND GND OUT 1 2 3 4 R2 SPI_SO0 2 2 47R2J-2-GP SPI_WP#0 10KR2J-3-GP 1 R575 1 R574 1 2 3 4 5 6 7 8 GND 19 SPI_CS# 35 EC_FLASH_SPI_DIN +3.3V_SUS PEN_CABLE_DET# PEN_SW#_R PEN_DET# PEN_LED#_3 2 1 X01 PEN1 36 PEN_CABLE_DET# 2 SSID = Flash.ROM 2 X01 Sheet E 33 of 53 A B SSID = USB 2 1 DY 1 R337 20 SB600_USBP0+ 1 1 DY USBP1_D+ 3 D26 VBUS DD+ GND SHELL#5 SHELL#6 SHELL#7 SHELL#8 22.10218.T31 4 +USB_SIDE0_PWR 1 2 3 4 5 6 7 8 SKT-USB-172-GP 2 0R2J-2-GP 22.10218.T31 4 +USB_SIDE0_PWR 4 EL4 DLW21SN900SQ2LUGP VBUS DD+ GND SHELL#5 SHELL#6 SHELL#7 SHELL#8 SKT-USB-172-GP 2 0R2J-2-GP USB2 USBP0_DUSBP0_D+ 3 1 1 DY 1 R474 20 SB600_USBP1+ 1 2 3 4 5 6 7 8 USBP1_DUSBP1_D+ 4 3 4 USB1 EL6 DLW21SN900SQ2LUGP 1 2 R336 0R2J-2-GP 20 SB600_USBP0- 1 2 R464 0R2J-2-GP 20 SB600_USBP1- TC18 ST150U6D3VDM-14GP 2 TPS2062D-GP TPS2062 1-A Continuous Current,Short-circuit output current (1.1 A min, 2.1 A max),Over-current trip threshold TYP 2.4A,MAX 3A. 1 8 7 6 5 OC1# OUT1 OUT2 OC2# 1 GND IN EN1# EN2# 2 C392 SC1U10V2KX-1GP +USB_SIDE0_PWR +USB_SIDE0_PWR +USB_SIDE0_PWR 100 mil C506 SCD1U10V2KX-4GP 1 4 1 2 3 4 2+5V_USB_SIDE0 36 USB_SIDE_EN# 1 R331 0R6J-3-GP USB-PORT0 USB_OC0_1# 20 U69 2 2 +5V_ALW E USB-PORT1 C505 SCD1U10V2KX-4GP USB-PORT0 POWER D 2 USB POWER C DY 2 PRTR5V0U2X-GP USBP1_D- USBP0_D+ 3 D15 2 PRTR5V0U2X-GP USBP0_D- 3 3 USB-PORT 2 SSID = PUSB 1 2 C419 SCD1U50V3KX-GP +PWR_SRC P-USB DC POWER 1 R350 2 100KR2J-1-GP Id=-4A,Vds=-30V SDA 6 PUSB_SDA 1 L42 BLM21PG600SN1-GP C425 SCD1U50V3KX-GP SCL 8 PUSB_SCL PRES# 7 DBAY_MODPRES#_R 1 2 R9 100R2J-2-GP SKT-USB-161-GP 1 2 F1 FUSE-1D5A24V-1GP R11 +3.3V_SUS 5 1 6 PWRUSB_EN 36 2 PWRUSB_OC 36 from KBC (PU on ECE5032 side) 2 2 2 4 2 R29 1 10KR2J-3-GP 1 PUSB_SDA 3 U6 2N7002DW-7F-GP 200KR2J-L1-GP R20 10KR2J-3-GP R349 10KR2J-3-GP PWRUSB_EN_1 PWRUSB_SMBUS_EN 2 0R2J-2-GP P-USB SMBUS 1 1 R402 2 1 2 6 R26 100KR2J-1-GP DBAY_MODPRES# 36 22.10218.R91 20 SB600_USBP2+ 5 Q37 FDC658P-2-GP 1 2 1 DY GND GND GND GND GND GND 2 4 9 10 11 12 13 EL5 DLW21SN900SQ2LUGP USB_PWRSRC_1 2 2 USB_PWR_SRC_2 PWRUSB_EN_2 3 1.5A/24V,It=3A USB_PWR_SRC_3 1 DD+ 3 2 3 4 1 USBP2_DUSBP2_D+ 20 SB600_USBP24 3A,60ohm@100MHz DCR:0.025ohm +PUSB_PWR PUSB1 POWER 1 POWER-DC 5 2 1 2 R401 0R2J-2-GP 23,35,40 THRM_SMBCLK 4 3 5 2 6 1 THRM_SMBDAT 23,35,40 PUSB_SCL U7 2N7002DW-7F-GP P-USB POWER 1 U77 from KBC USB_OC2# 20 OC1# OUT1 OUT2 OC2# TPS2062D-GP 8 7 6 5 +PUSB_PWR +PUSB_PWR 4 1 Wistron Corporation 100 mil C457 SCD1U10V2KX-4GP 1 GND IN EN1# EN2# C458 SCD1U10V2KX-4GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. DY TC17 ST150U6D3VDM-14GP Title USBP2_D+ 2 36 USB_BACK_EN# 1 2 3 4 1 +5V_PUSB 2 C452 SC1U10V2KX-1GP 2 1 1 R387 0R6J-3-GP 2 2 +5V_ALW 1 1 TPS2062 1-A Continuous Current,Short-circuit output current (1.1 A min, 2.1 A max),Over-current trip threshold TYP 2.4A,MAX 3A. 3 D23 USBP2_D2 PRTR5V0U2X-GP P-USB/USB Size Document Number Custom Rev A B C D SC Parker Date: Wednesday, March 21, 2007 Sheet E 34 of 53 33 EC_FLASH_SPI_CLK 33 EC_FLASH_SPI_DIN 33 EC_FLASH_SPI_DO 2 X01 CLK_PCI_5025 1 20,51 SIO_PWRBTN# 31 SNIFFER_YELLOW# 1 2 R223 10R2J-2-GP 2 ECE5021 BC bus DY CLK_PCI5025 SNIFFER_YELLOW# 36 BC_CLK 36 BC_DAT 36 BC_INT# BC_DAT C321 SC4D7P50V2CN-1GP MEC5025_XTAL1 MEC5025_XTAL2 DY 1 R497 FLCLK FLDATAIN FLDATAOUT 1 2 109 110 GPIO80 GPIO81 87 86 85 BC_CLK BC_DAT BC_INT# 2 SIO_XOSEL 10KR2J-3-GP 122 124 XTAL1 XTAL2 123 XOSEL Q45 2N7002-7F-GP HOST_DEBUG_TX +3.3V_ALW 1 3 DY SFPI_EN 1 SIO_EXT_SCI# 20 PS_ID 39 SIO_RCIN# 20 BEEP 29 TP159 Flash Recovery. 1=Enabled 0=Disabled +3.3V_ALW CAPS_LED# 37 SCRLK_LED# 37 NUM_LED# 37 SIO_SPI_CS# 19 Low= Write Protected. LOM_SMB_ALERT# 27 DOCK_SMB_ALERT# 38 52 FWP# 0.9V_DDR_VTT_ON 44,51 11 115 114 Flash Write Protect bottom 4K of internal bootblock flash. SIO_EXT_SMI# 20 BAT2_LED# 17 BAT1_LED# 17 GPIOA3/WINDMON 73 EXP_CARD_SB_WAKE# GPIO83/32KHZ_OUT 117 PWRGD RUNPWROK nRESET_OUT/OUT6 53 RESET_OUT# 48,51 TEST_PIN 72 C296 OE# 2 A VCC MEC_TEST_PIN R640 10KR2J-3-GP TP162 R642 10KR2J-3-GP 8051_RX 8051_TX DEBUG_ENABLE# 1 2 L28 BLM18AG121SN-1GP B C DY R641 1MR2J-1-GP DBG2 7 8051DBG 2 0R2J-2-GP 1 R643 5 4 3 2 DY 1 Not Stuff R921 0 ohm when doing Flash recovery. 6 MLX-CON5-10-GP Debug Serial Port Flash Recovery port. 1 2 L29 BLM18AG121SN-1GP +5V_RUN 1 Wistron Corporation DBG1 5 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 4 1 HOST_DEBUG_RX HOST_DEBUG_TX_C 2 3 5 1 2 R637 100KR2J-1-GP DY Title KBC MEC5025 MLX-CON3-9-GP Size A3 Document Number Rev D SC Parker Date: Wednesday, March 21, 2007 A 2 42,48,51 R583 1KR2J-1-GP SCD1U10V2KX-4GP EC_VSS_PLL R590 100KR2J-1-GP +3.3V_ALW X01 EC_32KHZ 36 +3.3V_ALW R586 100KR2J-1-GP EXP_CARD_SB_WAKE# 20 49 MEC5025-NU-GP R520 10KR2J-3-GP HOST_DEBUG_TX 32 HOST_DEBUG_RX 32 FWP# EC_VCC_PLL R523 10KR2J-3-GP 2 1 1 2 +3.3V_SUS 4 3 DY IMVP_VR_ON 42,51 WLAN_3V_ENABLE 32 3.3V_SUS_ON 46,47,51 BREATH_LED# 17 84 1 4 3 2 SFPI_EN DOCK_SMB_ALERT# 4 3 1 1 2 3 4 3 SB_EC_SPI_DO 1 SB_EC_SPI_DIN 2 RN50 SRN10KJ-5-GP IMVP_PWRGD 42,48,51 TP30 FAN1_TACH 23 IMVP_VR_ON WLAN_3V_ENABLE 4 47KR2J-2-GP 4 3 2 CAPS_LED# SCRLK_LED# NUM_LED# SIO_SPI_CS# 3 GND Y 4 U52 74AHCT1G125GW-1-GP Q47 MMBT3904-7-F-GP 2 DY 2 1 91 90 89 4 S 3 1 DY 1 2 SGPIO40 SGPIO41 SGPIO42 SGPIO43 2 121 21 44 65 83 116 HOST_DEBUG_TX HOST_DEBUG_RX 2 1 CPU_PROCHOT#_1 G 5 CPU_PROCHOT# 70 71 nFWP C566 SC4D7U6D3V3KX-GP To KBC 5025 D DY SYSOPT0/SGPIO32/LPC_TX SYSOPT1/SGPIO33/LPC_RX OUT7/nSMI nPWR_LED nBAT_LED EC_CPU_PROCHOT# R437 10KR2J-3-GP 1 1.25V_GFX_PCIE_ON DEBUG_ENABLE# GPIO96/TOUT1 103 106 108 1 2 EC_AGND L62 BLM18AG121SN-1GP DY 66 55 54 69 68 67 HSTCLK HSTDATAIN HSTDATAOUT 125 2 R416 10KR2J-3-GP nEC_SCI/SPDIN2 SGPIO45/MSDATA/SPDOUT2 SGPIO44/MSCLK/SPCLK2 SGPIO46/SPDIN1 SGPIO47/SPDOUT1 SGPIO31/TIN1/SPCLK1 SGPIO35 SGPIO36 (SFPI_EN) SGPIO37 +3.3V_ALW +5V_ALW 48 47 46 45 10KR2J-3-GP 1 SB_EC_SPI_DIN SB_EC_SPI_DO OUT2/PWM3 OUT9/PWM2 OUT11/PWM1 OUT10/PWM0 2 2 19 SB_EC_SPI_CLK 19 SB_EC_SPI_DIN 19 SB_EC_SPI_DO 102 105 107 FAN2_TACH 2 1 C200 SC15P50V2JN-4GP 43 42 41 4 3 2 SC12P50V2JN-3GP MEC5025_XTAL1 LRESET# PCICLK LFRAME# LAD0 LAD1 LAD2 LAD3 CLKRUN# SER_IRQ GPIO82/FAN_TACH3 GPIO16/FAN_TACH2 GPIO15/FAN_TACH1 LCD_SMBCLK 17 LCD_SMBDAT 17 DOCK_SMBCLK 38 DOCK_SMBDAT 38 1.8V_RUN_ON 47,51 LCDVCC_TST_EN 17 1.2V_SUS_ON 46,51 CPU_PWRGD 18 PBAT_SMBDAT 39 PBAT_SMBCLK 39 SBAT_DH_SMBDAT 38 SBAT_DH_SMBCLK 38 1.5V_RUN_ON 44,51 TP61 THRM_SMBDAT 23,34,40 THRM_SMBCLK 23,34,40 1 1 1 2 X1 X-32D768KHZ-43GP C173 57 58 59 60 61 62 63 64 56 CLK_PCI_5025 LCD_SMBCLK LCD_SMBDAT DOCK_SMBCLK DOCK_SMBDAT 1.8V_RUN_ON LCDVCC_TST_EN 1.2V_SUS_ON CPU_PWRGD PBAT_SMBDAT PBAT_SMBCLK SBAT_DH_SMBDAT SBAT_DH_SMBCLK 1.5V_RUN_ON 1.25V_RUN_ON THRM_SMBDAT THRM_SMBCLK SNIFFER_RTC_GPO 1 MEC5025_XTAL2 2 0R2J-2-GP 2 2 1 MEC5025_X2 1 R138 7,18,27,31,32,45,46,51 PLTRST# 18 CLK_PCI_5025 18,27 LPC_FRAME# 18,27 LPC_LAD0 18,27 LPC_LAD1 18,27 LPC_LAD2 18,27 LPC_LAD3 18,25 CLKRUN# 18,25,27 IRQ_SERIRQ 8 7 6 5 93 94 95 96 111 112 9 10 97 98 99 100 31 MAIN_PWR_SW# 17,51 ACAV_IN 23,40,41 TP116 2 2 GPIO94/IMCLK GPIO95/IMDAT KCLK KDAT GPIOA6/EMCLK GPIOA7/EMDAT GPIO20/PS2CLK/8051RX GPIO21/PS2DAT/8051TX AB1B_CLK/GPIOA4 AB1B_DATA/GPIOA2 AB1A_CLK AB1A_DATA GPIO11/AB2_DATA GPIO12/AB2_CLK GPIO13/AB1G_DATA GPIO14/AB1G_CLK GPIO87/AB1C_DATA GPIO86/AB1C_CLK GPIO85/AB1D_DATA GPIO84/AB1D_CLK GPIO93/AB1F_DATA GPIO92/AB1F_CLK GPIO91/AB1E_DATA GPIO90/AB1E_CLK ALWON 43,51 SNIFFER_PWR_SW# POWER_SW_IN1# 2 2 CLK_KBD DAT_KBD CLK_DOCK DAT_DOCK 8051_RX 8051_TX 75 76 77 78 79 80 81 82 +3.3V_ALW DOCK_SMBCLK 1 DOCK_SMBDAT 2 RN62 SRN10KJ-5-GP DOCK_SMB_ALERT#1 R524 HOST_DEBUG_RX 1 R571 LCD_SMBCLK 1 LCD_SMBDAT 2 RN63 SRN8K2J-3-GP PBAT_SMBCLK 1 PBAT_SMBDAT 2 RN12 SRN8K2J-3-GP THRM_SMBCLK 1 THRM_SMBDAT 2 RN15 SRN4K7J-8-GP SBAT_DH_SMBCLK 1 SBAT_DH_SMBDAT 2 RN64 SRN10KJ-5-GP 1 2 DY DY TP SIO_SPI_CS# 10KR2J-3-GP BC_DAT 100KR2J-1-GP BC_A_DAT 100KR2J-1-GP AC_OFF 10KR2J-3-GP 2 37 CLK_TP_SIO 37 DAT_TP_SIO TP152 TP153 TP146 TP142 32 8051_RX 32 8051_TX C652 SCD1U10V2KX-4GP R749 10KR2J-3-GP 2 1 R525 1 R527 1 R163 1 R147 SGPIO34/A20M OUT5/KBRST ALWON 1 +3.3V_ALW 92 50 C250 SCD1U10V2KX-4GP 2 20 SIO_A20GATE 31 SNIFFER_BLUE# 3 SNIFFER_BLUE# BC_A_DAT 120 119 126 127 128 118 VCC_PLL ECE1077 KSI7/GPIO19 KSI6/GPIO17 KSI5/GPIO10 KSI4/GPIO9 KSI3/GPIO8 KSI2/GPIO7/BC_A_INT# KSI1/GPIO6/BC_A_DAT KSI0/SGPIO30/BC_A_CLK AUX_ON SUS_ON RUN_ON AC_OFF NB_VCORE_PWRGD_R ALWON POWER_ SW_IN2#/GPIO23 POWER_ SW_IN1#/GPIO22 POWER_ SW_IN0# ACAV_IN BGPO0/GPIOA5 104 46,48,51 NB_VCORE_PWRGD 1 DAT_DOCK 2 CLK_DOCK RN68 SRN4K7J-8-GP 33 34 35 36 37 38 39 40 3.3V_RUN_ON 27 AUX_ON 47,48,51 SUS_ON 17,47,48,51 RUN_ON 39 AC_OFF 1 2 R156 0R2J-2-GP 37 BC_A_INT# 37 BC_A_DAT BC bus 37 BC_A_CLK X01 VSS_PLL +5V_RUN SB_RSMRST# M_ON 1.2V_ALW_SUS_ON DDR_ON VR_CAP 2 Note: MEC5025 KSO3/GPIOC3 pin 29 was 3V_5V_SUS_PWRGD, M08 platforms already had 3V_5V_SUS_PWRGD from the discrete component. 4 3 DY 7,48,51 NB_PWRGD TP115 20,23,48,51 SUSPWROK 20,51 SB_RSMRST# TP19 TP114 44,45,51 DDR_ON 37 TP_CABLE_DET# 43,51 ALW_PWRGD_3V_5V 20,51 SIO_SLP_S3# 20,51 SIO_SLP_S5# 47,51 3.3V_RUN_ON EC_CPU_PROCHOT# 2 NB_PWRGD_R 0R2J-2-GP ICH_CL_PWROK C255 SCD1U10V2KX-4GP +RTC_CELL 101 1 R508 VR_CAP 45,51 1.8V_SUS_PWRGD 22 TP121 DY 1 DAT_KBD 2 CLK_KBD RN72 SRN4K7J-8-GP ATI_Intel 3.3V_M_PWRGD 1 R506 100KR2J-1-GP KSO17/GPIOA1/AB1H_DATA KSO16/GPIOA0/AB1H_CLK GPIO5/KSO15 GPIO4/KSO14 KSO13/GPIO18 KSO12/OUT8 KSO11/GPIOC7 KSO10/GPIOC6 KSO9/GPIOC5 KSO8/GPIOC4 KSO7/GPIO3 KSO6/GPIO2 KSO5/GPIO1 KSO4/GPIO0 KSO3/GPIOC3 KSO2/GPIOC2 KSO1/GPIOC1 KSO0/GPIOC0 VSS VSS VSS VSS VSS LCDVCC_TST_EN 100KR2J-1-GP 12 13 14 15 16 17 18 19 20 23 24 25 27 28 29 30 31 32 AGND 2 4 CKG_SMBDAT 4 CKG_SMBCLK 26 51 74 88 113 3.3V_SUS_ON DDR_ON C314 SCD1U10V2KX-4GP VCC1 VCC1 VCC1 VCC1 VCC1 1 R507 100KR2J-1-GP 4 3 X01 VCC0 +3.3V_ALW 1 SCD1U10V2KX-4GP ATI versus Intel chipset to allow Place cap close to pin 121. power sequence differences. U30 ATI is Logic High. Intel is Logic Low. 2 DY 4 3 SC10U10V5KX-2GP C619 C567 SUS_ON RUN_ON 4 3 E Place these caps close to MEC5025. EC_VCC0 1 2 R505 0R2J-2-GP 2 SSID = KBC 1 AUX_ON 1.2V_SUS_ON D +3.3V_ALW 1 4 3 C +RTC_CELL 2 1.8V_RUN_ON 3.3V_RUN_ON 1 4 B 4 3 2 A 1 2 RN78 SRN2K2J-1-GP 1 2 RN61 SRN2K2J-1-GP 1 2 RN54 SRN2K2J-1-GP 1 2 RN65 SRN2K2J-1-GP 1 R521 Sheet E 35 of 53 A 1 2 C388 SCD1U10V2KX-4GP 1 C365 SCD1U10V2KX-4GP 2 1 C389 SCD1U10V2KX-4GP 2 1 2 C343 SCD1U10V2KX-4GP 1 2 1 C356 SCD1U10V2KX-4GP E +3.3V_ALW Place cap close to PIN 42,43 R270 10KR2J-3-GP +3.3V_ALW +3.3V_ALW 1 2 3 4 5 10 9 8 7 6 RP2 SRN100KJ-7-GP KB_LED_DET# PS_CABLE_DET# PEN_CABLE_DET# BATT_SLICE_DET# 4 34 57 85 108 U64 EC_32KHZ 24 25 26 27 58 59 60 GPIOH0 GPIOH1 GPIOH4 GPIOH5 BC_INT# BD_DAT BC_CLK 1 2 3 4 5 84 83 6 GPIOE0 GPIOE1 GPIOE2 GPIOE3 GPIOE4 GPIOE5 GPIOE6 GPIOE7 DOCKED DOCK_SMB_PME NB_MUTE# 1.2V_RUN_ON SPDIF_SHDN DOCK_HP_MUTE# HP_NB_SENSE PWRUSB_EN 65 66 67 68 69 70 71 73 74 75 76 77 78 79 80 81 82 GPIOB0 GPIOB1 GPIOC2 GPIOC3 GPIOC4 GPIOC5 GPIOC6 GPIOC7 GPIOD0 GPIOC1 GPIOC0 GPIOB7 GPIOB6 GPIOB5 GPIOB4 GPIOB3 GPIOB2 1.05V_RUN_ON 61 62 GPIOD1/CIRTX GPIOD2/CIRRX GFX_CORE_ON MODPRES# DBAY_MODPRES# HDDC_EN MODC_EN# 63 28 29 30 31 GPIOD3 GPIOD4 GPIOD5 GPIOD6 GPIOD7 IMVP6_PROCHOT# 5V_3V_1.8V_1.2V_RUN_PWRGD 32 33 GPIOH6 GPIOH7 88 89 90 91 92 93 94 95 GPIOG0 GPIOG1 GPIOG2 GPIOG3 GPIOG4 GPIOG5 GPIOG6 GPIOG7 106 107 GPIOH2 GPIOH3 VGA_IDENTIFY CHIPSET_ID1 109 110 111 112 GPIOF7 GPIOF6 GPIOF5 GPIOF4 IRTX CIRRX 113 114 CIRTX CIRRX 115 116 117 118 GPIOF3 GPIOF2 GPIOF1 GPIOF0 31 WIRELESS_ON/OFF# 31 BT_RADIO_DIS# 31 EXPRCRD_PWREN# 31 EXPRCRD_STDBY# 35 BC_INT# 35 BC_DAT 35 BC_CLK This resistor strapping will not change and is used to identify parker chipset as ATI 45 1.8V_EN# 3 33 PEN_DET# 33 PEN_LED# TP75 1 TP82 1 TP184 1 29,30 AUD_MIC_SWITCH 37 TABLET_DET# +3.3V_ALW X01 MEM_VEND_ID 1.8V_EN# AUD_SUB_SHDN_ON_BATT PEN_DET# PEN_LED# CAM_IMG_CAPTURE TABLET_DET# 1 34 USB_SIDE_EN# 34 PWRUSB_OC 2 R744 10KR2J-3-GP MEM_VEND_ID PANEL_BKEN 16,38 DOCKED 38 DOCK_SMB_PME 30 NB_MUTE# 47,51 1.2V_RUN_ON 29 SPDIF_SHDN 29 DOCK_HP_MUTE# 29,30 HP_NB_SENSE 34 PWRUSB_EN 1 2 R321 100KR2J-1-GP DY 2 DYR743 10KR2J-3-GP MEM_VEND_ID support H : Hynix L : Mircon 1 38 DOCK_PWR_EN 40 ADAPT_OC 40 ADAPT_TRIP_SET 3,4,5,20 ITP_DBRESET# 39 PSID_DISABLE# 1 10 PANEL_BKEN TP93 37 LID_CL_SIO# 45,51 1.05V_RUN_ON TP95 TP91 34 DBAY_MODPRES# 33 HDDC_EN TP92 42 IMVP6_PROCHOT# 48,51 5V_3V_1.8V_1.2V_RUN_PWRGD 1 1 1 USB_SIDE_EN# PWRUSB_OC QBUFEN# DOCK_PWR_EN ADAPT_OC ADAPT_TRIP_SET ITP_DBRESET# PSID_DISABLE# 1 2 R298 10KR2J-3-GP 27 LOM_LOW_PWR TP85 1 31,33 LED_MASK# 20 SIO_EXT_WAKE# 20 SB_PME# 20 SB_PCIE_WAKE# 32 WLAN_RADIO_DIS# 2 TP84 0R2J-2-GP 1 R288 1 LOM_LOW_PWR SC_DET# LED_MASK# GFX_DEVID2 SIO_EXT_WAK# 32 WWAN_RADIO_DIS# 27 LOM_CABLE_DETECT 27 LOM_TPM_EN# 27 LOM_SUPER_IDDQ VGA_IDENTIFY Low=UMA, High=Discrete 1105 1 R276 2 10KR2J-3-GP TP183 1 2 R273 10KR2J-3-GP 23 ATF_INT# 1 BID1 BID0 DYR282 10R2J-2-GP VCC1 GPIOJ7 GPIOK4 8 14 20 PEN_CABLE_DET# SNIFFER_DET# GPIOI1 119 PEN_SW# PEN_CABLE_DET# 33 SNIFFER_DET# 31 PEN_SW# 2 GPIOA0 GPIOA1 GPIOA2 GPIOA3 GPIOA4 GPIOA5 GPIOA6 GPIOA7 SBAT_PRES# CHG_PBATT CHG_SBATT PBAT_DSCHG SYS_PME# PCIE_WAKE# USB_BACK_EN# X01 CLK_PCI5021 33 1 97 98 99 100 101 102 103 104 39 PBAT_PRES# 38,41 SBAT_PRES# 41 CHG_PBATT 41 CHG_SBATT 41 PBAT_DSCHG 25 SYS_PME# 27,31,32 PCIE_WAKE# 34 USB_BACK_EN# 1 VCC1 VCC1 VCC1 VCC1 X01 CHIPSET_ID1 1 USB_SIDE_EN# H2_CABLE_DET# IO_CABLE_DET# LCD_CBL_DET# GPIOJ2 GPIOJ3 GPIOJ6 GPIOJ5 GPIOK0 GPIOK1 GPIOK3 GPIOK2 GPIOK5 GPIOK6 9 10 13 12 15 16 19 18 21 22 GPIOI6 GPIOI5 GPIOI2 CAP_LDO GPIOJ0 125 124 120 86 127 TEST_PIN 35 GPIOI7 126 GPIOI4 GPIOI3 123 122 VSS VSS VSS VSS VCC1 VSS VSS VSS NC#46 VSS VSS 54 52 49 47 42 41 56 37 46 44 39 VSS 64 KHZ_32 96 VSS VSS VSS VSS VCC1 VSS VSS VSS 55 53 50 48 43 38 45 40 PWRGD OUT65 GPIOJ4 VSS GPIOK7 VSS VSS VSS VSS VSS GPIOJ1 FAN1DET# 1 FAN2_DET# R300 PS_CABLE_DET# KB_LED_DET# BATT_SLICE_DET# LCD_CBL_DET# H2_CABLE_DET# IO_CABLE_DET# CCD_VDD_ON 2 0R2J-2-GP 1 TP86 1 TP88 1 1 TP89 TP90 DYC352 SC4D7P50V2CN-1GP FAN1_DET# 23 2 2 Place cap close to PIN 34,57,85,108,8 BID1 BID0 Board Rev. 0 0 ENG1(X00) 0 1 ENG1(X01) 1 0 ENG1(X02) 1 ENG1(X03) 1 2 D SSID = SIO DY 2 2 DY R272 10KR2J-3-GP 2 R275 10KR2J-3-GP BID0 BID1 CHIPSET_ID1 1 2 1 2 1 4 R269 10KR2J-3-GP C387 SCD1U10V2KX-4GP 1 R271 DY10KR2J-3-GP 2 R274 10KR2J-3-GP C +3.3V_ALW 1 1 Board ID Straps B +3.3V_ALW PS_CABLE_DET# 37 BATT_SLICE_DET# 38 LCD_CBL_DET# 17 H2_CABLE_DET# 37 +3.3V_ALW TABLET_DET# R290 DOCK_SMB_PME SIO_CAP_LDO 1 2 C361 SC4D7U6D3V3KX-GP RSV_TEST_PIN 2 1 2 R314 DBAY_MODPRES# 1 PWRUSB_OC R316 1 SYS_PME# R325 1 PCIE_WAKE# R268 1 R267 1.8V_EN# 1 LED_MASK# R280 1 R293 SNIFFER_DET# 1 PEN_DET# R661 1 FAN1_DET# R287 1 USB_BACK_EN# R299 1 R266 PEN_LED# 1 R27 TP96 1 1 3 100KR2J-1-GP 10KR2J-3-GP 2 2 10KR2J-3-GP 2 10KR2J-3-GP 2 10KR2J-3-GP 10KR2J-3-GP 2 2 10KR2J-3-GP 10KR2J-3-GP 2 2 100KR2J-1-GP 2 100KR2J-1-GP 2 100KR2J-1-GP 100KR2J-1-GP 2 100KR2J-1-GP +3.3V_RUN IMVP6_PROCHOT# 1.05V_RUN_ON 1.2V_RUN_ON CHG_PBATT EC_CLK32K 1 R281 0R2J-2-GP 2 CHG_SBATT LCD_TST EC_32KHZ 35 PWRUSB_EN DOCK_PWR_EN 1 R327 100KR2J-1-GP 1 R328 100KR2J-1-GP 1 2 RN48 SRN100KJ-6-GP 1 2 RN21 SRN100KJ-6-GP 1 2 RN49 SRN100KJ-6-GP 2 2 2 4 3 4 3 4 3 X01 7 105 LCD_TST 11 17 23 36 51 72 87 121 128 KB_LED LCD_TST 17 TP87 1 SIO_GPIOK7 1 R320 0R2J-2-GP 2 Parker 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title SIO ECE5021 ECE5021-NU-GP Size A3 Document Number Rev A B C D SC Parker Date: Wednesday, March 21, 2007 Sheet E 36 of 53 A B K/B CONN. C D SSID = User.interface 37 38 1 NC#37 NC#38 34 BC_DATA 35 BC_A_CLK 35 BC_CLK 35 BC_A_INT# 36 BC_INT# 35 BC_A_DAT 2 R638 0R2J-2-GP 1 ECE1077_TP 40 TEST_PIN 41 GND_PAD KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 R295 10KR2J-3-GP KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 35 CAPS_LED# +3.3V_ALW C359 KSO18 3 4 RN84 SRN10KJ-5-GP KSO18 17 KYBD_DET# INVERTER_CBL_DET# KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 1 2 3 4 5 6 7 8 1 CAPS_LED# 4 1 U62 2N7002DW-7F-GP CAPS_LED_1# 1 R304 2 SC100P50V2JN-3GP 2 CAPS_LED_1#_1 220R2J-L2-GP 1 6 2 5 3 4 SCRLK_LED_1 +5V_ALW 1 2 4 3 SRN100KJ-6-GP U60 2N7002DW-7F-GP 17 17 17 17 17 17 17 17 SCRLK_LED_#1 1 R302 C362 ECE1077-FZG-GP 3 5 3 Q62 2N7002-7F-GP KYBD_DET_1 1 G R682 RN23 INVERTER_CBL_DET# 17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 2 X01 CAPS_LED_1 2 1 SCRLK_LED# 35 SCRLK_LED# 6 D NC#39 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 32 33 S 39 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16/GPIO_0 KSO17/GPIO_1 KSO18/GPIO_2 KSO19/GPIO_3 KSO20/GPIO_4 KSO21/GPIO_5 KSO22/GPIO_6 1 VCC1 VCC1 R677 100KR2J-1-GP R283 100KR2J-1-GP KYBD_DET# 2 2 2 30 10 1 C353 SCD1U10V2KX-4GP 1 2 U59 C341 SCD1U10V2KX-4GP 2 1 4 KB LEDs +3.3V_ALW +5V_ALW +3.3V_ALW +3.3V_ALW E NUM_LED# 35 NUM_LED# 1 2 2 SCRLK_LED_#1_1 220R2J-L2-GP SC100P50V2JN-3GP 1 6 2 5 +5V_ALW 3 HRS-CON30-1-GP-U 1 NUM_LED_1# 1 R303 2 SC100P50V2JN-3GP 20.K0259.030 NUM_LED_1#_1 2 220R2J-L2-GP KSI3 EC10 SRC100P50V-2-GP KSO10 KSO11 KSO9 KSO14 8 7 6 5 DY EC15 SRC100P50V-2-GP KSO13 KSO15 KSO16 KSO12 8 7 6 5 1 2 3 4 DY EC14 SRC100P50V-2-GP KSO0 KSO2 KSO1 KSO3 8 7 6 5 1 2 3 4 DY EC13 SRC100P50V-2-GP KSO8 KSO6 KSO7 KSO4 8 7 6 5 DY 1 2 EC11 SC100P50V2JN-3GP PS_CABLE_DET# 4 3 SP_X SP_Y SP_V+ SP_GND 1 TP_SMBD HRS-CON6-3-GP LID_CL_SIO#_R C310 SCD1U10V2KX-4GP 1 SUPPLY 2 OUTPUT A3212ELHLT-T-GP X01 HSW1 TP CONN. 2 1 TP_SMBD TP_SMBC SP_X SP_Y SP_V+ SP_GND C729 SC1U10V2KX-1GP 1 2 1 TP AND POWER 2 3 4 5 6 7 8 9 10 12 36 TABLET_DET# C172 SCD1U10V2KX-4GP MEC5025 CONNECT 2 1 36 LID_CL_SIO# LID_CL_SIO#_R SP_X SP_Y SP_V+ SP_GND 1 TABLET_DET# 2 3 4 5 6 X01 8 MLX-CON6-13-GP 20.K0270.006 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 8 7 6 5 20.K0278.010 Title ECE1077 Size Document Number Custom Rev B C D SC Parker Date: Wednesday, March 21, 2007 A 1 Wistron Corporation 1 2 3 4 EC24 SRC100P50V-2-GP 2 C699 SCD047U10V2KX-2GP 1 R660 10R2J-2-GP 7 H2_CABLE_DET# 2 R659 1MR2J-1-GP C727 SCD1U10V2KX-4GP +3.3V_ALW 1 TP94 MLX-CON10-12-GP 11 1 35 TP_CABLE_DET# +5V_RUN 1 +3.3V_ALW 36 H2_CABLE_DET# 2 1 C709 SC10P50V2JN-4GP 3 GND 20.K0267.006 2 1 L64 BLM18AG601SN-3GP 2 C732 SC10P50V2JN-4GP TP_SMBC 2 8 7 6 5 U40 X01 1 35 CLK_TP_SIO DY EC8 SRC100P50V-2-GP +3.3V_ALW 8 C710 SC10P50V2JN-4GP 1 2 3 4 2 1 2 3 4 5 6 2 1 2 L65 BLM18AG601SN-3GP 2 C733 SC10P50V2JN-4GP 1 35 DAT_TP_SIO KSO5 KSI0 KSI1 KSI5 8 7 6 5 hall switch 1 36 PS_CABLE_DET# DY PSTICK1 7 2 1 2 SSID = TOUCH.PAD RN96 SRN4K7J-8-GP 1 2 3 4 EC12 SRC100P50V-2-GP POINT-STICK CONN. +5V_RUN 2 1 2 3 4 3 4 Layout swap DY 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NUM_LED_1 U61 2N7002DW-7F-GP C358 1 2 3 4 31 1 32 PLACE HOLDER KSI2 KSI4 KSI6 KSI7 4 KB1 2KYBD_DET_2 10KR2J-3-GP KSO10 KSO11 KSO9 KSO14 KSO13 KSO15 KSO16 KSO12 KSO0 KSO2 KSO1 KSO3 KSO8 KSO6 KSO7 KSO4 KSO5 KSI0 KSI3 KSI1 KSI5 KSI2 KSI4 KSI6 KSI7 CAPS_LED_1#_1 NUM_LED_1#_1 SCRLK_LED_#1_1 Sheet E 37 of 53 A B C D E SLICE1 105 108 SSID = MEDIA SLICE 107 NP1 27 DOCK_LOM_TRD027 DOCK_LOM_TRD0+ 4 27 DOCK_LOM_TRD127 DOCK_LOM_TRD1+ 27 DOCK_LOM_TRD227 DOCK_LOM_TRD2+ 27 DOCK_LOM_TRD327 DOCK_LOM_TRD3+ +3.3V_LAN +2.5V_LOM 27 DOCK_LOM_SPD10LED_GRN# 27 DOCK_LOM_SPD100LED_ORG# 27 DOCK_LOM_ACTLED_YEL# PS_ID_IN 39 PS_ID_IN 35 DOCK_SMBCLK 35 DOCK_SMBDAT 3 X01 10 NB_TMDS_HPD +3.3V_ALW 8 SDVO_INT+ 14 U85B 8 SDVO_INT- 4 6 8 SDVO_G+ 5 SDVO SIGNAL 7 SSLVC08APWR-GP 8 SDVO_G8 SDVO_B+ SDVO_INT+ SDVO_INTSDVO_G+ SDVO_GSDVO_B+ SDVO_B- 8 SDVO_B- USE TO BATT_SLICE_DET# GND USE TO BATT_SLICE GND ON/OFF CHARGER (battery slice side SYS_PRES#) +DOCK_PWR_SRC 103 1 51 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 102 104 +SBATT AUD_SPDIF_OUT BATT_SLICE_DET# 29 BATT_SLICE_DET# 36 NB_RED 4 NB_RED 10,16 NB_GREEN NB_GREEN 10,16 NB_BLUE NB_BLUE 10,16 D_DDC_DATA D_DDC_CLK D_DDC_DATA 16 D_DDC_CLK 16 D_HSYNC D_VSYNC +3.3V_ALW D_HSYNC 16 D_VSYNC 16 2 The green frame are used to battery_slice R14 10KR2J-3-GP SB600_USBP8+ 20 SB600_USBP8- 20 1 101 +SBATT SBAT_PRES# 36,41 DOCK_SMB_PME 36 DOCK_SMB_ALERT# 35 TPA1P 25 TPA1N 25 1394 TPB1P 25 TPB1N 25 Reserved for battery slice 3 SBAT_DH_SMBCLK 35 SBAT_DH_SMBDAT 35 SDVO_CTRLCLK SDVO_CTRLDATA SDVO_CTRLCLK 10 SDVO_CTRLDATA 10 SDVO_R- SDVO_R- 8 SDVO_R+ SDVO_R+ 8 SDVO SIGNAL SDVO_CLK- SDVO_CLK- 8 SDVO_CLK+ SDVO_CLK+ 8 DOCK_DET# DOCK_DET# 16 +DC_IN NP2 109 110 106 JAE-CONN100-1-GP-U3 2 2 20.F0968.100 2 2 8 7 6 5 +DOCK_PWR_SRC 2 D D D D EC1 SC1KP3KV8KX-GP FDS4435-1-GP X01 1 +3.3V_ALW DOCK_PWR_EN_5 1 1 2 +5V_ALW R125 100KR2J-1-GP 1 C118 SCD1U50V3KX-GP U24 S S S G 1 1 2 3 4 +PWR_SRC R112 100KR2J-1-GP R432 100KR2J-1-GP +3.3V_ALW DOCKED 16,36 X01 +3.3V_ALW 9 8 14 11 13 LOM_E_SWITCH 27 SSLVC08APWR-GP Q20 2N7002-7F-GP 1 DOCK_PWR_EN_1 G Wistron Corporation S 2 10 U85C SSLVC08APWR-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. R448 100KR2J-1-GP Title 1 7 36 DOCK_PWR_EN U85D 12 D 1 2 C474 SCD1U10V2KX-4GP 1 DOCKED 7 DOCKED 14 2 R1 IN 1 GND R2 Q46 DDTC144EUA-7F-GP 2 2 DOCK_DET# 3 OUT DOCK_PWR_EN_4 1 R414 100KR2J-1-GP MEDIA SLICE R451 1 DY 2 Size A3 0R2J-2-GP Document Number Rev A B C D SC Parker Date: Wednesday, March 21, 2007 Sheet E 38 of 53 A B C D E SSID = PWR.Support DY 1 +5V_ALW C4 SCD01U50V2KX-1GP 3 2 1 R371 2K2R2F-GP 2 G D19 BAV99-4-GP Q40 FDV301N-NL-GP 4 +DC_IN 1 2 PSID_DISABLE# 36 R365 100KR2J-1-GP 1 Reserved for EMI +3.3V_ALW 2 3 2 1 3 1 Q39 MMBT3904-7-F-GP 2 4 PSID_DISABLE#_1 D18 BAV99-4-GP R359 10KR2J-3-GP 1 R360 15KR2J-1-GP 1 2 2 +5V_ALW 1 DY 0R3-0-U-GP B E DY C Q38 PDTA124EU-1-GP 1 IN 35 AC_OFF R1 DY 3 OUT AC_OFF_2 1 R357 47KR3J-L-GP 1 +3.3V_ALW 1 D31 BAV99-4-GP 1 C771 SC2200P50V2KX-2GP 1 2 PBAT_SMBDAT 3 2 C770 SCD1U50V3KX-GP 2 1 D32 BAV99-4-GP 1 +PBATT 2 PBAT_SMBCLK 3 Now use 0 ohm 06003 ,wait VZ0603M260APT part 1 R733 1 R734 3 AC_OFF_1 2 35 PBAT_SMBDAT 35 PBAT_SMBCLK R5 4K7R5F-GP 2 GND This cap should be used only as last resort for EMI suppression. Batt Connecter C18 SC10U25V6KX-1GP 2 R2 Q41 DDTC124EUA-7F-GP 2 1 C8 SCD1U50V3KX-GP 2 C7 SCD1U50V3KX-GP 1 1 C6 SCD01U50V2KX-1GP 2 SI4835BDY-T1-GP 2 8 7 6 5 1 1 D D D D RV1 DY 1 RV2 0R3-0-U-GP R351 240KR3-GP U5 S S S G 2 1 2 L2 BLM41PG600-GP +DC_IN_SS 1 2 3 4 2 +DC_IN_GND SKT-JACK-190-GP 22.10140.321 DY 1 GND L1 BLM41PG600-GP C432 SCD1U50V3KX-GP C5 SCD47U25V3KX-1GP ID PIN 3,6,7,9 2 2 PIN 5 PS_ID 35 33R2J-2-GP +DC_IN 1 7 9 8 2 2 33R2J-2-GP 2 DC_IN- Place near DCIN1 1 R370 2 PIN 4,8 5 2 DY +DC_IN_L 2 3 DC_IN+ 1 1 DC_IN CONN PIN 1,2 1 PS_ID_1 S 2 1 2 4 6 3 R366 JACK_PSID Adapter In L43 BLM18BD102SN1D-GP 1 2 DCIN1 D R1 D20 B240A-13-GP D PS_ID_IN_1 2 R2 1 R367 0R2J-2-GP 38 PS_ID_IN PBAT_ALARM# 3 2 D29 BAV99-4-GP BATT1 2 9 1 8 PBAT_SMBDAT1 6 2 2 100R2F-L1-GP-U PBAT_SMBCLK1 7 100R2F-L1-GP-U BATT1BATT1+ BATT2BATT2+ BATT_ALERT BATT_PRES# SYS_PRES# 3 5 4 PBAT_ALARM1# PBAT_PRES1# 1 R735 1 R732 DY PBAT_ALARM# 2 2 100R2F-L1-GP-U 100R2F-L1-GP-U 1 R731 TP195 2 10KR2J-3-GP 1 PBAT_PRES# 36 +3.3V_ALW SMB_DATA SMB_CLK GND GND PBAT_PRES# 3 2 10 11 D30 BAV99-4-GP SYN-CON9-4-GP-U 1 1 20.80864.009 9 pin 20.80880.007 7 pin Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title DCIN / BATT CONN. Size A3 Document Number Rev A B C D SC Parker Date: Wednesday, March 21, 2007 Sheet E 39 of 53 D E Adapter Trip Current R1620 R1621 R1622 R1623 (W) (A) 65 3.17 57.6K 13.0K 105 24.9K 90 4.43 51.1K 17.8K 348 33.2K *R23 is populated if ADAPT_TRIP_SEL is used to program for the next lower adapter. SSID = CHARGER 1 2 1 G45 GAP-CLOSE-PWR 2 1 G44 GAP-CLOSE-PWR 2 G43 GAP-CLOSE-PWR 2 1 2 K A D14 1SS355PT-GP 2 DY 2 ISL88731_LX1 2 L66 IND-5D6UH-35-GP 8 7 6 5 ISL88731_DLO 1 NC#16 16 VFB 15 ISL88731HRZ-T-GP 4 3 2 1 1 2 R720 C405 SCD22U50V3ZY-1GP 2 +VCHGR +VCHGR_R 1 R338 0R2J-2-GP 2 2 DY R741 1K8R6J-GP X01 +3.3V_ALW 2 1MR2F-GP 1 1 2 G91 GAP-CLOSE-PWR 1 R730 +5V_ALW CHG_AGND 2 1 1 D G R329 CHG_AGND 10KR2F-2-GP 2 U68A LM393ADR-1-GP 1 ADAPT_OC1 S 23,35,41 ACAV_IN 1 1 2 2 - ISL88731_LDO CHG_AGND CHG_AGND 2 ISL88731_ACOK 0R2J-2-GP R681 15K8R3F-GP 1 CHG_AGND Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Charger CHG_AGND Size Document Number Custom Rev B C D SC Parker Date: Wednesday, March 21, 2007 A 1 R330 2 1 ISL88731_REF1_E DY 8 2 4 + C767 SC100P50V2JN-3GP 2 R725 13KR2F-GP 2 1 1 1 R727 24K9R3F-GP C768 SCD01U16V2KX-3GP 2 1 36 ADAPT_TRIP_SET CHG_AGND 2 CHG_AGND LM393ADR-1-GP 3 R722 1KR2J-1-GP 1 - CHG_AGND ISL88731_REF1 Q36 2N7002-7F-GP R728 105R2F-GP 7 2 1 U68B 2 + 1 2ISL88731_IINP_R R723 8K45R2F-2-GP C406 SCD1U10V2KX-4GP ISL88731_IINP CHG_AGND ISL88731_REF 1 2 R729 57K6R3F-2-GP C408 SC100P50V2JN-3GP +5V_ALW ADAPT_OC 36 R724 100KR2J-1-GP 2 2 C399 SCD01U50V2KX-1GP 1 1 R726 100KR2J-1-GP C401 SC100P50V2JN-3GP 6 1 ISL88731_CSIP 1 10R2J-2-GP ISL88731_CSIN 2 0R2J-2-GP 1 R713 1 GND VCOMP NC#5 ICOMP VREF NC#7 GND CHG_AGND 5 3 ICM 2 DY 8 2 C394 SCD1U10V2KX-4GP 1 C404 SC1U10V2KX-1GP 2 1 DY 6 5 4 3 7 12 SI4810BDY-T1-GP 29 8 1 17 4 1 2 C400 SCD01U50V2KX-1GP 1 TABLE MAXIM & INTERSIL BOM DIFFERENCES REF DES MAXIM INTERSIL R1610 8.45K 1% DUMMY C1412 0.01uF 0.1uF C1404 0.1uF 10V DUMMY C1408 1uF 10V DUMMY R1602 365K 1% 215K 1% R1609 0 5% 10 5% R1601 0 5% 10 5% C1402 DUMMY 0.22uF C1388 DUMMY 0.22uF C1406 0.01uF DUMMY C1409 0.1uF 10V DUMMY C1399 220pF 50V DUMMY D36 RB751V-40 DUMMY C1398 3.3nF DUMMY R1607 1 1% 0 5% R1612 100 5% 0 5% R1759 0 5% 8.45K 1% R1611 10K 5% 2.2K 5% C1405 0.01uF 0.01uF C1407 0.01uF 0.01uF R1606 1K 5% DUMMY D35 ISS355 DUMMY CSON ISL88731_CSIN_R ISL88731_IINP ISL88731_CCV ISL88731_CCI ISL88731_CCS ISL88731_REF ISL88731_DAC 1 R332 2K2R2J-2-GP C398 SCD01U50V2KX-1GP 2 2 C396 SCD01U50V2KX-1GP 1 1 1ISL88731_CCV1 2 DY CHG_AGND CSOP ISL88731_CSIP_R 2 1 This Resistor must be 1% tolerance. C393 SCD1U10V2KX-4GP 2 DY 2 DY 19 18 S S S G R706 8K45R2F-2-GP 2 U67 PGND NC#14 2 1 2 R698 D01R2512F-4-GP D D D D 14 +5V_VCHGR C413 SCD1U50V3KX-GP C410 SC2200P50V2KX-2GP 2 1 +VCHGR1 C769 SC3300P50V3KX-1GP C757 SC10U25V6KX-1GP 2 1 DY C758 SC10U25V6KX-1GP 2 1 20 DY 1 2 C416 SCD1U50V3KX-GP 2 0R3-0-U-GP 2 SC220P50V2JN-3GP C759 SC10U25V6KX-1GP 2 1 LGATE SDA 1 R346 1 C418 2 ISL88731_LX 1 PHASE G92 GAP-CLOSE-PWR 2 1 ISL88731_DHI 23 G93 GAP-CLOSE-PWR 24 SCL DY +VCHGR MPL73-5R6 9A 2 UGATE 1 2 C409 SC1U25V3KX-GP C412 SC10U25V6KX-1GP 2 1 5 6 7 8 DY 1 ISL88731_BST 1 2ISL88731_BST1 2 1 ISL88731_LDO R345 D16 0R3-0-U-GP RB751V-40-1-GP 2 25 21 D D D D BOOT VDDP U70 SI4800BDY-T1 C411 SC10U25V6KX-1GP 2 1 ACOK 9 23,34,35 THRM_SMBDAT ISL88731_CSSN_R ISL88731_VCC G S S S 13 10 27 26 C414 SC1U10V2KX-1GP 4 3 2 1 VDDSMB CHG_AGND 23,34,35 THRM_SMBCLK CSSN VCC R344 33R3J-2-GP CHG_AGND 11 C764 SCD1U10V2KX-4GP ISL88731_ACOK ISL88731_CSSP_R 1 ACIN 28 2 2 CSSP 1 1 DCIN 2 22 CHRG_IN R342 1KR3F-GP 2 1 +5V_ALW 2 1 2 +5V_ALW R347 10R2J-2-GP 1 2 C417 SCD22U50V3ZY-1GP 1 CHG_AGND U66 NC#1 2 C407 SCD01U50V2KX-1GP 1 4 2 C415 SC1U25V3KX-GP ISL88731_DCIN 2 CHG_AGND X01 DY 2 ISL88731_ACIN R721 49K9R2F-L-GP DY 1 R348 0R2J-2-GP 1 R343 0R2J-2-GP C434 SC2200P50V2KX-2GP 2 G10 GAP-CLOSE-PWR 1ISL88731_CSSN 1 2 1ISL88731_CSSP 1 G9 GAP-CLOSE-PWR 1 2 R28 D01R2512F-4-GP C17 SCD1U25V2ZY-1GP +SDC_IN R341 215KR3F-1-GP 3 C +DC_IN_SS 1 NAME DIFFERENCES* MAXIM INTERSIL GND NC REF VREF CCS ICOMP CCI NC CCV VCOMP DAC NC IINP ICM VDD VDDSMB BATSEL NC FBSA VFB FBSB NC CSIN CSON CSIP CSOP DLO LGATE LDO VDDP LX PHASE DHI UGATE BST BOOT means no-connect 1 4 *PIN PIN 1 3 4 5 6 7 8 11 14 15 16 17 18 20 21 23 24 25 "NC" B C761 SCD1U50V3KX-GP A Sheet E 40 of 53 A B C D E SSID = PWR.Support +SDC_IN R409 ACAV_IN_1 G 4 1 2 ACAV_IN_2 1 2 R397 100KR2J-1-GP 4 D S 10KR2J-3-GP 1 +PWR_SRC 2 1 2 3 4 U12 SI4835BDY-T1-GP C46 SCD1U25V2ZY-1GP Q43 2N7002-7F-GP S S S G 1 8 D 7 D 6 D 5 D D discharge path 2 10KR2J-3-GP 2 1 R372 C45 SC2200P50V2KX-2GP +PWR_SRC +SDC_IN_PD Q48 2N7002-7F-GP ACAV_IN G S 23,35,40 ACAV_IN 1 2 D9 B340LA-13-F-GP-U 8 7 6 5 +SBATT 8 1 7 2 6 3 5 4 D D D D S S S G 1 2 3 4 U38 SI4835BDY-T1-GP +SDC_IN CHG_SBAT 1 2 36 CHG_SBATT G 2 Q29 RHU002N06-1-GP S CHG_SBAT_N D CHG_SBATT_N 2 10KR2J-3-GP 1 R231 1 2 R232 100KR2J-1-GP 3 S 1 2 C324 SCD1U50V3KX-GP G CHG_PBATT_N D 1 2 C325 SCD1U50V3KX-GP 2 10KR2J-3-GP D D D D 5 6 7 8 +VCHGR U48 SI4835BDY-T1-GP S S S G 1 R240 1 2 D8 B340LA-13-F-GP-U 1 2 R233 100KR2J-1-GP 4 3 2 1 +PBATT 4 3 2 1 CHG_PBAT S S S G CHG_PBAT_N U50 SI4835BDY-T1-GP 5 6 7 8 S S S G 1 2 3 4 D 8 D 7 D 6 D 5 8 D 7 D 6 D 5 D +PBATT_1 U37 SI4835BDY-T1-GP 1 +SBATT 1 1 2 3 4 U28 SI4835BDY-T1-GP +SDC_IN PSBAT_SEL7 1 R220 S S S G 2 47KR2F-GP PBAT_G 3 2 1 Q28 RHU002N06-1-GP D D D D 36 CHG_PBATT R224 33KR2F-GP D10 RB715F-1-GP U49 FDS4935-NL-GP 3 SBAT_G 1 3 +VCHGR R235 D7 RB715F-1-GP 1 2 470KR2J-2-GP 2 2 2 R155 33KR2F-GP R225 10KR2J-3-GP R238 2 2 1 470KR2J-2-GP 8 D +PBATT 2 CHG_PBAT_1 47KR2F-GP CHG_PBAT_2 100KR2J-1-GP 3 + 2 - 1 CHG_PBAT_3 G U51A LM393ADR-1-GP Q30 RHU002N06-1-GP R237 S 2 1 1 R234 1 R236 4 +3.3V_ALW 2 470KR2J-2-GP PSBAT_SEL2 PSBAT_SEL5 2 147KR2F-GP 1 R262 +SBATT 1 R263 2 +3.3V_ALW 32K4R3F-GP A B GND VCC 5 Y 4 U53 NC7SZ32M5X-GP PSBAT_SEL 6 + 7 D13 PSBAT_SEL4 - 3 2 PSBAT_SEL6 U51B LM393ADR-1-GP RB715F-1-GP 2 1 2 3 5 1 G Q31 RHU002N06-1-GP S 36 PBAT_DSCHG 36,38 SBAT_PRES# 2 10KR2J-3-GP 1 PSBAT_SEL3 R261 100KR2J-1-GP 4 2 R252 D +3.3V_ALW 1 C338 SCD1U50V3KX-GP 1 PSBAT_SEL1 1 In M07,use ECE5011 GPIOA4 8 42K2R2F-L-GP 2 R264 2 C339 SCD1U50V3KX-GP 1 1 1 +PBATT Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title BATTERY SELECT Size A2 Date: A B C D Document Number Rev SC Parker Wednesday, March 21, 2007 E Sheet 41 of 53 B C237 SC470P50V2KX-3GP 2 1 3207_CSCOMP C22 SC1500P50V3KX-GP 1 5 6 7 8 5 6 7 8 2 CPU_PHASE1_E 1 +CPU_PWR_SRC 2 1 +PWR_SRC 1 2 G1 GAP-CLOSE-PWR 1 0.45u_MPC1040LR45_27A for Merom and Yonah dual 0.88u_MPC1040LR88_17A for Yonah sinigle R160 12KR2F-L-GP 1 R161 1 2 G2 GAP-CLOSE-PWR 1 2 G3 GAP-CLOSE-PWR 1 2 G4 GAP-CLOSE-PWR 2 2K37R2F-GP C247 2 1 2 G5 GAP-CLOSE-PWR 2 1 2 G6 GAP-CLOSE-PWR 1 R175 ADP3207_AGND +CPU_PWR_SRC 280KR3F-2-GP 2 TC13 SE68U25VM-L1-GP 1 4 3 2 1 4 3 2 1 3207_CSSUM1 2 3207_CSSUM 2 2 1 TC14 SE68U25VM-L1-GP 2 1 2 C435 SC10U25V6KX-1GP 2 1 C26 SC10U25V6KX-1GP 1 2 C433 SC10U25V6KX-1GP 1 C25 SC10U25V6KX-1GP 2 1 C10 SCD1U50V3KX-GP 2 1 2 C11 SC2200P50V2KX-2GP 5 6 7 8 D D D D G S S S 4 3 2 1 C80 SCD33U10V3KX-3GP 1 2 1 1 2 1 2 2 0R2J-2-GP U29 ADP3207AJCPZ-RL-GP DY 1 1 2 1 2 1 2 TC8 SE330U2VDM-6-GP 2 100R3J-4-GP TC1 SE330U2VDM-6-GP 2 1 DY C209 SCD01U50V2KX-1GP 3207_SW1 1 R146 3 SC1KP50V2KX-1GP TC3 SE330U2VDM-6-GP 1 R564 TC2 SE330U2VDM-6-GP De-populate when CPU is present Now use FDS6676AS-GP for footprint ,but BOM need use hand modify FDS7088SN3 NC SO-8 84.07088.A37 3207_PWM1 ADP3207_AGND 2 100R3J-4-GP DY 3207_DL1 3207_VRTT 3207_DCM# +VCC_CORE DY DY U8 FDS6676AS-GP ADP3207_AGND R181 392KR3F-GP 1 R218 3207_EN 1 2 R71 D001R2512J-1-GP R25 2D2R6J-3-GP 2 30 29 28 27 26 25 24 23 22 21 U75 FDS6676AS-GP 1 2 L49 IND-D45UH-2-GP 3207_RAMPAD1 1 R169 100R2J-2-GP C261 SC1KP50V2KX-1GP Single Core (YONAH ULV) 1. 2. 3. 4. Choke: L80 is 0.88uH R971 is 2.37K (Load line:-5.1m) R967 is 309K (OCP:14A) one Low side MFET Dual Core (MEROM ULV) 1. 2. 3. 4. Choke: L80 is 0.45uH R971 is 5.76K (Load Line:-2.1m) R967 is 215K (OCP:20A) Two Low side MFET 2 IMVP6_PROCHOT# 36 D 1 1 Q26 2N7002-7F-GP G Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. S 3207_VRTT 1 2 G7 GAP-CLOSE-PWR X01 ADP3207_AGND Title DC to DC CPU_Core Size Document Number Custom SSID = CPU.Regulator Rev B C D SC Parker Date: Wednesday, March 21, 2007 A 4 EXTPAD TTSENSE VRTT DCM# OD# PWM1 PWM2 PWM3 SW1 SW2 SW3 U16 ADP3419JRMZ-GP 2 40 39 38 37 36 35 34 33 32 31 VID0 VID1 VID2 VID3 VID4 VID5 VID6 DPRSTP# PSI# VCC ADP3207_AGND 2 ILIMIT VRPM RRPM RT RAMPADJ LLSET CSREF CSSUM CSCOMP GND 11 12 13 14 15 16 17 18 19 20 2 2 ADP3207_AGND R187 180KR2F-GP 1 3207_RRPM 3207_RT 1 R192 309KR2F-GP C271 SC1KP50V2KX-1GP 1 ADP3207_AGND C280 SC1KP50V2KX-1GP 2 1 3207_ILIMIT 3207_VRPM ADP3207_AGND VCCSENSE 6 VSSSENSE 6 C282 SC470P50V2KX-3GP C281 SCD012U25V2KX-GP 2 13207_STSET 1 2 Reversed for loop gain measurement purpose 2 EN PWRGD PMON CLKEN# FBRTN FB COMP SS STSET DPRSLP 2 1 2 R196 1K91R2F-1-GP 1 2 R198 1K91R2F-1-GP R211 DUMMY-R2 2 1 3207_FB1 1 3207_FB 3207_COMP 3207_SS 1 2 C278 SC18P50V2JN-1-GP 1 2 3 4 5 6 7 8 9 10 3207_RAMPAD 2 3207_PMON 1 2 1 23207_COMP11 R215 R203 1K65R2F-GP 20KR2F-L-GP C297 SC470P50V2KX-3GP R219 0R3-0-U-GP 1 2 C298 SC1U10V2KX-1GP ADP3207_AGND 1 0R2J-2-GP ADP3207_AGND 3207_DH1 CPU_PHASE1 S S S G 35,48,51 IMVP_PWRGD 2 10KR2J-3-GP 4,51 CLK_ENABLE# 1 2 C303 SC100P50V2JN-3GP 2 VID0_P IN BST SD# DRVH DRVLSD# SW CROWBAR GND VCC DRVL +VCC_CORE D D D D VID1_P 0R2J-2-GP 2 PM_DPRSLPVR1 2 1 499R2F-2-GP 3207_EN 1 0R2J-2-GP 0R2J-2-GP PWR_MON 23 1 R197 1 0R2J-2-GP 2 3207_VTTSENSE 2 +3.3V_RUN 3 2 ADP3207_AGND VID2_P 10 9 8 7 6 S S S G DY VID3_P 0R2J-2-GP 1 2 3 4 5 U73 FDS6298-GP D D D D 1 R199 2 R195 2 R194 5,18 H_DPRSLPVR 35,51 IMVP_VR_ON 35,48,51 RUNPWROK 0R2J-2-GP 2 R145 0R2J-2-GP ADP3207_AGND VID4_P 13207_VTTSENSE_1 2 2 GAP-CLOSE 0R2J-2-GP 2 41 1 VID5_P 2 R443 NTC-100K-3-GP G32 0R2J-2-GP 3207_VCC R144 7K32R2F-GP C233 SC1800P50V3KX-GP 2 1 4 ADP3207_AGND VID6_P 2 1 23207_BST1 D3 RB751V-40-1-GP R79 0R3-0-U-GP C59 SC4D7U10V5KX-1GP 3207_BST1_1 H_VID6 1 R164 H_VID5 1 R168 H_VID4 1 R174 H_VID3 1 R178 H_VID2 1 R183 H_VID1 1 R188 H_VID0 1 R190 2 0R2J-2-GP E +CPU_PWR_SRC 10R3J-3-GP DY D +5V_ALW R143 1 R158 6 H_VID[6..0] Thermistor should be placed close to the hot spot of the VR H_DPRSTP#_1 2 DY 1 1 R157 ADP3207_AGND C206 SC1U10V2KX-1GP R489 5 H_DPRSTP# +5V_ALW 2 0R2J-2-GP 1 5 H_PSI# 1 H_CPUPSI#_1 2 0R2J-2-GP 2 0R2J-2-GP 1 R490 1 C 2 A Sheet E 42 of 53 A +PWR_SRC B C D E +DC1_PWR_SRC +5V_ALW2 10/28 DY 1 1 2 R21 10R3J-3-GP 1 G13 GAP-CLOSE-PWR C12 SC4D7U10V5KX-1GP 0.1uF for ISL6236, Install with 1uF for Max8778 2 G14 GAP-CLOSE-PWR +PWR_SRC +5V_VCC1 2 No Install for ISL6236 Install 10 ohm for MAX8778 1 2 G15 GAP-CLOSE-PWR 1 2 G21 GAP-CLOSE-PWR 2 1 C79 SC2200P50V2KX-2GP 2 1 2 1 C489 SC10U25V6KX-1GP C71 SCD1U50V3KX-GP 1 2 G25 GAP-CLOSE-PWR 1 2 G26 GAP-CLOSE-PWR 4 3 2 1 1 DY 2 R384 0R2J-2-GP 1 2 1 2 R388 0R2J-2-GP 2 5 6 7 8 U20 FDS6676AS-GP Iomax=5A OCP>10A Sanyo 330uF 6D3V, D Size ESR=18mohm TC6 ST220U6D3VDM-13GP C517 SCD1U10V2KX-4GP IND-3D3UH-66-GP-U1 CHIP IND 3.3UH M MPL73-3R3 2 C52 SCD1U25V3KX-GP DY +3.3V_ALWP 2 1 R375 6236_ILIM2 1 2 182KR3F-L-GP 6236_SKIP# 1 R391 2 0R2J-2-GP 3V/5V_POK 3V/5V_EN 6236_UGATE2 6236_PHASE2 1 1 4 3 2 1 X01 32 31 30 29 28 27 26 25 2 1 2 5 6 7 8 C473 SC10U25V6KX-1GP 1 2 R374 0R2J-2-GP 1 2 1 1 C15 SC1U10V2KX-1GP 2 2 +3.3V_ALW2 R373 0R2J-2-GP L57 3V/5V_REFIN2 REFIN2 ILIM2 OUT2 SKIP# POK2 EN2 UGATE2 PHASE2 1 2 G24 GAP-CLOSE-PWR DELTA DCR=37mohm Irms=5.5A,Isat=10A 17 18 19 20 21 22 23 24 6236_OUT2 6236_BOOT1_1 1 R61 +5V_ALW2 6236_BOOT2 1 6236_LGATE2 GAP-CLOSE 2 1 2 G73 GAP-CLOSE-PWR 3 G74 GAP-CLOSE-PWR 1 2 G75 GAP-CLOSE-PWR 1 2 G77 GAP-CLOSE-PWR MAX8778_3/5V_AGND 2 1 2 G78 GAP-CLOSE-PWR C441 SCD1U25V3KX-GP 1 2 G79 GAP-CLOSE-PWR CLOSE TO PIN 30 1 C47 SC1U10V2KX-1GP 1 2 G86 GAP-CLOSE-PWR 2 6236_BOOT2_1 R62 0R3-0-U-GP G8 1 2 MAX8778_3/5V_AGND 26236_BOOT1 0R3-0-U-GP 6236_LGATE1 +3.3V_ALW 1 1 2 G76 GAP-CLOSE-PWR 1 2 Id=10A Qg=9~13nC, Rdson=12~15mohm 74.06236.073 ISL6236IRZA-T-GP MAX8778_3/5V_AGND 2 S S S G 1 8 7 6 5 D D D D 1 U19 FDS6676AS-GP C51 SCD1U25V3KX-GP 1 2 6236_PHASE1 BYP OUT1 FB1 ILIM1 POK1 EN1 UGATE1 PHASE1 6236_SECFB S S S G 1 2 3 4 1 2 G85 GAP-CLOSE-PWR R33 0R2J-2-GP 1 2 3 4 Sanyo 220uF 6D3V, V Size ESR=25mohm DY 2 1 2 C518 SCD1U10V2KX-4GP 1 2 1 2 G83 GAP-CLOSE-PWR 1 2 G84 GAP-CLOSE-PWR 9 10 6236_FB1 11 6236_ILIM1 12 3V/5V_POK 13 3V/5V_EN 14 6236_UGATE115 16 1 2 R41 91KR3F-GP X01 CHIP IND 4.7UH M MPL73-4R7 GND 1 C20 SCD1U25V3KX-GP MAX8778_3/5V_AGND 1 2 L58 IND-4D7UH-99-GP-U R34 0R2J-2-GP U21 FDS8880-NL-GP S S S G 1 2 G82 GAP-CLOSE-PWR 33 2 X01 +5V_ALWP DY D D D D 1 2 G81 GAP-CLOSE-PWR 3V/5V_TON 8 7 6 5 U9 CLOSE TO PIN 10 DELTA DCR=18mohm Irms=8A,Isat=14A TC5 ST220U6D3VDM-13GP +5V_ALW DY 1 2 R22 0R2J-2-GP 1 2 C16 SCD1U10V2KX-4GP DY S S S G 3 R12 0R2J-2-GP U18 FDS8880-NL-GP Id=5A Qg=8.7~13nC, Rdson=23~30mohm Iomax=5A OCP>10A 1 1 1 2 MAX8778_3/5V_AGND 3V/5V_EN D D D D 1 C471 SC10U25V6KX-1GP 2 1 1 C486 SC10U25V6KX-1GP 2 2 C69 SCD1U50V3KX-GP DY X01 DY C13 SCD1U25V3KX-GP 1 2 G23 GAP-CLOSE-PWR R23 0R3-0-U-GP +DC2_PWR_SRC D D D D 1 2 G19 GAP-CLOSE-PWR 2 1 G18 GAP-CLOSE-PWR C77 SC2200P50V2KX-2GP +DC1_PWR_SRC 8 7 6 5 4 3 2 1 2 LDOREFIN LDO VIN VREF3 EN_LDO VCC TON REF 1 G17 GAP-CLOSE-PWR +5V_VCC1 1 2 C14 SCD1U10V2KX-4GP 3V/5V_VIN 4 1 2 G22 GAP-CLOSE-PWR +2.0V_REF_3V5VREG BOOT1 LGATE1 PVCC SECFB GND PGND LGATE2 BOOT2 2 2 2 1 2 G16 GAP-CLOSE-PWR 1 R10 0R5J-5-GP 1 +5V_VCC1 +3.3V_ALW2 R6 0R5J-5-GP 2 G20 GAP-CLOSE-PWR +DC1_PWR_SRC 4 +DC2_PWR_SRC 1 2 1 MAX8778_3/5V_AGND MAX8778_3/5V_AGND 1 2 G87 GAP-CLOSE-PWR 1 2 G80 GAP-CLOSE-PWR D22 1 2 G88 GAP-CLOSE-PWR 3 10V_C 2 1 BAT54SW-2-GP D21 35,51 ALWON 3 15V_C 2 +15V_ALWP OCP:5x2=10A C439 SCD1U25V2ZY-1GP 1 1 R8 23 THERM_STP# 3V/5V_EN 2 1KR2J-1-GP 2 0R2J-2-GP 1 1 2 R410 200KR2J-L1-GP 1 2 2 BAT54SW-2-GP R411 39KR2J-GP 2 L=2.2uH Iocp=10-(4.2/2)~7.9A Vth=7.9A*15mOhm=119mV R(Ilim)=(119mV*10)/5uA ~238K--->R536 R43 2 1 R377 24D9R3F-GP 5V_C_2 1 2 C459 SCD1U25V2ZY-1GP 1 1 If L change to 3.3uH △I=(20-5)*5/(20*3.3u*0.4M)=2.8A Ripple voltage=2.8A*15mOhm=42mV Suggest ESR=15mohm to reduce ripple vol. R7 200KR2J-L1-GP 2 C440 SCD1U25V2ZY-1GP D24 BAT54-7-F-GP 1 L=2.2uH △I=(20-5)*5/(20*2.2u*0.4M)=4.2A Ripple voltage=4.2A*25mOhm=105mV Suggest ESR<=12mohm to reduce ripple vol. 2 5V_C_1 1 2 C460 SCD1U25V2ZY-1GP 3 2 2 1 MAX8778_3/5V_AGND 1 +3.3V_ALW L=3.3uH Iocp=10-(2.8/2)~8.6A Vth=8.6A*15mOhm=129mV R(Ilim)=(129mV*10)/5uA ~258K--->R536 X01 +15V_ALWP R36 100KR2J-1-GP 1 +15V_ALW 3V/5V_POK 1 2 G53 GAP-CLOSE-PWR Wistron Corporation 2 1 1 R32 0R2J-2-GP 2 ALW_PWRGD_3V_5V 35,51 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title 1 2 G56 GAP-CLOSE-PWR DC to DC 3.3V & 5V Size Document Number Custom SSID = PWR.Plane.Regulator_3V5V Date: Thursday, March 22, 2007 A B C D Rev SC Parker Sheet E 43 of 53 A B C D E SSID = PWR.Plane.Regulator_1.5V 1.5V_RUN +/- 5% Design Current: 0.9A Peak current 1.28A DC_1+1.5V_RUN_PWR_SRC 4 U39 OUTS 5 7 PGOOD SHDN PGND AGND 8 3 REFOUT 1 2 VCC 1 MAX8794ETB-T-GP C308 SC1U10V2KX-1GP 1 1 2 R193 0R3-0-U-GP 2 MAX8794_REFOUT C313 SC1U10V2KX-1GP 1 REFIN 11 2 4 2 6 1.5V_OUT 1 9 MAX8794_REFIN C302 DYSC1U10V2KX-1GP 2 1 R207 150KR2F-L-GP 2 1 2 R200 49K9R2F-L-GP OUT 2 BP 1.5V_RUN_ON_R 2 0R2J-2-GP +2.0V_REF_3V5VREG 1 1 R212 IN C309 SC10U4V3MX-GP 10 1 DY 2 R205 100KR2J-1-GP 48,51 1.5V_RUN_PWRGD 35,51 1.5V_RUN_ON 4 +1.5V_RUN 1 2 R228 0R3-0-U-GP +3.3V_ALW C289 SC10U4V3MX-GP +1.8V_SUS 3 3 SSID = PWR.Plane.Regulator_0.9V +1.8V_SUS 11 1 V_DDR_NB_REF 2 C286 SCD1U10V2KX-4GP +0.9V_P 1 2 3 4 5 U34 TPS51100DGQ-1-GP 74.51110.B79 1 VIN VDDQSNS S5 VLDOIN GND VTT S3 PGND VTTREF VTTSNS C283 SC10U4V3MX-GP 10 9 8 7 6 2 +0.9V_DDR_VTT 2 DDR_ON_0.9V 0R2J-2-GP 0.9V_DDR_VTT_ON_R 2 0R2J-2-GP 2 0.9 Volt +/- 5% Design Current: 1.05A Peak current 1.5A 1 1 35,51 0.9V_DDR_VTT_ON 1 R179 1 R206 GND 35,45,51 DDR_ON X01 C284 SC10U4V3MX-GP 1 2 1 2 +5V_ALW 1 2 G38 GAP-CLOSE-PWR 2 X01 TPS51100_LDOIN C269 SCD1U10V2KX-4GP 2 Please near U34/Pin10 C264 SC10U4V3MX-GP C775 SC4D7U10V5KX-3GP 2 1 +5V_ALW 2 G39 GAP-CLOSE-PWR 1 2 G40 GAP-CLOSE-PWR 1 2 G41 GAP-CLOSE-PWR 1 2 G42 GAP-CLOSE-PWR 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title DC to DC 1D5V / 0D9V Size A3 Document Number Date: Wednesday, March 21, 2007 A B C D Rev SC Parker Sheet E 44 of 53 A +PWR_SRC B C D E +DC_PWR_SRC REFIN2:tied to vref3=1.05V tied to vcc = 3.3V 1 2 G66 GAP-CLOSE-PWR 1 2 G67 GAP-CLOSE-PWR DY R1151 2 0R2J-2-GP 1 4 2 Frequency Select (Ton) GND - 400kHz/500kHz Ref (or open) - 400kHz/300kHz ** Vcc - 200kHz/300kHz +DC_PWR_SRC 1 G68 GAP-CLOSE-PWR +5V_VCC3 1 2 G69 GAP-CLOSE-PWR R121 0R3-0-U-GP 4 1 X01 2 1 +5V_VCC3 2 C50 SC1U10V2KX-1GP 1 2 C513 SC2200P50V2KX-2GP 1 C525 SCD1U50V3KX-GP 2 1 C524 SC10U25V6KX-1GP 2 2 1 1 4 5 3 6 2 7 1 8 2 U88 FDS6982AS-GP 1 2 3 2 G27 GAP-CLOSE-PWR 1 2 G28 GAP-CLOSE-PWR 1 2 G29 GAP-CLOSE-PWR Panasonic V Size 220uF, 2V ESR=15mohm Iripple=2.7A 21.05V_BOOT2_1 R60 0R3-0-U-GP G12 1 CHIP IND 3.3UH M MPL73-3R3 1 TC4 SE220U2VDM-8GP IND-3D3UH-66-GP-U1 1 2 +1.05V_RUNP 2 2 1.05V_SKIP# 1 1.05V_RUN_PWRGD 1.05V_RUN_ON_R 1.05V_UGATE2 1.05V_PHASE2 R95 0R2J-2-GP +1.05V_VCCP X01 L60 1 C106 SCD1U25V3KX-GP 2 1 2 GAP-CLOSE DY C512 SC10U25V6KX-1GP 1 2 1 2 1.05V_ILIM2 1 C48 SCD1U25V3KX-GP 1.05V_BOOT2 1 1.05V_LGATE2 1 2 R58 10R3J-3-GP 2 REFIN2 ILIM2 OUT2 SKIP# POK2 EN2 UGATE2 PHASE2 2 +5V_ALW X01 R103 93K1R3F-L-GP 32 31 30 29 28 27 26 25 BOOT1 LGATE1 PVCC SECFB GND PGND LGATE2 BOOT2 1.8V_BOOT1 2 0R3-0-U-GP X01 1 2 8 7 6 5 4 3 2 1 LDOREFIN LDO VIN VREF3 EN_LDO VCC TON REF 2 1 2 3 4 1.8V_BOOT1_1 1 R59 1.8V_LGATE1 Design Specs in default: TDC: A Peak:2.65A OCP:3.975A R110 113KR2F-1-GP 17 18 19 20 21 22 23 24 74.06236.073 ISL6236IRZA-T-GP C70 SCD1U25V3KX-GP C109 SCD1U10V2KX-4GP 2 1.05V_TON 1.8V/1.05V_REF3 2 U27 FDS6299S-GP 1 X01 DY 1 2 G30 GAP-CLOSE-PWR 1 2 G31 GAP-CLOSE-PWR C89 SCD1U25V3KX-GP 2 1 2 3 4 D D D D 8 7 6 5 IND-1D5UH-36-GP S S S G 1 C98 SC1000P50V3JN-GP R104 21KR3F-GP 1.8V_ILIM1 1 2 1.8V_SUS_PWRGD_R R97 DDR_ON_1.8V 118KR3F-GP 1.8V_UGATE1 1.8V_PHASE1 2 2 Sanyo V Size 330uF, 2D5V ESR=15mohm Iripple=3.7A R105 27K4R3F-GP 2 C221 SCD1U10V2KX-4GP 1 2 1 1 TC10 SE330U2D5VDM-LGP 2 1 2 1 1 BYP OUT1 FB1 ILIM1 POK1 EN1 UGATE1 PHASE1 1 2 1 C97 SCD1U10V2KX-4GP 1 2 8 7 6 5 9 10 11 12 13 14 15 16 GND 1 1 2 G37 GAP-CLOSE-PWR TC9 SE330U2D5VDM-LGP 1 2 G35 GAP-CLOSE-PWR 1 2 G36 GAP-CLOSE-PWR X01 L63 +1.8V_SUSP 2 1 2 G34 GAP-CLOSE-PWR C574 SC10U25V6KX-1GP 1 2 C559 SC10U25V6KX-1GP 2 1 C565 SCD1U50V3KX-GP 1 2 C532 SC2200P50V2KX-2GP X01 1 2 G33 GAP-CLOSE-PWR 33 1.05V_REFIN2 S2 CHIP IND 1.5UH M MPL74-D1R5 U17 R111 100KR2F-L1-GP G2 U92 FDS6298-GP G S S S +1.8V_SUS D D D D 3 1.8 Volt +/- 5% Design Current: 7.3A for +1.8V_SUSP Maximum current 10.5A for +1.8VSUSP OCP point is 12.7A for +1.8VSUSP +5V_VCC3 DY 1 2 R122 0R2J-2-GP 1.05V_REF D2 DY 2 D2 X01 DY 1 R113 0R2J-2-GP S1 G72 GAP-CLOSE-PWR 0R2J-2-GP G1 2 C114 SCD1U25V3KX-GP +DC_PWR_SRC DYR114 D1 +DC_PWR_SRC 1 2 G71 GAP-CLOSE-PWR 1 1.8V/1.05V_VIN_SRC D1 1 2 G70 GAP-CLOSE-PWR C112 SC1U10V2KX-1GP 2 1.8V_FB1 1 1 +3.3V_RUN +3.3V_SUS 1 2 R89 100KR2J-1-GP 1 2 0R2J-2-GP 1.8V_SUS_PWRGD_R 1 R91 2 0R2J-2-GP DDR_ON_1.8V R88 3 2 1 2 35,51 1.8V_SUS_PWRGD 4 36,51 1.05V_RUN_ON R78 1 0R2J-2-GP 2 1.05V_RUN_PWRGD 1.05V_RUN_ON_R 5021 GPIO 1.05V_RUN_ON / NB_VCORE_RUN_ON U23 2N7002DW-7F-GP 1 1.8V_EN#1 1 2 Wistron Corporation +5V_ALW 1 2 R131 0R2J-2-GP 36 1.8V_EN# 5 6 35,44,51 DDR_ON 1 46,48,51 1.05V_RUN_PWRGD 2 RST#_1.8V_EN# 1 1 2 R132 C145 10KR2J-3-GP SCD1U10V2KX-4GP PLTRST# 1.8V_EN#2 7,18,27,31,32,35,46,51 R86 100KR2J-1-GP ENABLE NB CORE 2 R106 95K3R3F-GP High: Vout=1.6V Low: Vout=1.8V 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 3 1.8V_EN#3 Q22 MMBT3904-7-F-GP 1 2 R130 4K7R2J-2-GP Title SSID = PWR.Plane.Regulator_1.8V1.05V DC to DC 1D8V / 1D05V Size Document Number Custom Rev Date: Wednesday, March 21, 2007 A B C D SC Parker Sheet E 45 of 53 1 2 3 4 NB_VCORE_CNTRL_1 D 1 S 2 S C496 SCD01U50V2KX-1GP D 2 1 2 1 2 2 U76 SI4800BDY-T1 C451 SC2200P50V2KX-2GP 1 C450 SCD1U50V3KX-GP 1 2 C449 SC10U25V6KX-1GP 1 2 C448 SC10U25V6KX-1GP D D D D DY Design Specs in default: TDC: 2.46A Peak: 3.51A OCP:5.25A 4 3 2 1 2 1.2V_BOOT1 0R3-0-U-GP 1.2V_LGATE1 +5V_ALW +5V_VCC4 2 2 2 IND-3D3UH-66-GP-U1 2 U80 10/28 4 3 2 1 1 C504 SCD1U25V3KX-GP SI4810BDY-T1-GP Sanyo V Size 330uF, 2.5V ESR=15mohm Iripple=2.7A 2N_Vcore_BOOT2_1 R444 0R3-0-U-GP G11 1 TC15 SE330U2D5VDM-LGP NB_VCORE_SKIP# 1 NB_VCORE_PWRGD NB_VCORE_RUN_ON N_Vcore_UGATE2 N_Vcore_PHASE2 R418 0R2J-2-GP +1.2V/1.0V_VCCP C436 SCD1U10V2KX-4GP 2 1 2 2 1 NB_VCORE_ILIM2 1 +NB_VCORE L44 1 8 7 6 5 32 31 30 29 28 27 26 25 1 3 2 G55 GAP-CLOSE-PWR 1 2 G51 GAP-CLOSE-PWR 1 2 G46 GAP-CLOSE-PWR 1 2 G52 GAP-CLOSE-PWR 1 2 G54 GAP-CLOSE-PWR 1 2 G47 GAP-CLOSE-PWR C68 SCD1U25V2ZY-1GP 2 X01 GNDA_1P25V_GPU_CORE 1 1 REFIN2 ILIM2 OUT2 SKIP# POK2 EN2 UGATE2 PHASE2 GAP-CLOSE C498 SC1U10V2KX-1GP CHIP IND 3.3UH M MPL73-3R3 X01 R415 255KR3F-GP N_Vcore_BOOT2 1 N_Vcore_LGATE2 1 DY 2 R447 10R3J-3-GP GNDA_1P25V_GPU_CORE 2 C456 SC1U10V2KX-1GP PLTRST_SYS# HIGH HIGH LOW LOW +3.3V_RUN GNDA_1P25V_GPU_CORE 1 1.2V_SUS_PWRGD 48,51 1.2V_SUS_PWRGD 1 1 2 1 C468 SCD1U10V2KX-4GP 2 BYP OUT1 FB1 ILIM1 POK1 EN1 UGATE1 PHASE1 74.06236.073 ISL6236IRZA-T-GP 1.2V_BOOT1_1 1 R446 Panasonic GNDA_1P25V_GPU_CORE V Size 220uF, 2V ESR=15mohm Iripple=2.7A GNDA_1P25V_GPU_CORE 1 C507 SCD1U25V3KX-GP 2 1 5 6 7 8 D D D D 1.2V_FB1 1.2V_ILIM1 2 80K6R3F-1-GP 1.2V_SUS_ON_R 1.2V_UGATE1 1.2V_PHASE1 9 10 11 12 13 14 15 16 S S S G 1 1 C464 SC1000P50V3JN-GP 2 U79 SI4810BDY-T1-GP 4 N_Vcore_PWRSRC1 8 7 6 5 4 3 2 1 GND 1 2 3 4 1 2 G61 GAP-CLOSE-PWR R404 17K8R2F-GP 2 1 2 1 2 G60 GAP-CLOSE-PWR R412 24K9R3F-GP C463 SCD1U10V2KX-4GP 1 2 1 2 G59 GAP-CLOSE-PWR DY 1 R417 DY NB_VCORE_CNTRL 10,20 GNDA_1P25V_GPU_CORE GNDA_1P25V_GPU_CORE S S S G 1 2 G58 GAP-CLOSE-PWR GNDA_1P25V_GPU_CORE X01 1 2 L48 IND-4D7UH-99-GP-U R408 0R2J-2-GP 1 DY 2 G D D D D G57 GAP-CLOSE-PWR TC16 SE220U2VDM-8GP 2 1 +1.2V_SUSP 2 DY PLTRST# 7,18,27,31,32,35,45,51 Q52 BSS138-7F-GP GNDA_1P25V_GPU_CORE U81 G S S S 1 R407 0R2J-2-GP 1 2 2 10KR2J-3-GP G S S S C61 SCD1U25V2ZY-1GP 33 CHIP IND 4.7UH M MPL73-4R7 +1.2V_SUS 2 1 1 1 2 8 7 6 5 1 2 C479 SC10U25V6KX-1GP 1 2 C491 SC10U25V6KX-1GP 2 1 C469 SCD1U50V3KX-GP 1 2 C466 SC2200P50V2KX-2GP +5V_VCC4 GNDA_1P25V_GPU_CORE G NB_VCORE_CNTRL_2 NB_VCORE_REFIN2 GNDA_1P25V_GPU_CORE U78 SI4800BDY-T1 3 R400 0R2J-2-GP NB_VCORE_TON GNDA_1P25V_GPU_CORE D D D D 1.2 Volt +/- 5% Thermal Design Current: 2.163A Maximum current 3.1A OCP: 3.75A R431BSS138-7F-GP 243KR2F-GP GNDA_1P25V_GPU_CORE +3.3V_ALW3 DY +5V_VCC4 1.2V/NB_CORE_VIN_SRC NB_VCORE_REF C455 SCD1U25V3KX-GP N_Vcore_PWRSRC R438 121KR2F-L-GP 5 6 7 8 2 X01 1 1 2 G94 GAP-CLOSE-PWR R386 0R5J-5-GP 2 X01 1 2 G65 GAP-CLOSE-PWR R392 0R5J-5-GP Q49 2 1 2 G50 GAP-CLOSE-PWR 2 1 2 G64 GAP-CLOSE-PWR GNDA_1P25V_GPU_CORE R396 0R2J-2-GP 2 1 4 1 N_Vcore_PWRSRC 2 1 2 G49 GAP-CLOSE-PWR 1 1 2 G63 GAP-CLOSE-PWR C487 SC1KP50V2KX-1GP 2 G48 GAP-CLOSE-PWR R430 80K6R2F-GP 2 G62 GAP-CLOSE-PWR 2 2 LDOREFIN LDO VIN VREF3 EN_LDO VCC TON REF 1 R428 1 BOOT1 LGATE1 PVCC SECFB GND PGND LGATE2 BOOT2 2 2 1 E Install 0.01uF for ISL6236, +3.3V_RTC_LDO Install 1uF for MAX8778 1 N_Vcore_PWRSRC1 D C447 SC1000P50V3JN-GP 1 +PWR_SRC N_Vcore_PWRSRC C 17 18 19 20 21 22 23 24 +PWR_SRC B C454 SCD01U16V2KX-3GP A NB_VCORE_CNTRL LOW HIGH LOW HIGH Vout 1.0V 1.2V 1.2V 1.2V R441 1 R427 DY 2 1.2V_SUS_ON_R 0R2J-2-GP 100KR2J-1-GP 2 35,51 1.2V_SUS_ON NB_VCORE_PWRGD 35,47,51 3.3V_SUS_ON DY 1 R87 0R2J-2-GP NB_VCORE_RUN_ON 2 1 1 R90 0R2J-2-GP 2 DY C85 SCD1U10V2KX-4GP 2 45,48,51 1.05V_RUN_PWRGD NB_VCORE_PWRGD 35,48,51 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title DC to DC 1D2V / NB_Core SSID = PWR.Plane.Regulator_1.2V.NB_VCORE Size Document Number Custom Date: Wednesday, March 21, 2007 A B C D Rev SC Parker Sheet E 46 of 53 A B C D E RUN POWER DISCHARGE DY R204 1KR2J-1-GP DY R460 1KR2J-1-GP DY R687 1KR2J-1-GP 1 +3.3V_RUN 1 1 +3.3V_RUN_NB R120 1KR2J-1-GP DY DY +5V_ALW R710 1KR2J-1-GP 3V_PD +3.3V_ALW2 R696 S S DY DY G 2N7002-7F-GP 2N7002-7F-GP G 2 100KR2J-1-GP DY G 2 D D DY 2N7002-7F-GP 2N7002-7F-GP 1 2 3 4 SI4810BDY-T1-GP 100KR2J-1-GP Q21 G 2N7002-7F-GP U105 R699 S S S G D D D D 4 C736 SC4D7U25V5KX-GP RUN_ON_5V#_5 1 6 2 5 C737 3 4 SC4700P50V2KX-1GP 2 DY G Q70 S G 2N7002-7F-GP S DY 2N7002-7F-GP S DY G Q54 S Q23 Q63 S Q27 D D Q42 D D D 1 4 +5V_RUN Q61 5 6 7 8 1 3V_NB_PD 2 5V_PD 2 2.5V_PD 2 1.5V_PD 2 1.2V_PD 2 2 1.8V_PD 2 +15V_ALW 1 R135 1KR2J-1-GP 1 1 DY +5V_RUN 1 R399 1KR2J-1-GP +2.5V_RUN 2 DY +1.5V_RUN 1 +1.2V_RUN 1 +1.8V_RUN 2N7002DW-7F-GP RUN_ON 17,35,48,51 RUN_ON RUN_ON_5V# SUS POWER DISCHARGE +1.8V_SUS +3.3V_ALW +5V_ALW 3 1 2 R654 100KR2J-1-GP D R626 100KR2J-1-GP S G SUS_ON_5V# 2 Q58 OUT 3 R1 GND 1 2N7002-7F-GP 2 IN 6 2 5 3 4 D D D D S S S G RUN_ON_5V#_3 1 1 2 3 4 Q32 SI4336DY-E3-GP 1 3.3V_RUN_ON_1 1 C673 SC470P50V2KX-3GP 2 +3.3V_ALW2 1.8VS_PD 1 1 U96 8 7 6 5 2 +15V_ALW R604 47R2J-2-GP C336 SC4D7U6D3V3KX-GP 2 +3.3V_RUN 1 2 R647 100KR2J-1-GP 3 2N7002DW-7F-GP SUS_ON 35,48,51 R2 35,51 3.3V_RUN_ON Q59 DDTC144EUA-7F-GP 3.3V_RUN_ON +1.8V_SUS 1 2 R369 100KR2J-1-GP +15V_ALW +3.3V_ALW2 2 5 3 4 +5V_SUS SI3456BDV-T1-GP C470 SC470P50V2KX-3GP C202 SC4D7U10V5KX-3GP +1.2V_SUS 2N7002DW-7F-GP +15V_ALW 1 R440 8 7 6 5 2 100KR2J-1-GP U83 1 2 R429 100KR2J-1-GP +3.3V_SUS POWER ENABLE 1.2V_RUN_ON_1 6 2 5 3 4 +3.3V_ALW 3.3V_SUS_ON RUN_ON_5V#_1.2 C508 SCD1U10V2KX-4GP D 6 D 5 S 4 1.2V_RUN_ON 1 SI3456BDV-T1-GP DY C134 SC4D7U6D3V3KX-GP 2 2N7002DW-7F-GP C351 SC4700P50V2KX-1GP 1 4 U102 D D G 1 2 5 3 DY 35,46,51 3.3V_SUS_ON 1 2 3 3.3V_SUS_ON_2 R675 100KR2J-1-GP 2 1 2 2 36,51 1.2V_RUN_ON +3.3V_SUS U54 2 1 R286 100KR2J-1-GP 3.3V_SUS_ON_1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title SSID = Reset.Suspend POWER ENABLE Size Document Number Custom Rev B C D SC Parker Date: Wednesday, March 21, 2007 A 1 2 3 4 2N7002DW-7F-GP 1 +3.3V_ALW2 6 S S S G 2 +15V_ALW 1 D D D D SI4336DY-E3-GP 1 1 +3.3V_ALW2 R644 100KR2J-1-GP +1.2V_RUN Q50 X01 C497 SC4D7U6D3V3KX-GP SI3456BDV-T1-GP C155 SC4700P50V2KX-1GP 1 4 2 1.8V_RUN_ON 2 3 SUS_ON_5V2 35,51 1.8V_RUN_ON D 6 D 5 S 4 1 5 U26 D D G 2 6 2 2 1 1 2 3 1 2 2 U25 R128 100KR2J-1-GP 35,48,51 SUS_ON 1 +1.8V_RUN D 6 D 5 S 4 2N7002DW-7F-GP 1 R133 100KR2J-1-GP SUS_ON_5V1 U82 D D G +5V_ALW 1 2 1 2 3 RUN_ON_5V#_1.8 1 6 1 1.8V_RUN_ON_1 1 2 +3.3V_ALW2 C465 SC4D7U6D3V3KX-GP U74 +5V_SUS POWER ENABLE 1 2 R368 100KR2J-1-GP 2 +15V_ALW Sheet E 47 of 53 A B C D E 1 +3.3V_RUN 5V_3V_1.8V_1.2V_RUN_PWRGD R684 +3.3V_SUS 36,51 100KR2J-1-GP 1 2 C753 SCD1U10V2KX-4GP 1 U107A SSLVC08APWR-GP 14 2 +5V_RUN 5V_3V_1.8V_1.2V_RUN_PWRGD 4 4 1 3 2 6 1 R708 2N7002DW-7F-GP 2 100KR2J-1-GP 1 RUN_ON_WW U107B SSLVC08APWR-GP +3.3V_SUS 2 2 0R2J-2-GP 2 0R2J-2-GP 2 0R2J-2-GP 0R2J-2-GP DY DY 9 RUNPWROK 8 +1.2V_RUN_PWRGD_1 17,35,47,51 RUN_ON 1 R700 7 2 enable V-core 10 U107C 3 +1.2V_RUN RUN_ON_SS 2 0R2J-2-GP RUNPWROK 35,42,51 SSLVC08APWR-GP Q68 MMBT3904-7-F-GP 1 2 3 1 R709 1 R717 1 R718 1 R712 6 5 R683 100KR2J-1-GP ONLY FOR NB 3.3V POWER 1 2+1.2V_RUN_PWRGD R339 10KR2J-3-GP 1.5V_RUN_PWRGD 2.5V_RUN_PWRGD 1.05V_RUN_PWRGD NB_VCORE_PWRGD 4 14 44,51 23,51 45,46,51 35,46,51 +3.3V_RUN_NB +3.3V_SUS 14 5 +3.3V_RUN 7 Q67 MMBT3904-7-F-GP 1 2 1 2+1.8V_RUN_PWRGD R711 10KR2J-3-GP RUNON_ALL 7 3 RUN_PWRGD_SS 5V_RUN_PWRGD_R 4 3 +1.8V_RUN 2 U104 1 2 R719 100KR2J-1-GP 3 1 +3.3V_SUS +3.3V_SUS R693 1 2 1 R694 46,51 1.2V_SUS_PWRGD 2 2 C752 SCD1U10V2KX-4GP 14 100KR2J-1-GP SUSPWROK_1 12 0R2J-2-GP 11 SUSPWROK 20,23,35,51 13 7 35,47,51 SUS_ON KBC have delay 47ms U107D SSLVC08APWR-GP X01 2 2 +3.3V_ALW X01 1 3 2 U85A SSLVC08APWR-GP 1 R695 0R2J-2-GP 2 SB_PWRGD SB_PWRGD 20,23,51 2 2 RUNPWROK_DELAY 0R2J-2-GP 7 35,42,51 IMVP_PWRGD RESET_OUT# 1 R450 IMVP_PWRGD C754 SC1U10V2KX-1GP DY 1 14 35,51 RESET_OUT# NB_PWRGD NB_PWRGD 7,35,51 SSID = Reset.Suspend 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title POWER ON LOGIC Size A3 Document Number Rev A B C D SC Parker Date: Wednesday, March 21, 2007 Sheet E 48 of 53 A B C D E DP2 PLATFORMS POWER UP AC MODE 4 4 +RTC_CELL +DC_IN +5V_RUN CONTROL BY RUN_ON +SDC_IN +3.3V_RUN CONTROL BY 3.3V_RUN_ON KBC5025 KSO0/GPIOC0 +PWR_SRC +2.5V_RUN T1 ACAV_IN +1.8V_RUN CONTROL BY 1.8V_RUN_ON KBC5025 GPIO11/AB2_DATA KBC5025 ACAV_IN KBC Output BATTERY MODE ALWON +1.5V_RUN CONTROL BY 1.5V_RUN_ON KBC5025 GPIO93/AB1F_DATA KBC5025 ALWON T2 +5V_ALW T14 T15 T16 T17 T18 +1.2V_RUN T19 CONTROL BY 1.2V_RUN_ON ECE5021 GPIOB6 T20 +1.05V_VCCP +3V_ALW CONTROL BY 1.05V_RUN_ON ECE5021 GPIOD2/CIRRX T3 MAIN_PWR_SW# +NB_VCORE (1V or 1.2V) KBC5025 MAIN_PWR_IN0# 3 KBC Output RUN_ON KBC5025 KSI5/GPIO10 SUS_ON KBC5025 KSI6/GPIO17 T21 CONTROL BY 1.05V_RUN_PWRGD (HW ouotput) KBC_Output +5V_SUS CONTROL BY SUS_ON T23 +VCC_CORE T6 +3.3V_SUS CONTROL BY 3.3V_SUS_ON KBC5025 OUT11/PWM1 T7 +1.8V_SUS CONTROL BY DDR_ON KBC5025 KSO5/GPIO1 T8 +1.2V_SUS T9 CONTROL BY 1.2V_SUS_ON KBC5025 GPIO13/AB1G_DATA BIOS_Output TO SB SB_RSMRST# KBC5025 KSO8/GPIOC4 BIOS_Output TO SB T10 SIO_PWRBTN# KBC5025 GPIO80 T11 SIO_SLP_S5# T12 SIO_SLP_S3# 2 T13 RUN_ON SB Input to KBC CONTROL BY IMVP_VR_ON KBC5025 OUT2/PWM3 BATTERY MODE T5 +15V_SUS 3 BIOS_Input T22 RUNPWROK T4 CLK-GEN INPUT T24 CLK_ENABLE# BIOS_Output T25 RESET_OUT# KBC5025 nRESET_OUT/OUT6 T26 NB_PWRGD T27 SB_PWRGD T28 H_PWRGOOD T29 PLTRST#(A_RST#) SB Input to KBC PCI_RST# BIOS_Output H_RESET# T30 T31 2 KBC5025 KSI5/GPIO10 NB SEQUENCE PANEL SEQUENCE +1.8V_SUS T35 +1.8V_RUN ENVDD T36 +3.3V_RUN_NB T32 LCDVDD T37 +1.2V_RUN T33 1 +1.05V_VCCP 1 Wistron Corporation NB_CORE_POWER (1V or 1.2V) T34 T38 VALID CLOCK/DATA LINES 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. T39 T40 T41 LCD_BL_ON Title POWER ON SEQUENCE Size Document Number Custom Control by SMBUS Rev Date: Wednesday, March 21, 2007 A B C D SC Parker Sheet E 49 of 53 A B C D E Power Signal Name 4 3 Test Position U5.1;Page 39 GFX_PWR_SRC +DC_IN_SS U5.8;Page 39 +RTC_CELL C266.1;Page 18 +SDC_IN U12.8;Page 41 VCC_RUN_SB L31.1;Page 18 +VCHGR U48.8;Page 41 VCC_SB_PVDD C315.1;Page 18 +PBATT U37.1;Page 41 VCC_SB_VDDR C245.1;Page 18 +SBATT U38.8;Page 41 SB_AVDDCK1.2 C181.1;Page 21 +DOCK_PWR_SRC U24.8;Page 38 +3.3V_RUN_HW C275.1;Page 19 +PWR_SRC U12.1;Page 41 +3.3V_SB_USB_TX C156.1;Page 20 +VCC_CORE TC2.1;Page 42 +3.3V_SB_USB_RX C183.1;Page 20 +RTC_CELL C258/1 ; Page 18 +NB_VCORE C150/1 ; Page 11 +15V_ALW R696.1;Page 47 +3.3V_SB_AVDDC C135.1;Page 20 +DC_IN U5/1 ; Page 41 RUNPWROK U107/8 ; Page 48 +5V_ALW R413.1;Page 18 +SB_AVDDCK3.3 C182.1;Page 21 +SDC_IN U12/8 ; Page 41 +VCC_CORE TC2/1 ; Page 42 +3.3V_ALW U11.1;Page 17 SB_5V_REF C620.1;Page 21 +PWR_SRC U12/1 ; Page 41 CLK_ENABLE# R572/1 ; Page 4 +3.3V_ALW2 C14.2;Page 43 +2.5V_RUN C552.1;Page 23 ACAV_IN R329/2 ; Page 40 RESET_OUT# U30/53 ; Page 35 +1.5V_RUN R193.2;Page 44 THERMAL_LDO_IN C553.1;Page 23 ALWON R43/1 ; Page 43 NB_PWRGD R695/1 ; Page 48 +0.9V_DDR_VTT C718.1;Page 15 +3.3V_PCI7402_AVDD C348.1;Page 24 +3.3V_ALW C314/1 ; Page 35 SB_PWRGD R695/2 ; Page 48 +1.8V_SUS R170.1;Page 7 +3.3V_PCI7402 C364.1;Page 24 +5V_ALW Q61/5 ; Page 47 H_PWRGOOD R568/2 ; Page 5 +1.05V_VCCP C102.1;Page 11 +3.3V_PCI7402_VCCP C656.1;Page 24 MAIN_PWR_SW# R511/2 ; Page 17 PLTRST# R664/1 ; Page 18 +1.2V_SUS Q50.8;Page 47 +3.3V_PCI7402_VDDPLL33 C730.1;Page 24 SUS_ON U30/34 ; Page 35 PCI_RST# R621/2 ; Page 18 +NB_VCORE U26.6;Page 47 PCI7402_VR_PORT C703.1;Page 24 +5V_SUS U26/4 ; Page 47 H_RESET# R512/2 ; Page 5 +5V_SUS U26.6;Page 47 +3.3V_RUN_CARD C763.1;Page 26 +15V_ALWP R377/1 ; Page 43 ENVDD D4/2 ; Page 17 +3.3V_SUS U102.6;Page 47 +3.3V_LAN U93.4;Page 27 +3.3V_SUS RN50/3 ; Page 35 LCDVDD U11/4 ; Page 17 +5V_RUN Q61.1;Page 41 +2.5V_LOM C62.1;Page 27 +1.8V_SUS U82/1 ; Page 47 +3.3V_RUN Q32.1;Page 47 +2.5V_BIASVDD L51.1;Page 27 +1.2V_SUS Q50/8 ; Page 47 +1.8V_RUN U82.6;Page 47 +2.5V_XTALVDD L53.1;Page 27 SB_RSMRST# U30/23 ; Page 35 +1.2V_RUN Q50.1;Page 47 +2.5V_AVDD L59.1;Page 27 SIO_PWRBTN# U30/109 ; Page 35 CLK_VDDREF C331.1;Page 4 +1.2V_LOM C492.1;Page 27 SIO_SLP_S5# U30/31 ; Page 35 CLK_VDD48 C330.1;Page 4 +1.2V_AVDDL L55.2;Page 27 SIO_SLP_S3# U30/30 ; Page 35 CLK_VDDA C248.1;Page 4 +1.2V_GPHY_PLLVDD L52.2;Page 27 RUN_ON U30/35 ; Page 35 +3.3V_RUN_CLK C246.1;Page 4 +1.2V_PCIE_PLLVDD L61.2;Page 27 +5V_RUN Q61/1 ; Page 47 V_CPU_GTLREF R54.1;Page 5 +1.2V_PCIE_SDVDD L16.2;Page 27 +3.3V_RUN Q32/1 ; Page 47 C43.1;Page 7 CODEC_DVDD_CORE U31.1;Page 29 +2.5V_RUN R460/1 ; Page 47 U31.40;Page 29 +1.8V_RUN U82/4 ; Page 47 L50.2;Page 30 +1.5V_RUN R193/2 ; Page 44 V_DDR_NB_REF C616.1;Page 9 CODEC_DVDD_CORE_PIN40 U10.1;Page 17 4 Power Sequence Signal Name Test Position +1.8V_RUN_NB_IOPLLVDD18 C168.1;Page 7 +5V_SPK_AMP +1.2V_RUN_NB_IOPLLVDD12 C133.1;Page 7 +VDDA C268.1;Page 30 +1.2V_RUN Q50/1 ; Page 47 +1.8V_RUN_NB_PLLVDD18 C35.1;Page 10 +3.3V_CARDSUS C403.1;Page 31 +1.05V_VCCP R108/2 ; Page 7 +1.2V_RUN_NB_PLLVDD12 C55.1;Page 10 +1.5V_CARD C765.1;Page 31 +1.2V_NB_VDDPLL_PCIE C124.1;Page 10 +3.3V_CARD C390.1;Page 31 +1.8V_RUN_NB_AVDDD C88.1;Page 10 +3.3V_WLAN U98.6;Page 32 +1.8V_RUN_NB_AVDDQ C49.1;Page 10 +3.3V_RUN_HDD U100.6;Page 33 +1.8V_RUN_NB_VDDLT18 C129.1;Page 10 +1.8V_RUN_NB_LTP18VDD C21.1;Page 10 +3.3V_RUN_NB_AVDD C65.1;Page 10 +3.3V_RUN_NB_VDDR33 C66.1;Page 10 +3.3V_RUN_NB_VDDLT33 C130.1;Page 10 +3.3V_RUN_NB 1 Signal Name +DC_IN +1.05V_VCCP_NB_CPU_VREF 2 Test Position Signal Name Test Position 3 2 U22.6;Page 10 +1.8V_RUN_NB_VDD18CPU C115.1;Page 11 +1.8V_RUN_NB_VDD18MEN C228.1;Page 11 +1.2V_RUN_NB_VPCIE C179.1;Page 11 5V_CRT_S0 C426.1;Page 16 LCDVDD U11.4;Page 17 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title POWER ON TIMING Size A3 Document Number Date: Wednesday, March 21, 2007 A B C D Rev SC Parker Sheet E 50 of 53 A B C D E SSID=EMI 34.43G01.002 34.43G01.002 34.45V09.001 35,47,48 SUS_ON H14 HOLE H16 HOLE H8 HOLE 3 35,46,47 3.3V_SUS_ON H7,BOSS 34.4S701.001 35,44,45 DDR_ON 35,45 1.8V_SUS_PWRGD 1 1 1 1 1 1 1 35,46 1.2V_SUS_ON 46,48 1.2V_SUS_PWRGD ZZ.0HOLE.XXX ZZ.0HOLE.XXX H1 HOLE ZZ.0HOLE.XXX H18 HOLE ZZ.0HOLE.XXX H12 HOLE ZZ.0HOLE.XXX H17 HOLE ZZ.0HOLE.XXX H2 HOLE ZZ.0HOLE.XXX H19 HOLE 20,23,35,48 SUSPWROK 20,35 SB_RSMRST# 20,35 SIO_PWRBTN# 1 1 1 1 1 1 20,35 SIO_SLP_S5# 20,35 SIO_SLP_S3# 17,35,47,48 RUN_ON ZZ.0HOLE.XXX ZZ.0HOLE.XXX ZZ.0HOLE.XXX ZZ.0HOLE.XXX 2 1 1 1 2 3 4 5 35,43 ALW_PWRGD_3V_5V H3 HOLE LAN Shading-Lock 3 ZZ.0HOLE.XXX 4 ZZ.0HOLE.XXX H20 MLX-CON2-7-GP 34.45V09.001 SSID=Mechanical H11 HOLE ZZ.0HOLE.XXX ZZ.0HOLE.XXX 1 34.45V09.001 17,35 MAIN_PWR_SW# H7 HOLE H9 HOLE 4 CLK-GEN Shading-Lock 35,43 ALWON H5 HOLE H10 HOLE DY SW4 SPRING-17 1 SW2 SPRING-17 1 SPR7 SPRING-48-GP 1 1 H13 ACES-CON5-7-GP-U DY 34.45T31.001 34.45T31.001 34.45T31.001 34.45T31.001 34.45T31.001 SW3 SPRING-17 SPR8 SPRING-48-GP H15 HOLE 1 SPR5 SPRING-24-GP LAN Shading BOX H6 HOLE 1 SPR3 SPRING-24-GP 1 1 SPR4 SPRING-24-GP 6 34.45T31.001 SPR6 SPRING-24-GP 1 SPR1 SPRING-24-GP 1 SPR2 SPRING-24-GP 7 4 1 1 1 CLK-GEN Shading BOX ZZ.0HOLE.XXX ZZ.0HOLE.XXX 35,47 3.3V_RUN_ON 23,48 2.5V_RUN_PWRGD 35,47 1.8V_RUN_ON 35,44 0.9V_DDR_VTT_ON 35,44 1.5V_RUN_ON 2 44,48 1.5V_RUN_PWRGD ALWON MAIN_PWR_SW# ALW_PWRGD_3V_5V SUS_ON 3.3V_SUS_ON DDR_ON 1.8V_SUS_PWRGD 1.2V_SUS_ON 1.2V_SUS_PWRGD SUSPWROK SB_RSMRST# SIO_PWRBTN# SIO_SLP_S5# SIO_SLP_S3# RUN_ON 3.3V_RUN_ON 2.5V_RUN_PWRGD 1.8V_RUN_ON 0.9V_DDR_VTT_ON 1.5V_RUN_ON 1.5V_RUN_PWRGD TP29 TPAD28 36,47 1.2V_RUN_ON TP120 TPAD28 36,48 5V_3V_1.8V_1.2V_RUN_PWRGD TP17 TPAD28 36,45 1.05V_RUN_ON TP99 TPAD28 45,46,48 1.05V_RUN_PWRGD TP80 TPAD28 35,46,48 NB_VCORE_PWRGD TP129 TPAD28 35,42,48 RUNPWROK TP8 TPAD28 35,42 IMVP_VR_ON TP110 TPAD28 4,42 CLK_ENABLE# TP186 TPAD28 35,42,48 IMVP_PWRGD TP191 TPAD28 35,48 RESET_OUT# TP139 TPAD28 7,35,48 NB_PWRGD TP119 TPAD28 20,23,48 SB_PWRGD TP16 TPAD28 5,18 H_PWRGOOD TP14 TPAD28 7,18,27,31,32,35,45,46 1.2V_RUN_ON TP111 TPAD28 5V_3V_1.8V_1.2V_RUN_PWRGD 1.05V_RUN_ON TP6 1.05V_RUN_PWRGD TP194 TPAD28 NB_VCORE_PWRGD TP193 TPAD28 RUNPWROK TP189 TPAD28 IMVP_VR_ON CLK_ENABLE# TP160 TPAD28 IMVP_PWRGD TP118 TPAD28 RESET_OUT# TP144 TPAD28 NB_PWRGD TP187 TPAD28 SB_PWRGD TP188 TPAD28 H_PWRGOOD TP169 TPAD28 TP185 TPAD28 PCI_RST# TP190 TPAD28 18,25 PCI_RST# TP177 TPAD28 3,5,7 H_RESET# TP98 TPAD28 5,7 H_ADS# 3 TP149 TPAD28 PLTRST# PLTRST# TP97 TPAD28 TPAD28 TP5 H_RESET# TPAD28 TP12 TPAD28 H_ADS# TP13 TPAD28 TP175 TPAD28 TP56 TPAD28 TP150 TPAD28 2 TP192 TPAD28 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title EMI/HOLE Size A3 Document Number Rev A B C D SC Parker Date: Wednesday, March 21, 2007 Sheet E 51 of 53 A DATE 2006/11/03 B VERSON ITEM PAGE X00 25 30 26 32 27 32 28 33 29 35 30 35 31 35 32 35 33 35 34 35 35 36 36 36 37 36 38 36 39 37 40 37 41 38 42 38 43 40 44 43 Modify List REMOVE DVI CHIP TO MEDIA SLICE SIDE Dummy ITP1 Add R616,R617, Dummy R607,R610 Change R221,R595 to 15 ohm , RN14 to 22 ohm Change PCI-E GPP_TX Add R742 10K ohm in NB_TMDS_HPD_R Change +1.8V_RUN_NB_VDD18MEN TO +1.8V_RUN_NB_VDD18MEM Change R629,R630,R632,R633 to 0 ohm and Add R736,R737 100 ohm Change Onboard memory to Hynix and Mircon Change L37, L38, L39, L40, L41 to BLM18BA100SN1D Change R47 to 150 ohm Change LVDS1 Power circuit Add R738,R739,R740 0 ohm connect SATA power and GND Add C776 22pF De-pop and Change R445,R514,R529 to 47 ohm Change Memory SMBus support to SB SMBus 0 and Del U101,RN58 Del L23 and Change AVDDRX power to +3.3V_SB_USB_TX Change signal IRQ_SERIRQ to U63/Pin H1;Change U63/Pin H2 to signal MFUNC2 Change C385,C386 to 12PF Change R260,R265,R294,R305 to 200 ohm , R291 to 75 ohm Change C510 to 33PF Change R420 to 1.18K ohm Change U31/Pin 4 AUD_SPK_DET signal to U35/Pin P8 Change U32 to TI TPA6040A4 and setting Change U40/Pin 5 Power to +3.3V_RUN Change C446, C453 to 1uF 25V 0603 Swap ESD1 and De-pop C369, C377 Change U98 to Vishay SI3424DV Change R548,R573 to 0 ohm , R575 to 47 ohm and Add C772,C773, C774 22pF De-pop Dummy DBG1, DBG2 Change R641 to 1M ohm Change RN54,RN61,RN65,RN78 to 2.2K ohm Change C173 to 12PF ,C200 to 15PF De-pop R321 Add R749 10K ohm to +RTL_CELL Add R269 10K ohm, Dummy R270 Add MEM_VEND_I Detect in U64 Pin 1 Change U64 Pin 7 signal connect GND Add PEN_SW# connector to U64/Pin 119 Change KB1 signal Change LID_CL_SIO#_R to U40/Pin 2 , TABLET_DET# to HSW1/Pin 4 Change U85 power source to +3.3V_ALW Add DOCKED signal use U85 to LOM and Change U86/Pin E3 signal to LOM_E_SWITCH Add 1K8 ohm 1206 De-pop in +VCHGR to GND Change TC5 to 220U6D3V 45 44 Add C775 near U34/Pin 10 46 45 47 46 48 48 1 18 2 3 3 4 4 4 5 8 6 10 7 11 8 12 4 3 2007/03/21 X01 9 13 10 16 11 17 12 17 13 19 14 19 15 20 16 20 17 25 18 25 19 26 20 27 21 27 22 29 23 30 24 30 2 49 1 C Change , R103 Change Change Change D E Issue Description ATI Desgin check issues OWNER EE EE EE , SW EE EE EE EE EE EE EE EE EE EE RF SW EE TI multi function setting issues EE , SW Change SPEC Ext Clock Frequency select to 133MHz EA report fail issues PCI-E GPP error BIT issues BIT issues DDR clock driver issues Sansung memory can't support issues EA report fail issues EA report fail issues LCD Power issues No support SATA HDD issues SPI ROM issues Memory controller issues Crytal result issues EE EE EE EE SW EE EE EE EE Power SDIO Rise time fall issues Crytal result issues LOM Driver issues Audio detect issues AMP Main source change issues BIT issues Audio issues WWAN's SIM error WLAN Power issues SPI ROM issues 3 EE EE EE EE , EE EE EE , EE , SW EE EE , EE , ME EE BIT issues SUS and RUN power open two time issues Crytal result issues BIT issues Pen switch issues Board ID issues Memory controller for SPD issues BIT issues Pen switch issues Keyboard issues Hall switch support change issues BIT issues LOM Docking switch issues EE BIT issues EE EE EE BIT issues BIT issues L63 to IND-1D5UH , TC9,TC10 to SE330U2D5VVD , R97 to 118K to 93.1K R417 to 80.6K ohm , R415 to 255K ohm , TC15 to 330U2D5V R695 to 0 ohm , Del R666, C730 Power use Gap to Clise Gap 4 SW SW SW SW KBC Power issues Power Power issues Power Power Power Power sequence issues 2 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title HISTORY Size Document Number Custom Rev A B C D SC Parker Date: Thursday, March 22, 2007 Sheet E 52 of 53 5 DATE 4 VERSON ITEM PAGE 3 Modify List 2 1 Issue Description OWNER 1 2 3 4 5 D D 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 C C 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 B 37 B 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 A 53 A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title HISTORY2 Size Document Number Custom Rev SC Parker Date: Wednesday, March 21, 2007 Sheet 53 of 53