Transcript
PCI-AIO02
PCI Analog I/O data Acquisition(AD/DA) board INTRODUCTION This product is designed for the data acquisition system which utilize PCI interface to get analog data and to generate analog waveform. The PCI-AIO02 is a board having the functions of analog I/O PCI board with the 16bit DAC 8 channels, 12/14/16-bit ADC 8 channels.
GENERAL DESCRIPTION
▪ Full 33Mhz burst read/write operation
♦ Multi-function Data acquisition board
▪ Average data rate is 30MB data to, 8MB
♦ PCI target 32bit/33Mhz
data from the board without DMA.
♦ 12/14/16 bit ADC 8 channel In
▪ Very flexible to upgrade because of FPGA
(8-ch SE or 4-ch DI)
is used as PCI bridge and overall board
♦ 16 bit DAC 8 channel Out
control.
♦ Max 100Ksps conversation for each ADC ♦ Trigger function for analog In/Out sync.
▣ Analog Input ▪ 12bit resolution
APPLICATION
▪ 8 Single ended or 4 Differential Input
♦ PCI development and evaluation
▪ 0 to +5V, 0 to 10V, ±5. ±10,V Software-
♦ Data acquisition
Programmable input range
♦ Laboratory instrumentation
▪ Can change sampling interval in auto
♦ Process control systems
scanning mode by 10uSEC increment
♦ Factory automation
▪ Power on auto-calibration
SOFTWARE
▪ ±1 (LSB) INL/DNL
▣ Operating System
▪ ±1uA analog input leakage current
▪ Windows 2000/XP
▪ 20pF analog input capacitance
▣ Application Programming Interface
▪ On-board 1024 x 16 data FIFO
▪ Direct control through WDM driver
▪ User can select ADC data storage, FIFO or
▪ Windows DLL API
SRAM ▪ In auto scanning mode, user can select
SPECIFICATION
any channel order.
▣ Flexible Board ▪ PCI Target 32bit/33Mhz ▪ PCI 5V/3.3V compatible
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▣ Analog Output ▪ 16bit resolution ▪ 8 channel output ▪ 0 to +5V, 0 to +10V, +10.8V, ±5V, ±10V, ±10.8V output range ▪ MAX 500K (2uSEC) update rate ▪ Can change update interval in waveform generation mode by 2uSEC increment ▪ Simultaneous update of outputs ▪ ±16 (LSB) INL ▪ ±1 (LSB) DNL ▪ ±3 (LSB) Offset error ▪ ±1 (LSB) Gain error ▪ Slew Rate 0.7V/u sec ▪ On-board 1024 x 16 waveform generation dual-port RAM ▪ In waveform generation mode, user can select any channel order. ▣ External connection ▪ 25pin D-sub(Analog Input Channel) ▪ 15pin D-sub((Analog Output Channel)
EXT_PACE_OUT1
25
EXT_TRG1
24
EXT_FACE_IN0
23
AGND
22
N.C
21
N.C
20
N.C
19
N.C
18
ADC IN7 ADC IN5
13
DGND
12
EXT_FACE_IN1
11
EXT_PACE_OUT0
10
EXT_TRG0
9
EREF25
8
N.C
7
N.C
6
N.C
5
N.C
4
ADC IN6
3
ADC IN4
AGND
ADC IN2
AGND
AGND
10
17
AGND
15
ADC IN1
14
2
4
14 9
16
ADC IN3
5
15
3
13 8
2
12 7
1
DGND
ADC IN0
1
11 6
2
DAC_STEP0_OUT DAC_STEP1_OUT DAC_OUT6 DAC_OUT7 DAC_OUT4 DAC_OUT5 DAC_OUT2 DAC_OUT3 DAC_OUT0 DAC_OUT1
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PHYSICAL/ENVIRONMENTAL ▣ Dimensions ▪ Dimension (not including connectors) : 175mm x 95mm ▣ Temperature ▪ 0 to 70℃, Operating ▪ -20 to + 80℃ Storage ▣ Relative Humidity ▪ 20 to 80 percent, Non-condensing ▣ Power Requirement ▪ +5VDC(±5%) at Max. 1A
BLOCK DIAGRAM PCI BUS
PCI-AIO02 INTERNAL BLOCK
External Interface
Local Bus Address Data(Mem,I/O)
PCI Target
DAC 8ch 16bit Resolution
BUS Mux
MEM Decoder To each IO Module
IO Decoder ADC 8SE/4DI 12/14/16-bit Resolution
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