Transcript
PCI and PCI Variations
Agenda • Introduction to PCI – PCI Overview – PCI Applications – Different Flavors of PCI – Market Trends
• PCI Technology overview • PCI Solutions – Spartan-IIE Overview – Spartan-IIE PCI Solutions • PCI 64-bit/66 Overview
– PCI Example Boards
• Summary
PCI Overview • Peripheral Component Interconnect • Originated in the PC industry • High performance bus that provides a processor independent data path between the CPU and high-speed peripherals • Robust interconnect mechanism developed to relieve the I/O bottlenecks • Used in the multiple high performance peripherals for graphics, full motion video, SCSI, LAN & embedded systems
Vast array of PCI Applications • PC board applications • Laptops • Servers • Telecom • Networking • Computing • Instrumentation • Video and Image Processing
Emerging Applications Require Higher PCI Bandwidth PCI Performance Maximum Throughput [MB/s]
600
528 MB/s
500 400 264 MB/s
300 200
132 MB/s
100 0 32-bit/33MHz
64-bit/33MHz 32-bit/66MHz
64-bit/66MHz
• • • • •
Mass-Storage/RAID High-end Printer I/Fs DSP/Imaging Gigabit Ethernet ATM, Fibre Channel
PCI Throughput (Max) • Maximum Usable Bus Bandwidth • 32-bit PCI protocol allows for four byte transfer every clock • If the burst length is infinite, then maximum throughput is – (4 bytes) * 33.3333MHz = 133 Mbytes/sec (PCI 32-bit/33MHz) Spec PCI-X [64-bit/133MHz] Fibre Channel PCI [64-bit/66MHz] AGP 2X PCI [32-bit/33MHz] Wide Ultra2 SCSI IEEE-1394 USB
Throughput (max) > 1 Gbytes/sec ~ 1Gbytes/sec 533 Mbytes/sec 533 Mbytes/sec 133 Mbytes/sec 80 Mbytes/sec 400 Mbits/sec 12 Mbits/sec
132 Mbytes/sec
Different Flavors of PCI Embedded PCI Variations PC PCI Variations PMC
PCI (Slot) Mini-PCI
PCI/PCI-X PC Local Bus
Cardbus PCI-X (Slot)
AGP
Small PCI CompactPCI
The PCI Market Keeps Growing...
Dollars (billion)
PCI Forecast (sub-set) 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0
Mini-PCI PCI-X PMC cPCI PCI
2001
2002
2003
2004
Year Source: Electronic Trend Publications and IDC
PC Local Bus PCI variations PCI-X • PCI-X is an extension of the existing PCI bus interface • The PCI-X spec specifies a bus design that can increase data throughput to over 1GBp/sec • PCI-X is backward compatible with the existing PCI bus – PCI-X adapter can operate in a conventional PCI system, and vice-versa
• Used in higher bandwidth applications: – NICs supporting multiple gigabit devices – Routers, Hubs and Switches – RAID Controllers – Clustered Server Interconnects
PC Local Bus PCI variations: PCI-X differences from PCI • PCI-X doubles the throughput to 1056MBp/sec from 528MBp/sec possible with regular PCI 64/66 • PCI-X relaxes the strict timing constraints required by the PCI 64/66 specification, which makes it easier to design • PCI-X improves bus efficiency by enhancing PCI protocol – – – – –
Attribute Phase Split Transactions Optimized Use of Wait States Standard Block Size Movements Improved Parity Error Handling
• PCI-X supports up to four slots at 66MHz as opposed to two with PCI 64/66, two slots at 100MHz and one slot at 133MHz
PC PCI Variations - Cardbus • Few removals and additions from traditional PCI signals • PCI in a PCMCIA form factor – PCMCIA 16-bit 5 volt ISA standard – CardBus 32-bit 3.3 volt PCI standard
• Point-to-point • Portable environment – NICs – Modems – Sound cards – CF adapters
PC PCI Variations: Mini PCI • New portable PCI proposal • Same electrical and protocols • Different form factor – Type 1: For full-featured systems that allow increased flexibility in placement via cabling to the I/O connectors – Type 2: For makers of value-priced notebooks and mobile computing devices, with RJ11 and/or RJ45 connectors that eliminate the cost of the intermediate cable – Type 3: Designed for ultra-thin notebooks uses SO-DIMM style connectors
• Targeted at Modems and NICs
PC PCI Variations - Small PCI • Small form factor • 32-bit PCI bus • Aimed at highly integrated peripheral controller components, peripheral add-in boards, and processor / memory systems • Less widespread acceptance
PC PCI Variations: AGP • Advanced Graphics Port • Designed to remove major load from the PCI bus and improve graphics performance – Specifically for 3-D rendering
• Point-to-Point graphics bus to link graphics engine with main memory • Higher throughput – No internal competition (point-to-point) – No cache coherence checking – No wait states – Supports long bursts
PC PCI Variations - AGP • Uses main memory to hold rendering images and moves them fast enough to minimize frame buffer usage – Main memory cheaper than frame memory (DRAM vs. SRAM) – Cuts overall bandwidth requirements as most data is retrieved from main memory or hard disk – Main memory is easier and cheaper to expand
• Uses 1.5V or 3.3V signaling
Embedded PCI Variations - PMC • PCI Mezzanine Card • Defines the mechanics of a slim, modular, parallel mezzanine card family • Uses the logical and electrical layers of the PCI specification for the local bus • Used where slim, parallel board mounting is required such as in single-board computer host modules with the addition of expander cards or option cards • Mainly aimed at industrial applications such as backplane expansion
Embedded PCI Variations CompactPCI • Uses standard PCI specification for devices • Eurocard form factor with unique physical and mechanical requirements with high-reliability features • Used as backplane with up to eight slots • PCI Industrial Computers Manufacturers Group (PICMG) defines CompactPCI - Xilinx is member CompactPCI (Eurocard) Standard PCI Slot
Embedded PCI Variations CompactPCI • Live insertion and removal of cards – High availability systems
• Electrical issues – Pre-charge signal lines to ~1V – Leakage current important – 4ms from long to short pin – Limited Early Power (2 Amp max)
• Adds Hot Swap Register • Three levels of compliance – Ready, Friendly, Capable
Power/Ground PCI Signals Enable
X8438
Staged pins on backplane
Other Embedded PCI Variations • PCI (slot) – Local bus for standard PCI cards on passive backplane or active motherboard – Widespread acceptance in all sorts of embedded applications
• PCI-X (slot) – Local bus for standard PCI-X cards on passive backplane or active motherboard – Gaining high adoption in high-performance embedded applications
Technology Overview
PCI Local Bus Architecture • The PCI Local Bus Specification covers many different requirements for PCI compliance Timing
Mechanical
PCI PCI Specifica Specifica tion tion 2.2 2.2 Electrical
Protocol
Basic Bus Architecture Add--in Cards Add
Host Host Bridge Bridge
56K 56K Modem Modem
ISA
Processor Processor System System
MPEG MPEG Video Video Capture Capture Card Card
Expansion Expansion Bus Bus Bridge Bridge
PCI PCI Local Local Bus Bus SCSI SCSI Controller Controller
100 100 Mbit Mbit Ethernet Ethernet
LAN
M otherboard
3D 3D Graphics Graphics Card Card
3D 3D Sound Sound Card Card
PCI-to-PCI Bridge and Peer-to-Peer Processor Processor System System
Upstream Transaction
Agent Agent
PCI Local Local Bus Bus BB #0 #0 PCI
Agent Agent
Peer-to-Peer Host Host Bridge Bridge
Agent Agent
Primary Bus PCI PCI Local Local Bus Bus AA #0 #0 PCI-to-PCI PCI-to-PCI Bridge Bridge
Agent Agent
Downstream Transaction
Secondary Bus PCI PCI Local Local Bus Bus AA #1 #1
Protocol Compliance
Key Terms • Initiator – or Master – Owns the bus and initiates the data transfer – Every Initiator must also be a Target
• Target – or Slave – Target of the data transfer (read or write)
• Agent – Any initiator/target or target on the PCI bus
Distributed Address Decoding • PCI uses Distributed Address Decoding Distributed Address Decoding Programmable decoders Each agent decodes address on PCI bus. The agent reacts if its address is on PCI bus
Agent Agent
Agent Agent
Agent Agent
Agent Agent
Decoder Decoder
Decoder Decoder
Decoder Decoder
Decoder Decoder
AD[31:0]
Initiator Initiator Dedicated Address Decoding Separate Chip Selects generated by a Central Address Decoder
Decoder Decoder
Bridge Bridge
CS0
Agent
CS1
Agent
CS2
Agent
Address Decoder
PCI Bandwidth
Transfer rate (Mbytes/sec)
• Distributed access decode speed effects throughput • Latencies and wait states reduces PCI throughput • Burst size has a big impact on PCI bandwidth 140 120 100 80 60 40 20 0
Effect of burst size on PCI bandwidth
Ideal PCI Write Ideal PCI Read
0
10 20 30 Double-Word Burst size
40
PCI Bus Arbitration
REQ#
GNT#
Q RE #
T# GN
Arbiter
GN T# RE Q#
• Arbitration is the process of providing rights to the PCI bus to one of the PCI agents by the arbiter • PCI spec does not specify the design of the arbiter, only that it be fair to prevent starvation • Common arbiters includes Round-Robin, Priority, and Two-level Priority Agent Agent Agent
Central Resource
PCI Arbitration Concept • Arbitration is “hidden” by current transaction – Reduces arbitration latency
• Receiving GNT# means you will be the next owner of the bus after the bus goes IDLE • Losing GNT# when you are the bus owner is called Preemption – Does not mean you lose the bus immediately
PCI Commands
With IDSEL With IDSEL
CBE
Command
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate
Memory Spaces • Each PCI target has three memory regions • Memory – 2 Gbyte max, 16 bytes min – Recommend 4Kbyte min
• I/O – 2 Gbyte max, 4 bytes min – For 80X86 systems, 256 bytes max because of legacy ISA issues
• Configuration – 256 bytes – First 64 bytes is the Configuration Header – Rest is user defined
PCI Configuration • Part of “Plug & Play” – Allows add-in cards to be plugged into any slot without changing jumpers or switches – Card must contain information for the BIOS and/or operating system • Type of card and device • Memory space requirements • Interrupt requirements
• Configuration Header – First 64 bytes of the configuration space – Contains all the necessary information
Base Address Registers (BAR) • Distributed Address Decoding • Two types - memory and I/O • Up to six BARs – Mix and Match of types
• • • •
Most applications use one or two Read returns address size request Software then writes base address into BAR Target responsible for tracking address during burst
Address Size (Hardwired)
Mask
Base Address
Address Comparator
Address on Bus
Hit
Electrical Compliance
Electrical Specification • Very detailed Electrical Specifications which cover – Device DC characteristics – Device timing requirements – Board level issues
• Electrical Compliance Checklist – Must be filled out for every device – One checklist for 5V signaling and another for 3.3V signaling
• Please refer to PCI specification for details
Reflective Wave Switching • PCI Bus is unterminated - replies on Reflective Wave Switching • Signal must be valid on the first reflected wave • Detailed Electrical Spec to guarantee proper signal switching Far End
Driver End 50pF Load
HSPICE Simulation of Intel PCI Speedway
Signaling Environment • Two different electrical specs – 5V signaling – 3.3V signaling
• Name has nothing to do with the supply voltage!! • 5V signaling is most common • 66MHz is 3.3V signaling only • Some devices can support both - Universal
Signaling Environment - DC Spec All parameters are functions of VDD!
+5V Signaling Vdd = 5.0V
3.3V Devices are OK
+3.3V Signaling VDD = 3.3V
Logic High
VOH = 0.9 X VDD = 2.97V VOH = 2.4V
Logic High
VIH = 2.0V VIH = 0.5 X VDD = 1.65V
VIL = 0.8V
Logic Low
VOL = 0.55V Vss = 0V
VIL = 0.3 X VDD = 0.99V
VOL = 0.1 X VDD = 0.33V VSS = 0V
Logic Low
I/V Curves Pull Up
Pull Down
Vcc
Vcc AC drive point Voltage
Voltage
test point
2.4 2.2 DC drive point
1.4
DC drive point
0.55
AC dri ve point
-2
test point
-44
Current (mA)
-176
Figure 1. Pull Up V/I Curve for 5 V Signaling Environment
3, 6
95
Current (mA)
380
Figure 2. Pull Down V/I Curve for 5 V Signaling Environment
One set of 5v and another for 3.3v Signaling
Clamp Diodes • Clamp diodes to GND always required • Clamp diodes to VCC required for 3.3 signaling – Optional for 5V signaling – Protect device I/O structure against large undershoots and overshoots – Needed to help dampen reflections on the bus
Bad Clamping - 5V Signaling Environment Vdd = 3.3v
Vdd = 5.0v PCI Bus
Chip Output
Chip Input
Timing Compliance
33MHz PCI Timing Specification 30ns Bus Cycle Time tval
tprop
tsu
tskew
11ns
10ns
7ns
2ns
Wave Propagation
Input Setup
Max Clock-to-valid
Other Requirements: Hold time : 0ns Min Clock-to-out : 2ns Output off time : 28ns
Clock skew
All timing Parameters are measured at the package pin
66MHz PCI - Timing Comparison 30ns Bus Cycle Time tval
tprop
tsu
tskew
11ns
10ns
7ns
2ns
Wave Propagation
Input Setup
Clock skew
Max Clock-to-valid
15ns Bus Cycle Time tval
tprop
tsu
tskew
6ns
5ns
3ns
1ns
Setup
Clk skew
Clk-to-out
Wave Prop
Other Requirements: Hold time : 0ns Min Clock-to-out : 2ns Output off time : 14ns
Why is PCI timing so tough? 7ns + clock_delay Logic
11ns - clock_delay FF
PCI Signal High Fanout
PCI CLK
• • • •
PCI handshaking performed every clock cycle => no pipelining 7ns Setup + clock_delay => 100+ MHz!! 3ns Setup + clock_delay => 240+ MHz!! [66MHz PCI] I/O tends to be the slower part of FPGAs
PCI Signal
Mechanical Compliance
Add-in Card Design • Trace length – All 32-bit PCI signals must be no more than 1.5” – All 64-bit extension signals must be no more than 2.0”
• Clock trace must be 2.5” exact! [+/- 0.1”] – Routed to only one load
• PCI Device Requirements – One pin per signal! – Max input capacitance is 10pF • If device is on motherboard, then 16pF is OK
5V and 3.3V Add-in Cards • Cards are “keyed” for 5V or 3.3V signaling
Face Plate
– Universal cards have both “keys”
3.3v Key
5v Key
64-bit ext.
System Issues - Bus Loading • No PCI spec requirement as to the loading on the bus, but – Must meet the 10ns propagation delay on the bus
• Rule of thumb is “Ten loads maximum for 33MHz” – Motherboard devices count as one load – Each add-in card slot counts as two load – Since most PC motherboards must have two or more PCI devices, they usually have no more than four slots
• More slots are available using PCI-to-PCI bridges or Peerto-Peer PCI systems
Spartan-IIE PCI Solutions for Consumer Digital Video
Spartan-IIE: The Total Solution
More Gates
Feature Rich
300K Gates Distributed and Block RAM Fast I/O Performance
DLLs System I/OTM (19) LVDS/LVPECL
More Performance
Cores Easy Design Flow Free WebPACK SW Fast, Predictable Routing
Time-to-Market
Port B
Differential I/O • 400 Mbps • LVDS • Bus LVDS • LVPECL
Dual-Port 4Kbit BRAM
Block RAM • Up to 64Kbits • 200 MHz
CL I O B I O B I O B I O B I O B I O B
DLL IOB
IOB
IOB
IOB
IOB
B R A M
CLB CLB CLB CLB CLB
B R A M
CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB
IOB DLL CL I CLB B O R B A I CLB M O B I CLB B O R B A I CLB M O B
B CLB CLB CLB CLB CLB CLB B R R A A M M CLB CLB CLB CLB CLB CLB M
CL DLL IOB
IOB
System I/OTM • 19 signaling standards • Chip to Backplane • Chip to Memory • Chip to Chip
IOB
IOB
IOB
I O B I O B
2ns
Spartan-IIE Technology
s 2n
2ns
CLB Tiles • Fast, predictable interconnect
IOB DLL CL
CLK0 CLK90 CLK180 CLKFB CLK270 CLK2X CLKDV RST LOCKED
CLKIN
Delay Lock Loops • 200+ MHz performance • 4 DLLs in every device • Deskew 4 system Clks • Zero-delay clock conv.
Performance & Density
FPGA Application Trends
Consumer Set-Top Boxes Digital TV Cable Modem PCI/PCI-X Bluetooth FEC Home Networking FFT/FIR Filters Digital Video IMA (ATM) Networking Encryption xDSL Modems Data Path MP3 Decoder Line Cards Memory Computers Controllers Graphic Cards Counters uControllers Printers Adders Bio-Medical, Industrial 7400 Series
1980s
1990s
2000s
High Performance Moves Beyond Enterprise Networking
Digital Video Requires High DSP & Interconnectivity Performance Source: Microprocessor Report
Flexibility - Interconnectivity • Plethora of interconnectivity standards – Video standards • VGA, SVGA, XGA, SXGA, UXGA, WXGA
– System interfaces/buses • LVDS, PCI/PCI-X, AGP, processor
– High speed video memory • HSTL, SSTL-based SRAM, DRAM solutions
– High speed video interfacing standards • IEEE-1394, IEEE-1355, USB 2.0, wireless
– Preferences and options vary by geography
PCI Solutions Today • Standard PCI Chips – Specialized on PCI – Price $15-$35 – Offers complete solution • Reference designs, boards, drivers, application notes
– Limitations • Extra PLD(s) often required for glue logic – A standard PCI chip is a bridge to a specific bus
• Cannot be customized or upgraded – Limited performance in some applications
PCI Solutions Today • ASICs with PCI core – Usual ASIC issues – High NRE – No flexibility (essential for fully compliant PCI) – Long development time
Aggregate Bandwidth Mb/sec
Xilinx has a Rich PCI Heritage 40 Gbps Ethernet
50000
Xilinx PCI Performance
10000
64-bit 133MHz
ma p d a Ro
5000 64-bit 66MHz
1000 32-bit 33MHz
500
64-bit 66MHz 1 Gbps Fibre Channel Ethernet
100
1994
1996
1998
2000
10 Gbps Fibre Channel Ethernet
2.5 Gbps Ultra 320 SCSI 2Gbps Fibre Channel
Internet Backbone
2002
Xilinx PCI in End Applications • Xilinx PCI Solutions are used in a Wide-Array of Applications – Processor Bus to PCI Bus Conversions – Data Encryption/Decryption – High Speed Networking – Digital Video Applications – I/O Communications Ports – Memory Interfaces – High Speed Data Input/Output (Acquisition) – Multimedia Communications – And many many more!!!
Spartan-IIE PCI Solution Overview • 64-bit PCI solution – Supports 66MHz PCI
• 32-bit PCI solution – Supports up to 66MHz PCI Designs
• Customizable asynchronous FIFO reference designs – Integrate seamlessly with PCI cores
Spartan-IIE PCI Customer Benefits • Reduces cost over PCI ASSPs – Cost savings of more than 50%
• Integrate and replace system functions – PLL/DLL clock management devices – SSTL-3/HSTL translators – LVDS – Backplane logic and drivers – External memory devices – System & caches controllers
• Significant time-to-market advantage
ASSP Replacement & Integration PCI ASSP
System & Memory Controllers, DLLs, Level Translators ($20)
Standard Chip PCI Master I/F
($15)
Glue Logic External PLD PCI Master I/F ($5)
*Supported Devices XC2S50E XC2S100E XC2S150E XC2S200E XC2S300E
Memory ($9)
Real-PCI from Xilinx • Real Compliance – Guarantees Setup, Hold and Min/Max Clock-to-Out timing
• Real Flexibility – Supports a wide range of Spartan-II devices allowing for easy device migration – Back-end decoupled from the PCI Interface to allow customization without affecting PCI timing
• Real Performance – Zero-wait state – Up to 528MBps sustained throughput
• Real Availability - Right Here Right Now!
Spartan-IIE LogiCORE PCI Block Diagram
Modular Architecture Best Flexibility and Predictability Proven core with predictable timing
On-chip scalable, dual-port FIFOs
PCI PCI
Backend Interface
PCI FIFO(s)
DMA(s)
User UserDesign Design Up Uptoto25,000 25,000 System SystemGates Gates
De-coupled “Soft” Reference Designs for easy customization Xilinx low-cost Spartan-IIE FPGA
Supporting Reference Designs • Asynchronous FIFOs and DMA Controller • Power Management Module
Up to 135,000 System Gates
Custom DMA Controller
Real-PCI Interface
PCI 64 PCI 32
PCI Bus
User Design
Asynchronous FIFOs
User Interface
Power Management Module
PCI - A Successful Programmable Solution Relative Component Cost
1
0.5
0.1
External PLD 7K Gates
Spartan-IIE FPGAs Lower Overall System Cost
External DLLs, memories, Controllers and translators
PCI ASSP PCI Master and Slave I/F
XC2S50E-5 PQ208 35K Gates Extra Logic PCI Master I/F
Standard Chip
Solution <$5 <$5 Solution per silicon silicon per basis basis
The 64-bit/66 MHz PCI Solution
The Xilinx PCI64/66 Solution • Solves timing issues – Enabled by Spartan-II/Spartan-IIE, Virtex/Virtex-E/Virtex-II – Guaranteed through Smart-IP
• No performance limitations – Full 64-bit data path – Zero wait-state burst
• Implemented in standard FPGAs – Best flexibility – Off-the-shelf devices – Large-scale manufacturing - low cost – Excellent testability – Cutting edge process technologies
The Real 64/66 PCI from Xilinx Real Flexibility
Real Compliance
• Uses standard Spartan-IIE FPGA • Back-end de-coupled from core
User Design DMA(s)
PCI64/66 Zero wait-state
Real Performance 260,000 gates in XC2S300E
• Compliant zero wait-state at 66MHz • Full 64-bit data path
64-bit, 66MHz PCI
FIFO(s)
64-bit Interface
• PCI v2.2 Initiator and Target • Guaranteed timing
Predictable and Flexible • Only PCI core for FPGAs with guaranteed timing – Including 2ns clock-to-out min timing, and 0 ns hold – FPGA characterized together with core – Pre-defined critical placement and routing
• First parameterizable PCI core – Configurable on the web
• First core with modular architecture – Core de-coupled from back-end design – Back-end customizable without affecting PCI timing
Real Compliance to PCI v2.2 Protocol, Timing and Electrical • PCI64 core is based on PCI32 – Has been used in over 1,000 customer designs – Many are fully compliant add-in boards
• Timing guaranteed through Smart-IP • Protocol verified with internal testbench – simulates over 6 million PCI cycles
• Meets the electrical PCI specification – Fast multi-standard System I/OTM interface allows a single I/O per PCI signal - required by the PCI spec
The Real 64/66 PCI Guarantees The Critical Path Setup: 3ns Hold time: 0ns
Clk-out max: 6ns Clk-out min: 2ns
FF
Logic PCI Signal
20 loads
72 loads
PCI Signal
PCI CLK
• The critical path is equivalent to • Uses Xilinx unique Smart-IP technology to guarantee min, max & hold tim e – Core and silicon characterized together
The Real 64/66 PCI: Summary • Real Compliance - guaranteed timing • Real Flexibility - implemented in standard Spartan-IIE FPGAs • Real Performance - full 528 Mbytes/sec • Real Availability - downloadable from Xilinx web site now
Spartan-IIE PCI Solutions
* PCI32: 66 MHz design available using Xilinx XPERTs or Design Services
PCI Over the Internet
• All design files are released on WebLINX • Instant access of new releases and updates • Intuitive GUI generates guaranteed design files • Verified for – – – –
Synopsys Synplicity MTI Cadence Verilog XL
PCI Training Classes • Two day PCI course – Basic PCI concepts – Xilinx PCI solution – Designing with Xilinx PCI – Design debug
PCI Expertise • Provide worldwide access to certified PCI experts that can provide – Support for targeting additional devices – Implementation of additional features – Complete turnkey integration
• Xilinx design center
MULTI VIDEO DESIGN
Xilinx PCI Board Examples
"With High-resolution display the Real 64/66 controller for the medical PCI products from imaging market. Handles transfers Xilinx, we were able to implement a fully compliant of over 500 MB/s from the host. PCI interface – plus other functions such as direct memory access (DMA), 4 dual-port FIFOs, and 200,000 gates of our own unique design – in a single device,” said John Beck Principal Engineer, DOME Imaging, Inc. "After evaluating different solutions in the market, we found that only Xilinx could meet the demanding requirements for full 66MHz PCI compliance.”
High-Performance Color Copier Interface
(Bloomington, Minnesota)
EDOX Document Server • Fully compliant PCI board • PCI and back-end: Xilinx
Graphics Accelerator PCI boards
(Huntsville, AL)
TDZ 2000
• Fully compliant PCI boards • PCI and back-end: Xilinx • More: 14x Analog Devices DSP processors
PCI Summary • Recognized as the industry leader in PCI solutions – Over 1,200 proven working designs
• Xilinx offers rich support for PCI – Real Compliance - guaranteed timing – Real Flexibility - industry’s most flexible PCI solution – Real Performance - full 528Mbytes/sec – Real Availability - download from Xilinx web site now
• Xilinx PCI with Spartan-IIE cost-effectively meets needs of digital convergence market
