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PCIe-20AO8C500K 20-Bit 8-Output 500KSPS Precision Wideband PCI Express Short-Card Analog Output Module
Features Include:
Eight Single-ended or 3-Wire Differential 20-Bit analog output channels.
Simultaneous Clocking; Individual R-2R 20-Bit DAC per output channel.
Clocking rates from zero to 500KSPS.
Software-selectable fullscale output ranges: ±10V and ±5V; Optionally ±5V and ±2.5V.
256K-sample output FIFO buffer.
Low Glitch Impulse; Typically 3.8nV-Sec on ±5V range.
Low-Noise DACs and output sections produce 95dB SNR.
Clocking from either external or internal sample rate generator.
Hardware trigger and clock I/O for multiboard synchronization; Selectable as LVDS or TTL.
8 Bidirectional TTL Digital I/O lines.
Conforms to PCI Express Specification revision 1.0a.
Optional Outputs Disconnect feature supports multiple card redundancy, and ensures quiet outputs during autocalibration.
Standard PCI Express Short-Card form factor.
Same pinout as that used for the PCIe-18AO8, with similar software interface.
Available also in 16-Channel configuration in full-length format.
DMA Engine supports block-mode and demand-mode transfers.
Remote ground sensing to minimize single-ended errors.
On-demand autocalibration of all channels.
Applications:
Precision Voltage Source
Acoustic Research
Waveform Synthesis
Audio Synthesis
Process Control
Industrial Robotics
REV: 070816
PCIe-20AO8C500K Preliminary
FUNCTIONAL DESCRIPTION The PCIe-20AO8C500K is a precision 20-Bit analog output product that provides eight simultaneously clocked output channels in a PCI Express short-card form factor. Outputs can be clocked at rates up to 500 KSPS per channel, and are supported by a 256K-Sample FIFO data buffer. Both continuous and burst clocking modes are supported, and voltage ranges are softwareselectable as ±10V and ±5V, or optionally as ±5V and ±2.5V. Clocking and triggering rates can be derived from an internal rate generator, or from external clock and trigger sources to support the synchronous operation of multiple boards. Each analog output channel implements a weighted-DAC R-2R configuration, which minimizes latency and has no minimum clocking rate. The outputs can be software-configured for singleended operation or for 3-wire differential operation. An optional outputs-disconnect feature ensures quiet outputs during autocalibration, and supports multiple-card redundancy. On-demand autocalibration determines and applies error correction for all output channels. Eight bidirectional digital I/O lines are programmable as inputs or outputs.
Analog Outputs (8)
Outputs Disconnect Autocalibration Loopback
COMPARATOR
System I/O Conn
8 AO, 8 DIO, Sync I/O
Voltage Reference Test Data External Clock and Sync I/O;
Digital I/O 20-Bit DAC (8)
PCIe Conn
Host Conn
+3.3/+12VDC
Power Conversion
PCI Express Interface Adapter
Regulated Power Voltages
Local Controller
Local Bus
Figure 1. PCIe-20AO8C500K; Functional Organization This product is functionally compatible with the PCI Express Specification revision 1.0a. System input/output connections are made at the front panel through a high-density 68-Pin connector. Power requirements consist of +3.3 VDC and +12 VDC in compliance with the PCI Express specification, and operation over the specified temperature range is achieved with conventional air cooling.
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PCIe-20AO8C500K Preliminary
PERFORMANCE SPECIFICATIONS At +25 OC, with specified operating voltages
Analog Output Parameters: Configuration:
Eight simultaneously clocked analog output channels with a dedicated 20-Bit R-2R DAC per channel. Software-selectable as either 2-wire single-ended outputs, or as 3-wire balanced differential outputs. Four-Channel version also available.
Voltage Ranges:
Software-selectable as ±10V and ±5V, or optionally as ±5V and ±2.5V.
Output Resistance:
Without outputs-disconnect: 1.0 Ohm max at I/O connector pins. With outputs-disconnect: 3.0 Ohms max when connected, 10K min when disconnected.
Output protection:
Withstands sustained short-circuiting to ground
Loading:
Zero to ±5ma per channel. Stable with any load capacitance up to 20,000 PFD.
Line Imbalance:
(With optional 3-Wire differential output configuration) ±15mV max.
Signal/Noise Ratio (SNR):
95dB typical on ±10V range; 10Hz - 250kHz.
Glitch Impulse:
3.8 nV-s, typical on the ±5V range
Transfer Characteristics: Resolution:
20 Bits (0.0001 percent of FSR)
Output Access:
256 K-Sample FIFO buffer.
DC Accuracy: (Max error, no-load)
High Range Set; ±10V, ±5V S.E. Range S.E. Zero Accuracy ±10V ±0.6mV ±5V ±0.4mV Diff Range* Diff Zero Accuracy ±10V ±1.5mV ±5V ±1.2mV Low Range Set; ±5V, ±2.5V S.E. Range S.E. Zero Accuracy ±5V ±0.5mV ±2.5V ±0.4mV Diff Range* ±5V ±2.5V
Diff Zero Accuracy ±1.2mV ±0.7mV
S.E. ±Fullscale Accuracy ±1.7mV ±1.2mV Diff ±Fullscale Accuracy ±4.5mV ±3.0mV S.E. ±Fullscale Accuracy ±1.6mV ±1.1mV Diff ±Fullscale Accuracy ±2.7mV ±1.5mV
* Differential output is measured between OUT-XX-HI and OUT-XX-LO.
Settling Time:
8us to 0.1 percent of step, typical with halfscale step, no-load.
Bandwidth:
Typically -3dB at 250kHz
Crosstalk Rejection:
95 dB minimum, DC-100 kHz
Integral Nonlinearity:
±0.002 percent of FSR, maximum
Differential Nonlinearity:
±0.0005 percent of FSR, maximum
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PCIe-20AO8C500K Preliminary
Operating Modes and Controls Output Data Buffer:
256 K-sample FIFO
Sample Clock Sources:
Internal rate generator; External Clock I/O, Software clock. 500kHz max.
Triggering Sources:
Internal rate generator, TTL external trigger I/O, Software trigger.
Clocking Modes:
Continuous or periodic. Supports triggered functions.
Internal Rate Generator:
Programmable from 3 to 500,000 output clocks per second. Divides Master Clock frequency to clocking rate using a 24-bit divider.
Low-Pass Filter:
Fixed-frequency 3rd-order low-pass Butterworth filter for each output channel. Enabled or disabled through software. Standard cutoff frequency: 100kHz.
External Sync I/O:
Front-panel: Clock and trigger, software-selectable as TTL or LVDS. Internal Connector: Clock and trigger, software-selectable as TTL or LVDS.
Outputs Disconnect:
All outputs can be disconnected from the system I/O connector under software control. This feature has no effect on autocalibration or selftest operations.
Output Data Format:
20 Bits, selectable as offset binary or two's complement coding, with attached end-of-function flag and channel number.
Remote Ground Sense (Single-ended outputs only; See ordering options): Single input to correct for differences in ground potentials between single-ended outputs and their loads. Accuracy: Input impedance: Compliance (range): Bandwidth:
±1% (E.g.: 100mV potential difference is corrected to within ±1mV). 5K ±0.1K ±1.0V. 600 Hz, typical.
If not used, may be left disconnected or connected to OUT xx RTN.
Digital Input/Outputs: Eight TTL I/O lines in two groups of four bits, group-configurable as inputs or outputs. 0.2ma maximum input loading as current source, 8ma output loading as either source or sink. Direct register control.
PCI Express Compatibility: Conforms to PCI Express Specification revision 1.0a. DMA transfers as bus master with two DMA channels.
Power Requirements: +3.3VDC ±0.2 VDC from the PCIe bus, 0.9 Amps typical, 1.0 Amps maximum. +12VDC ±0.4 VDC from the PCIe bus, 0.5 Amps typical, 0.6 Amps maximum. Total power consumption: 9.4 Watts typical, 11 Watts maximum.
Physical Dimensions (PCI Express short card): Height: 110.1 mm (4.37 in) Width: 18.7 mm (0,74 in) not including bracket..21.6 mm (0.85 in) with Bracket. Depth: 174.63 mm (6.60 in)
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PCIe-20AO8C500K Preliminary
Environmental Specifications: Ambient Temperature Range: Standard Temperature:
Operating: 0 to +70 Degrees Celsius * Storage: -40 to +85 Degrees Celsius
Extended Temperature:
Operating: -40 to +80 Degrees Celsius * Storage: -40 to +85 Degrees Celsius * Air temperature at board surface.
Relative Humidity:
0 to 95%, non-condensing
Altitude:
Operation to 10,000 ft.
Cooling:
Conventional air cooling; 150 LFPM
Ordering Information: Specify the basic product model number followed by an option suffix "-A-B-C-D-E-F", as indicated below. For example, model number PCIe-20AO8C500K-8-10V-49.152M-NOD-0-0 describes a PCI Express short card with eight output channels, ±10V and ±5V output ranges, a 49.152MHz master clock frequency, no outputs disconnect, Pin A33 grounded, and standard low-pass filter.
Table 1. Ordering Options Optional Parameter
Value
Number of Channels:
Output Ranges:
Master Clock Frequency
Output Disconnect:
I/O Pin A33 Function
Low-Pass Filter
1
Specify Option:
8 output channels
A=8
4 output channels
A=4
Software-selectable ±10V, ±5V Output Ranges
B = 10V
Software-selectable ±5V, ±2.5V Output Ranges
B = 5V
Standard 49.152MHz
C= 49.152M
Custom frequency (Mhz)
C= xx.xxxM
With outputs disconnect feature
D = OD
No outputs disconnect
D = NOD
Output Return
2
E = 0 or NGS
Remote ground sense input
E = GS
Standard cutoff frequency = 100kHz
F = 100K or '0'
Custom Frequency
3
F = xxxK
1
Contact factory for custom frequencies from 47MHz to 53MHz. Typical stability 25PPM. For full I/O compatibility with the PMC/PCIe-18AO8 product, Pin A33 is Output Return. . 3 10kHz to 500kHz, ±12-15%. Contact Sales for availability of specific frequencies. 2
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PCIe-20AO8C500K Preliminary
SYSTEM INTERFACE CONNECTORS Table 1. System I/O Connector ROW-B
SIGNAL OUT 00 LO OUT 00 HI OUT RTN 00 OUT RTN 00 OUT 01 LO OUT 01 HI OUT RTN 01 OUT RTN 01 OUT 02 LO OUT 02 HI OUT RTN 02 OUT RTN 02 OUT 03 LO OUT 03 HI OUT RTN 03 OUT RTN 03 OUT 04 LO OUT 04 HI
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
SIGNAL DIGITAL RTN DIGIO 00 DIGITAL RTN DIGIO 01 DIGITAL RTN DIGIO 02 DIGITAL RTN DIGIO 03 DIGITAL RTN DIGIO 04 DIGITAL RTN DIGIO 05 DIGITAL RTN DIGIO 06 DIGITAL RTN DIGIO 07 DIGITAL RTN DIGITAL RTN
19
OUT RTN 04
19
CLOCK INPUT LO
Row B
Pin 34
I/O Conn
PWB
Pin 1
a. I/O Connector (panel pin-view)
1
1
20
OUT RTN 04
20
CLOCK INPUT HI
21 22
OUT 05 LO OUT 05 HI
21 22
DIGITAL RTN DIGITAL RTN
23
OUT RTN 05
23
CLOCK OUTPUT LO
OUT RTN 05
24
CLOCK OUTPUT HI
25 26
OUT 06 LO OUT 06 HI
25 26
DIGITAL RTN DIGITAL RTN
27
OUT RTN 06
27
TRIGGER INPUT LO
OUT RTN 06
28
TRIGGER INPUT HI
1
Cable-B *
1
24
28
Pin-1 Wire * 34-Conductor Ribbon Cable; 0.050-in Spacing
OUT 07 LO OUT 07 HI
29 30
DIGITAL RTN DIGITAL RTN
31
OUT RTN 07
31
TRIGGER OUTPUT LO
OUT RTN 07
32
33
OUT RTN 07/REM SENSE
34
OUT RTN 07
2
TRIGGER OUTPUT HI
33
DIGITAL RTN
34
DIGITAL RTN
1
1
(Table 1 and Table 2) Edge-detected LVDS or TTL. When TTL sync I/O is selected, 'HI' pins use TTL signal levels, and 'LO' pins are left disconnected. Software-selected assertion on LOW or HIGH transition.
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Ordering option; output return or remote ground sense input.
PIN 1
Pin-1 Wire Front Panel
b. System Cable Connector
1
(All output returns "OUT RTN XX' are connected together internally.)
Table 2. Internal Sync-I/O Connector
Cable-A *
1
1
29 30 32
Row-A
Cable Connector
ROW-A PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Figure 2. System I/O Connector
System Cable Mating Connector: 68-pin 0.050" Subminiature connector with metal shield: AMP #749621-7 or equivalent. I/O Connector Installed on Board (Ref): Amp # 787170-7.
SIGNAL AUX CLOCK I/O LO
1 1
2 3 4 5
AUX CLOCK I/O HI DIGITAL RTN DIGITAL RTN 1 AUX TRIGGER I/O LO
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AUX TRIGGER I/O HI
1
Recommended Sync-I/O mating cable connector is: Molex# 51146-0600. General Standards Corporation assumes no responsibility for the use of any circuits in this product. No circuit patent licenses are implied. Information included herein supersedes previously published specifications on this product and is subject to change without notice.
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