Pd6729 — Routing Pcmcia Interrupts In A Pci-based System Application Note May 2001

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PD6729 — Routing PCMCIA Interrupts in a PCI-Based System Application Note May 2001 As of May 2001, this document replaces the Basis Communications Corp. document AN-PD3. Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The PD6729 — Routing PCMCIA Interrupts in a PCI-Based System may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. Application Note PD6729 — Routing PCMCIA Interrupts in a PCI-Based System Contents 1.0 Introduction .................................................................................................................. 5 2.0 Routing PCMCIA Interrupts in a PCI-Based System ................................... 6 Figures 1 Application Note A Common Mapping of PD6729 Interrupt Pins to System Interrupt Lines .......................................................................................... 6 3 PD6729 — Routing PCMCIA Interrupts in a PCI-Based System 4 Application Note CL-PD6729 — Routing PCMCIA Interrupts in a PCI-Based System 1.0 Introduction The PD6729 is a single-chip PCMCIA interface controller capable of controlling two PCMCIA or compact Flash sockets, respectively. It is designed for use in embedded applications and notebook systems where reduced form factor and low power consumption are critical design objectives. Current typical application examples include: ■ Routers ■ Integrated access devices ■ Access network servers ■ DSLAMs ■ PBXs ■ Terminal servers ■ Vending machines ■ Point of Sale terminals ■ Portable handheld systems ■ Navigation systems ■ Data acquisition systems ■ Measurement equipment ■ Settop boxes With the PD6729, a complete dual-socket PCMCIA solution with power-control circuitry can occupy less than 2 square inches (13 square centimeters) of board space. The PD6729 controller is completely compatible with the standards of PCMCIA (Personal Card Memory International Association) Release 2.0 Standard as well as JEIDA (Japan Electronic Industry Development Association) Version 4.1 Standard, and PCI 2.1. The PD6729 controller also offers special power-saving features such as Automatic Low-power Dynamic Mode and Suspend Mode. The PD6729 is a true mixed-voltage device that can operate at +5 volts, +3.3 volts, or a combination of these at various interfaces. The controllers have full internal buffering and require no additional circuitry to interface to the PCI Bus or to PCMCIA sockets. Application Note 5 CL-PD6729 — Routing PCMCIA Interrupts in a PCI-Based System 2.0 Routing PCMCIA Interrupts in a PCI-Based System Current PCMCIA software is programmed to expect management and general-control interrupts to occur on standard ISA-type interrupt lines. Typical PC/AT-compatible system hardware and software also assume certain IRQ activation for specific peripherals. For example, some ISRs (Interrupt Service Routines) for serial peripherals assume the activation of specific IRQ lines for the COM port used. Some ISRs expect a fax/modem card to use either the COM1 port and activate the IRQ4 interrupt line or use COM2 and activate IRQ3. Some ISRs also expect certain cards to use COM3 and activate IRQ4 or use COM4 and activate IRQ3. The PD6729 PC Card (PCMCIA) controller has 10 pins available for interrupt routing. A common connection is shown in Figure 1. Figure 1. A Common Mapping of PD6729 Interrupt Pins to System Interrupt Lines IRQ3/INTA# IRQ4/INTB# IRQ5/INTC# IRQ7/INTD# IRQ9 PD6729 IRQ10 IRQ11 IRQ12 IRQ14/EXT_CLK IRQ15/RI_OUT* PCMCIA Note: P C I B u s Bridge CPU ISA Bus or PIC IRQ14/EXT_CLK and IRQ15/RI_OUT* have two functions on the PD6729. The PD6729 allows custom routing of interrupt signals from the PD6729 pins to the PCI bus. Connections can be made to INTA#, INTB#, INTC#, or INTD# on the PCI bus. Refer to the PD6729 data sheet for detailed information. The routing of IRQ lines on the bridge side, however, is highly system-dependent. If the correct IRQ is not activated on the PIC (Peripheral Interrupt Controller) inside the bridge chip, it is possible that the wrong ISR could be activated by the CPU, and the PCMCIA card would not function correctly. One way to alleviate the current interrupt routing problem during the evaluation process is to connect the IRQ pins on the PD6729 directly to the corresponding IRQ line on the ISA bus. This can easily be accomplished on a motherboard for planar implementation of the PD6729. Alternately, the IRQ lines can be routed from the PD6729 via a cable to a companion ISA plug-in card. (This latter scheme is the one used by the PD6729 demonstration boards.) The polarities of the interrupt signals (IRQ on ISA and INT# on PCI) must be considered. However, physical connection to the IRQ lines on the ISA bus may not be practical on some PCI motherboards, and on some system boards the ISA expansion bus may not be available. Design engineers should be careful with their system implementation to avoid problems with interrupts. It should be noted, however, that the interrupt routing mostly depends on the system design and is often beyond the scope of PCMCIA implementation. 6 Application Note 1 2 3 4 5 6 5V 13 25 36 47 STOP# IRDY# T R D Y# RST# DEVSEL# FRAME# IDSEL 32 29 30 207 31 27 15 LED SPKR 133 132 1 PCI_CLK 203 204 205 206 58 59 60 61 62 63 195 197 199 141 143 145 147 149 196 198 200 144 146 148 150 152 B_D0 B _ D1 B _ D2 B _ D3 B _ D4 B_D5 B _ D6 B _ D7 B _ D8 B _ D9 B_D10 B_D11 B_D12 B_D13 B_D14 B_D15 193 191 190 187 185 183 181 179 162 159 153 157 176 164 166 174 172 163 165 167 169 171 173 175 178 180 B_A0 B_A1 B_A2 B_A3 B_A4 B_A5 B_A6 B_A7 B_A8 B_A9 B_A10 B_A11 B_A12 B _ A13 B_A14 B_A15 B_A16 B_A17 B _ A18 B_A19 B_A20 B_A21 B_A22 B _ A23 B_A24 B_A25 139 131 3# 2# 1# 0# STOP# IRDY# T R D Y# RST# DEVSEL# FRAME# IDSEL A_SOCKET_VCC A_SOCKET_VCC LED OUT* SPKR OUT* A_VPP_PGM A_VPP_VCC A_VCC_3 A_VCC_5 PCI CLK CORE RING RING RING RING RING RING RING 2 3 208 D AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 AA25 AA24 AA23 AA22 AA21 AA20 AA19 AA18 AA17 AA16 AA15 AA14 AA13 AA12 AA11 AA10 AA9 AA8 AA7 AA6 AA5 AA4 AA3 AA2 AA1 AA0 G N T# REQ# J10 PCI_CLK_REQ 188 161 1 2 C O RE_VCC C30 0.1uF 3V 134 135 136 138 5V_VCC J4 1 2 3 B_VPP_PGM B _ VPP_VCC B_VCC_3 B_VCC_5 109 111 113 81 107 125 83 85 80 93 118 116 66 126 75 79 95 64 CORE_VCC B J3 1 2 3 A_RESET A_WAIT A_INPACK A_VS1 A_VS2 A_W P A_IORD A_IOWR A_OE A_W E A_BVD1 A_BVD2 A _ C D1 A _ C D2 A_CE1 A_CE2 A_RDY A_REG 78 102 PCI_VCC 5V_VCC J5 5V 1 GND GND GND GND GND GND GND GND C J6 AVCC A_VPP_PGM A _ V P P _ VCC A _ V C C_3 A _ V C C_5 2 AVCC 1 LINK ETCH J9 26 177 137 91 56 44 28 14 2 BVCC 1 LINK ETCH |LINK |6729SA.SCH |6729SB.SCH |6729P.SCH |6729PCI.SCH 6 7 29 D Cirrus Logic Inc. Title P D 6 7 2 9 Pin Interface AD[15..0] Size B Date: 5 2 LINK ETCH AVCC 127 128 129 130 A A [ 2 5 . .0] 4 C33 0.1uF C O N3A 2 3 5V C27 0.1uF BVCC CON2 1 PCI_VCC BVCC IRQ3/INTA# IRQ4/INTB# IRQ5/INTC# IRQ7/INTD# IRQ9 IRQ10 IRQ11 IRQ12 IRQ14/EXT_CLK IRQ15 NC NC NC IR3 IR4 IR5 IR7 IR9 IR10 IR11 IR12 IR14 IR15 A RESET A -WAIT A -INPACK A VS1 A VS2 A WP/-IOIS16 A -IORD A -IOWR A -OE A -WE A BVD1/-STSCHG A BVD2/-SPKR A -CD1 A -CD2 A -CE1 A -CE2 A RDY/-IRQ A -REG PAR SERR# PERR# C/BE C/BE C/BE C/BE A B_RESET B _ WAIT B_INPACK B_VS1 B_VS2 B_WP B_IORD B_IOWR B_OE B_WE B_BVD1 B_BVD2 B_CD1 B_CD2 B_CE1 B_CE2 B_RDY B_REG A_D0 A_D1 A_D2 A_D3 A_D4 A_D5 A_D6 A_D7 A_D8 A_D9 A_D10 A_D11 A_D12 A_D13 A_D14 A_D15 C/BE3# C/BE2# C/BE1# C/BE0# B RESET B -WAIT B -INPACK B VS1/GPIO1 B VS2/GPIO2 B WP/-IOIS16 B -IORD B -IOWR B -OE B -WE B BVD1/-STSCHG B BVD2/-SPKR B -CD1 B -CD2 B -CE1 B -CE2 B RDY/-IRQ B -REG 184 186 189 156 182 201 158 160 155 168 194 192 142 202 151 154 170 140 C O N3A 119 121 123 65 67 69 71 73 120 122 124 68 70 72 74 76 35 34 33 C31 0.1uF U? B_VPP_PGM B_VPP_VCC B -VCC_3 B -VCC_5 PD6729 BVCC C32 0.1uF B SOCKET VCC B SOCKET VCC A_A0 A_A1 A_A2 A_A3 A_A4 A_A5 A_A6 A_A7 A_A8 A_A9 A_A10 A_A11 A_A12 A_A13 A_A14 A_A15 A_A16 A_A17 A_A18 A_A19 A_A20 A_A21 A_A22 A_A23 A_A24 A_A25 PAR SERR# PERR# AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 A D 10 A D 11 A D 12 A D 13 A D 14 A D 15 A D 16 A D 17 A D 18 A D 19 A D 20 A D 21 A D 22 A D 23 A D 24 A D 25 A D 26 A D 27 A D 28 A D 29 A D 30 A D 31 117 115 114 112 110 108 106 104 86 84 77 82 101 88 90 99 97 87 89 92 94 96 98 100 103 105 C 57 55 54 53 52 51 49 48 46 45 43 42 41 40 39 38 24 23 22 20 19 18 17 16 12 11 10 9 8 7 5 4 CORE VDD +5V 6 21 37 50 PCI VCC PCI VCC PCI VCC PCI VCC AD[31..0] B AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AVCC B D [ 1 5..0] BD15 BD14 BD13 BD12 BD11 BD10 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 PCI_VCC AD[31..0] 8 B A [25..0] CORE_VCC A 7 6 Document Number CL-PD6729 Demo Board T u e s d a y , D e c e m b e r 0 5, 1995S h e e t 7 Rev 1.1 1 of 8 5 1 2 AVCC 3 4 5 6 7 8 AVCC 5V_VCC J7 C39 0.1uF R26 100K AD3T AD5T AD7T ACE1 AOE A A 11 AA8 A A 14 AWE AVCC AVPP A A 16 A A 15 AA7 AA5 AA3 AA2 AA0 AD1T AWP J14 AVPP A 1 2 3 A V PP C38 0.1uF AVS1 CON3A J13 1 2 3 AVS2 CON3A A A [ 2 5 ..0] AD[15..0] AA[25..0] 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 AD4T AD6T AA10 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 A AA9 AA13 ARDY AVCC AA12 AA6 AA4 120 120 120 120 120 120 120 120 R10 R11 R12 R14 R15 R16 R17 R42 AD0 AD1 AD2 AD7 AD5 AD6 AD4 AD3 AD0T AD1T AD2T AD7T AD5T AD6T AD4T AD3T AA1 AD0T AD2T C O N 40A AD[15..0] CON1 B C AA0 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 29 28 27 26 25 24 23 22 12 11 8 10 21 13 14 20 19 46 47 48 49 50 53 54 55 56 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 30 31 32 2 3 4 5 6 64 65 66 37 38 39 40 41 D A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 CE1 CE2 WE OE IORD IOWR BVD1 BVD2 WP/IOIS16 RDY/BSY RESET WAIT INPACK REG CD1 CD2 VS1 VS2 VCC VCC VPP VPP D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 GND GND GND GND B 7 42 15 9 44 45 ACE1 ACE2 AWE AOE AIORD AIOWR A _ CE1 A _ CE2 A_W E A_OE A_IORD A_IOWR 63 62 33 16 58 59 60 61 ABVD1 ABVD2 AWP A R E S ET A R E S ET AWAIT AINP AREG A_BVD1 A_BVD2 A_W P A_RDY A_RESET A_WAIT A_INP A_REG 36 67 ACD1 ACD2 A_CD1 A_CD2 43 57 AVS1 AVS2 C35 CAP J8 ACD1 A D 1 1T A D 1 3T A D 1 5T ACE2 AIORD AIOWR AA18 AA20 ARDY AVCC AA22 AA24 AWAIT AINP ABVD2 AD8T A D 1 0T ACD2 A_VS1 A_VS2 17 51 AVCC 18 52 AVPP 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 A D 1 2T A D 1 4T A A 17 A A 19 A A 21 AVPP AD10 AD8 AD15 AD13 R18 R19 R20 R21 120 120 120 120 AD10T AD8T AD15T AD13T AD11 AD14 AD12 R23 R24 R25 120 120 120 AD11T AD14T AD12T A A 23 A A 25 ARESET AREG ABVD2 AD9 C C O N 4 0A C34 CAP 1 34 35 68 D S L OT-68 Cirrus Logic, Inc. Title P C M C I A S o c k e t A Interface Size B Date: 1 2 3 4 5 6 Document Number CL-PD6729 DEMO BOARD T u e s d a y , D e c e m b e r 0 5, 1995S h e e t 7 Rev 1.0 2 of 8 5 1 2 BVCC C29 0.1uF R13 100K 3 4 5 6 7 8 B V CC BVPP BVPP C28 0.1uF A A B A [25..0] B D [ 15..0] BA[25..0] BD[15..0] CON2 BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 BA8 BA9 BA10 BA11 BA12 BA13 BA14 BA15 BA16 BA17 BA18 BA19 BA20 BA21 BA22 BA23 BA24 BA25 B BD0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 BD8 BD9 BD10 BD11 BD12 BD13 BD14 BD15 C 29 28 27 26 25 24 23 22 12 11 8 10 21 13 14 20 19 46 47 48 49 50 53 54 55 56 30 31 32 2 3 4 5 6 64 65 66 37 38 39 40 41 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 CE1 CE2 WE OE IORD IOWR BVD1 BVD2 WP/IOIS16 RDY/BSY RESET WAIT INPACK REG CD1 CD2 VS1 VS2 VCC VCC VPP VPP D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 7 42 15 9 44 45 B_CE1 B_CE2 B_OE B_WE B_IORD B_IOWR 63 62 33 16 58 59 60 61 B_BVD1 B_BVD2 B_WP B_RDY B_RESET B _ WAIT B_INPACK B_REG 36 67 43 57 BVS1 BVS2 17 51 BVCC 18 52 BVPP B 5V_VCC J12 1 2 3 BVS1 B_CD1 B_CD2 C O N3A B_VS1 B_VS2 1 2 3 J11 BVS2 C O N3A C GND GND GND GND 1 34 35 68 S L OT-68 D D Cirrus Logic, Inc. Title P C M C I A S o c k et B Interface Size B Date: 1 2 3 4 5 6 Document Number CL-PD6729 DEMO BOARD T u e s d a y , D e c e m b e r 0 5, 1995S h e e t 7 Rev 1.0 3 of 8 5 1 2 5V_VCC 3 4 5V_VCC Q1A SI9953DY 8 3 A _ V C C_5 6 8 5V_VCC BVCC B_VCC_5 A_SLOT_VCC R3 470 B _ S L O T _VCC A B_VCC_3 Q2B 3 6 8 SI9953DY 2 2 3V AVCC 3V C3 10uF 1 Q4A 1 8 6 SI9953DY Q2A SI9953DY D1 LED BVCC 4 A _ V C C_3 4 A 7 4 BVCC 6 Q1B SI9953DY 2 1 5 C9 10uF 3 5V_VCC LED J15 Q4B SI9953DY 1 2 3 4 5 6 7 8 9 10 POWER CONTROL VCC 3.3 VOLT OR 5 VOLT SWITCH 20 19 18 17 16 15 14 13 12 11 (OPTIONAL) SPARE LED CIRCUIT ATA MODE ONLY B B SPARE 20 PIN 5V_VCC 12V_VCC U1 1 2 3 4 5 6 7 A _ VPP A_SLOT_VCC B _ S L O T_VCC B_VPP VPPOUT1 NC + V C C1 VPPIN + V C C2 GND VPPOUT2 VDD HI-Z/LOW1 EN0-1 EN1-1 HI-Z.LOW2 EN0-2 EN1-2 14 13 12 11 10 9 8 A _ V P P _ VCC A_VPP_PGM 5V_VCC 10uF J1 SPKR MIC2558 C C5 B _ VPP_VCC B_VPP_PGM 1 2 R1 3 4 10K POT AVPP A V PP BVPP GAIN 1 GAIN 2 -INPUT BYPASS +INPUT VS GND VOUT 8 C6 22uF 6 C7 C11 10uF BVPP C10 10uF LS1 5 22uF C4 0.05uF LM386 C23 1.0uF C 7 C22 0.1uF SPEAKER R4 15 (OPTIONAL) POWER CONTROL VPP 5 VOLT OR 12 VOLT SWITCH SPEAKER CIRCUIT D D Note: The CL-PD6720-A-DM1-2 EVAL board uses the 12V supplied from the ISA bus as the 12V input for the VPP circuit. CIRRUS LOGIC, INC. PCMCIA 2.01 specification Title requires a VPP voltage level of 12V +\- 5%. In actual applications we suggest P O W E R CONTROL LOGIC that the designer use a 12V regulator circuit to guareent that the VPP voltage is Size B Document Number CL-PD6729 DEMO BOARD Rev 1.1 within the PCMCIA 2.01 specification. Date: 1 2 3 4 5 6 T u e s d a y , D e c e m b e r 0 5, 1995S h e e t 7 4 of 8 5 1 2 3 4 5 6 7 8 ADD IN CONFIGURATION 25 WATT MAX. PRSNT#1 (pin B9) GND PRSNT#2 (pin B11) OPEN 3V_SYS 3V_SYS 3V 12V_VCC Q5 2N6034 A J25 INTB# INTD# CLK REQ# AD31 AD29 AD27 AD25 B C/BE3# AD23 AD21 AD19 AD17 C/BE2# IRDY# DEVSEL# PERR# SERR# C/BE1# AD14 AD12 AD10 C AD8 AD7 AD5 AD3 AD1 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 KEYWAY A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 KEYWAY A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 AD[31..0] 3 R6 AD[31..0] J2 VIN C25 0.1uF R7 1K 10K ADJ 12V_VCC U2 LM317T VOUT 1 2 3 2 C O N3A 1 5V_VCC A R9 240 C12 10uF INTA# INTC# 5V_VCC C26 1.0uF R5 Q3 2N4401 R8 390 R2 1K 4.7 K RST# D2 GNT# 2.1V ZEINER AD30 AD28 AD26 B NOTE: INSTALL EITHER R2 OR R8 DO NOT INSTALL BOTH RESISTORS AD24 IDSEL AD22 AD20 AD18 AD16 3.3V Volt Regulator FRAME# T R DY# STOP# PAR AD15 AD13 AD11 5V_VCC C J16 AD9 1 CLK 14 5V_VCC J17 C/BE0# AD6 AD4 7 CON4 AD2 AD0 8 3 2 1 PCI_CLK C36 0.1uF CON3A PCI CONN EXTERNAL CLOCK SOURCE D D CIRRUS LOGIC, INC. 3V 3V 3V 3V_SYS 3V_SYS 12V_VCC 12V_VCC 5V_VCC 5V_VCC 5V_VCC 5V_VCC 5V_VCC 5V_VCC Title ISA BUS INTERFACE C2 10uF C8 10uF C20 0.1uF C16 10uF C17 0.1uF C14 10uF C21 0.1uF C1 10uF C13 10uF C15 10uF C18 0.1uF C24 0.1uF C37 0.1uF Size B Date: 1 2 3 4 5 6 Document Number CL-PD6729 DEMO BOARD T u e s d a y , D e c e m b e r 0 5, 1995S h e e t 7 Rev 1.0 5 of 8 5