Transcript
11/17/2009 16:00
PDL-MF
PowerDAQ Lab PCI Multifunction Board
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• 16 single-ended/16 pseudo-differential or 8 differential A/D channels • 16-bit, 50 kS/s sampling rate • Two 12-bit analog outputs; 48 digital I/O lines; three 24-bit counter/timers • Simultaneous operation of all susbsystems • 64 entries in channel-gain list; programmable gains: 1, 2, 5, 10 • Stream-to-disk capability Supports UEIDaq Framework Data Acquisition Software Library for Windows. Linux and QNX drivers available. Visit our website for more details.
General Description:
The data-acquisition community has come to appreciate the power and flexibility of the architecture in the PowerDAQ II family of PCI data acquisition cards. They’ve also come to value the easy programming this architecture affords as well as the extensive support software that accompanies each board. Now UEI is making it even easier for users to take advantage of these features by lowering the entry-level price. This comes with the most recent member of the PCI-bus PowerDAQ family: the PowerDAQ Lab card. Not only does this latest member drop the price considerably over the previous member with similar functionality, it does so in a short-slot card, making it suited for positioning in chassis slots shortened by peripherals or in laptop PCs with limited slot sizes. Nonetheless, it does not sacrifice on any of the functionality users have come to expect in a PowerDAQ card, because this multifunction card supplies a full complement of analog I/O as well as digital I/O - and all these subsystems can run simultaneously.
Technical Specifications: Analog Inputs Resolution Number of channels: Single-Ended Pseudo-Differential Differential Max. sampling rate Onboard FIFO Channel gain list Input ranges Max working voltage for AIn single-ended differential pseudo-differential Programmable gains Drift Zero Gain Input impedance Input bias current Input Overvoltage A/D conversion time A/D settling time DC Accuracy Nonlinearity System noise AC Accuracy Effective number of bits Channel crosstalk Clocking and Trigger Input Max. A/D pacer clock aggregate throughput @ 0.01% accuracy External A/D sample clock maximum frequency Minimum pulse width External digital (TTL) trigger: High-level input voltage Low-level input voltage Minimum pulse width Digital trigger United Electronic Industries, Inc. Tel: (508) 921-4600
Analog Outputs Number of channels Resolution Update rate Onboard FIFO
16 bit 16 16 8 50 kS/s 1k samples 64 entries 0-10V, ±5V, ±10V (softw. selectable)
Analog output range Current output Output impedance Capacitive drive capability Nonlinearity Protection Power-on voltage Settling time to 0.01% of FSR Slew rate Digital I/O Input channels Output channels High-level input voltage Low-level input voltage High-level input current Low-level input current Output driver high voltage Output driver low voltage Current sink
±10V ±13V (signal + common mode) ±13V (signal + EXT_GND) 1, 2, 5, 10 ±30 µV/°C ±30 ppm/°C 10MΩ ±20 nA ±35V cont., 10mA max 2 µs 4.1 µs (@ g=1) ±1 LSB 1.2 LSB 14.8 -80 dB @ 1kS/s
Counter/Timer Number of channels Resolution Max frequency
50 kS/s
Min frequency 50 kHz Min pulse width Output high level Output low level Protection Input low voltage Input high voltage
20 ns 2.0V min 0.8V min 20 ns start/stop 1
2 12 bits 100 kS/s each 2k samples; 64k samples with PD-64KMEM upgrade option ±10V ±20 mA max 0.3Ω typ 1000 pF ±1 LSB short circuit to analog ground 0V ±10 mV 10µs, 20V step; 1µs, 100mV step 30 V/µs 24 24 2.0V min 0.8V max 20 µA -20 µA 2.5V min, 3.0V typ (IOH = -32mA) 0.55V max (IOL = 64mA) -32/64 mA max, lines 8-16 -24/24 mA max, lines 0-7 250mA per port 3 24 bits 16.5 MS/s for external clock, 33 MS/s for internal DSP clock 0.00002 Hz for internal clock, no low limit for external clock 20 ns 2.0V min @ -4 mA 0.5V min @ 4 mA 7 kV ESD, ±30V over/undershoot 0.0 - 0.8V 2.0 - 5.0V
http://www.ueidaq.com Fax: (508) 668-2350
PDL-MF - PowerDAQ Lab PCI Multifunction Data Acquisition Card
Block Diagram:
Pinout Diagrams: Analog Input Calibration DACs
Voltage Reference
Analog Input Power Conditioner
+
16 Channel Analog Multiplexer
PGIA Gain Amp.
Counter/Timers
Ext. Trigger Ext. Aln Clock In Aln Clock Out
Remote Ground
16
16-bit Sampling A/D Converter
-
J6 24
24
Aln Control
Control & Timing Logic
DAC0
Address
DAC1
Analog Output Calibration DACs
DIn Control
DOut Control
Local Data Bus
Control
Digital Output (Driver) Configuration & Calibration EEPROM
Motorola 66MHz DSP 56301
Voltage Reference
Digital Input Buffer Latch
Addr/Data
Analog Output Amplifiers
J1 — 100-pin connector (female):
J1
100-pin Connector
J1
AIN8 AGND AIN9 AGND AIN10 AGND AIN11 AGND AIN12 AGND AIN13 AGND AIN14 AGND AIN15 AGND AOUT0 AGND DIN1 DIN3 DIN5 DIN7 DIN9 DIN11 DIN13 DIN15 DGND DIN17 DIN19 DIN21 DIN23 DOUT1 DOUT3 DOUT5 DOUT7 DGND DOUT9 DOUT11 DOUT13 DOUT15 DOUT17 DOUT19 DOUT21 DOUT23 DGND EXT_TRIG_IN CV_OUT EXT_TRIG_OUT CL_OUT EXT_CLK
1 51 2 52 3 53 4 54 5 55 6 56 7 57 8 58 9 59 10 60 11 61 12 62 13 63 14 64 15 65 16 66 17 67 18 68 19 69 20 70 21 71 22 72 23 73 24 74 25 75 26 76 27 77 28 78 29 79 30 80 31 81 32 82 33 83 34 84 35 85 36 86 37 87 38 88 39 89 40 90 41 91 42 92 43 93 44 94 45 95 46 96 47 97 48 98 49 99 50 100
AIN0 AGND AIN1 AGND AIN2 AGND AIN3 AGND AIN4 AGND AIN5 AGND AIN6 AGND AIN7 EXT_GND AOUT1 AGND DIN0 DIN2 DIN4 DIN6 DIN8 DIN10 DIN12 DIN14 DGND DIN16 DIN18 DIN20 DIN22 DOUT0 DOUT2 DOUT4 DOUT6 +5VPJ2 DOUT8 DOUT10 DOUT12 DOUT14 DOUT16 DOUT18 DOUT20 DOUT22 DGND TMR2 DGND TMR1 DGND TMR0
J6 — 3-pin jumper header: 3 2 1
32-bit PCI Bus
Connection Schemes: Connector On The Board J1
Cable Required PDL-CBL-100*
Target Panel PDL-STP
Description Carries 16 analog input lines, 2 analog output lines, 24 digital input and 24 digital output lines, 3 counter/timer lines to terminal panel. PDL-STP allows further connection to 5B signal conditioning panel (for analog input signals).
* Pins 1 - 50 from PDL-MF’s J1 connector are transfered to the first 50-pin IDC header of PDL-CBL-100 cable without remapping (pin-to-pin number match). Remaining 51 - 100 pins are transfered to the second 50-pin IDC header as follows: 51 to 1, 52 to 2, ... 99 to 49, 100 to 50.
Analog Input Configuration: Configuration is performed using J6 jumpers. J6 Jumper Position 3 2 1
3 2 1 (default)
Analog Input Configuration pseudo-differential single-ended differential
Ordering Information: Part Number PDL-MF-333 PDL-STP PDL-CBL-100 PD-64KMEM PDL-MF-CONN
Description 333 kS/s; 16-bit; 16SE/16PDI or 8DI; gains: 1, 2, 5, 10; 2 DAs; 3 counter/timers; 48 digital I/O 16-channel screw-terminal panel with two 50-way headers. 18-inch, 100-way, “Y“-split flat ribbon cable for connecting PDL-MF board to PDL-STP terminal panel. DSP FIFO upgrade to 64k samples 100-pin connector assembly (male) for direct connection to PDL-FM board
United Electronic Industries, Inc. Tel: (508) 921-4600
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http://www.ueidaq.com Fax: (508) 668-2350
