Transcript
Per Pin Parametric Measurement Unit/Source Measure Unit AD5520 FEATURES
GENERAL DESCRIPTION
Force/measure functions FIMV, FVMI, FVMV, FIMI, FNMV Force/measure voltage range ±11 V 4 user programmable force/measure current ranges ±4 μA, ±40 μA, ±400 μA, ±4 mA (external resistors) 2 user programmable extended current ranges Up to 6 mA without external driver Higher currents with external driver Clamp circuitry and window comparators on board Guard amplifier 64-lead LQFP package
The AD5520 is a single-channel, per pin parametric measurement unit (PPMU) for use in semiconductor automatic test equipment. The part is also suited for use as a source measurement unit for instrumentation applications. It contains programmable modes to force a pin voltage and measure the corresponding current, or force a current and measure the voltage. The AD5520 can force/measure over a ±11 V range or user-programmable currents up to ±4 mA with its on-board force amplifier. An external amplifier is required for wider current ranges. The device provides a force sense capability to ensure accuracy at the tester pin. A guard output is also available to drive the shield of a force/sense pair. The AD5520 is available in a 64-lead LQFP package.
APPLICATIONS Automatic test equipment Per pin PMU, shared pin PMU, device power supply instrumentation Source measure, parametric measurement, precision measurement
COMPOUT1
COMPOUT2
COMPOUT0
COMPIN2
AD5520
COMPIN1
COMPIN0
FUNCTIONAL BLOCK DIAGRAM AVEE AVCC
FOH
BW SELECT
FOH3 FOH2
FIN
FOH1 FOH0 MEASI5H CLAMP DETECT
MEASI4H MEASI3H MEASI2H
CLH
MEASI1H
CLL
MEASI0H
REFGND G = 16
MEASIOUT
MEASIL
ISENSE INST AMP VSENSE INST AMP
MEASOUT
GUARDIN G=1
MEASVOUT COMPARATOR CPH
MEASVL
CPOH
AGND QM5
03701-001
DGND
CS DVDD
QM4 AC0 AC1
CLLDETECT
MOE
CLHDETECT
AM0
AM1
AM2
MSEL
FSEL
CPSEL
CPCK
STB
CPL
STANDBY
LOGICS CPOL
GUARD MEASVH
G=1
Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
AD5520 TABLE OF CONTENTS Features .............................................................................................. 1
Force Control Amplifier............................................................ 15
Applications....................................................................................... 1
Comparator Function and Strobing ........................................ 15
General Description ......................................................................... 1
Clamp Function.......................................................................... 15
Functional Block Diagram .............................................................. 1
High Current Ranges ................................................................. 15
Specifications..................................................................................... 3
Circuit Operation ........................................................................... 16
Timing Characteristics..................................................................... 6
Force Voltage............................................................................... 16
Absolute Maximum Ratings............................................................ 7
Measure Current......................................................................... 16
ESD Caution.................................................................................. 7
Force Current.............................................................................. 17
Pin Configuration and Function Descriptions............................. 8
Measure Voltage ......................................................................... 17
Typical Performance Characteristics ........................................... 10
Short Circuit Protection ............................................................ 17
Theory of Operation ...................................................................... 13
Settling Time Considerations ....................................................... 18
Interface ........................................................................................... 14
PCB Layout and Power Supply Decoupling................................ 19
Standby Mode ............................................................................. 14
Typical Connection Circuit for the AD5520 .............................. 20
Force Voltage or Force Current ................................................ 14
Typical Application Circuit ........................................................... 21
Measured Parameter .................................................................. 14
Evaluation Board for the AD5520................................................ 22
Current Ranges ........................................................................... 14
Outline Dimensions ....................................................................... 24
RS Selection.................................................................................. 14
Ordering Guide .......................................................................... 24
REVISION HISTORY 9/05—Rev. A to Rev. B Updated Format..................................................................Universal Changes to Features.......................................................................... 1 Changes to Figure 1.......................................................................... 1 Changes to Specifications ................................................................ 3 Changes to Force Current Section................................................ 17 Changes to Figure 26 ..................................................................... 20 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24
10/03—Rev. 0 to Rev. A Changes to Specifications.................................................................3 Updated Ordering Guide .................................................................5 9/03—Revision 0: Initial Version
Rev. B | Page 2 of 24
AD5520 SPECIFICATIONS AVCC = +15 V ± 5%, AVEE = −15 V ± 5%, DVDD = 5 V ± 10%, AGND = 0 V, REFGND = 0 V, DGND = 0 V. All specifications 0°C to 70°C, unless otherwise noted. Table 1. Parameter VOLTAGE FORCE MODE Force Control Output Voltage Range FOH Output Impedance FOH0 FOH1 FOH2 FOH3 Input Offset Error Input Offset Error Temperature Coefficient Gain Error Clamp Current Error 2 CURRENT MEASURE/FORCE FOH0 FOH1 FOH2 FOH3 CURRENT MEASURE MODE High Sense Input Range, VMEASIxH Linearity 3 Input Bias Current Input Bias Current Drift1 Output Offset Error
Output Offset Error Temperature Coefficient Gain Error Gain Error Temperature Coefficient 4 MEASIOUT Output Load Current CMRR CURRENT FORCE MODE Input Offset Error Gain Error Clamp Voltage Error2 VOLTAGE MEASURE MODE Differential Input Range Low Sense Input Voltage Range Linearity3 Input Offset Error Input Offset Error Temperature Coefficient1 Gain Error Gain Error Temperature Coefficient4 Input Bias Current Input Bias Current Drift4 MEASVOUT Output Load Current CMRR4
Min
Typ 1
Max
±11 70 2.5 3 500 60 ±1 ±10
±5 1 ±1
±4 ±40 ±400 ±4
±1 50
±11 ±0.01 ±3
±0.35
V Ω kΩ kΩ Ω Ω mV μV/°C % % FS
RLOAD = 10 kΩ, CLOAD = 50 pF
V % FSR nA pA/°C mV mV mV mV μV/°C % ppm/°C mA dB
±10 1 ±1
mV % % FS
±11
V mV % FSR mV μV/°C % ppm/°C nA pA/°C mA dB
±100 ±5 ±15 ±0.03 2 ±1 50 ±4 73
Test Conditions/Comments
μA μA μA mA
±100 ±100 ±100 ±100 ±10 ±0.1 30 ±4 95
Unit
+0.005 ±10 ±0.15 ±3
Rev. B | Page 3 of 24
of FIN Suggested values; set with external sense resistors MODE0, RS = 125 kΩ MODE1, RS = 12.5 kΩ MODE2, RS = 12.5 kΩ MODE3, RS = 125 Ω
+11 V > VFOL > −11 V
MODE0 (±4 μA) MODE1 (±40 μA) MODE2 (±400 μA) MODE3 (±4 mA) Gain of 16
@ DC with MODE0, MODE1, MODE2, MODE3 of FIN
MEASVL +11 V > VMEASVH to VMEASVL > −11 V FIN = 0 V, measured @ MEASVOUT Gain of 1
@ DC
AD5520 Parameter AMPLIFIER SETTLING TIME4, 5 VSENSE Amp ISENSE Amp LOOP SETTLING4, 5 COMPIN2 = 100 pF
Min
Max
20 12 450 285 170 2 1.8 5.75 50 4.3 1.28
COMPIN1 = 1000 pF COMPIN0 = 3000 pF SLEW RATE4, 5
COMPARATOR CPH, CPL Input Range Input Offset GUARD DRIVER Output Voltage Output Impedance Output Offset Voltage Load Current4 Output Settling Time4 ANALOG REFERENCE INPUTS Force Control Input Range Force Control Input Impedance Clamp Control Input Range Clamp Control Input Impedance Comparator Threshold Input Range Comparator Threshold Input Impedance Input Capacitance4 LEAKAGE CURRENT MEASIxx, MEASVx, MEASOUT Leakage ANALOG MEASUREMENT OUTPUTS Voltage Measure Output Impedance Current Measure Output Impedance Multiplexed Sense Output Impedance Input Capacitance MEASIxH, MEASVH, FOHx LOGIC INPUTS Input Current Input Low Voltage, VINL Input High Voltage, VIHL Input Capacitance4 LOGIC OUTPUTS Output Low Voltage, VOL4 Output High Voltage, VOH4
Typ 1
130 400 ±4 0.5
Unit
Test Conditions/Comments
μs μs
to 0.2% to 0.2% Settling to within 0.024% of 8 V step MODE0 MODE1 MODE2, MODE3 MODE0 MODE1, MODE2, MODE3 MODE0, MODE1, MODE2, MODE3 COMPIN2 = 100 pF COMPIN1 = 1000 pF COMPIN0 = 3000 pF
600 390 240 2.5 2.4 8.7
μs μs μs ms ms ms mV/μs mV/μs mV/μs
±11 ±7
V mV
±11
V Ω mV mA μs
2
±11
V MΩ V MΩ V MΩ pF
1 ±11 1 ±11 1 3 ±3
±20
VCPH > VCPL
Capacitive load only
100 pF capacitive load
VCLH > VCLL
nA
2 3 1
Ω Ω kΩ
8
pF ±1 0.8
μA V V pF
All digital inputs together
0.4
V V
ISINK = 2 mA ISOURCE = 2 mA
2.0 3
2.4
Rev. B | Page 4 of 24
AD5520 Parameter POWER REQUIREMENTS AVCC AVEE Power Supply Rejection Ratio, PSRR1 FOH
MEASOUT DC PSR DVDD IAVCC IAVEE IDVDD
Min
Typ 1
Max
Unit
Test Conditions/Comments
14.25 −14.25
15 −15
15.75 +15.75
V V
for specific performance 6
100 kHz 500 kHz 1 MHz 100 kHz 500 kHz
12 12 0.5
dB dB dB dB dB dB V mA mA mA
−25 −16 −15 −55 −10 90 5
1
Typical values are at 25°C and nominal supply, unless otherwise noted. Full-scale = 11 V. Full-scale range = 22 V. 4 Guaranteed by design and characterization, but not subject to production test. 5 Force control amplifier dominates slew rate and settling time. 6 Operational with ±12 V supplies, force/measure range is reduced to ±8.5 V. 2 3
Rev. B | Page 5 of 24
Digital inputs at supply rails
AD5520 TIMING CHARACTERISTICS AVCC = +15 V ± 5%, AVEE = −15 V ± 5%, AGND = 0 V, REFGND = 0 V, DGND = 0 V. All specifications 0°C to 70°C, unless otherwise noted. 1, 2 Table 2. DVDD Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13
Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min μs min ns min ns min ns min
Conditions/Comments CS falling edge to STB falling edge setup time STB pulse width STB rising edge to CS rising edge setup time Data setup time CS falling edge to CPCK rising edge setup time CPCK pulse width CPCK to STB falling edge setup time STB rising edge to QMx, CLxDETECT valid STB rising edge to CPOH, CPOL valid Comparator setup time, MODE2, MODE3 settling Comparator hold time Comparator output delay time Comparator strobe pulse width
See Figure 2. All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
CS
t1
t2
t3
STB
t4 AMx, ACx, FSEL, MSEL, CPSEL
t5
t6
t7
CPCK
t6
t9
QM4, QM5, CLHDETECT, CLLDETECT
03701-002
2
3.3 V 0 200 70 40 560 320 500 800 440 240 500 440 320
CPOL, CPOH
Figure 2. Timing Diagram
t11
MEASVOUT OR MEASIOUT CPCK
CPOH, CPOL
t13
t10 t12
Figure 3. Comparator Timing
Rev. B | Page 6 of 24
03701-003
1
5 V ± 10% 0 30 40 0 550 320 450 150 100 240 150 100 320
AD5520 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVCC to AVEE AVCC to AGND AVEE to AGND DVDD Digital Inputs to DGND Analog Inputs to AGND CLH to CLL CPH to CPL REFGND, DGND Operating Temperature Range Commercial (J Version) Storage Temperature Range Maximum Junction Temperature, (TJ max) Package Power Dissipation Thermal Impedance θJA Lead Temperature (Soldering 10 sec) IR Reflow, Peak Temperature
Rating 34 V −0.3 V, +17 V +0.3 V, −17 V −0.3 V to +6 V −0.3 V to DVDD + 0.3 V AVCC + 0.3 V to AVEE – 0.3 V −0.3 V to +34 V −0.3 V to +34 V AVCC + 0.3 V to AVEE – 0.3 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
0°C to 70°C −65°C to +150°C 150°C (TJ max – TA)/θJA 47.8°C /W 300°C 220°C
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. B | Page 7 of 24
AD5520
64 63 62 61 60 59 58
FOH
AVCC_B
COMPOUT0
COMPOUT1
COMPOUT2
COMPIN0
COMPIN1
COMPIN2
REFGND
MEASOUT
REFGND
MEASIOUT
MEASVOUT
FIN
CLH
CLL
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
57 56 55 54 53 52 51 50 49
CPH
1
CPL
2
48 AVEE_B
DVDD
3
46 MEASI4H
CPOH
4
45 FOH3
CPOL
5
44 MEASI3H
CPCK
6
DGND
7
CLHDETECT
8
CLLDETECT
9
PIN 1
47 MEASI5H
43 FOH2
AD5520
42 MEASI2H
TOP VIEW (Not to Scale)
41 FOH1 40 MEASI1H
QM4 10
39 FOH0
QM5 11
38 MEASI0H
MOE 12
37 MEASIL
CS 13
36 MEASVH
STB 14
35 GUARD(NC)
AC0 15
34 MEASVL
AC1 16
33 AVCC_G
03701-004
GUARDIN
NC
GUARD
AVEE_G
AGND
AVCC
AVEE
CPSEL
MSEL
FSEL
STANDBY
AM0
AM1
AM2
DVDD
NC = NO CONNECT
DGND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions Pin No. 1 2 3, 18 4 5 6 7, 17 8 9 10
Mnemonic CPH CPL DVDD CPOH CPOL CPCK DGND CLHDETECT CLLDETECT QM4
11
QM5
12 13 14
MOE CS STB
15
AC0
16
AC1
19
AM2
20
AM1
21
AM0
22
STANDBY
Description Upper Comparator Threshold Voltage Input, CPH > CPL. Lower Comparator Threshold Voltage Input, CPL < CPH. Digital Supply Voltage. Logic Output. When high, indicates MEASVOUT or MEASIOUT > CPH. Logic Output. When high, indicates MEASVOUT or MEASIOUT < CPL. Logic Input. Used to initiate comparator sampling and update CPOH and CPOL. Digital Ground. Logic Output. When high, indicates upper clamp active. See the Clamp Function section. Logic Output. When high, indicates lower clamp active. See the Clamp Function section. Logic Output. When high, indicates current range Mode 4 is enabled. May be used to drive external relay or switch. See the High Current Ranges section. Logic Output. When high, indicates current range Mode 5 is enabled. May be used to drive external relay or switch. See the High Current Ranges section. Active Low MEASOUT Enable. Active Low Logic Input. The device is selected when this pin is low. See the Interface section. Active Low Logic Input. Used in conjunction with CPCK and CS to configure the device for different configurations. Rising edge of STB triggers sequence inputs. See the Interface section. Logic Input. Used in conjunction with AC1 to select one of three external compensation capacitors. See the Force Control Amplifier section. Logic Input. Used in conjunction with AC0 to select one of three external compensation capacitors. See the Force Control Amplifier section. Logic Input. Used in conjunction with AM1 and AM0 to select one of six current ranges or to enable standby mode. See the Current Ranges section. Logic Input. Used in conjunction with AM2 and AM0 to select one of six current ranges or to enable standby mode. See the Current Ranges section. Logic Input. Used in conjunction with AM2 and AM1 to select one of six current ranges or to enable standby mode. See the Current Ranges section. Logic Input. When high, device is in standby mode of operation. See the Standby Mode section. Rev. B | Page 8 of 24
AD5520 Pin No. 23
Mnemonic FSEL
24
MSEL
25
CPSEL
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57, 59 58 60 61 62 63 64
AVEE AVCC AGND AVEE_G GUARD NC GUARDIN AVCC_G MEASVL GUARD(NC) MEASVH MEASIL MEASI0H FOH0 MEASI1H FOH1 MEASI2H FOH2 MEASI3H FOH3 MEASI4H MEASI5H AVEE_B FOH AVCC_B COMPOUT0 COMPOUT1 COMPOUT2 COMPIN0 COMPIN1 COMPIN2 REFGND MEASOUT MEASIOUT MEASVOUT FIN CLH CLL
Description Logic Input. Force mode select. Used to select between current or voltage force operation. See the Force Voltage or Force Current section. Logic Input. Measure mode select. Used to connect MEASOUT to either MEASIOUT when high or MEASVOUT when low. Logic Input. Comparator select. Used to compare CPL, CPH to MEASVOUT when low, or to MEASIOUT when high. See the Comparator Function and Strobing section. Most Negative Supply Voltage. Most Positive Supply Voltage. MEASx Input Ground. Most Negative Supply Voltage. Guard Output. No Connect. Guard Input. Most Positive Supply Voltage. DUT Voltage Sense Inputs (Low Sense). No Connect. DUT Voltage Sense Inputs (High Sense). DUT Current Sense Inputs (Low Sense). DUT Current Sense Inputs (High Sense). Force Control Voltage Output. DUT Current Sense Inputs (High Sense). Force Control Voltage Output. DUT Current Sense Inputs (High Sense). Force Control Voltage Output. DUT Current Sense Inputs (High Sense). Force Control Voltage Output. DUT Current Sense Inputs (High Sense). DUT Current Sense Inputs (High Sense). Most Negative Supply Voltage. External Force Driver Control Voltage Output. Most Positive Supply Voltage. Compensation Capacitor 0 Output. Compensation Capacitor 1 Output. Compensation Capacitor 2 Output. Compensation Capacitor 0 Input. Compensation Capacitor 1 Input. Compensation Capacitor 2 Input. Analog Input/Output Reference Ground. Multiplexed DUT Voltage/Current Sense Output. See the Measured Parameter section. DUT Current Sense Output. DUT Voltage Sense Output. Force Control Voltage Input. Upper Clamp Voltage Input CLH > CLL. Lower Clamp Voltage CLL < CLH.
Rev. B | Page 9 of 24
AD5520 TYPICAL PERFORMANCE CHARACTERISTICS 0.0030
0.0030 VDD = +15V VSS = –15V MODE 3
0.0025
0.0020
IM LINEARITY (%)
0.0015
0.0010
0.0015
0.0010
0.0005 03701-005
0.0005
0.0020
0 0
10
20
30 40 50 TEMPERATURE (°C)
60
03701-008
VM LINEARITY (%)
0.0025
VDD = +15V VSS = –15V MODE 3
0
70
0
Figure 5. Voltage Sense Amplifier Linearity vs. Temperature
20
30 40 50 TEMPERATURE (°C)
60
70
Figure 8. Current Sense Linearity vs. Temperature
80
140 VDD = +15V VSS = –15V TA = 25°C
70
VDD = +15V VSS = –15V TA = 25°C
120
60
ISENSE CMRR
100
50
CMRR (dB)
40
80
60
30 40
20
20
03701-006
10 0 1
10
100 1k 10k FREQUENCY (Hz)
100k
03701-009
AMPLITUDE (dB)
10
0 1
1M
Figure 6. Voltage Sense Amplifier CMRR vs. Frequency
10
100 1k 10k FREQUENCY (Hz)
100k
1M
Figure 9. Current Sense Amplifier CMRR vs. Frequency
10
5 0
CCOMP = 0.1nF
0
–5 AMPLITUDE (dB)
–20 CCOMP = 1.0nF –30
CCOMP = 0.1nF
–10 –15 CCOMP = 1.0nF
–20 –25
–40 CCOMP = 3.3nF VDD = +15V VSS = –15V TA = 25°C
–60 100
–30
1k
10k FREQUENCY (Hz)
–35
–40 100
100k
Figure 7. Force Amplifier Bandwidth, Mode 0 (4 μA)
CCOMP = 3.3nF
VDD = +15V VSS = –15V TA = 25°C
03701-010
–50
03701-007
AMPLITUDE (dB)
–10
1k
10k FREQUENCY (Hz)
Figure 10. Force Amplifier Bandwidth, Mode 1 (40 μA)
Rev. B | Page 10 of 24
100k
AD5520 0
0 VDD = +15V VSS = –15V TA = 25°C
–5 CCOMP = 0.1nF
–15 –20 CCOMP = 1.0nF
–25 –30
CCOMP = 3.3nF
–40 –45 100
1k
–15 –20 CCOMP = 1.0nF
–25 –30
CCOMP = 3.3nF
–35 03701-011
–35
CCOMP = 0.1nF
–10
AMPLITUDE (dB)
AMPLITUDE (dB)
–10
VDD = +15V VSS = –15V TA = 25°C
10k FREQUENCY (Hz)
03701-014
–5
–40 –45 100
100k
Figure 11. Force Amplifier Bandwidth, Mode 2 (400 μA)
1k
10k FREQUENCY (Hz)
100k
Figure 14. Force Amplifier Bandwidth, Mode 3 (4 mA)
5
30 VDD = +15V VSS = –15V TA = 25°C
0
ISENSE
20
–10
AMPLITUDE (dB)
AMPLITUDE (dB)
–5
–15 –20 –25
10
0
–10
VSENSE
–30
–40 1
10
100
1k 10k 100k FREQUENCY (Hz)
1M
10M
–30 100
100M
Figure 12. Guard Amplifier Bandwidth
1k
10k 100k FREQUENCY (Hz)
1M
10M
Figure 15. Voltage Sense and Current Sense Amplifier Bandwidths
20 10
VDD = +15V VSS = –15V TA = 25°C
03701-015
03701-012
–20 –35
0 VDD = +15V VSS = –15V TA = 25°C
–5
VDD = +15V VSS = –15V TA = 25°C
AMPLITUDE (dB)
–10 –20 –30
–10
–15
–20
–40
–60 100k
1M FREQUENCY (Hz)
–30 100k
10M
Figure 13. Current Sense Amplifier AC PSRR
03701-016
–25
–50
03701-013
AMPLITUDE (dB)
0
1M FREQUENCY (Hz)
Figure 16. Force Amplifier AC PSRR, Mode 3, CCOMP = 100 pF
Rev. B | Page 11 of 24
10M
AD5520 20 10
16 VDD = +15V VSS = –15V TA = 25°C
14 VCC 12 10
–10
VOLTAGE (V)
–20 –30
8 6 4
–40
VDUT
2 03701-017
–50 –60 100k
1M FREQUENCY (Hz)
03701-019
AMPLITUDE (dB)
0
0 –2 0
10M
5
Figure 17. Voltage Sense Amplifier AC PSRR
10
15
20 25 TIME (ms)
30
35
40
45
Figure 19. Power Up
700
9 COMPIN2 = 100pF 8
COMPIN1 = 1000pF
600 GUARD
7
VOLTAGE (V)
6
400 VSENSE
300
200
5 COMPIN2 = 3000pF 4 3 2
FOH
ISENSE 0 10
100
1k FREQUENCY (Hz)
10k
03701-020
1 100
03701-018
nV/√Hz
500
0 –1
100k
0
Figure 18. Noise Spectral Density
0.001
0.002
0.003
0.004 0.005 TIME (s)
0.006
Figure 20. Settling Time, Mode 2
Rev. B | Page 12 of 24
0.007
0.008
AD5520 THEORY OF OPERATION The AD5520 is a single-channel per pin parametric measurement unit (PPMU) for use in semiconductor automatic test equipment. It contains programmable modes to force a pin voltage and measure the corresponding current (FVMI), force current measure voltage (FIMV), force current measure current (FIMI), force voltage measure voltage (FVMV), and force nothing measure voltage (FNMV). The PPMU can force or measure a voltage from −11 V to +11 V. It can force or measure currents up to 6 mA using the internal amplifier, while the addition of an external amplifier enables higher current ranges. External resistors allow users to choose the optimum ranges for their needs.
The AD5520 has an on-board window comparator that provides two bits of useful information, DUT too low or too high. Also provided on the chip is clamp circuitry that flags via CLHDETECT and CLLDETECT if the voltage applied to FIN or across the DUT exceeds the voltage applied to CLL and CLH. On-chip is clamp circuitry that clamps the output of the force amplifier if the voltage at MEASIOUT and MEASVOUT exceeds CLL or CLH.
The device provides a force sense capability to ensure accuracy at the tester pin. A guard output is also available to drive the shield of a force/sense pair.
Rev. B | Page 13 of 24
AD5520 INTERFACE The AD5520 PPMU is controlled via a number of digital inputs, which are discussed in detail in the following sections. All inputs are TTL-compatible. CS is used to select the device while STB (active low input) latches data available on the other digital inputs and updates any required digital outputs. The rising edge of STB triggers sequence inputs. The remaining digital inputs control the function of the PMU. They also determine which measure mode the PMU is in, the compensation capacitor used, and the selected current range.
STANDBY MODE The AD5520 can be placed into standby mode via the standby logic input. In this mode, the force amplifier is disconnected from the force input (FIN). In addition, the switch in series with the force output pins (FOHx) is opened, and the current measure amplifier is disconnected from the sense resistors. The voltage measure amplifier is still connected across the DUT; therefore, DUT voltage measurements may still be made while in standby mode. Figure 21 shows the configuration of the PMU while in standby mode. Table 5. Standby Mode Standby Low High
MEASURED PARAMETER MEASOUT is a muxed output that tracks the sensed parameter. MSEL (digital input) connects the MEASOUT to the output of the current sense amplifier or the voltage sense amplifier, depending on which is the measured parameter of interest. The MEASOUT pin is connected back to an ADC to allow the measured value to be converted to a digital code. Table 7. MEASOUT Connected to Voltage or Current MSEL Low High
Function MEASOUT = DUT Voltage MEASOUT = DUT Current
The MEASOUT pin can also be made high impedance through the MOEB logic input. Table 8. MOEB Allows MEASOUT to Go High Impedance MOEB Low High
Function Enable MEASOUT Output Hi-Z MEASOUT Output
CURRENT RANGES A number of current ranges are possible with the AD5520. The AM0, AM1, and AM2 pins are digital inputs used to establish full-scale current range of the PMU.
Function Normal Force Mode Standby Mode
Table 9. Selection of Current Range DAC
FIN FOHx
G = 16
MEASIOUT
MEASIHx
MEASVH MEASVL
DUT 03701-021
G=1
AM2 Low Low Low Low High
High
Low
High
Low High
High High
High High
Function Current Range MODE0 (4 μA) Current Range MODE1 (40 μA) Current Range MODE2 (400 μA) Current Range MODE3 (4 mA) Current Range MODE4 (External Buffer Mode) Current Range MODE5 (External Buffer Mode) Standby (Same as STANDBY = High) Standby (Same as STANDBY = High)
RS SELECTION
Figure 21. PMU in Standby Mode
FORCE VOLTAGE OR FORCE CURRENT FSEL is an input that determines whether the PPMU forces a voltage or current. Table 6. FSEL Function FSEL Low High
AM1 Low Low High High Low
RS
MEASIL
MEASVOUT
AM0 Low High Low High Low
Function Voltage Force and Current Clamp with MEASIOUT Voltage Current Force and Voltage Clamp with MEASVOUT Voltage
The AD5520 is designed to ensure the voltage drop across each of the RS resistors is less than ±500 mV when maximum current is flowing through them. To support other current ranges, these sense resistor values can be changed. The force amplifier can drive a maximum of 6 mA. It is not recommended to increase the maximum current above the nominal range. The two external current ranges use an external buffer to drive higher current. The example in Figure 26 uses 40 mA and 160 mA ranges. These ranges can be changed to suit user requirements for a high current range.
Rev. B | Page 14 of 24
AD5520 FORCE CONTROL AMPLIFIER
CLAMP FUNCTION
The force control amplifier requires external capacitors connected between the COMPOUTx and COMPINx pins. For stability with large capacitance at the DUT, the largest capacitance value (3000 pF) should be selected. The force control amplifier should always contribute the dominant pole in the control loop. Settling times increase with larger capacitances. ACx inputs select which external compensation capacitor is used.
Clamp circuitry, which is also included on-chip, clamps the force amplifier’s output if the voltage or current applied to the DUT exceeds the clamp levels, CLL and CLH. The clamp circuitry also comes into play in the event of a short or open circuit. When in force current range, the voltage clamps protect the DUT from an open circuit. Likewise, when forcing a voltage and a short circuit occurs, the current clamps protect the DUT. The clamps also function to protect the DUT if a transient voltage or current spike occurs when changing to a different operating mode, or when programming the device to a different current range.
Table 10. AC0, AC1 Compensation Capacitor Selection AC0 Low High Low
AC1 Low Low High
Function Select External Compensation Capacitor 0 Select External Compensation Capacitor 1 Select External Compensation Capacitor 2
The digital output flags, which indicate a clamp limit has been hit, are CLHDETECT for the upper clamp, and CLLDETECT output for the lower clamp.
COMPARATOR FUNCTION AND STROBING
Table 13. Clamp Detect Outputs
The AD5520 has an on-board window comparator that provides two bits of useful information, DUT too low or DUT too high. CPSEL is the digital input that controls this function, selecting whether it should compare to the voltage sense or the current sense amplifier.
CLHDETECT Low High CLLDETECT Low High
Table 11. Comparator Function Select CPSEL Low High
Function Compare CPL, CPH to MEASVOUT Compare CPL, CPH to MEASIOUT
HIGH CURRENT RANGES
After CPSEL has selected which amplifier output is of interest, logic input CPCK is used to initiate comparator sampling and update the logic outputs CPOH and CPOL. This indicates whether the voltages at MEASIOUT or MEASVOUT have exceeded voltages set at CPL or CPH (thus providing DUT too high or DUT too low information). A rising edge on STB is required to clock the CPOH and CPOL data out. Table 12. CPCK Synchronous Logic Outputs CPOH Low High CPOL Low High
Function MEASVOUT or MEASIOUT < CPH MEASVOUT or MEASIOUT > CPH Function MEASVOUT or MEASIOUT > CPL MEASVOUT or MEASIOUT < CPL
Function Upper Clamp Inactive Upper Clamp Active Function Lower Clamp Inactive Lower Clamp Active
With the use of an external high current amplifier, two high current ranges are possible. The current range values can be set as required in the application through appropriate selection of the sense resistors connected between MEASI5H, MEASI4H, and MEASIL. When one of these high current ranges (Mode 4 or Mode 5) is selected via the AMx control lines, the appropriate QM4 or QM5 output is enabled. As a result, these outputs can be used to control relays connected in series with the high current amplifier, as shown in Figure 26. Table 14. High Current Range Logic Outputs QM4 High Low
Rev. B | Page 15 of 24
QM5 Low High
Function Current Range Mode 4 Enable Output Current Range Mode 5 Enable Output
AD5520 CIRCUIT OPERATION FORCE VOLTAGE
MEASURE CURRENT
Most PMU measurements are performed while in force voltage and measure current modes; for example, when the device is used as a device power supply, or in continuity or leakage testing. In the force voltage mode, the voltage at analog input FIN is mapped directly to the voltage forced at the DUT.
Figure 23 shows a simplified diagram of the PMU when in force voltage mode. The control loop consists of the force amplifier with the voltage sense amplifier making up the feedback path. Current flowing through the DUT is measured by sensing the current flowing through a selectable sense resistor, which is in series with the DUT. The current sense amplifier (Gain = 16) generates a voltage at its output, which is proportional to the current flowing through the DUT. This voltage is compared to the CLL and CLH levels to ensure the clamp voltages have not been exceeded. Strobing CPCK and STB provides information about the voltage level with respect to the comparator levels, CPH and CPL.
When in force voltage and measure current modes, the maximum voltage applied to the input corresponds to the maximum current outputs. Figure 22 shows the transfer function when forcing a voltage. VDUT
FIN
VCLH ×
RDUT RS × 16
FOHx MEASIHx G = 16
CLH
MEASIL MEASVH
CLL
RS × 16
VCLH
VCLL REFGNDI/V
V V
IDUT
MEASIOUT
RDUT MEASVOUT
VCLL ×
G=1
RDUT MEASVL
VMEASVOUT VMEASIOUT
CONDITION
VCLH > IDUT × RS × 16 VCLL < IDUT × RS × 16
VCLH < IDUT × RS × 16 VCLL < IDUT × RS × 16
VCLH > IDUT × RS × 16 VCLL > IDUT × RS × 16
OUTPUT
VDUT = VFIN
VDUT = VCLH
VDUT = VCLL
Figure 23. Force Voltage, Measure Current Mode
VCLH RS × 16
VCLH VCLH
RS
VFIN
VCLL
03701-022
RS × 16
Figure 22. Force Voltage Transfer Function
Rev. B | Page 16 of 24
03701-023
VFIN
VFIN
AD5520 FORCE CURRENT
SHORT CIRCUIT PROTECTION
In force current mode, the voltage at FIN is now converted to a current through the following relationship:
The AD5520 is designed to withstand a direct short circuit on any of the amplifier outputs.
Force Current = VFIN/(RSENSE × 16) Figure 24 shows a simplified diagram of the PMU when in force current mode. The control loop consists of the force amplifier with the current sense amplifier making up the feedback path. In this case, voltage at the DUT is sensed across the voltage measure amplifier (Gain = 1) and presented at the MEASVOUT output.
Figure 25 illustrates the transfer function of the current force mode. IDUT
VCLH RDUT
FIN
VFIN
FOHx MEASIHx G = 16
CLH
MEASIL MEASVH
VCLL REFGNDI/V
V V
CONDITION OUTPUT
MEASIOUT
MEASVOUT
CLL VCLH
RS
G=1
RDUT MEASVL
VDUT
VMEASVOUT VMEASIOUT
VCLH > VDUT VCLL < VDUT IDUT =
VFIN RS
VCLH < VDUT VCLL < VDUT IDUT =
VCLH RS
VCLH
VCLH > VDUT VCLL > VDUT IDUT =
VCLL RS
03701-024
VFIN
VCLL RDUT
VCLH
Figure 24. Current Force, Voltage Measure Mode
VCLH
MEASURE VOLTAGE
VFIN
Rev. B | Page 17 of 24
03701-025
VCLH
A DUT voltage is tested via the voltage measure amplifier by a window comparator to ensure that CPH and CPL levels are not exceeded. In addition, the DUT voltage is automatically tested against the voltage levels at the clamp, and clamp flags are enabled if the DUT voltage exceeds either of the levels.
Figure 25. Current Force Transfer Function
AD5520 SETTLING TIME CONSIDERATIONS Fast throughput is a key requirement in automatic test equipment because it relates directly to the cost of manufacturing the DUT; thus reducing the time required to make a measurement is of greatest importance. When taking measurements using a PMU, the limiting factor is usually the time it takes the output to settle to the required accuracy so a measurement can be taken. DUT capacitance, measurement accuracy, and the design of the PMU are the major contributors to this time. Figure 26 shows a simplified block diagram of the AD5520 PMU. In brief, the device consists of a force control amplifier, access to a number of selectable sense resistors, a voltage measure instrumentation amplifier, and a current measure instrumentation amplifier. To optimize the performance of the device, there are also nodes provided where external compensation capacitors are added. As mentioned, making an accurate measurement in the fastest time while avoiding overshoots and ringing is the key requirement in any automatic test equipment (ATE) system. Doing so provides challenges, however. The external compensation capacitors set up different settling times or bandwidths on the force control amplifier, and while one compensation capacitor value may suit one range, it may not suit other ranges. To optimize measurement performance and speed, differences in signal behavior on each range and frequency of use of each range need to be taken into account.
When selecting a faster settling time, there is a trade-off. A small compensation value results in faster settling, but may incur penalties in overshoots or ringing at the DUT. Compensation capacitor selection should be optimized to ensure minimum overshoots while still giving decent settling time performance. While careful selection of the compensation capacitor is required to minimize the settling time, another factor can greatly contribute to the overall settling of the loop if the feedback loop is broken in some manner, and the force control amplifier goes to either the positive or negative rails. There is a finite amount of time required for the amplifier to recover from this condition, typically 85 μs, which adds to the settling of the loop. Ensuring that the force control amplifier never goes into saturation is the best solution. This solution can be helped by putting the device into standby mode any time the operating mode or range selection is changed. In addition, ensure that the selected output range can supply the required current needed by the DUT.
Rev. B | Page 18 of 24
AD5520 PCB LAYOUT AND POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration to the power supply and the ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5520 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the PMU is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. This PMU should have ample supply bypassing of 10 μF in parallel with 0.1 μF on the supply and should be located as close as possible to the package, ideally right up against the device. The 0.1 μF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Low ESR (1 μF to 10 μF) tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple.
Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane while signal traces are placed on the solder side. It is good practice to use compact, minimum lead length PCB layout design. Leads to the input should be as short as possible to minimize IR drops and stray inductance.
Rev. B | Page 19 of 24
AD5520 TYPICAL CONNECTION CIRCUIT FOR THE AD5520 Figure 26 shows the AD5520 as connected in a typical application. The external components required are three compensation capacitors and six sense resistors, depending on the number of ranges required. If high current ranges >6 mA are required, an external amplifier must be used with relays (or some form of high current switch) to switch in the different current ranges to the DUT. Other components are also required to make the PMU function.
The PMU requires a number of discrete voltage levels: five DAC levels for each PMU used in the system, two levels each for the comparator and clamps, and one voltage level for the AD5520 force input voltage. To use the information measured at the DUT, an ADC such as the AD7665 (a 16-bit ADC), must be connected to the MEASOUT pin to convert the measured current or voltage to digital for analysis.
3000pF 1000pF 100pF
COMPOUT2
COMPOUT1
COMPOUT0
COMPIN2
COMPIN1
AD5520
COMPIN0
+15V –15V AVEE AVCC AD815 FOH
BW SELECT
RELAY
FOH3 FOH2
FIN
FOH1 FOH0
FORCE AMPLIFIER
<±11.5V
MEASI5H
CLAMP DETECT
MEASI4H
3.126Ω
MEASI3H
12.5Ω
MEASI2H
CLH
125Ω
MEASI1H
CLL
1.25kΩ 12.5kΩ
MEASI0H REFGND
125kΩ G = 16
MEASIOUT
MEASIL
ISENSE INST AMP
GUARDIN
MEASOUT
VSENSE INST AMP
G=1
MEASVH
G=1
MEASVOUT COMPARATOR CPH
GUARD
AGND
<±100mV
Figure 26. Typical Configuration of the AD5520 as Used in an ATE Circuit
Rev. B | Page 20 of 24
03701-026
DGND
CS DVDD
QM4
AC0 AC1
CLLDETECT
CLHDETECT
MOE
QM5
AM0
AM1
AM2
MSEL
FSEL
CPSEL
STB
CPCK
STANDBY
LOGICS
CPL
DUT
MEASVL
CPOH CPOL
≥±11V
AD5520 TYPICAL APPLICATION CIRCUIT Figure 27 shows the AD5520 as in an ATE system. This device can used as a per pin parametric unit in order to speed up the rate at which testing can be done. It can also be used as a DUT power supply, as shown in the application circuit.
The flexible function of the AD5520 also makes it suited for use in instrumentation applications such as source measure units. Source measure units are programmable instruments capable of sourcing and measuring voltage or current simultaneously. The AD5520 provides a more integrated solution in such equipment.
The central PMU shown in the block diagram (Figure 27) is usually a highly accurate PMU and is shared among a number of pins in the tester. In general, many discrete levels are required in an ATE system for the pin drivers, comparators, clamps, and active loads. DAC devices, such as the AD5379, offer a highly integrated solution for a number of these levels. The AD5379 is a dense 40-channel DAC designed with high channel requirements, such as ATE.
CENTRAL PMU DAC
GUARD AMP
ADC DAC
DAC
VCH
ADC
VTERM
DAC TIMING DATA MEMORY
PPMU
VH
DAC
DEVICE UNDER TEST (DUT) RELAYS
TIMING GENERATOR DLL, LOGIC
FORMATTER DE-SKEW
VCL
VL
DAC
DAC
DEVICE POWER SUPPLIES VTH
FORMATTER DE-SKEW
GUARD AMP
GND SENSE
DAC
DAC
COMP VTL
ADC DAC ACTIVE LOAD IOL
DAC
VCOM DAC
DAC
03701-027
COMPARE MEMORY
50Ω COAX
DRIVER
IOH
Figure 27. Typical Application ATE Circuit
Rev. B | Page 21 of 24
AD5520 EVALUATION BOARD FOR THE AD5520 A full-featured evaluation kit is available for the AD5520. It includes an evaluation board with direct hookup via a 36-way Centronics connector to a PC. PC-based software to control the AD5520 is also part of the evaluation kit. The evaluation board schematic is shown in Figure 28. Note that VDD and VSS must provide sufficient headroom for the force and measure voltage range. In addition to the supply voltages for the evaluation board, it is necessary to provide the voltage levels for the clamp, comparator, and the force input pins (CLL, CLH, CPL, CPH, and FIN). SMB connections are provided for these voltage inputs. To use the evaluation board, it is also necessary to provide a DUT connected via the gold pins.
Both AGND and DGND inputs are provided on the board. The AGND and DGND planes are connected at one location close to the AD5520. It is recommended not to connect AGND and DGND elsewhere in the system to avoid ground loop problems. REFGND is routed back to AGND at the power block to maintain a clean ground reference for accurate measurements. Each supply is decoupled to the relevant ground plane with 10 μF and 0.1 μF capacitors. The device supply pin is again decoupled with a 10 μF and 0.1 μF capacitor pair to the relevant ground plane. Care should be taken when replacing devices to ensure that the pins line up correctly with the PCB pads.
Rev. B | Page 22 of 24
03701-028
C26 0.1μF
C27 0.1μF
Figure 28. Evaluation Board Schematic
Rev. B | Page 23 of 24
J1–2 J1–3 J1–4 J1–5 J1–6 J1–7 J1–8 J1–9
J1–36
J1–31
J1–1
J1–14
D[0:7]
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
2 3 4 5 6 7
8 D6 9 D7
D0 D1 D2 D3 D4 D5
19 18 17 16 15 14 13 12
19 18 17 16 15 14 13 12
11 C 1 OE
U3
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
74HCT573
U4
Q4 Q5 Q6 Q7
Q0 Q1 Q2 Q3
J1–19 J1–20 J1–21 J1–22 J1–23 J1–24 J1–25 J1–26 J1–27 J1–28 J1–29 J1–30
19 18 17 16 15 14 13 12
U2
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
74HCT573
11 C 1 OE
2 3 4 5 6 7 8 9
11 C 1 OE
2 3 4 5 6 7 8 9
J10–2
J10–1 C20 0.1μF
20V
C6 10μF
C5 0.1μF
C21 10μF
C9, 3.3nF
C8, 1nF
C7, 100pF
20V
C4 10μF
C3 0.1μF
COMPIN0 COMPOUT0
COMPIN1 COMPOUT1
COMPIN2 COMPOUT2
CPOH CPOL CHL-DET CLL-DET QM4 QM5
AM0 AM1 AM2 FSEL CPSEL MSEL AC0 AC1
STANDBY STB CPCK MOEB CSB
AVCC AVCC_G
20V
+5VD
J11–3
J11–2
J11–1
3
58 60 61 62 63 64 1 2
C24 0.1μF
C22 0.1μF
AGND 28
MEASVH NC MEASVL GAURDIN NC GUARD
MEASI5H MEASI4H FOH3 MEASI3H FOH2 MEASI2H FOH1 MEASI1H FOH0 MEASIOH MEASIL
FOH
T12
J2 T4
C25 10μF
C23 10μF
36 35 34 32 31 30
47 46 45 44 43 42 41 40 39 38 37
49
59 REFGND 57 REFGND
MEASOUT MEASIOUT MEASVOUT FIN CLH CLL CPH CPL
DVDD
DGND DGND 7 17
26 AVEE 29 AVEE_G 48 AVEE_B
54 51
55 52
56 53
4 5 8 9 10 11
21 20 19 23 25 24 15 16
22 14 6 12 13
27 33 50
DVDD
18
20V C1 0.1μF
T5
J3
C14
R12 5kΩ
T6
J4
+15V
–15V
20V
20V
LK1
R1, 124kΩ
+5VD
T8
J6
T9
J7
R11 5kΩ
AD815ARB
U5–A
T7
J5
C18
C17
R2, 12.4kΩ
+15V
R10
R4, 124Ω
74HCT573
R3, 1.24kΩ
C28 0.1μF
T10
J8
RELAY–G6H
8
9
T11
J9
C19
7
R6
+5VD
R5, 12.4Ω
C2 10μF
R7
U2, U3, U4 BYPASS CAPACITORS
4
2
B
RL1
C15 10pF
–15V
E
Q1
C
10
1
20V C11 0.1μF
C10 10μF
7
8
9
QM4
R8 10kΩ
D1
RELAY–G6H
+15V
20V
C13 10μF
12 AD815ARB–24 U5–C –VS +VS C12 13 0.1μF
3
+5VD
4
3
2
T2
16 15
T1
E
Q1
C
10
1
B
RL2
14
T3
QM5
R9 10kΩ
D2
AD815ARB–24
U5–B
C16 10pF
+5VD
AD5520
AD5520
Preliminary Technical Data
OUTLINE DIMENSIONS 0.75 0.60 0.45
12.00 BSC SQ
1.60 MAX
64
49
1
48 PIN 1
10.00 BSC SQ
TOP VIEW (PINS DOWN)
1.45 1.40 1.35 0.15 0.05
SEATING PLANE
0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY
VIEW A
16
33 32
17
VIEW A
0.50 BSC LEAD PITCH
0.27 0.22 0.17
ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD
Figure 29. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters
ORDERING GUIDE Model AD5520JST AD5520JST-REEL AD5520JSTZ-REEL 1 EVAL-AD5520EB 1
Temperature Range 0°C to 70°C 0°C to 70°C 0°C to 70°C
Package Description 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board and Software
Z = Pb-free part.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03701-0-9/05(B)
Rev. B | Page 24 of 24
Package Option ST-64-2 ST-64-2 ST-64-2
