Transcript
Performance Analysis of GPS L5 Signal Processing Board for GNSS Ground Sensor Station 1
Jaehyun Kim1, Cheon Sig Sin1, Sanguk Lee1, and Jae Hoon Kim1 Satellite & Wireless Convergence Research Department, ETRI, Daejeon, 305-700, Korea (Tel:82-42-860-6731, E-mail:
[email protected])
BIOGRAPHY Jaehyun Kim studied Electrical Engineering at the Hangyang University. From 2007 to 2009 he was a research associate at the Electronics and Telecommunication Research Institutes where his research area has been the signal processing for GPS and Galileo receiver R&D project. Cheon Sig Sin studied Electrical Engineering at the Hangyang University. From 1990 to 2006 he was a research associate at the Electronics and Telecommunication Research Institutes where his research area has been the satellite frequency & orbit coordination and the satellite system design. Since 2007 he works for the ETRI in the GPS and Galileo receiver R&D division. Sanguk Lee received his Ph’D degree in Astronomy Engineering at the University of Applied Science in Auburn Alabama. From 1993 to 2006 he was especially engaged and responsible for the development of software designs for satellite ground control systems. Since 2007 he works at ETRI in the project manager focusing on hardware and FPGA development for GNSS Ground System and Search & Rescue Terminals. Jae Hoon Kim received his Ph’D degree in Computer Engineering at Chungbuk University in KOREA. From 1983 to 2009 he was a research associated at the Electronics Telecommunication Research Institutes for satellite ground control system research technology and team leader. Currently he is involved in GNSS ground system R&D project and LEO Satellite Ground Control System where he is managing the Project and Team Leader.
ABSTRACT The GPS L5 signal added newly in the GPS modernization plan was designed to improve the accuracy and availability for civilian users. In order to
apply the structural property of this signal, new receiver architectures are needed. In Korea, ETRI is developing technologies of GNSS ground infrastructure and next generation search and rescue beacon from 2007 up to 2010. We are going to develop hardware board per signal frequency for the development of the high performance GNSS receiver which monitors not only GPS but also Galileo system. The combined GNSS receiver is consisted of H/W Antenna, RF/IF units and Signal Processing Unit. The receiver can process wide-bandwidth multiple frequency for GPS L1/L2C/L5 and Galileo E1/E5a signal. In this paper, we are focusing to design and performance of the GPS L5 signal processing board. The hardware board receives IF signal of RF/IF Frontend and process IF signal in the ADC, FPGA, and DSP for baseband process. And the performance of GPS L5 signal processing is verified by compare accuracy, sensitivity with ETRI specification for the Spirent simulator.
INTRODUCTION After Korea decided to join Galileo Project in 2006, some GNSS research based on National GNSS program was launched. ETRI is under development of some key technologies for GNSS ground station and Search and Rescue Distress Beacon as shown in Fig. 1. The GNSS ground station developed by ETRI is consisted of GNSS sensor station for GPS/Galileo Open Service signal monitoring, Monitoring and Control system for controlling and monitoring ground facilities and navigation data processing, and Uplink Station for uploading GNSS augmentation and integrity data. The system configuration of GNSS sensor station facilities is shown as Fig. 2. The main purpose of the GNSS ground sensor station is to develop the key technologies such as high precision receiving function of GPS/Galileo combined receiver unit. This paper describes design and performance of the GPS/Galileo Combined Receiver, developed as monit-
GNSS Augmentation/integrity data GPS
Galileo Return Link Message (1544 MHz)
GNSS Signal (L1,L2C,L5, E1, E5a)
Up-Link Station
SAR Distress Signal (406.037 MHz)
SAR Distress Beacon
GNSS Data & Monitoring
Data Archiving
Navigation Analysis
Control Data
GNSS Control Center
GNSS Sensor Station Monitoring and Control
Fig. 1 Infrastructure of GNSS ground station and Search and Rescue Distress Beacon oring receiver. The receiver is based on a cPCI(compact PCI) platform where the Control Board (slot-0) serves as the navigation processor and user interface. The front-end occupy two slots and baseband board can occupy five slots of cPCI platform to serve any of the GPS/Galileo radiofrequency bands L1, L2C, L5, and E6. As the baseband units are FPGA (field programmable gate arrays) and DSP (digital signal processing) based, the structure of all boards is equally designed. The four Block IIF satellite signals are demanded at last in order to verify operation of baseband board. Unfortunately the real satellite signal of sufficient number will not be reached until FOC (Full Operational Capability) of Block III satellite after 2013. The test of baseband board is accomplished by Spirent simulator.
Fig. 2 Sensor Station structure
GPS/Galileo Combined Receiver
GPS/Galileo Combined Receiver is consisted of Splitter & CLK_GEN, RF/IF Converter, signal processing boards, control board as shown in Fig. 3 and exchange data between boards by cPCI backplane. GPS/Galileo Combined Receiver is build up by using a cPCI platform with 8 slots for 6U modules. Using cPCI, the backplane offers a dedicated clock distribution with a 10MHz clock signal and additional dedicated signal lines. The real shape of GPS/Galileo combined receiver is presented as shown in Fig. 4 All baseband boards use the same clock signal provided by cPCI backplane from Splitter & CLK_GEN board. Splitter & CLK_GEN board can select either external Rubidium or internal TCXO (temperature compensated crystal oscillator) depending upon environment. Through reserve line of the cPCI backplane, the clock signal is distributed to all receivers in order to provide coherent clocking of all processing modules. To synchronize the local clocks of all receivers, a special cPCI line (Global Sync, Gal Sync, and GPS Sync) is used to distribute a sync signal, which triggers the measurement on all receiver boards. The antenna is connected to Splitter & CLK_GEN board that also serves as a power supply for the antenna. Splitter & CLK_GEN board splits the antenna signal into each frequency L1, L2C, L5. Each of these outputs is connected to the corresponding RF/IF Converter. Splitter & CLK_GEN board is not a cPCI card and is mounted only in the cPCI platform. The only connection with cPCI system is the power supply. To acquire function of ADC (analog to digital converter) module removal in receiver board, the sampling clock signal is required. The sampling clock signal is generated by clock signal and is distributed to all receivers.
Combined Receiver or receiver boards. Control board have controller and operation function of receiver boards. If there is more than one receiver board available, it must coordinate the receivers in terms of channel management and has to acquire all measurements from four baseband boards and calculate PVT solution.
Signal Processing Board Fig. 3 GPS/Galileo Combined Receiver Architecture
The Signal Processing Board is consisted of ADC module with 112MHz sampling frequency and 8bit quantization, FPGA-1 for signal processing, DSP-1 for floating point arithmetic, DSP-2 for message parsing, data transfer and PVT, FPGA-2 for hardware configuration.
Fig. 4 GPS/Galileo Hardware Combined Receiver RF/IF Converter occupy one cPCI slot and convert separately incoming antenna signal to analog IF signal and transfer to receiver board, which occupies one cPCI slot. The 8-bit ADC module of receiver board convert analog IF signal to digitized IF signal with sampling clock signal. The receiver board process digitized IF signal and transfer result to control board by cPCI backplane.
Fig. 6 Signal Processing Board Architecture Overview Selection of the band to serve is performed by software through programming the appropriate configuration file onto the baseband FPGA. Two FPGA arrays and one FPGA of the latest Virtex5 are used for the baseband processing and hardware configuration. Two FPGA array can be configured independently within the same RF-band to allow tracking of GPS and Galileo signals simultaneously on one baseband board.
Fig. 5 RF/IF Front-End Block Diagram Table.1 Frequency Allocation of RF/IF Front-End Center IF Sampling Signal BW Freq. Freq. Freq. Name (MHz) (MHz) (MHz) (MHz) L1/E1
1575.42
25
140
112
L2C
1227.60
22
140
112
L5/E5a 1176.45
26
140
112
Control board is commercial product as standard compact PCI board. It acts as an interface between the Monitoring and Control system and GPS/Galileo
Fig. 7 Block Diagram of Signal Processing Board FPGA-1 performs acquisition, fixed point arithmetic of tracking loop, code and carrier measurement generation function. The correlator of tracking function receives increment value for code and carrier NCO (numerical controlled oscillator) and compensates code and carrier error. In order to calculate exact error, DSP1 of floating point arithmetic function is selected.
The DSP-2 extract navigation message using bits acquired from tracking loop result. It transfers the measurements of correlator and navigation message to control board and calculate rough PVT solution in standalone mode. The FPGA-1, DSP-1, and DSP-2 are used for process of navigation signal. But the FPGA-2 is used in order to configure initial hardware environment and select operation scenario, operation parameter for each navigation signal. The Fig. 8 present real hardware signal process shape.
The processing result of receiver board is simply displayed in comparison with GUI of Control Board. The GUI of receiver board has shape as below figure and is consisted of channel measurement, channel navigation data, satellite sky plot, and PVT plot.
Fig. 9 GUI of Signal Processing Board
Fig. 8 Signal Processing Board
Performance To characterize the receiver performance, the result comparison of S/W and H/W receiver is accomplished. In order to verify operation of S/W receiver, the commercial data acquisition device of National Instrument is used. It can store analog IF signal or digitized IF signal to digital file simultaneously with H/W receiver.
The performance of receiver board must satisfy ETRI specification for Accuracy, Sensitivity, and TTFF. In code noise, as shown in Fig. 10, the result of S/W receiver for 0.125 E-L spacing is 7.73cm (RMS) @ 45dB-Hz and the result of H/W receiver is 8.08cm (RMS) @ 45dB-Hz. The noise difference of S/W and H/W depends on delay time between FPGA and DSP. The effect of delay time must be analyzed more detail. Because the test result of code noise satisfies ETRI specification and the difference is small, the algorithm optimization will be accomplished as next work. Also, the code noise is 29cm (RMS) @ 45dB-Hz in EL spacing is 0.5. Therefore, the correlator spacing must have small value after frame synchronization. 1
0.6 0.4
GPS L5
IF Freq.
28MHz
E-L Spacing
0.125
Code Integration Time
100ms
Carrier Integration Time
20ms
Code Noise (m)
Table.2 Parameter of HW/SW Receiver Parameter
SW(d=0.125) HW(d=0.125) HW(d=0.5)
0.8
0.2 0 -0.2 -0.4 -0.6 -0.8 -1
0
50
100 Time (100ms)
150
200
Fig. 10 Code Noise @ 45dB-Hz 8
Dot-Product
Carrier Discriminator
Atan2
Tracking Type
Pilot Only
DLL Order/ BW
2 / 1Hz
SW(d=0.125) HW(d=0.125) HW(d=0.5)
6
4 Carrier Phase Noise (mm)
Code Discriminator
2
0
-2
-4
PLL Order/ BW
2 / 10Hz
Measurement Rate
10 Hz
-6
-8
0
200
400
600 Time (20ms)
800
Fig. 11 Carrier Noise @ 45dB-Hz
1000
In carrier noise, the result of S/W receiver is 1.8mm (RMS) @ 45dB-Hz and the result of H/W receiver is 1.6mm (RMS) @ 45dB-Hz. The noise difference of S/W and H/W depend on SIN, COS Lookup Table size (S/W:256, H/W:4096). The sensitivity test is accomplished by decrease of power level after nominal tracking. The sensitivity level is determined at signal level that tracking is maintained. The tracking of S/W receiver is maintained normally at -152dBm (20dB-Hz), as shown in Fig. 12. The accurate measurement in lower signal requires more preparation because of spirent simulator.
solution verification. The signal process by Spirent simulator was successfully performed. But the performance of signal process for accuracy is required more improvement in comparison with commercial receiver. As next work, the implementation of Kalman filter will be carried out in order to acquire lower code noise.
ACKNOWLEDGEMENTS This work was supported by the IT R&D program of the IITA. [2007-S-301-01, Development of GNSS ground station and SAR beacon technologies].
REFERENCES
Fig. 12 Sensitivity Result of Software Receiver
CONCLUSION The main goal of GPS L5 signal processing board is multichannel signal processing and basic navigation
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