Transcript
MITSUBISHI
PM200RLA060 FLAT-BASE TYPE INSULATED PACKAGE
PM200RLA060 FEATURE a) Adopting new 5th generation IGBT (CSTBT) chip, which performance is improved by 1µm fine rule process. For example, typical Vce(sat)=1.5V @Tj=125°C b) I adopt the over-temperature conservation by Tj detection of CSTBT chip, and error output is possible from all each conservation upper and lower arm of IPM. c) Current rating of brake part increased. 50% for the current rating of inverter part. • 3φ 200A, 600V Current-sense IGBT type inverter • 100A, 600V Current-sense regenerative brake IGBT • Monolithic gate drive & protection logic • Detection, protection & status indication circuits for, shortcircuit, over-temperature & under-voltage (P-Fo available from upper arm devices) • Acoustic noise-less 22kW class inverter application • UL Recognized Yellow Card No.E80276(N) File No.E80271
APPLICATION General purpose inverter, servo drives and other motor controls
PACKAGE OUTLINES
Dimensions in mm 135
6.05
6.05
110±0.5
6-M5 Nuts
26
26
10.5
10.5
40.5
11.7
10.5
13(Screwing Depth)
13
18.7 U
3-2
10.5 3-2
10
3-2
10
3.25
20
10
19-
5
0.5
1
30.15
6.05
9
11
4
Terminal code
L A B E L
34.7
2-φ2.5
13
33.6
4-φ5.5 Mounting Holes
19
24.1 +1 -0.5
11
16.5
10.5
6-2
P
66.5 3.25
78±0.5
20
N
71.5
110
10.5
B
V
21.5
18
W
6.05
13
6
6
1. 2. 3. 4. 5.
VUPC 6. UFO 7. UP 8. VUP1 9. VVPC 10.
VFO VP VVP1 VWPC WFO
11. 12. 13. 14. 15.
WP VWP1 VNC VN1 Br
16. 17. 18. 19.
UN VN WN Fo
Jan. 2005
MITSUBISHI
PM200RLA060 FLAT-BASE TYPE INSULATED PACKAGE
INTERNAL FUNCTIONS BLOCK DIAGRAM
Br Fo
VNC WN
VN1
WP VWP1 VWPC WFO
UN
VN
1.5k
Gnd In
Gnd
1.5k
Fo Vcc
Si Out
VP VVPC
OT
Gnd In
Gnd
Fo Vcc
Si Out
OT
Gnd In
Gnd
B
Fo Vcc
Si Out
OT
Gnd In
Gnd
Fo Vcc
Si Out
OT
N
Gnd In
Gnd
UP VUPC
VUP1 UFO
1.5k
Fo Vcc
Si Out
VVP1 VFO
OT
Gnd In
Gnd
W
V
1.5k
Fo Vcc
Si Out
Gnd In
OT
Gnd
Fo Vcc
Si Out
U
OT
P
MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted) INVERTER PART Symbol VCES ±IC ±ICP PC Tj
Parameter Collector-Emitter Voltage Collector Current Collector Current (Peak) Collector Dissipation Junction Temperature
Condition VD = 15V, VCIN = 15V TC = 25°C TC = 25°C TC = 25°C
(Note-1)
Ratings 600 200 400 600 –20 ~ +150
Unit V A A W °C
Ratings 600 100 200 343 600 100 –20 ~ +150
Unit V A A W V A °C
Ratings
Unit
20
V
20
V
20
V
20
mA
BRAKE PART Symbol VCES IC ICP PC VR(DC) IF Tj
Parameter Collector-Emitter Voltage Collector Current Collector Current (Peak) Collector Dissipation FWDi Rated DC Reverse Voltage FWDi Forward Current Junction Temperature
Condition VD = 15V, VCIN = 15V TC = 25°C TC = 25°C TC = 25°C TC = 25°C TC = 25°C
(Note-1)
CONTROL PART Symbol
Parameter
VD
Supply Voltage
VCIN
Input Voltage
VFO
Fault Output Supply Voltage
IFO
Fault Output Current
Condition Applied between : VUP1-VUPC VVP1-VVPC, VWP1-VWPC, VN1-VNC Applied between : UP-VUPC, VP-VVPC WP-VWPC, UN • VN • WN • Br-VNC Applied between : UFO-VUPC, VFO-VVPC, WFO-VWPC FO-VNC Sink current at UFO, VFO, WFO, FO terminals
Jan. 2005
MITSUBISHI
PM200RLA060 FLAT-BASE TYPE INSULATED PACKAGE TOTAL SYSTEM Symbol
Parameter Supply Voltage Protected by VCC(PROT) SC VCC(surge) Supply Voltage (Surge) Module Case Operating TC Temperature Storage Temperature Tstg Viso Isolation Voltage
Ratings
Condition VD = 13.5 ~ 16.5V, Inverter Part, Tj = +125°C Start
Unit
400
V
500
V
(Note-1)
–20 ~ +100
°C
60Hz, Sinusoidal, Charged part to Base, AC 1 min.
–40 ~ +125 2500
°C Vrms
Applied between : P-N, Surge value
(Note-1) Tc (base plate) measurement point is below. V
W
B
U P
N
Top view
Tc
THERMAL RESISTANCES Symbol
Condition
Parameter
Rth(j-c)Q Rth(j-c)F Rth(j-c)Q Rth(j-c)F Rth(j-c)Q Rth(j-c)F Rth(j-c)Q Rth(j-c)F
Junction to case Thermal Resistances
Rth(c-f)
Contact Thermal Resistance
Inverter IGBT (per 1 element) Inverter FWDi (per 1 element) Brake IGBT Brake FWDi Inverter IGBT (per 1 element) Inverter FWDi (per 1 element) Brake IGBT Brake FWDi Case to fin, (per 1 module) Thermal grease applied
(Note-2) (Note-2) (Note-2) (Note-2) (Note-1) (Note-1) (Note-1) (Note-1) (Note-2)
Min. — — — — — — — —
Limits Typ. — — — — — — — —
Max. 0.16* 0.25* 0.28* 0.44* 0.21 0.33 0.36 0.57
—
—
0.023
Unit
°C/W
* If you use this value, Rth(f-a) should be measured just under the chips. (Note-2) Tc (under the chip) measurement point is below. arm axis X Y
UP IGBT FWDi 23.7 23.0 56.7 43.7
VP IGBT FWDi 57.2 56.5 56.7 43.7
Unit : mm
WP IGBT FWDi 87.7 86.5 56.7 43.7
UN IGBT FWDi 37.7 38.0 28.7 41.8
VN IGBT FWDi 70.2 71.5 28.7 41.8
WN IGBT FWDi 100.7 101.5 28.7 41.8
Br IGBT 11.0 26.7
FWDi 7.7 60.9
Bottom view Y
X
ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted) INVERTER PART Symbol VCE(sat) VEC ton trr tc(on) toff tc(off) ICES
Parameter
Condition
Collector-Emitter Saturation Voltage FWDi Forward Voltage
VD = 15V, IC = 200A (Fig. 1) VCIN = 0V –IC = 200A, VD = 15V, VCIN = 15V
Switching Time
VD = 15V, VCIN = 0V↔15V VCC = 300V, IC = 200A Tj = 125°C Inductive Load
Collector-Emitter Cutoff Current
VCE = VCES, VCIN = 15V
Tj = 25°C Tj = 125°C (Fig. 2)
(Fig. 3, 4) (Fig. 5)
Tj = 25°C Tj = 125°C
Min. — — — 0.5 — — — — — —
Limits Typ. 1.6 1.5 2.2 1.0 0.2 0.4 1.2 0.5 — —
Max. 2.1 2.0 3.3 2.4 0.4 1.0 2.5 1.0 1 10
Unit V V
µs
mA Jan. 2005
MITSUBISHI
PM200RLA060 FLAT-BASE TYPE INSULATED PACKAGE
BRAKE PART Symbol VCE(sat) VFM ICES
Condition
Parameter Collector-Emitter Saturation Voltage FWDi Forward Voltage Collector-Emitter Cutoff Current
VD = 15V, IC = 100A VCIN = 0V IF = 100A
(Fig. 1)
VCE = VCES, VCIN = 15V
(Fig. 5)
Tj = 25°C Tj = 125°C (Fig. 2) Tj = 25°C Tj = 125°C
Min. — — — — —
Limits Typ. 1.6 1.5 2.2 — —
Max. 2.1 2.0 3.3 1 10
Min. — — 1.2 1.7 400 200
Limits Typ. 24 6 1.5 2.0 — —
Max. 34 12 1.8 2.3 — —
Unit V V mA
CONTROL PART Symbol
Parameter
Condition VN1-VNC V*P1-V*PC
ID
Circuit Current
VD = 15V, VCIN = 15V
Vth(ON) Vth(OFF)
Input ON Threshold Voltage Input OFF Threshold Voltage
SC
Short Circuit Trip Level
Applied between : UP-VUPC, VP-VVPC, WP-VWPC UN • VN • WN • Br-VNC Inverter part –20 ≤ Tj ≤ 125°C, VD = 15V (Fig. 3,6) Brake part
toff(SC)
Short Circuit Current Delay Time
VD = 15V
Over Temperature Protection
VD = 15V Detect Tj of IGBT chip
Supply Circuit Under-Voltage Protection
–20 ≤ Tj ≤ 125°C
Fault Output Current
VD = 15V, VFO = 15V
(Note-3)
Minimum Fault Output Pulse Width
VD = 15V
(Note-3)
OT OTr UV UVr IFO(H) IFO(L) tFO
(Fig. 3,6) Trip level Reset level Trip level Reset level
Unit mA V A
—
0.2
—
µs
135 — 11.5 — — —
145 125 12.0 12.5 — 10
— — 12.5 — 0.01 15
°C
1.0
1.8
—
V mA ms
(Note-3) Fault output is given only when the internal SC, OT & UV protections schemes of either upper or lower arm device operate to protect it.
MECHANICAL RATINGS AND CHARACTERISTICS Symbol — — —
Condition
Parameter Mounting torque Mounting torque Weight
Main terminal Mounting part
screw : M5 screw : M5 —
Min. 2.5 2.5 —
Limits Typ. 3.0 3.0 800
Max. 3.5 3.5 —
Unit N•m N•m g
RECOMMENDED CONDITIONS FOR USE Symbol VCC
Parameter Supply Voltage
VD
Control Supply Voltage
VCIN(ON) VCIN(OFF) fPWM
Input ON Voltage Input OFF Voltage PWM Input Frequency Arm Shoot-through Blocking Time
tdead
Condition Applied across P-N terminals Applied between : VUP1-VUPC, VVP1-VVPC VWP1-VWPC, VN1-VNC (Note-4) Applied between : UP-VUPC, VP-VVPC, WP-VWPC UN • VN • WN • Br-VNC Using Application Circuit of Fig. 8 For IPM’s each input signals
Recommended value ≤ 400
Unit V
15 ± 1.5
V
(Fig. 7)
≤ 0.8 ≥ 9.0 ≤ 20
kHz
≥ 2.0
µs
V
(Note-4) With ripple satisfying the following conditions: dv/dt swing ≤ ±5V/µs, Variation ≤ 2V peak to peak
Jan. 2005
MITSUBISHI
PM200RLA060 FLAT-BASE TYPE INSULATED PACKAGE PRECAUTIONS FOR TESTING 1. Before appling any control supply voltage (VD), the input terminals should be pulled up by resistores, etc. to their corresponding supply voltage and each input signal should be kept off state. After this, the specified ON and OFF level setting for each input signal should be done. 2. When performing “SC” tests, the turn-off surge voltage spike at the corresponding protection operation should not be allowed to rise above VCES rating of the device. (These test should not be done by using a curve tracer or its equivalent.) P, (U,V,W,B) IN Fo
VCIN
P, (U,V,W)
Ic
V
IN Fo
VCIN
–Ic
V
(15V)
(0V)
U,V,W, (N)
VD (all)
U,V,W,B, (N)
VD (all)
Fig. 1 VCE(sat) Test
Fig. 2 VEC, (VFM) Test
a) Lower Arm Switching P
VCIN (15V)
Fo
Signal input (Upper Arm)
trr CS
Ic
Vcc
Fo
Signal input (Lower Arm)
VCIN
VCE
Irr
U,V,W
90%
90% N
VD (all)
b) Upper Arm Switching
Ic
10%
10%
10%
10%
P
tc(on)
Fo
Signal input (Upper Arm)
VCIN
VCIN
U,V,W
CS
VCIN (15V)
tc(off)
Vcc
td(on)
tr
tf
td(off)
Fo
Signal input (Lower Arm)
(ton= td(on) + tr)
(toff= td(off) + tf)
N
Ic
VD (all)
Fig. 3 Switching time and SC test circuit
Fig. 4 Switching time test waveform
VCIN Short Circuit Current
P, (U,V,W,B) A
VCIN (15V)
Constant Current
IN Fo
SC Pulse VCE
Ic
VD (all)
U,V,W, (N)
Fo toff(SC)
Fig. 5 ICES Test
Fig. 6 SC test waveform
IPM’ input signal VCIN (Upper Arm)
1.5V
0V IPM’ input signal VCIN (Lower Arm)
0V
2V
tdead
2V
1.5V
1.5V
tdead
2V
t
t
tdead
1.5V: Input on threshold voltage Vth(on) typical value, 2V: Input off threshold voltage Vth(off) typical value
Fig. 7 Dead time measurement point example
Jan. 2005
MITSUBISHI
PM200RLA060 FLAT-BASE TYPE INSULATED PACKAGE
P ≥10µ
20k
VUP1
→
VD
UFo
IF
1.5k
Vcc Fo
UP
OT OUT
In
VUPC
+ –
Si U
GND GND
≥0.1µ
VVP1 VFo
VD
1.5k
Fo
VP
1.5k
Vcc Fo
WP
M
OT OUT Si W
GND GND
20k
Vcc
≥10µ
IF
V
In
VWPC
→
Si
GND GND
VWP1
VD
OT OUT
In
VVPC
WFo
Vcc
Fo UN
OT OUT Si
In GND GND
≥0.1µ
N OT
20k
→
Vcc
≥10µ
IF
Fo
VN
OUT Si
In GND GND
≥0.1µ 20k
→
VD
Vcc
≥10µ
IF
Fo
WN ≥0.1µ
In
IF
Vcc Fo
Br 1k
Fo
OT OUT Si
GND GND
VNC
4.7k
→
5V
VN1
In 1.5k
B
OT OUT Si
GND GND
: Interface which is the same as the U-phase
Fig. 8 Application Example Circuit
NOTES FOR STABLE AND SAFE OPERATION ; Design the PCB pattern to minimize wiring length between opto-coupler and IPM’s input terminal, and also to minimize the stray capacity between the input and output wirings of opto-coupler. Connect low impedance capacitor between the Vcc and GND terminal of each fast switching opto-coupler. Fast switching opto-couplers: tPLH, tPHL ≤ 0.8µs, Use High CMR type. Slow switching opto-coupler: CTR > 100% Use 4 isolated control power supplies (VD). Also, care should be taken to minimize the instantaneous voltage charge of the power supply. Make inductance of DC bus line as small as possible, and minimize surge voltage using snubber capacitor between P and N terminal. Use line noise filter capacitor (ex. 4.7nF) between each input AC line and ground to reject common-mode noise from AC line and improve noise immunity of the system.
• • • • • • •
Jan. 2005
