Transcript
MITSUBISHI MITSUBISHI MODULES>
PM75CSD060 PM75CSD060 FLAT-BASE FLAT-BASE TYPE TYPE INSULATED INSULATED PACKAGE PACKAGE
PM75CSD060
FEATURE a) Adopting new 4th generation IGBT chip, which performance is improved by 1µm fine rule process. For example, typical Vce(sat)=1.7V b) Using new Diode which is designed to get soft reverse recovery characteristics. c) Keeping the package compatibility. The layout/position of both terminal pin and mounting hole is same as S-series 3rd generation IPM. • 3φ 75A, 600V Current-sense IGBT type inverter • Monolithic gate drive & protection logic • Detection, protection & status indication circuits for overcurrent, short-circuit, over-temperature & under-voltage (P-Fo available from upper leg devices) • Acoustic noise-less 5.5/7.5kW class inverter application
APPLICATION General purpose inverter, servo drives and other motor controls
PACKAGE OUTLINES
Dimensions in mm
3-2
17.02
10
110±1 95±0.5 3-2 3-2 10 10
6-2
Screwing depth Min9.0
4-φ5.5 MOUNTING HOLES
3.22
9 11 10 12
B P
1. 2. 3. 4. 5. 6. 7. 8. 9. 10.
13 15 17 19 14 16 18
89±1
567 8
74±0.5
20
2±0.5
1234
20
VUPC UFO UP VUP1 VVPC VFO VP VVP1 VWPC WFO
11. 12. 13. 14. 15. 16. 17. 18. 19.
WP VWP1 VNC VN1 Br UN VN WN Fo
N
17.5
12 4.5
17
PBT
Terminal code
10
φ2.54 U
24.5
4-R6 26
26
+1.0
6-M5NUTS
22 –0.5
66.44
A
0.5
0.5
22
19.4
LABEL
A : DETAIL
4
32.6
31.6
3-2
2-φ2.54 1.6
19-
3.22
21.2
10.6
V
11.6
W
0.5±0.3
Sep. 2000
MITSUBISHI
PM75CSD060 FLAT-BASE TYPE INSULATED PACKAGE
INTERNAL FUNCTIONS BLOCK DIAGRAM Rfo=1.5kΩ WP NC Fo
VNC W N
VN1
VN
UN
VWPC
Rfo
VWP1 VP VVP1 UP VUP1 WFO VFO UFO VVPC VUPC
Rfo
Gnd In
Gnd
Fo Vcc Gnd In
Si Out
Gnd
Fo Vcc
Si Out
Gnd In
Gnd
Fo Vcc
Si Out
Gnd In
Gnd
Fo Vcc
Si Out
Rfo
Gnd In
Gnd
Rfo
Fo Vcc Gnd In
Si Out
Gnd
Fo Vcc
Si Out
Th
NC
N
W
V
U
P
MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted) INVERTER PART Symbol VCES ±IC ±ICP PC Tj
Parameter Collector-Emitter Voltage Collector Current Collector Current (Peak) Collector Dissipation Junction Temperature
Condition VD = 15V, VCIN = 15V T C = 25°C T C = 25°C T C = 25°C
Ratings 600 75 150 255 –20 ~ +150
Unit V A A W °C
Ratings
Unit
20
V
20
V
20
V
20
mA
CONTROL PART Symbol
Parameter
VD
Supply Voltage
VCIN
Input Voltage
VFO
Fault Output Supply Voltage
IFO
Fault Output Current
Condition Applied between : VUP1 -VUPC VVP1-VVPC, VWP1-VWPC, V N1-VNC Applied between : UP-VUPC, V P-VVPC WP-VWPC, U N • VN • WN-VNC Applied between : UFO-VUPC, V FO-VVPC, WFO-VWPC FO -VNC Sink current at UFO, VFO, WFO, FO terminals
Sep. 2000
MITSUBISHI
PM75CSD060 FLAT-BASE TYPE INSULATED PACKAGE TOTAL SYSTEM Symbol
Parameter Supply Voltage Protected by VCC(PROT) OC & SC VCC(surge) Supply Voltage (Surge) Module Case Operating TC Temperature Storage Temperature Tstg
Applied between : P-N, Surge value
Viso
60Hz, Sinusoidal Charged part to Base, AC 1 min.
Isolation Voltage
Condition VD = 13.5 ~ 16.5V, Inverter Part, Tj = 125°C Start
(Note-1)
Ratings
Unit
400
V
500
V
–20 ~ +100
°C
–40 ~ +125
°C
2500
Vrms
PBT
(Note-1) Tc measurement point
B P N W
V
63mm
U
Tc
ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted) INVERTER PART Symbol VCE(sat) VEC ton trr tc(on) toff tc(off) ICES
Parameter
Test Condition
Collector-Emitter Saturation Voltage FWDi Forward Voltage
VD = 15V, IC = 75A Tj = 25°C (Fig. 1) Tj = 125°C VCIN = 0V, Pulsed –IC = 75A, VD = 15V, VCIN = 15V
(Fig. 2)
Switching Time
VD = 15V, VCIN = 15V↔0V VCC = 300V, IC = 75A T j = 125°C Inductive Load
(Fig. 3)
Collector-Emitter Cutoff Current
VCE = VCES , VD = 15V (Fig. 4)
Tj = 25°C Tj = 125°C
Min. — — — 0.8 — — — — — —
Limits Typ. 1.7 1.7 2.2 1.2 0.15 0.4 2.4 0.6 — —
Max. 2.3 2.3 3.3 2.4 0.3 1.0 3.3 1.2 1 10
Unit V V µs µs µs µs µs mA
Sep. 2000
MITSUBISHI
PM75CSD060 FLAT-BASE TYPE INSULATED PACKAGE
CONTROL PART Symbol ID
Parameter Circuit Current
VCIN(ON) Input ON Voltage VCIN(OFF) Input OFF Voltage Over Current Trip Level
OC
SC toff(OC) OT OTr UV UVr IFO(H) IFO(L) tFO
Test Condition VN1 -VNC VXP1-VXPC
VD = 15V, VCIN = 15V
Applied between : UP-VUPC, V P-VVPC, WP-VWPC UN • VN • WN-VNC Tj = –20°C (Fig. 5,6) Tj = 25°C Tj = 125°C
VD = 15V
Short Circuit Trip Level Over Current Delay Time
VD = 15V
Over Temperature protection
VD = 15V, (Lower arm)
Supply Circuit Under-Voltage Protection
–20 ≤ Tj ≤ 125°C
Fault Output Current
VD = 15V, VCIN = 15V
(Note-2)
Minimum Fault Output Pulse Width
VD = 15V
(Note-2)
–20≤ Tj ≤ 125°C, VD = 15V (Fig. 5,6) (Fig. 5,6) Trip level Reset level Trip level Reset level
Min. — — 1.2 1.7 — 192 115
Limits Typ. 40 13 1.5 2.0 — 226 —
Unit
Max. 55 18 1.8 2.3 380 320 —
mA V
A
—
241
—
A
— 111 — 11.5 — — —
10 118 100 12.0 12.5 — 10
— 125 — 12.5 — 0.01 15
µs °C °C V V mA mA
1.0
1.8
—
ms
(Note-2) Fault output is given only when the internal OC, SC, OT & UV protections schemes of either upper or lower arm device operate to protect it.
THERMAL RESISTANCES Symbol Rth(j-c)Q Rth(j-c)F Rth(j-c’)Q
Junction to case Thermal Resistances
Rth(j-c’)F Rth(c-f)
Test Condition
Parameter
Contact Thermal Resistance
Inverter IGBT part (per 1/6 module) Inverter FWDi part (per 1/6 module) Tc measured point is just under the chips Inverter IGBT part (per 1/6 module) Tc measured point is just under the chips Inverter FWDi part (per 1/6 module) Case to fin, (per 1 module) Thermal grease applied
Min. — —
Limits Typ. — —
Max. 0.49 1.38
°C/W °C/W
—
—
0.30*
°C/W
—
—
0.47*
°C/W
—
—
0.027
°C/W
Min. 2.5 2.5 —
Limits Typ. 3.0 3.0 560
Max. 3.5 3.5 —
Unit
*: If you use this value, Rth(f-a) should be measured just under the chips.
MECHANICAL RATINGS AND CHARACTERISTICS Symbol — — —
Test Condition
Parameter Mounting torque Mounting torque Weight
Main terminal Mounting part
screw : M5 screw : M5 —
Unit N•m N•m g
Sep. 2000
MITSUBISHI
PM75CSD060 FLAT-BASE TYPE INSULATED PACKAGE
RECOMMENDED CONDITIONS FOR USE Symbol VCC
Parameter Supply Voltage
VD
Control Supply Voltage
VCIN(ON) VCIN(OFF) fPWM
Input ON Voltage Input OFF Voltage PWM Input Frequency Arm Shoot-through Blocking Time
tdead
Test Condition Applied across P-N terminals Applied between : VUP1-VUPC , VVP1-VVPC VWP1-VWPC, VN1 -VNC
Recommended value ≤ 400
Unit V
15 ± 1.5
V
Applied between : UP-VUPC, V P-VVPC, WP-VWPC UN • VN • WN-V NC Using Application Circuit of Fig.8
≤ 0.8 ≥ 4.0 ≤ 20
V V kHz
For IPM’s each input signals
≥ 2.5
µs
(Note-3)
(Fig. 7)
(Note-3) With ripple satisfying the following conditions dv/dt swing ≤ ±5V/µs, Variation ≤ 2V peak to peak
Sep. 2000
MITSUBISHI
PM75CSD060 FLAT-BASE TYPE INSULATED PACKAGE PRECAUTIONS FOR TESTING 1. Before appling any control supply voltage (VD), the input terminals should be pulled up by resistores, etc. to their corresponding supply voltage and each input signal should be kept off state. After this, the specified ON and OFF level setting for each input signal should be done. 2. When performing “OC” and “SC” tests, the turn-off surge voltage spike at the corresponding protection operation should not be allowed to rise above VCES rating of the device. (These test should not be done by using a curve tracer or its equivalent.) P, (U,V,W) IN Fo
VCIN
P, (U,V,W)
Ic
V
IN Fo
VCIN
–Ic
V
(15V)
(0V)
U,V,W, (N)
VD (all)
U,V,W, (N)
VD (all)
Fig. 1 VCE(sat) Test
Fig. 2 VEC Test
a) Lower Arm Switching P
VCIN (15V)
Fo
Signal input (Upper Arm)
trr CS
VCIN
Signal input (Lower Arm)
VCE
Irr
U,V,W
Ic
Vcc
Fo
90%
90% N
b) Upper Arm Switching
VD (all)
Ic
10%
10%
10%
10%
P
VCIN
tc (on)
Fo
Signal input (Upper Arm)
VCIN
U,V,W
CS
VCIN (15V)
tc (off)
Vcc
td (on)
tr
td (off)
tf
Fo
Signal input (Lower Arm)
(ton= td (on) + tr)
(toff= td (off) + tf)
N
Ic
VD (all)
Fig. 3 Switching time Test circuit and waveform
P, (U,V,W) A
VCIN (15V)
VCIN
IN Fo
Pulse VCE
U,V,W, (N)
VD (all)
Over Current
OC
IC toff (OC)
Fig. 4 ICES Test P, (U,V,W)
Constant Current
Short Circuit Current
IN Fo
VCC
Constant Current SC
VCIN IC VD (all)
U,V,W, (N)
IC
Fig. 5 OC and SC Test
Fig. 6 OC and SC Test waveform P
VD VCINP
U,V,W
Vcc
VD VCINN
N Ic
VCINP 0V
t VCINN
0V
t
tdead
tdead
Fig. 7 Dead time measurement point example
Sep. 2000
MITSUBISHI
PM75CSD060 FLAT-BASE TYPE INSULATED PACKAGE
P 20kΩ
≥10µ
VUP1
→
VD
UFO
IF
Rfo
Vcc Fo
UP
OUT
+ –
Si
In
VUPC
U
GND GND
≥0.1µ
VVP1 VFO
VD
Rfo
Vcc Fo
VP
Si
In
VVPC
WFO
V
GND GND
VWP1 Rfo
Vcc Fo
VD
OUT
WP
OUT Si
In
VWPC
M
W
GND GND
20kΩ
→
Vcc
≥10µ
IF
Fo UN
OUT Si
In GND GND
≥0.1µ
N TEMP
20kΩ
→
Vcc
≥10µ
IF
Fo
VN
Th
OUT Si
In GND GND
≥0.1µ 20kΩ
→
VD
VN1
Vcc
≥10µ
IF
Fo
WN ≥0.1µ
In
OUT Si
GND GND
VNC
NC
NC 5V
1kΩ
Fo
Rfo
: Interface which is the same as the U-phase
Fig. 8 Application Example Circuit
NOTES FOR STABLE AND SAFE OPERATION ; Design the PCB pattern to minimize wiring length between opto-coupler and IPM’s input terminal, and also to minimize the stray capacity between the input and output wirings of opto-coupler. Connect low impedance capacitor between the Vcc and GND terminal of each fast switching opto-coupler. Fast switching opto-couplers : tPLH, tPHL ≤ 0.8µs, Use High CMR type. Slow switching opto-coupler : CTR > 100% Use 4 isolated control power supplies (VD). Also, care should be taken to minimize the instantaneous voltage charge of the power supply. Make inductance of DC bus line as small as possible, and minimize surge voltage using snubber capacitor between P and N terminal. Use line noise filter capacitor (ex. 4.7nF) between each input AC line and ground to reject common-mode noise from AC line and improve noise immunity of the system.
• • • • • • •
Sep. 2000
