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Preliminary Technical Data

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a Video Encoder with six 10-Bit DACs, 54MHz Oversampling and Progressive Scan Inputs ADV7192 Preliminary Technical Data FEATURES Macrovision Rev. 7.1 CGMS (Copy Generation Management System) WSS (Wide Screen Signalling) Closed Captioning support. Teletext Insertion Port (PAL-WST) 2 Wire Serial MPU Interface (I 2C Compatible & Fast I2C) I2C Interface 6 high Quality 10-Bit Video DACs 10-Bit Internal Digital Video Processing Multi-Standard Video Input Multi-Standard Video Output 4xOversampling with internal 54MHz PLL Programmable Video Control includes: Digital Noise Reduction Gamma Correction Black Burst LUMA Delay CHROMA Delay Multiple Luma & Chroma Filters Luma SSAF™ (Super Sub-Alias Filter) APPLICATIONS DVD Playback Systems, PC Video/Multimedia Playback Systems Progressive Scan Playback Systems Y R A IN AL M IC I L N E H A R T P EC A T D Average Brightness detection Field Counter GENERAL Supply Voltage 5V & 3.3V Operation 80-Pin LQFP Package DESCRIPTION The ADV7192 is part of the new generation of video encoders from Analog Devices. The device builds on the performance of previous video encoders and provides new features like interfacing progressive scan devices, Digital Noise Reduction, Gamma Correction, 4xOversampling and 54MHz operation, Average Brightness Detection, Black Burst Signal Generation, Chroma Delay, an additional Chroma Filter, etc. For a more information about the ADV7192s features refer to DETAILED DESCRIPTION. Simplified Block Diagram DIGITAL INPUT: 27MHZ CLOCK VIDEO INPUT PROCESSING: VIDEO OUT PUT PROCESSING: YCrCb TO YUV MATRIX AR L IN I M I CA EL HN PR C TA DA & COLOR CONTROL DNR GAMMA CORRECTION ANALO OUT PUT : 10-BIT DAC CHROMA LPF TE 8-BIT YCrCb IN 4:2:2 FORMAT VIDEO SIGNA PROCESSING: PLL & 54 MHz DEMUX ITU-R BT. 656/601 The ADV7192 supports NTSC-M, NTSC-N (Japan), PAL N, PAL M,PAL-B/D/G/H/I and PAL-60 standards. Input standards supported include ITU-R.BT656 4:2:2 YCrCb in 8-Bit or 16-Bit format and 3x10-Bit YCrCb progressive scan format. The ADV7192can output Composite Video (CVBS), SVideo (Y/C), Component YUV* or RGB and analog progressive scan in YPrPb format. The analog component output is also compatible with Betacam, MII and SMPTE/EBU N10 levels, SMPTE 170M NTSC and ITU-R.BT 470 PAL. SSAF LPF VBI TELETEX LUMA LPF 2x OVE RSAM PLING OR 4x OVE RSAM PLING 10-BIT DAC COMPOSITE VIDEO 10-BIT DAC C [S-VIDEO] 10-BIT DAC RG B YUV Y Pr Pb Y [S-VIDEO] TV-SCREEN OR PROGRESSIVE SCAN DISPAY 10-BIT DAC 10-BIT DAC CLOSED CAPTION CGMS/ WSS I2C INTERFACE ADV7192 REV Pr F 03/00 Notes: SSAF is a trademark of Analog Devices Inc. This device is protected by U.S. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommondations. I2C is a registered trademark of Philips Corporation. One Technology Throughout the document YUV refers to digital or analog component video. Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700. World Wide Web Site: http://www.analog.com Fax: 617/326-8703 Analog Devices, Inc., 2000 Preliminary Technical Data ADV7192 CONTENTS APPENDIX 4 WSS.......................................................64 FEATURES..........................................................1 APPENDIX 5 APPLICATIONS..................................................1 Teletext Insertion.....................................65 BLOCK DIAGRAM..............................................1 SPECIFICATIONS APPENDIX 6 Static Performance 5 V.............................3 Static Performance 3.3 V..........................4 Dynamic Specification 5V.........................5 Dynamic Specification 3.3V......................6 Timing Specification 5V.......................... .7 Timing Specification 3.3V.........................8 Optional output filter................................66 APPENDIX 7 DAC Buffering.........................................67 APPENDIX 8 ABSOLUTE MAXIMUM RATINGS.....................11 PACKAGE THERMAL PERFORMANCE.............11 PIN CONFIGURATION......................................11 PIN DESCRIPTION............................................ 12 Recommended Register Settings ................68 NTSC Register Settings........................... .69 PAL BDGHI Register Settings.................. 69 PAL N Register Settings ......................... .70 Power-on-Reset Register Settings. ........... .70 Y R A IN AL M IC I L N E H A R T P EC A T D GENERAL DESCRIPTION..................................14 DATA PATH DESCRIPTION..............................15 APPENDIX 9 NTSC, PAL, UV waveforms.....................73 INTERNAL FILTER RESPONSE.........................15 Output wave forms....................................76 FUNCTIONAL DESCRIPTION..........................26 TIMING DESCRIPTION APPENDIX 10 NTSC, PAL Vector Plots.........................82 APPENDIX 11 Reset Sequence........................................30 MPU Port Timing....................................9 Pixel Data and Control Data Timing..........9 Teletext Timing.......................................9 Progressive Scan Input Timing..................10 RTC Timing...........................................31 MPU PORT DESCRIPTION Outline Dimensions................................83 Register Access........................................39 Mode Registers 0 - 9............................... 40 Timing Registers......................................47 Sub-carrier frequency & phase Registers... 48 Closed Captioning Registers..................... 48 Pedestal Register......................................49 Teletext Registers.....................................49 CGMS_WSS Registers........................... 50 Y-Scale, U-Scale, V-Scale Registers.......51 Hue Adjust, Brightness Control, Sharpness Control Registers................... 52 DNR Registers.........................................55 Gamma Correction Registers.....................58 Brightness Detect Register.........................59 Output Clock Register......... .....................59 APPENDIX 1 Board Design and Layout Considerations....60 APPENDIX 2 Closed Captioning....................................62 APPENDIX 3 CGMS....................................................63 REV. Pr F 2 ADV7192 Preliminary Technical Data 5V SPECIFICATIONS1 Parameter (VAA = + 5V, VREF = 1.235 V, RSET1,2 =1200 Ω unless otherwise noted. All specifications TMIN to TMAX2 unless otherwise noted) Min Typ STATIC PERFORMANCE Resolution (each DAC) Accuracy (each DAC) Integral Nonlinearity3 Differential Nonlinearity3 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN Input Leakage Current8 Input Leakage Current9 DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Tri-State Leakage Current10 Tri-State Leakage Current11 Tri-State Output Capacitance ANALOG OUTPUTS Output Current(max) Output Current(min) DAC to DAC Matching3 Output Compliance, VOC Output Impedance, ROUT Output Capacitance, COUT VOLTAGE REFERENCE Reference Range, VREF4 POWERREQUIREMENTS V AA Normal Power Mode IDAC4 ICCT (2xOversampling)6,7 ICCT (4xOversampling)6,7 IPLL Sleep Mode IDAC ICCT 2.0 0 6 1 200 Max Units 10 Bits ±1.0 ±1.0 LSB LSB 0.8 +/-1 10 V V µA pF µA µA Y R A IN AL M IC I L N E H A R T P EC A T D 2.4 4.125 0 1.112 4.75 0.8 10 200 6 0.4 4.33 2.16 0.4 4.625 100 6 1.235 10 2.5 1.4 Guaranteed monotonic VIN = 0.4 V or 2.4 V V V µA µA pF ISOURCE = 400 µA ISINK = 3.2 mA mA mA % V kΩ pF RL = 300Ω RL = 600Ω,RSET1,RSET2 = 2400Ω 1.359 V 5.0 5.25 V 29 80 120 6 35 120 170 10 mA mA mA mA 0.01 85 Test Conditions IOUT = 0 mA µA µA NOTES 1 All measurements are in 4xOversampling Mode unless otherwise specified. 2 Temperature range TMIN to TMAX : 0°C to +70° C. 3 Guaranteed by Characterisation 4 Measurement made in 2xOversampling Mode. 5 IDAC is the total current required to supply all DACs including the Vref circuitry. 6 All six DACs on. 7 ICCT or the circuit current, is the continuous current required to drive the digital core without IPLL. 8 For all inputs but PAL_NTSC and ALSB 9 For PAL_NTSC and ALSB inputs 10 For all outputs but VSO/TTX/CLAMP 11 For VSO/TTX/CLAMP output Specifications subject to change without notice. 3 REV. Pr F Preliminary Technical Data ADV7192 3.3V SPECIFICATIONS1 Parameter Min (VAA = + 3.3V, VREF = 1.235 V, RSET1,2 = 1200 Ω unless otherwise noted. All specifications TMIN to TMAX2 unless otherwise noted) Typ STATIC PERFORMANCE Resolution (each DAC) Accuracy (each DAC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Leakage Current7 Input Leakage Current8 Input Capacitance, CIN DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Tri-State Leakage Current9 Tri-State Leakage Current10 Tri-State Output Capacitance ANALOG OUTPUTS Output Current (max) Output Current (min) DAC to DAC Matching Output Compliance, VOC Output Impedance, ROUT Output Capacitance, COUT VOLTAGE REFERENCE Reference Range, VREF 3 POWER REQUIREMENTS V AA Normal Power Mode IDAC(max)4 ICCT (2xOversampling)5,6 ICCT (4xOversampling)5,6 IPLL Sleep Mode IDAC ICCT 2 0.8 1 200 6 Max 10 Bits ±1.0 ±1.0 LSB LSB +/-1 10 V V µA µA µA pF Y R A IN AL M IC I L N E H A R T P EC A T D 2.4 0.4 10 200 6 4.125 4.33 2.16 0.4 100 6p 10 4.625 2.5 1.4 1.235 3.15 VIN = 0.4 V or 2.4 V mA mA % V KΩ pF RL = 300Ω RL = 600Ω,RSET1, SET2 = 2400Ω V IVREFOUT=20µA V 29 42 68 6 54 86 mA mA mA mA µA µA 4 Guaranteed Monotonic ISOURCE = 400 µA ISINK = 3.2 mA 3.6 0.01 85 Test Conditions V V µA µA pF 3.3 NOTES 1 All measurements are made in 4xOversampling unless otherwise specified and are guaranteed by characterisation. In 2x Oversampling the power requirement for the ADV7192 is typically 3.0V 2 Temperature range TMIN to TMAX : 0°C to +70°C. 3 Measurement made in 2xOversampling Mode. 4 IDAC is the total current required to supply all DACs including the VREF circuitry. 5 All 6 DACs on. 6 ICCT or the circuit current, is the continuous current required to drive the digital core without IPLL. 7 For all inputs but PAL_NTSC and ALSB 8 For PAL_NTSC and ALSB inputs 9 For all outputs but VSO/TTX/CLAMP 10 For VSO/TTX/CLAMP output Specifications subject to change without notice. REV. Pr F Units IOUT = 0 mA ADV7192 Preliminary Technical Data 1 5V DYNAMIC-SPECIFICATIONS Parameter Min Typ (VAA = + 5V ± 250mV, VREF = 1.235 V, RSET1,2 =1200Ω Ω unless otherwise noted. All specifications TMIN to TMAX2 unless otherwise noted) Max Units o Hue Accuracy 0.5 Color Saturation Accuracy 0.7 Chroma Nonlinear Gain 0.7 Chroma Nonlinear Phase 0.5 ±o Chroma/Luma Intermod 0.1 ±% Chroma/ Luma Gain Inequality 1.7 % Chroma/ Luma Delay Inequality 2.2 ns Luminance Nonlinearity Chroma AM Noise Chroma PM Noise Differential Gain Differential Phase SNR (Pedestal) SNR (Pedestal) SNR (Ramp) SNR (Ramp) % 0.9 ±% Y R A IN AL M IC I L N E H A R T P EC A T D 0.6 Test Conditions 0.7 Referenced to 40 IRE ±% 82 dB 72 dB 0.1 0.3 % 0.4 0.5 o 78.5 dB rms RMS 78 dB p-p Peak Periodic 61.7 dB rms RMS 62 dB p-p Peak Periodic 2XOVERSAMPLING MODE Differential Gain 0.4 0.5 % Differential Phase 0.15 0.3 o SNR (Pedestal) 78 dB rms RMS SNR (Pedestal) 78 dB p-p Peak Periodic SNR (Ramp) 61.7 dB rms RMS SNR (Ramp) 63 dB p-p Peak Periodic NOTES 1 All measurements are made in 4xOversampling unless otherwise specified and are guaranteed by characterisation. 2 Temperature range TMIN to TMAX : 0°C to +70° C. Specifications subject to change without notice. 5 REV. Pr F Preliminary Technical Data ADV7192 +/-150mV, V 3.3V DYNAMIC-SPECIFICATIONS1 (Vnoted.= +All3.3Vspecifications T = 1.235 V, RSET1,2 = 1200 Ω unless otherwise to TMAX2 unless otherwise noted) MIN AA Parameter Min Typ Max REF Units Hue Accuracy 0.5 o Color Saturation Accuracy 0.8 % Luminance Nonlinearity 0.6 ±% Chroma AM Noise 83 dB Chroma PM Noise 71 dB Chroma Nonlinear Gain 0.7 ±% Chroma Nonlinear Phase 0.5 ±o Chroma/Luma Intermod Y R A IN AL M IC I L N E H A R T P EC A T D Test Conditions Referenced to 40 IRE 0.1 ±% 2.0 % 2.5 ns 0.2 % 0.5 o 78.5 dB rms RMS 78 dB p-p Peak Periodic 62.3 dB rms RMS 61 dB p-p Peak Periodic Differential Gain 0.5 % Differential Phase 0.2 o SNR (Pedestal) 78 dB rms RMS SNR (Pedestal) 78 dB p-p Peak Periodic SNR (Ramp) 62 dB rms RMS SNR (Ramp) 62.5 dB p-p Peak Periodic Chroma/ Luma Gain Inequality Chroma/ Luma Delay Inequality Differential Gain Differential Phase SNR (Pedestal) SNR (Pedestal) SNR (Ramp) SNR (Ramp) 2XOVERSAMPLING MODE NOTES 1 All measurements are made in 4xOversampling unless otherwise specified. 2 Temperature range TMIN to TMAX : 0° C to +70°C. Specifications subject to change without notice. REV. Pr F 6 ADV7192 Preliminary Technical Data 5V TIMING–SPECIFICATIONS Parameter Min MPU PORT2 SCLOCK Frequency SCLOCK High Pulse Width, t1 SCLOCK Low Pulse Width, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition) , t8 ANALOG OUTPUTS2 Analog Output Delay DAC Analog Output Skew 0 0.6 1.3 0.6 0.6 100 RESET CONTROL Reset Low Time PLL Max Units 400 kHz µs µs µs µs ns ns ns µs 300 300 0.6 8 0.1 ns ns 27 13 12 57 67 MHz ns ns ns ns ns ns ns ns Clock cycles Clock cycles 11 3 6 ns ns ns Test Conditions After this period the 1st clock is generated Relevant for repeated Start Condition Y R A IN AL M IC I L N E H A R T P EC A T D CLOCK CONTROL AND PIXEL PORT3 FCLOCK Clock High Time t9 Clock Low Time t10 Data Setup Time t11 Data Hold Time t12 Control Setup Time t11 Control Hold Time t12 Digital Output Access Time t13 Digital Output Hold Time t14 Pipeline Delay t15(2xOversampling) Pipeline Delay t15(4xOversampling) TELETEXT PORT4 Digital Output Acces Time t16 Data Setup Time t17 Data Hold Time t18 Typ Ω unless otherwise (VAA = + 5V ± 250mV, VREF = 1.235 V, RSET1,2 =1200Ω noted. All specifications TMIN to TMAX1 unless otherwise noted) 8 8 6 5 6 4 3 20 ns 2 PLL Output Frequency 54 MHz NOTES 1 Temperature range TMIN to TMAX : 0°C to +70° C. 2 Guaranteed by characterization. 3 Pixel Port consists of the following: Data: P9-P0, Y9/P10-Y9/P19 Pixel Inputs Control: HSYNC, VSYNC, BLANK Clock: CLKIN Input 4 Teletext Port consists of the following: Digital Output:TTXRQ Data: TTX Specifications subject to change without notice. 7 REV. Pr F Preliminary Technical Data ADV7192 3.3V TIMING–SPECIFICATIONS2 Parameter MPU PORT SCLOCK Frequency SCLOCK High Pulse Width, t1 SCLOCK Low Pulse Width, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition) , t8 ANALOG OUTPUTS Analog Output Delay DAC Analog Output Skew CLOCK CONTROL AND PIXEL PORT3 FCLOCK Clock High Time t9 Clock Low Time t10 Data Setup Time t112 Data Hold Time t122 Control Setup Time t112 Control Hold Time t122 Digital Output Access Time t13 Digital Output Hold Time t14 Pipeline Delay t15 TELETEXT PORT4 Digital Output Acces Time t16 Data Setup Time t17 Data Hold Time t18 RESET CONTROL Reset Low Time Min Typ 0 0.6 1.3 0.6 0.6 100 0.6 2 (VAA = + 3.3V +/-150mV, VREF = 1.235 V, RSET1,2 = 1200 Ω unless otherwise noted. All specifications TMIN to TMAX1 unless otherwise noted) Max Units 400 kHz µs µs µs µs ns ns ns µs 300 300 8 0.1 ns ns 27 13 12 37 MHz ns ns ns ns ns ns ns ns Clock cycles 11 3 6 ns ns ns 8 8 6 4 2.5 3 3 20 54 ns MHz NOTES 1 Temperature range TMIN to TMAX : 0° C to +70°C. 2 Guaranteed by characterization. 3 Pixel Port consists of the following: Data: P9-P0, Y9/P10-Y9/P19 Pixel Inputs Control: HSYNC, VSYNC, BLANK Clock: CLKIN Input 4 Teletext Port consists of the following: Digital Output:TTXRQ Data: TTX Specifications subject to change without notice. REV. Pr F After this period the 1st clock is generated Relevant for repeated Start Condition Y R A IN AL M IC I L N E H A R T P EC A T D PLL PLL Output Frequency Test Conditions 8 ADV7192 Preliminary Technical Data t5 t3 t3 SD A t6 t1 SC L t2 t7 t4 t8 Figure 1. MPU Port Timing Diagram Y R A IN AL M IC I L N E H A R T P EC A T D CLOCK t9 CO NTRO L I/ P S t12 t10 HS YNC , VS YN C , BLANK P I X E L IN P U T D ATA Cb Y Cr Y Cb t11 CO NTRO L O /PS Y t1 3 HS YNC , VS YN C , BLANK CSO_HSO, VSO, CLAM P t14 Figure 2. Pixel and Control Data Timing Diagram ~ ~ ~ ~ TXTREQ t1 6 CLOCK t1 7 ~ ~ t1 8 T XT ~ ~ 4 CLOCK C YC L E S 4 CLOCK C YC L E S 4 CLOCK C YC L E S 3 CLOCK C YC L E S 4 CLOCK C YC L E S Figure 3. Teletext Timing Diagram 9 REV. Pr F Preliminary Technical Data ADV7192 CLOCK t9 { P R O G R E S S IV E S C A N IN P U T Y0-Y9 IN C L U D IN G SYNC IN F O R M A T IO N t1 2 t1 0 Y0 Y1 Y2 Y3 Y4 Y5 C b 0 -C b 9 Cb0 Cb1 Cb2 Cb3 Cb4 Cb5 C r 0 -C r 9 Cr0 Cr1 Cr2 Cr3 Cr4 Cr5 t1 1 Y R A IN AL M IC I L N E H A R T P EC A T D Figure 4. Progressive Scan Input Timing REV. Pr F 10 ADV7192 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS * PACKAGE THERMAL PERFORMANCE The 80pin package is used for this device. The junction-toambient (θJ-A) thermal resistance in still air on a four layer PCB is 24.7OC/W. VAA to GND.............................................................7V Voltage on any Digital Input Pin...........GND-0.5V to VAA+0.5V Storage Temperature (TS)....................-65OC to +150OC Junction Temperature(TJ)..................................+150OC Body Temperature (Soldering, 10 secs)................+220°C Analog Outputs to GND1.....................GND -0.5 to VAA To reduce power consumption when using this part the user can run the part on a 3.3V supply, turn off any unused DACs. The user must at all times stay below the maximum junction temperature of 110OC. The following equation shows how to calculate this junction temperature: NOTES * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 Analog Output Short Circuit to any Power Supply or Common can be of an indefinite duration. Junction Temperature = [VAA x ( IDAC + ICCT) ] x θJ-A + 70OC(TAMB) ORDERING GUIDE Average current consumed by each powered-on DAC = (VREF x K ) / RSET LQFP Y R A IN AL M IC I L N E H A R T P EC A T D VREF = 1.235V K = 4.2146 69 68 67 66 65 64 63 62 CSO _ HSO 70 Cr [0] 7 2 71 VSO /T TX/C LAM P Cr [5] DG ND 73 Cr [1] Cr [7] Cr [6] 75 74 Cr [3] Cr [8] 76 Cr [2] Cr [ 9] 77 VDD Cb [1] Cb [0] 78 Cr [4] Cb [2] 80 79 DG ND Cb [3] PIN CONFIGURATION VDD 61 6 0 RE SE T NC 1 P IN 1 ID E N T IF IE R NC 2 5 9 PAL_ NTS C P0 3 5 8 R SE T 1 P1 4 5 7 V R EF P2 5 5 6 CO M P1 P3 6 55 P4 7 5 4 DAC B DAC A 5 3 VAA P5 8 P6 9 P7 1 0 Y[0]/ P8 1 1 A D V 71 9 2 LQ FP 5 2 AG ND TOP VIEW (Not to Scale) 5 0 DAC D 5 1 DAC C 4 9 AG ND Y[1]/ P9 1 2 V AA Y[2]/ P1 0 1 3 48 Y[3]/ P1 1 1 4 4 7 DAC E Y[4]/ P1 2 1 5 4 6 DAC F Y[5]/ P1 3 1 6 4 5 CO M P2 Y[6]/ P1 4 1 7 4 4 R SE T 2 32 33 34 35 36 37 38 39 40 CL KO UT V AA SDA SCL 31 AG ND 29 30 CL KIN 28 VDD 26 27 DG ND 25 Cb [9] 24 TTX RE Q 23 Cb [8] 22 Cb [5] 21 Cb [7] 4 1 S C R ES ET / R TC /TR Cb [6] ALS B Y[9] 2 0 Cb [4] DG ND 42 BLAN K 43 Y[8] 1 9 VSYN C Y[7]/ P1 5 1 8 HSYNC 0oC to 70oC VD D ADV7192 KST IDAC = 10 mA + (sum of the average currents consumed by each powered-on DAC) Temperature Range Package Option DG ND Model Figure 5. Pin Configuration ADV7192 11 REV. Pr F Preliminary Technical Data ADV7192 PIN DESCRIPTION Mnemonic Input/Output Function AGND G Analog Ground ALSB I TTL Address Input. This signal sets up the LSB of the MPU address. BLANK I/O Video Blanking Control Signal. This signal is optional. For further information see page 29. CLKIN I TTL Clock Input. Requires a stable 27MHz reference clock for standard operation. Alternatively a 24.5454MHz (NTSC) or 29.5MHz (PAL) can be used for square pixel operation. CLKOUT O Clock Output pin. COMP 1 O Compensation Pin for DACs A, B and C. Connect a 0. lµF Capacitor from COMP1 to VAA. COMP 2 O CSO_HSO O DAC A O DAC B O DAC C O DAC D O DAC E O DAC F O S-Video C / Pr /V / RED Analog Output. This DAC is capable of providing 4.33mA output DGND G Digital Ground HSYNC I/O HSYNC (Modes 1, 2 and 3) Control Signal. This pin may be configured to be an output (Master Mode) or an input (Slave Mode) and accept Sync signals. P0-P7 I 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port. The LSB of the input data is set up on pin P0 (pin number 3). Cb0 - Cb9 I 1x10Bit Progressive scan input port for Cb data. Cr0 - Cr9 I 1x10Bit Progressive scan input port for Cr data. PAL_NTSC I Input signal to select PAL or NTSC mode of operation, pin set to Logic 1 selects PAL. REV. Pr F Y R A IN AL M IC I L N E H A R T P EC A T D Compensation Pin for DACs D, E and F. Connect a 0. lµF Capacitor from COMP2 to VAA. Dual function CSO or HSO output sync signal at TTL level. Composite/ Y (progressive scan) / Y / GREEN Analog Output. This DAC is capable ofproviding 4.33mA output. S-Video Y /Pb / U / BLUE Analog Output. This DAC is capable of providing 4.33mA output. S-Video C / Pr / V /RED Analog Output. This DAC is capable of providing 4.33mA output. Composite / Y (progressive scan) / Y / GREEN Analog Output. This DAC is capable of providing 4.33mA output. S-Video Y / Pb / U/ BLUE Analog Output. This DAC is capable of providing 4.33mA output. 12 ADV7192 Preliminary Technical Data SCRESET/RTC/TR I Multifunctional Input: Real Time Control(RTC) input, Timing Reset input, Subcarrier Reset input. RESET I The input resets the on-chip timing generator and sets the ADV7192 into default mode See Appendix 8 for default register settings. R SET1 I A 1200 Ohm resistor connected from this pin to GND is used to control fullscale amplitudes of the Video Signals from the DAC A, B, C. R SET2 I A 1200 Ohm resistor connected from this pin to GND is used to control fullscale amplitudes of the Video Signals from the DAC D, E, F. SCL I MPU Port Serial Interface Clock Input. SDA I/O MPU Port Serial Data Input/Output. TTXREQ O Teletext Data Request Output Signal, used to control teletext data transfer. V AA P Analog Power Supply (+3.3V to + 5 V). VDD P Digital Power Supply (+3.3V to + 5 V). V REF I/O Voltage Reference Input for DACs or Voltage Reference Output (1.235V ). An external VREF can not be used in 4xOversampling Mode. VSO/TTX/CLAMP I/O Multifunctional pin. VSO Output Sync Signal at TTL level.Teletext Data Input pin. CLAMP TTL Output Signals can be used to drive external circuitry to enable clamping of all video signals. VSYNC I/O VSYNC control signal. This pin may be configured as an output (Master Mode) or or as an input (Slave Mode) and accept VSYNC as a control signal. Y 0/P8 -Y7/P15 I 16-Bit 4:2:2 Multiplexed YCrCb Pixel Port (bits 8-15). 1x10-Bit Progressive scan input port for Y data (bits 0-7). Y8-Y9 I 1x10Bit Progressive scan input port for Y data (bits 8 and 9). Y R A IN AL M IC I L N E H A R T P EC A T D 13 REV. Pr F Preliminary Technical Data ADV7192 DETAILED DESCRIPTION Digital Noise Reduction allows improved picture quality in removing low amplitude, high frequency noise. The block diagram below shows the DNR functionality in the two modes available. The ADV7192 features: Clocking: Single 27MHz Clock required to run the device 4xOversampling with internal 54MHz PLL Square Pixel operation Advanced Power Management Programmable Video Control features: Digital Noise Reduction Black Burst Signal Generation Pedestal level Hue, Brightness, Contrast and Saturation Clamping Output signal VBI (Vertical Blanking Interval) Sub-Carrier Frequency and Phase LUMA Delay CHROMA Delay Gamma Correction Luma & Chroma Filters Luma SSAF (Super Sub-Alias Filter) Average Brightness detection Field Counter Interlaced/Non Interlaced Operation Complete on-chip Video Timing Generator Programmable Multi-Mode Master/Slave Operation Macrovision Rev 7.1 CGMS (Copy Generation Management System) WSS (Wide Screen Signalling) Closed Captioning support. Teletext Insertion Port (PAL-WST) 2 Wire Serial MPU Interface (I2C Compatible & Fast I2C) I2C Registers synchronised to VSYNC DNR M ode B lo c k s iz e c o n t ro l Border area B lo c k o f f s e t G A IN C o r in g G a in D a t a C o r in g G a in B o rd e r N O IS E S I G N A L PA T H Su b trac t sig n al in T hresh o ld ran g e fro m orig ina l s ig n al IN P U T F IL T E R BLOCK Y D ata IN P U T F IL T E R O U T P U T < T H R ES H O L D ? F IL T E R O U T P U T > THRESHO LD - M A IN SIG N A L P A T H + DNR S harpness M ode Σ DN R O U T D N R C O NT R OL B lo c k s iz e c o n t ro l B o rd e r a r e a B lo c k o ff s e t G AI N C o rin g G a in D a t a C o ri n g G a i n B o rd e r N O IS E S IG N AL PA T H Ad d s ig n al ab o ve T h resh o ld ran g e to origin al sig na l IN P U T F IL T E R BL O C K Y D a ta INP UT F I L T E R O U T PU T > TH R E S HO L D ? F IL T ER O U T P U T < THRESHO L D + + M A IN SIG N A L P AT H Y R A IN AL M IC I L N E H A R T P EC A T D Σ DNR OU T Figure xx Block diagram for DNR Mode and DNR Sharpness Mode Programmable gamma correction is also available. The figure below shows the response of different gamma values to a ramp signal. G am m a Correction B lock O utput to a Ramp In p ut for arious G am m a Va lue s 250 G am m a C orre c tio n Blo c k Ou tp ut to a R a m p In put f or a rio u s G am m a Va lue s G a m m a C orre ct ed A m plitu d e 200 The ADV7192 is an integrated Digital Video Encoder that converts digital CCIR-601/656 4:2:2 8 or 16 bit component video data into a standard analog baseband television signal compatible with world wide standards. Additionally there is the possibility to input video data in 3x10 bit YCrCb progressive scan format to faciliate interfacing devices such as progressive scan systems. There are six DACs available on the ADV7192, each of these DACs is capable of providing 4.33mA of current. In addition to the composite output signal there is the facility to output S-Video (Y/C Video), RGB Video and YUV Video. All YUV formats (SMPTRE/EBU N10, MII or Betacam) are supported. 0.5 1.5 150 1.8 100 S ig na l In pu t 50 50 100 150 200 250 Location Figure xx The on-board SSAF (Super Sub-Alias Filter) with extended luminance frequency response and sharp stop-band attenuation enables studio quality video playback on modern TVs, giving optimal horizontal line resolution. An additional sharpness control feature allows high frequency enhancement on the luminance signal. REV. Pr F D N R C ON TR OL 14 Signal Input (Ramp) and selectable Gamma Output curves ADV7192 Preliminary Technical Data The ADV7192 also supports both PAL and NTSC square pixel operation. In this case the encoder requires a 24.5454 MHz Clock for NTSC or 29.5MHz Clock for PAL square pixel mode operation. All internal timing is generated on-chip. The device is driven by a 27 MHz clock. Data can be output at 27Mhz or 54Mhz (on-board PLL) when 4xOversampling is enabled. Also, the output filter requirements in 4xOversampling and 2xOversampling differ, as can be seen in the figure below. An advanced power management circuit enables optimal control of power consumption in both normal operating modes or sleep modes. 2X Filter Requireme nts 0 dB 4X Filter Requirements The functional features or controls are described in detail on page 26 - 30. - 3 0 dB 13.5M Hz 6.7 5M Hz 27.0M Hz 40.5M Hz The Output Video Frames are synchronised with the incoming data Timing Reference Codes. Optionally the Encoder accepts (and can generate) HSYNC, VSYNC & FIELD timing signals. These timing signals can be adjusted to change pulse width and position while the part is in master mode. 54.0M Hz Figure xx. Output Filter Requirements in 4xOversampling Mode HSO/CSO and VSO TTL outputs are also available and are timed to the analog output video. Y R A IN AL M IC I L N E H A R T P EC A T D AD V7192 2 X ENO CD ER CORE P ixel B us MPEG2 27M H z 54M H z PLL A separate teletext port enables the user to directly input teletext data during the vertical blanking interval. 6 I N T E R P O L A T I O N D A C The ADV 7192 also incorporates WSS and CGMS-A data control generation. 54M H z O U TP U T RATE O U T P U T S The ADV7192 modes are set up over a two wire serial bi-directional port (I2C Compatible) with 2 slave addresses and the device is register compatible with the ADV7172/73. Figurexx PLL and 4xOversampling block diagram The ADV7192 is packaged in a 80-Pin LQFP package. DETAILED BLOCKDIAGRAM PAL_NTSC HSYNC VSYN C C G M S /W S S & C L O S E D C A P T IO N N IN G C O N TR O L SD A ALSB I2 C M P U P O R T L E TE LE TE XT IN S E R T IO N BLOCK C PR OGR AM M ABLE CHROM A F IL T E R 1 0 - B IT D AC DAC A 1 0 - B IT D AC DAC B 1 0 - B IT D AC DAC C VR EF Y C L K IN V A 10 V T 10 L A U 10 S A T U R A T IO N CONTROL & ADD BU RST & IN T E R P O L A T O R I N T E R P O L A T O R R S E T2 CO M P2 R A 10 M U L T I P L E X E R C b 0 -C b9 DAC C O N TR O L BLOCK PR OGR AM M ABLE LUM A F IL T E R & SH AR PN ESS F IL T E R IC U DNR & GAMMA C O R R E C T IO N N P15 10 A DEMUX Y C rC b TO YU V M A T R IX D 10 P0 Y Y H 10 10 10 B R IG H T N E S S CONTROL & ADD SYNC & IN T E R P O L A T O R C r0 -Cr9 IN IM T AD V 7192 TTX YU V TO R G B M A T R IX & YUV L EVEL CONTROL BLO CK E R RE SET TTX R Q Y 0 -Y 9 P V ID E O T IM I N G G E N E R A TO R BLAN K SC L CSO _H SO V S O /C L A M P M O D U L ATO R & HUE CONTROL I N T E R P O L A T O R 1 0 - B IT D AC DAC F 1 0 - B IT D AC DAC E DAC C O N TR O L BLOCK PLL DAC D 1 0 - B IT D AC R S E T1 CO M P1 CLKOU T R E A L -T IM E C O N TR O L C IR C U I T S IN /C O S DDS BLOCK S C R E S E T /R T C /T R 15 REV. Pr F Preliminary Technical Data ADV7192 DATA PATH DESCRIPTION. The YCrCb data is also used to generate RGB data with appropriate sync and blank levels. The YUV levels can be scaled to output the suitable SMPTE/EBU N10, MII or Betacam levels. For PAL B,D,G,H,I, M, N and NTSC M, N modes, YCrCb 4:2:2 Data is input via the CCIR-656 /601 compatible Pixel Port at a 27MHz Data Rate. The Pixel Data is de-multiplexed to form three data paths. Y has typically a range of 16 to 235, Cr and Cb have typically a range of 128+/-112, however it is possible to input data from 1 to 254 on both Y, Cb and Cr. The ADV7192 supports PAL (B,D,G,H,I,N, M) and NTSC M, N (Japan)[with and without Pedestal] and PAL60 standards. Each DAC can be individually powered off if not required. A complete description of DAC output configurations is given on page 41. Video output levels are illustrated in Appendix 9. When used to interface progressive scan systems, the ADV7192 allows to input YCrCb signals in Progressive Scan format (3x10Bit) before these signals are routed to the interpolation filters and the DACs. Digital Noise Reduction can be applied to the Y signal. Programmable gamma correction can also be applied to the Y signal if required. The Y data can be manipulated for contrast control and a setup level can be added for brightness control. The Cr, Cb data can be scaled to achieve color saturation control. All settings become effective at the start of the next field when double buffering is enabled. The appropriate sync, blank and burst levels are added to the YCrCb data. Closed-Captioning and Teletext levels are also added to Y and the resultant data is interpolated to 54MHz (4xOversampling Mode). The interpolated data is filtered and scaled by three digital FIR filters. The U and V signals are modulated by the appropriate SubCarrier Sine/Cosine waveforms and a phase offset may be added onto the colour subcarrier during active video to allow hue adjustment. The resulting U and V signals are added together to make up the Chrominance Signal. The Luma (Y) signal can be delayed by up to 6 clock cycles (at 27 MHz) and the Chroma signal can be delayed by up to 8 clock cycles (at 27 MHz). The Luma and Chroma signals are added together to make up the Composite Video Signal. All timing signals are controlled. INTERNAL FILTER RESPONSE The Y Filter supports several different frequency responses including two low-pass responses, two notch responses, an Extended (SSAFTM) response with or without gain boost/ attenuation, a CIF response and a QCIF response. The UV Filter supports several different frequency responses including five low-pass responses, a CIF response and a QCIF response, as- can be seen in the figures on the following pages. Y R A IN AL M IC I L N E H A R T P EC A T D In Extended Mode there is the option of twelve responses in the range from -4dB to +4dB. The desired response can be chosen by the user by programming the correct value via the I2C. The variation of frequency responses can be seen in the figures on the following pages. For more detailed filter plots refer to the application note ANxxx. P A S S B A N D R IP P L E 1 F IL T E R S E L E C T IO N F IL T E R T Y P E 3 d B B A N W ID T H 2 (M H z ) (d B ) S TO P B AN D S TO P BA N D C U T O F F 3 ( M H z ) A T T E N U A T IO N 4 (d B ) M R 04 M R 03 MR02 L O W P A S S (N T S C ) 0 0 0 0.16 4.24 6.05 L O W P A S S (P A L ) 0 0 1 0.1 4.81 6.41 -6 4 .6 N O T C H (N T S C ) 0 1 0 0.09 2.27/4.9/6.6 8.03 -8 7 .3 N O T C H (P A L ) 0 1 1 0.1 3.1/5.6/6.38 8.02 -7 9 .7 E X T E N D E D (S S A F ) 1 0 0 0.043 6.45 8.03 -8 6 .6 C IF 1 0 1 0.127 3.02 5.09 -6 2 .6 Q C IF 1 1 0 M onotonic 1.5 3.74 -8 8 .2 -7 5 .2 Figure 6. Luminance Internal Filter Specifications (4xOversampling) F IL T E R S E L E C T IO N F IL T E R T Y P E PASSBAND 3 d B B A N W ID T H 2 S TO P BA N D S TO P B AN D R IP P L E 1 (d B ) (M H z ) C U T O F F 3 (M H z ) A T T E N U A T IO N 4 (d B ) M R 07 M R 06 MR05 1 .3 M H z L O W P A S S 0 0 0 0.09 1.397 2.46 0 .6 5 M H z L O W P A S S 0 0 1 M onoto nic 0.653 2.41 -7 1 .1 1 .0 M H z L O W P A S S 0 1 0 M onoto nic 1.0 1.89 -6 4 .4 3 2 .0 M H z L O W P A S S 0 1 1 0.048 2.22 3.1 -6 5 .9 3 .0 M H z L O W P A S S 1 0 0 M onoto nic 3.2 5.3 - 84 .5 C IF 1 0 1 M onoto nic 0.653 2.41 -7 1 .1 Q C IF 1 1 0 M onoto nic 0.5 1.75 -3 3 .1 -8 3 .9 Figure 7. Chrominance Internal Filter Specifications (4xOversampling) 1 Passband Ripple refers to the maximum fluctuations from the 0dB response in the passband, measured in [dB]. The pass band is have 0 [Hz] to fc [Hz] frequency limits for a low pass filter, 0[Hz] to f1[Hz] and f2 [Hz] to infinity for a notch filter, where fc, f1, f2 are the -3dB points. 2 3dB bandwidth refers to the -3dB cut off frequency. 3 Stopband Cutoff refers to the frequency [MHz] at attenuation point [dB] refered to under note 4. 4 Stopband Attenuation refers to the attenuation[dB] at the frequency [MHz] refered to under note 3. REV. Pr F 16 defined to ADV7192 Preliminary Technical Data 0 -10 M ag nitude [dB] -20 -30 -40 -50 -60 -70 0 Y R A IN AL M IC I L N E H A R T P EC A T D 2 4 6 8 10 12 Freq uency [M H z] Figure 8 Luma NTSC Low Pass Filter (4xOversampling) 0 Ma g nitud e [d B ] -10 -20 -30 -40 -50 -60 -70 0 2 4 6 8 10 12 Freq ue ncy [M Hz ] Figure 9 Luma PAL Low Pass Filter (4xOversampling) 17 REV. Pr F Preliminary Technical Data ADV7192 0 M a g nitud e [d B ] -1 0 -2 0 -3 0 -4 0 -5 0 -6 0 -7 0 0 Y R A IN AL M IC I L N E H A R T P EC A T D 2 4 6 8 10 12 Freq ue nc y [M H z] Figure 10 Luma NTSC Notch Filter (4xOversampling) 0 M ag nitude [dB] -10 -20 -30 -40 -50 -60 -70 0 2 4 6 8 10 Freq uenc y [M Hz] Figure 11 Luma PAL Notch Filter (4xOversampling) REV. Pr F 18 12 ADV7192 Preliminary Technical Data 0 Ma g nitud e [dB] -10 -20 -30 -40 -50 -60 -70 0 Y R A IN AL M IC I L N E H A R T P EC A T D 2 4 6 8 10 12 Freq ue nc y [MH z] Figure 12 Extended (SSAF) Luma Filter (4xOversampling) 4 2 Magnitud e (dB) 0 -2 -4 -6 -8 -10 -12 0 1 2 3 4 5 6 7 Frequency (M Hz) Figure 13. Extended (SSAF) Luma Filter and programmable gain/attenuation, showing range +4/-12 dB (4xOversampling Mode) 19 REV. Pr F Preliminary Technical Data ADV7192 5 4 Magnitud e (dB) 3 2 1 Y R A IN AL M IC I L N E H A R T P EC A T D 0 -1 0 1 2 3 4 5 6 7 Frequency (M Hz) Figure 14 Extended (SSAF) Luma Filter and programmable gain, showing range -0/+4 dB (4xOversampling Mode) 1 0 Magnitud e (dB) -1 -2 -3 -4 -5 0 1 2 3 4 5 6 Frequency (MHz) REV. Pr F Figure 15. Extended (SSAF) Luma Filter and programmable attenuation, showing range 0/-4dB (in 4xOversampling Mode) 20 7 ADV7192 Preliminary Technical Data 0 M ag nitude [dB] -10 -20 -30 -40 -50 -60 -70 0 Y R A IN AL M IC I L N E H A R T P EC A T D 2 4 6 8 10 12 Freq uency [M H z] Figure 16 Luma CIF Filter (4xOversampling) 0 M ag nitude [dB] -10 -20 -30 -40 -50 -60 -70 0 2 4 6 8 10 12 Freq uenc y [M hz] Figure 17 Luma QCIF Filter (4xOversampling) 21 REV. Pr F Preliminary Technical Data ADV7192 0 -10 M ag nitude [dB] -20 -30 -40 Y R A IN AL M IC I L N E H A R T P EC A T D -50 -60 -70 0 2 4 6 8 10 12 Freq uenc y [M Hz] Figure 18 Chroma 0.65MHz Low Pass Filter (4xOversampling) 0 -10 M a g nitude [dB] -20 -30 -40 -50 -60 -70 0 2 4 6 8 Freq uenc y [M H z ] Figure 19 REV. Pr F Chroma 1.0MHz Low Pass Filter (4xOversampling) 22 10 12 ADV7192 Preliminary Technical Data 0 -10 Ma g ni tud e [ dB] -20 -30 -40 Y R A IN AL M IC I L N E H A R T P EC A T D -50 -60 -70 0 2 4 6 8 10 12 Frequency [MHz] Figure 20 Chroma 1.3MHz Low Pass Filter (4xOversampling) 0 -10 M agnitude [dB ] -20 -30 -40 -50 -60 -70 0 2 4 6 8 10 12 Freque ncy [M Hz ] Figure 21 Chroma 2.0MHz Low Pass Filter (4xOversampling) 23 REV. Pr F Preliminary Technical Data ADV7192 0 -10 M agnitude [dB] -20 -30 -40 Y R A IN AL M IC I L N E H A R T P EC A T D -50 -60 -70 0 2 4 6 8 10 12 Frequency [M Hz] Figure 22 Chroma 3.0MHz Low Pass Filter (4xOversampling) 0 -1 0 M a g nitud e [dB ] -2 0 -3 0 -4 0 -5 0 -6 0 -7 0 0 2 4 6 8 Freq ue nc y [M H z] Figure 23 Chroma CIF Filter (4xOversampling) REV. Pr F 24 10 12 ADV7192 Preliminary Technical Data 0 -10 Mag nitude [dB] -20 -30 -40 -50 Y R A IN AL M IC I L N E H A R T P EC A T D -60 -70 0 2 4 6 8 10 12 Freq uenc y [MHz] Figure 24 Chroma QCIF Filter (4xOversampling) 25 REV. Pr F Preliminary Technical Data ADV7192 CLAMP O/P signals FEATURES: FUNCTIONAL DESCRIPTION BLACK BURST OUTPUT It is possible to output a black burst signal from two DACs. This signal output is very useful for professional video equipment since it enables two video sources to be locked together.[Mode Register 9 ]. CVBS output pin MR57=1 CLAMP output pin MR57=0 Figure 27 Clamp output timing CSO, HSO AND VSO OUTPUTS D IG IT A L D A T A G E N E R A TO R A D V 7192 The ADV7192 supports 3 output timing signals, CSO (composite sync signal), HSO (horizontal sync signal) andVSO (vertical sync signal). These output TTL signals are aligned with the analog video outputs. See figure below for an example of these waveforms.[Mode Register 7]. C V B S B L A C K B U R S T O U T P U T C V B S D IG IT A L D A T A G E N E R A TO R A D V 7192 Exam p le:- N TS C Figure 25 Possible application for the Black Burst Output signal. 5 25 1 2 3 Y R A IN AL M IC I L N E H A R T P EC A T D 4 5 6 7 8 9 10 1 1-1 9 O utput Vid eo BRIGHTNESS DETECT This feature is used to monitor the average brightness of the incoming Y video signal on a field by field basis . The information is read from the I2C and based on this information the color saturation, contrast and brightness controls can be adjusted ( for example to compensate for very dark pictures).[Brightness Detect Register ]. CS O HS O VS O Figure 28 CSO, HSO, VSO timing diagram COLOR BAR GENERATION The ADV7192 can be configured to generate 100/7.5/75/7.5 colorbars for NTSC or 100/0/75/0 colorbars for PAL. [Mode Register 4]. CHROMA/LUMA DELAY The luminance data can be delayed by maximum of 6 clock cycles. Additionally the Chroma can be delayed by a maximum of 8 clock cycles (one clock cycle at 27MHz). [Timing Register 0 and Mode Register 9]. n COLOR BURST CONTROL The burst information can be switched on and off the composite and chroma video output.[Mode Register 4]. COLOR CONTROLS LU M A DEL AY CHRO M A DELAY n Figure 26 Chroma Delay / Luma Delay CLAMP OUTPUT The ADV7192 has a programmable clamp TTL output signal. This clamp signal is programmable to the front and back porch. The clamp signal can be varied by 1-3 clock cycles in a positive and negative direction from the default position. [Mode Register 5, Mode Register 7]. REV. Pr F 26 The ADV7192 allows the user to control the brightness, contrast, hue and saturation of the color. The control registers may be double buffered, meaning that any modification to the registers will be done outside the active video region and therefore changes made will not be visible during active video. Contrast Control Contrast adjustment is achieved by scaling the Y input data by a factor programmed by the user. This factor allows the data to be scaled between 0% and 150%. [Contrast Control Register]. Brightness Control The brightness is controlled by adding a programmable setup level onto the scaled Y data. This brightness level may be added onto the Y data. For NTSC with pedestal the setup can vary from 0 IRE to 22.5 IRE. For NTSC without pedestal and PAL the setup can vary from -7.5IRE to 15IRE. [Brightness Control Register]. Color Saturation Color adjustment is achieved by scaling the U and V input data by a factor programmed by the user.This factor allows the data to be scaled between 0% and 200%. [U Scale Register and V Scale Register]. Hue Adjust Control The hue adjustment is achieved on the composite and chroma outputs by adding a phase offset onto the color subcarrier in the active video but leaving the color burst unmodified i.e. only the phase between the video and the colorburst is modified and hence the hue is shifted. The ADV7192 provides a range of +/22° in increments of 0.17578125°.[Hue Adjust Register]. ADV7192 Preliminary Technical Data CHROMINANCE CONTROL PEDESTAL CONTROL The color information can be switched on and off the compos- In NTSC mode it is possible to have the pedestal signal ite, chroma and color component video outputs. [ Mode generated on the output video signal. Register 4]. [Mode Register 2]. UNDERSHOOT LIMITER A limiter is placed after the digital filters. This prevents any synchronization problems for TVs. The level of undershoot is programmable between -1.5 IRE, -6 IRE, -11 IRE when operating in 4xOversampling Mode. In 2xOversampling Mode the limits are -7.5IRE and 0 IRE .[Mode Register 9 and Timing Register 0]. POWER-ON RESET After power-up, it is necessary to execute a RESET operation. A reset occurs on the falling edge of a high to low transistion on the RESET pin. This initializes the pixel port such that the data on the pixel inputs pins is ignored. See Appendix 8 for the register settings after RESET is applied. See page 30 for RESET timing sequence . DIGITAL NOISE REDUCTION DNR is applied to the Y data only. A filter block selects the high frequency, low amplitude components of the incoming signal ('DNR Input Select'). The absolute value of the filter output is compared to a programmable threshold value ('DNR Threshold Control'). There are two DNR modes available: DNR Mode and DNR Sharpness Mode. In DNR Mode, if the absolute value of the filter output is smaller than the threshold, it is assumed to be noise. A programmable amount ('Coring Gain Control') of this noise signal will be subtracted from the original signal. In DNR Sharpness Mode, if the absolute value of the filter output is less than the programmed threshold, it is assumed to be noise, as before. Otherwise, if the level exceeds the threshold, now being identified as a valid signal, a fraction of the signal ('Coring Gain Control') will be added to the original signal in order to boost high frequency components and to sharpen the video image. In MPEG systems it is common to process the video information in blocks of 8x8 pixels for MPEG2 systems, or 16x16 pixels for MPEG1 systems ('Block Size Control'). DNR can be applied to the resulting block transition areas which are known to contain noise. Generally the block transition area contains 2 pixels. It is possible to define this area to contain 4 pixels ('Border Area Control'). It is also possible to compensate for variable block positioning or differences in YCrCb pixel timing with the use of the ('Block Offset Control'). [Mode Register 8, DNR Registers 0 -2]. PROGRESSIVE SCAN INPUT It is possible to input data to the ADV7192 in progressive scan format. For this purpose the input pins Y0-9, Cb0-Cb9 and Cr0-Cr9 accept 10-bit Y data, 10-bit Cr data and 10-bit Cb data. The data is clocked into the part at 27Mhz. The data is then filtered and sinc corrected in an 2xInterpolation filter and then output to three video DACs at 54 Mhz (to interface to a progressive scan monitor, for example). Y R A IN AL M IC I L N E H A R T P EC A T D 0 10 A M PL IT UD E ( d B) 20 30 40 50 60 70 0 5 10 15 20 25 F RE QU E NC Y (M H z ) Figure 29. Plot of the interpolation filter for the Y data DOUBLE BUFFERING GAMMA CORRECTION CONTROL Gamma correction may be performed on the Luma data. The user has the choice to use either of two different gamma curves, A or B. At any one time one of these curves is operational if gamma correction is enabled. Gamma correction allows the mapping of the Luma data to a user defined function. [Mode Register 8, Gamma Correction Registers 0-13]. 27 0 10 20 30 A M PLITUD E (d B) Double buffering can be enabled or disabled on the following registers: Closed Captioning Registers, Brightness Control, VScale, U-Scale, Contrast Control, Hue Adjust Register, Macrovision Registers and the Gamma Curve Select bit. These registers are updated once per Field on the falling edge of the VSYNC signal. Double Buffering improves the overall performance of the ADV7192, since modifications to register settings will not be made during active video, but take effect on the start of the active video. [Mode Register 8]. 40 50 60 70 0 5 10 15 20 25 FR E Q UENC Y (M H z) Figure 30. Plot of the interpolation filter for the CrCb data REV. Pr F Preliminary Technical Data ADV7192 It is assumed that there is no color space conversion or any other such operation to be performed on the incoming data. Thus if these DAC outputs are to drive a TV, all relevant timing and synchronization data should be contained in the incoming digital Y data. The block diagram below shows a possible configuration for progressive scan mode using the ADV7192. ADV7194 PLL MPEG2 54MH z 27MHz Pixel Bus PRO GESSIVE SCAN DECODER ENOCDER CORE 30-BIT INTERFACE 2 X I N T E R P O L A T I O N 6 D A C O U T P U T S frequency on a line by line basis. This digital datastream is 67 bits wide and the subcarrier is contained in Bits 0 to 21. Each bit is 2 clock cycles long. 00Hex should be written into all four Subcarrier Frequency registers when using this mode. [Mode Register 4]. SCH PHASE MODE The SCH phase is configured in default mode to reset every four(NTSC) or eight(PAL) fields to avoid an accumulation of SCH phase error over time. In an ideal system, zero SCH phase error would be maintained forever, but in reality, this is impossible to achieve due to clock frequency variations. This effect is reduced by the use of a 32-bit DDS, which generates this SCH. Resetting the SCH phase every four or eight fields avoids the accumulation of SCH phase error, and results in very minor SCH phase jumps at the start of the four or eight field sequence. Resetting the SCH phase should not be done if the video source does not have stable timing or the ADV7192 is configured in RTC mode. Under these conditions (unstable video) the Subcarrier Phase Reset should be enabled but no RESET applied. In this configuration the SCH Phase will never be reset, this means that the output video will now track the unstable input video. The Subcarrier Phase Reset when applied will reset the SCH phase to Field 0 at the start of the next field (e.g. Subcarrier Phase Reset applied in Field 5(PAL) on the start of the next field SCH phase will be reset to Field 0). [Mode Register 4]. Y R A IN AL M IC I L N E H A R T P EC A T D Figure 31. Block diagram of using the ADV7192 in Progressive Scan Mode The progressive scan decoder deinterlaces the data from the MPEG2 decoder. This now means that there are 525 video lines per field in NTSC mode and 625 video lines per field in PAL mode. The duration of the video line is now 32 µs. It is important to note that the data from the MPEG2 decoder is in 4:2:2 format. The data output from the progressive scan decoder is in 4:4:4 format. Thus it is assumed that some form of interpolation on the color component data is performed in the progressive scan decoder IC. [Mode Register 8]. SLEEP MODE If after RESET , the SCRESET/RTC/TR and NTSC_PAL pins are both set high , the ADV7192 will power up in Sleep Mode to facilitate low power consumption before all registers have been initialised. If 'Power-Up In Sleep Mode' is disabled, Sleep Mode control passes to the 'Sleep Mode' control in Mode Register 2 (i.e. control via I2C). [Mode Register 2 and Mode Register 6]. REAL TIME CONTROL , SUBCARRIER RESET AND TIMING RESET Together with the SCRESET/RTC /TR pin and of Mode Register 4 ('Genlock Selection'), the ADV7192 can be used in ( a) Timing Reset Mode, (b) Subcarrier Phase Reset Mode or SQUARE PIXEL MODE (c) RTC Mode. The ADV7192 can be used to operate in square pixel mode. (a) A TIMING RESET is achieved in holding this pin For NTSC operation an input clock of 24.5454MHz is high. In this state the horizontal and vertical counters required. Alternatively, for PAL operation, an input clock of will remain reset. On releasing this pin (set to low), 29.5MHz is required. The internal timing logic adjusts the internal counters will commence counting again. accordingly for square pixel mode operation.Square pixel The minimum time the pin has to be held high is mode is not available in 4xOversampling mode. [Mode 37ns (1 clock cycle at 27MHz), otherwise this reset Register 2]. signal might not be recognized. (b) The SUBCARRIER PHASE will reset to that of Field 0 at the start of the following field when a low to high transition occurs on this input pin. (c) In RTC MODE, the ADV7192 can be used to lock to an external video source. The real time control mode allows the ADV7192 to automatically alter the subcarrier frequency to compensate for line length variations. When the part is connected to a device that outputs a digital datastream in the RTC format (such as a ADV7185 video decoder, see page 31), the part will automatically change to the compensated subcarrier REV. Pr F 28 ADV7192 Preliminary Technical Data VERTICAL BLANKING DATA INSERTION AND BLANK INPUT the incoming data.There are two options available: to run the device throughout at 27MHz or to enable the PLL. In the latter case even if the incoming data runs at 27MHz, 4xOversampling and the internal PLL will output the data at 54MHz. Note In 4xOversampling Mode the requirements for the optional output filters are different than from those in 2xOversampling. For further details see Appendix 6. [Mode Register 1, Mode Register 6]. It is possible to allow encoding of incoming YCbCr data on those lines of VBI that do not have line sync or pre/postequalisation pulses . This mode of operation is called "Partial Blanking". It allows the insertion of any VBI data (Opened VBI) into the encoded output waveform, this data is present in digitized incoming YCbCr data stream (e.g. WSS data, CGMS, VPS etc.). Alternatively the entire VBI may be blanked (no VBI data inserted) on these lines. VBI is available in all timing modes. The complete VBI comprises of the following lines: 525/60 systems, Lines 525 to 21 for field one and Lines 262 to Line 284 for field two. 625/50 systems, Lines 624 to Line 22 and Lines 311 to 335. The "Opened VBI" consists of: 525/60 systems, Lines 10 to 21 for field one and second half of Line 273 to Line 284 for field two. 625/50 systems, Line 7 to 22 and Lines 319 to 335. [Mode Register 3]. A DV 71 92 2 X M P EG 2 Pixel Bus E NO C DE R CO R E 27M H z Y R A IN AL M IC I L N E H A R T P EC A T D It is possible to allow control over the BLANK signal using Timing Register 0. When the BLANK input is enabled (TR03 = '0' and input pin tied low), the BLANK input can be used to input externally generated blank signals in Slave Mode 1, 2 or 3. When the BLANK input is disabled (TR03 = '1' and input pin tied low or tied high) the BLANK input is not used and the ADV7192 automatically blanks all normally blank lines as per CCIR-624. [Timing Register 0]. YUV LEVELS This functionality allows the ADV7192 to output SMPTE levels or Betacam levels on the Y output when configured in PAL or NTSC mode. Sync Video Betacam 286mV 714mV SMPTE 300mV 700mV MII 300mV 700mV PL L 54MH z I N T E R P O L A T I O N 6 D A C O U T P U T S 54M H z OU TPU T R AT E Figure32 PLL and 4xOversampling block diagram 2X Filter Requirements 0 dB 4X Filter Requirements - 30 dB As the datapath is branched at the output of the filters the luma signal relating to the CVBS or S-Video Y/C output is unaltered. It is only the Y output of the YUV outputs which is scaled. This control allows color component levels to have a peak-peak amplitude of 700 mV, 1000mV or the default values of 934 mV in NTSC and 700mV in PAL. [Mode Register 5]. 6.75MHz 13.5MHz 27.0MHz 40.5MHz 54.0MHz Figure 33. Output Filter Requirements in 2x- and 4xOversampling Mode 16-BIT INTERFACE It is possible to input data in 16-bit format. In this case the interface only operates if the data is accompanied by separate HSYNC/VSYNC/BLANK signals. 16-bit mode is not available in Slave Mode 0 since EAV/SAV timing codes are used. [Mode Register 8]. 4xOVERSAMPLING AND INTERNAL PLL It is possible to operate all six DACs at 27MHz (2xOversampling) or 54 MHz (4xOversampling). The ADV7192 is supplied with a 27MHz clock synced with 29 REV. Pr F Preliminary Technical Data ADV7192 VIDEO TIMING DESCRIPTION. The ADV7192 is intended to interface to off-the-shelf MPEG1 and MPEG2 Decoders. As a consequence the ADV7192 accepts 4:2:2 YCrCb Pixel Data via a CCIR-656 Pixel Port and has several Video Timing Modes of operation that allow it to be configured as either System Master Video Timing Generator or a Slave to the System Video Timing Generator. The ADV7192 generates all of the required horizontal and vertical timing periods and levels for the analog video outputs. The ADV7192 calculates the width and placement of analog sync pulses, blanking levels and color burst envelopes. Color bursts are disabled on appropriate lines and serration and equalisation pulses are inserted where required. In addition the ADV7192 supports a PAL or NTSC square pixel operation (2xOversampling Mode only). The part requires an input pixel clock of 24.5454MHz for NTSC square pixel operation and an input pixel clock of 29.5MHz for PAL square pixel operation. The internal horizontal line counters place the various video waveform sections in the correct location for the new clock frequencies. RESET SEQUENCE When RESET becomes active the ADV7192 reverts to the default output configuration (see Appendix 8 for register settings). The ADV7192 internal timing is under the control of the logic level on the NTSC_PAL pin. When RESET is released Y, Cr, Cb values corresponding to a black screen are input to the ADV7192. Output timing signals are still suppressed at this stage. DACs A,B C are switched off and DACs D,E, F are switched on. When the user requires valid data, 'Pixel Data Valid' Control is enabled (MR26 = '1') to allow the valid pixel data to pass through the encoder. Digital output timing signals become active and the encoder timing is now under the control of the Timing Registers. If at this stage, the user wishes to select a different video standard to that on the NTSC_PAL pin, 'Standard I2C' Control should be enabled (MR25 = '1') and the video standard required is selected by programming Mode Register 0 ('Output Video Standard Selection'). Figure 34 illustrates the RESET sequence timing. Y R A IN AL M IC I L N E H A R T P EC A T D The ADV7192 has 4 distinct Master and 4 distinct Slave timing configurations.Timing Control is establised with the bi-directional HSYNC, BLANK and VSYNC pins. Timing Register 1 can also be used to vary the timing pulse widths and where they occur in relation to each other. [Mode Register 2, Timing Register 0,1 ] RES ET DAC D, DAC E XXXXXXX XXXXXXX DAC F XXXXXXX XXXXXXX DAC A, DAC B, DAC C XXXXXXX V a lid V id e o B la c k V a lue V a lid V id e o OFF M R26 P ix e l_ da ta _ va lid XXXXXXX D i g it a l T im i n g XXXXXXX 1 0 D i g i t a l T im i n g S i g n a l s S u p p r e s s e d Figure 34. RESET Sequence Timing Diagram REV. Pr F V a lid V id e o B la c k V a lu e W ith S y n c 30 T i m in g A c t iv e ADV7192 Preliminary Technical Data C LO CK GRE E N /C OM P O S ITE /Y S C RE S E T / RT C /T R B LUE /LUM A /U LLC 1 CO M P O SIT E VID EO e.g., VC R OR CA B LE G LL RE D/CH R OM A /V P 7-P 0 V ID E O DE C O D E R AD V 7 1 8 5 P19-P12 GRE E N /COM P O S ITE /Y M U X B LUE /LUM A /U RE D/CH R OM A/V H SYN C MPEG DE C O D E R VSY N C A D V7192 H/LT RA N S IT ION CO U NT S T A R T S E Q UE N CE RE S E RV E D B IT 2 RE S E T 4 B IT S RE S E RV E D 5 B IT S RE S E RV E D B IT 3 LO W 128 13 14 B IT S RE S E RV E D 0 FS C P LL IN C RE M E NT 1 21 0 RTC TIM E SLOT : 01 14 67 68 19 Y R A IN AL M IC I L N E H A R T P EC A T D NO T USE D IN ADV7192 VA LID SA M P LE INV A LID SA M P LE 8/LIN E LO CK E D C LO C K NO TES: 1F SC PLL INCREM ENT IS 22 BITS LONG , VALUED LOADED INTO A DV 7192 FSC DDS RE GIS TER IS F SC PLL INCREM ENTS BITS 21:0 PLUS BITS 0:9 O F SUB CARRIE R FRE QUE NCY RE GIS TERS. ALL ZE ROS S HOULD BE W RITTEN TO THE SUB CARRIER FREQ UENCY REGISTERS O F THE A DV 7192. 2SEQ UENCE BIT P AL: 0 = LINE NORM AL, 1 = LINE INVERTED NTS C: 0 = NO CHANGE. 3RESET BIT RESET ADV7192’s DDS. Figure 35. RTC Timing and Connections Mode 0 (CCIR-656) :- Slave Option. (Timing Register 0 TR0 = X X X X X 0 0 0 ) The ADV7192 is controlled by the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the Pixel Data. All timing information is transmitted using a 4-byte Synchronisation Pattern. A Synchronisation pattern is sent immediately before and after each line during active picture and retrace. Mode 0 is illustrated in Figure 36. The HSYNC,VSYNC and BLANK (if not used) pins should be tied high during this mode. Blank output is available. A NA L O G V ID E O EAV C O D E IN PU T P IX E L S F C Y Y F r 0 0 0 X 0 Y 4 C LO C K SAV CODE 8 0 1 8 0 0 1 0 0 F F A A A 0 F F B B B 8 0 C C 1 8 1 F 0 0 X C Y C Y C Y Y b r b r 0 0 0 F 0 0 Y b A N C IL LA R Y D A TA (H A N C ) 4 C LO C K 268 C LO C K NT S C /PA L M S YS T EM (5 2 5 L INE S / 6 0 Hz) 4 C LO C K 4 C LO C K 280 C LO C K PA L SY S T E M (6 2 5 L INE S / 5 0 Hz) 1440 C LO C K EN D O F AC TIV E VID EO LIN E 1440 C LC O K S TAR T O F A C TIV E V ID E O LIN E Figure 36. Timing Mode 0 (Slave Mode) 31 REV. Pr F Preliminary Technical Data ADV7192 Mode 0 (CCIR-656) :- Master Option. (Timing Register 0 TR0 = X X X X X 0 0 1 ) The ADV7192 generates H, V and F signals required for the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is output on the VSYNC pin. Mode 0 is illustrated in Figure 37(NTSC) and Figure 38(PAL). The H, V and F transitions relative to the video waveform are illustrated in Figure 39. D IS PL AY D IS PL AY VE RT ICA L BLA N K 522 523 524 525 1 2 3 4 6 5 7 8 10 9 11 20 21 22 H V EV EN F IE LD F D IS PL AY O DD F IELD Y R A IN AL M IC I L N E H A R T P EC A T D D IS PL AY VE RT ICA L BLA N K 260 261 262 263 264 H V 265 266 O DD F IELD F 267 268 269 270 271 272 273 283 274 284 285 EV EN F IE LD Figure 37. Timing Mode 0 (NTSC Master Mode) D ISPL A Y D IS P L A Y V E R T IC A L B LA N K 622 623 624 625 1 2 3 4 5 6 7 21 22 23 H V EVEN F IE LD F O D D F IELD D IS P L AY D ISPL A Y V E R T IC A L B LA N K 309 310 311 312 313 314 315 316 317 318 319 H V F O D D F IELD EVEN F IE LD Figure 38. Timing Mode 0 (PAL Master Mode) REV. Pr F 32 320 334 335 336 ADV7192 Preliminary Technical Data ANALOG V ID E O H F V Y R A IN AL M IC I L N E H A R T P EC A T D Figure 39. Timing Mode 0 Data Transitions (Master Mode) Mode 1 :- Slave Option. HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 0 1 0 ) In this mode the ADV7192 accepts Horizontal SYNC and Odd/ Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame i.e. Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7192 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 40(NTSC) and Figure 41(PAL). D ISPL AY 522 523 D ISPL AY VE R TIC AL BLA N K 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 HS Y N C BL A NK F IE L D EVEN F IE LD O DD F IELD D ISPL AY D ISP L AY VE R T IC AL BLA N K 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 HS YN C BL A NK F IE L D O DD F IELD E VE N F IE LD Figure 40. Timing Mode 1 (NTSC) 33 REV. Pr F Preliminary Technical Data ADV7192 D ISPL AY D IS PL AY VE RT ICA L BLA N K 622 623 624 625 1 2 3 4 6 5 7 21 22 23 HS Y N C BL A NK F IE L D EV EN F IE LD O DD F IELD D IS PL AY D ISPL AY VE RT ICA L BLA N K 309 HS Y N C BL A NK F IE L D 310 311 Y R A IN AL M IC I L N E H A R T P EC A T D 312 O DD F IELD 313 314 315 316 317 318 319 320 334 335 336 EVEN F IE LD Figure 41 Timing Mode 1 (PAL) Mode 1 :- Master Option. HSYNC,, BLANK, FIELD.. (Timing Register 0 TR0 = X X X X X 0 1 1 ) In this mode the ADV7192 can generate Horizontal SYNC and Odd / Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame i.e. Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7192 automatically blanks all normally blank lines as per CCIR-624 . Pixel data is latched on the rising clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 43(NTSC) and Figure 44(PAL). Figure 42 illustrates the HSYNC, BLANK and FIELD for an odd or even field transition relative to the pixel data. HS Y N C F IE L D PAL = 12 * C L O C K/2 N TSC = 16 * C L O C K/2 BL A NK PIX E L D AT A Cb Y Cr PAL = 132 * C LO C K/2 N TSC = 122 * C L O C K/2 Figure 42. Timing Mode 1 Odd/Even Field Transitions Master/Slave REV. Pr F 34 Y ADV7192 Preliminary Technical Data Mode 2 :- Slave Option HSYNC, VSYNC, BLANK.. (Timing Register 0 TR0 = X X X X X 1 0 0 ) In this mode the ADV7192 accepts Horizontal and Vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an Even Field. The BLANK signal is optional. When the BLANK input is disabled the ADV7192/93 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 46(NTSC) and Figure 47(PAL). DISP LAY DISP LAY 522 V ER TICA L B LA NK 523 524 525 1 2 3 4 6 5 7 8 10 9 20 11 21 22 HS Y N C BLA N K VS Y N C EV EN F IEL D DISP LAY OD D F IE LD Y R A IN AL M IC I L N E H A R T P EC A T D DISP LAY V ER TICA L B LA NK 260 261 262 263 HS Y N C BL A NK VS Y N C 264 265 266 267 268 269 270 271 272 273 283 274 284 285 EV EN F IELD OD D F IE LD Figure 43 Timing Mode 2 (NTSC) DISP LAY 622 623 DISP LAY V ER TICA L B LA NK 624 625 1 2 3 4 5 6 7 21 22 23 HS Y N C BLA N K VS Y N C ODD F IE LD EV EN F IELD DISP LAY DISP LAY 309 310 V ER TICA L B LA NK 311 312 313 314 315 316 317 318 319 320 334 335 336 HS Y N C BLA N K VS Y NC OD D FIE LD EV EN F IELD Figure 44. Timing Mode 2 (PAL) 35 REV. Pr F Preliminary Technical Data ADV7192 Mode 2 :- Master Option HSYNC,, VSYNC,, BLANK.. (Timing Register 0 TR0 = X X X X X 1 0 1 ) In this mode the ADV7192 can generate Horizontal and Vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an Even Field. The BLANK signal is optional. When the BLANK input is disabled the ADV7192 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 43 (NTSC) and Figure 44 (PAL). Figure 45 illustrates the HSYNC, BLANK and VSYNC for an even to odd field transition relative to the pixel data. Figure 46 illustrates the HSYNC, BLANK and VSYNC for an odd to even field transition relative to the pixel data. HS Y N C VS YNC PAL = 12* C LO C K/2 BL A NK PIX E L D AT A N TSC = 16 * C L O C K/2 Y R A IN AL M IC I L N E H A R T P EC A T D Cb Y PAL = 132 * C L O C K/2 N TSC = 122 * C LO C K/2 Figure 45. Timing Mode 2 Even to Odd Field Transistion Master/Slave HS Y N C VSYNC PAL = 864 * C LO C K/2 N TSC = 858 * C L O C K/2 PAL = 12 * C LO C K/2 N TSC = 16 * C L O C K/2 BL A NK Cb PIX E L D AT A Y Cr Y Cb PAL = 132 * C L O C K/2 N TSC = 122 * C L O C K/2 Figure 46. Timing Mode 2 Odd to Even Field Transistion Master/Slave REV. Pr F 36 Cr Y ADV7192 Preliminary Technical Data Mode 3 :- Master/Slave Option HSYNC, BLANK, FIELD. (Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1) In this mode the ADV7192 accepts or generates Horizontal SYNC and Odd / Even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame i.e. Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7192 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in Figure 47 (NTSC) and Figure 48 (PAL). D ISPL AY D IS PL AY VE RT ICA L BLA N K 522 523 524 525 1 2 3 4 5 6 7 10 9 8 11 20 21 22 HS YN C BL A NK EV EN F IE LD F IE L D O DD F IE LD Y R A IN AL M IC I L N E H A R T P EC A T D D ISPL AY D ISPL AY VE RT ICA L BLA N K 260 261 262 263 264 HS YN C BL A NK 265 266 267 O DD F IELD F IE L D 268 269 270 271 272 273 283 274 284 285 EV EN F IE LD Figure 47. Timing Mode 3 (NTSC) D ISPL AY D IS P L A Y V E R T IC A L B LA N K 622 623 624 625 1 2 3 4 5 6 7 21 22 23 HS Y N C BL A NK EVEN F IE LD F IE L D O D D F IELD D ISPL AY D ISPL AY V E R T IC A L B LA N K 309 310 311 312 313 314 315 316 317 318 319 320 334 335 336 HS Y N C BL A NK F IE L D O D D F IEL D EVEN F IE LD Figure 48. Timing Mode 3 (PAL) 37 REV. Pr F Preliminary Technical Data ADV7192 MPU PORT DESCRIPTION. The ADV7192 support a two wire serial (I2C compatible) microprocessor bus driving multiple peripherals. Two inputs Serial Data (SDA) and Serial Clock (SCL) carry information between any device connected to the bus. Each slave device is recognized by a unique address. The ADV7192 has four possible slave addresses for both read and write operations. These are unique addresses for each device and are illustrated in Figure 49. The LSB sets either a read or write operation. Logic level "1" corresponds to a read operation while logic level "0" corresponds to a write operation. A1 is set by setting the ALSB pin of the ADV7192 to logic level "0" or logic level "1". When ALSB is set to "0", there is greater input bandwidth on the I2C lines, which allows high speed data transfers on this bus. When ALSB is set to "1", there is reduced input bandwidth on the I2C lines, which means that pulses of less than 50ns will not pass into the I2C internal controller. This mode is recommended for noisy systems. 0 1 0 1 0 1 A1 X SET UP BY ALS B READ / W RITE CO NTRO L 0 1 W RITE READ Fig 49. ADV7192 Slave Address To control the various devices on the bus the following protocol must be followed. First the master initiates a data transfer by establishing a Start condition, defined by a high to low transistion on SDA whilst SCL remains high. This indicates that an address/data stream will follow. All peripherals respond to the Start condition and shift the next eight bits (7-Bit address + R/W bit). The bits are tranferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA and SCL lines waiting for the Start condition and the correct transmitted address. The R/W bit determines the direction of the data. S SLAVE AD DR A(S) SU B A D D R A(S) S SLAVE AD DR S = STA RT BIT P = STO P BIT A(S) Stop and Start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, then these cause an immediate jump to the idle condition. During a given SCL high period the user should only issue one Start condition, one Stop condition or a single Stop condition followed by a single Start condition. If an invalid subaddress is issued by the user, the ADV7192 will not issue an acknowledge and will return to the idle condition. If in auto-increment mode, the user exceeds the highest subaddress then the following action will be taken: 1. In Read Mode, the highest subaddress register contents will continue to be output until the master device issues a no-acknowledge. This indicates the end of a read. A noacknowledge condition is where the SDA line is not pulled low on the ninth pulse. 2. In Write Mode, the data for the invalid byte will be not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7192 and the part will return to the idle condition. SDAT A SCLO CK S 1-7 8 1-7 8 9 1-7 SUBAD D R ESS ACK D AT A A(S) S 9 P ACK STO P Figure 50 illustrates an example of data transfer for a read sequence and the Start and Stop conditions. Figure 51 shows bus write and read sequences. A(S) D AT A A(S) P LSB = 1 SU B A D D R 8 Figure 50. Bus Data Transfer SLAVE AD D R A(S) = AC KN O W L ED G E B Y SLAVE A(M ) = AC KN O W L EDG E BY M A STE R A(S) D AT A A(M ) A(S) = N O -AC KNO W LE D G E BY SL AVE A(M ) = N O -AC KN O W LED G E BY M AST ER Figure 51 Write and Read Sequences REV. Pr F 9 STAR T ADD R R / W ACK D AT A LSB = 0 R EAD SEQ U EN C E The ADV7192 acts as a standard slave device on the bus. The data on the SDA pin is 8 bits long supporting the 7-Bit addresses plus the R/W bit. It interprets the first byte as the device address and the second byte as the starting subaddress. The subaddresses auto-increment allowing data to be written to or read from from the starting subaddress. A data transfer is always terminated by a Stop condition. The user can also access any unique subaddress register on a one by one basis without having to update all the registers. There is one exception. The Sub-Carrier Frequency Registers should be updated in sequence, starting with SubCarrier Frequency Register 0. The auto-increment function should be then used to increment and access Sub-Carrier Frequency Registers 1, 2 and 3. The Sub-Carrier Frequency Registers should not be accessed independently. Y R A IN AL M IC I L N E H A R T P EC A T D ADDR ESS CO NTRO L W R IT E SEQ U EN C E A logic "0" on the LSB of the first byte means that the master will write information to the peripheral. A logic "1" on the LSB of the first byte means that the master will read information from the peripheral. 38 D AT A A(M ) P ADV7192 Preliminary Technical Data REGISTER ACCESSES The MPU can write to or read from all of the registers of the ADV7192 except the Subaddress Registers which are write only registers. The Subaddress Register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the Subaddress Register. Then a read/write operation is performed from/to the target address which then increments to the next address until a Stop command on the bus is performed. Subaddress Register Figure 52 shows the various operations under the control of the Subaddress Register. "0" should always be written to SR7. Register Select (SR6-SR0): These bits are set up to point to the required starting address. REGISTER PROGRAMMING The following section describes each register. All registers can be read from as well as written to. SR 7 SR 6 SR 5 SR 3 SR 4 (SR7-SR0) The Communications Register is an eight bit writeonly register. After the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. The Subaddress Register determines to/from which register the operation takes place. SR2 SR 1 SR 0 SR 7 Z ERO SH OU L D BE W RIT T E N HE R E Y R A IN AL M IC I L N E H A R T P EC A T D A D V7192 SUB A D D RESS REG IST ER Addre 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh SR6 SR5 SR4 SR3 SR2 SR1 SR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MODE REGISTER 0 MODE REGISTER 1 MODE REGISTER 2 MODE REGISTER 3 MODE REGISTER 4 MODE REGISTER 5 MODE REGISTER 6 MODE REGISTER 7 MODE REGISTER 8 MODE REGISTER 9 TIMING REGISTER 0 TIMING REGISTER 1 SUB C ARRIER F REQUENCY REGISTER 0 SUB C ARRIER F REQUENCY REGISTER 1 SUB C ARRIER F REQUENCY REGISTER 2 SUB C ARRIER F REQUENCY REGISTER 3 SUB C ARRIER PHASE REGISTER CLOSED CAPTIONING EXTEN DED DATA BYTE 0 CLOSED CAPTIONING EXTEN DED DATA BYTE 1 CLOSED CAP TIONING ATA BYTE 0 CLOSED CAP TIONING ATA BYTE 1 NTSC PEDESTAL/TELETEXT C ONTROL REGISTER NTSC PEDESTAL/TELETEXT C ONTROL REGISTER NTSC PEDESTAL/TELETEXT C ONTROL REGISTER NTSC PEDESTAL/TELETEXT C ONTROL REGISTER CGMS/WSS CGMS/WSS CGMS/WSS TELETEXT REQUES CONTROL REGISTER CONTRAST CONTROL REGISTER U SCALE REGISTER V SCALE REGISTER HUE A DJUST REGISTER BRIGHTNESS CONTROL REGISTER SHARPNESS CONTROL REGISTER DNR REGISTER 0 DNR REGISTER 1 DNR REGISTER 2 GAMMA CORRECTION REGISTER 0 GAMMA CORRECTION REGISTER 1 GAMMA CORRECTION REGISTER 2 GAMMA CORRECTION REGISTER 3 GAMMA CORRECTION REGISTER 4 GAMMA CORRECTION REGISTER 5 GAMMA CORRECTION REGISTER 6 GAMMA CORRECTION REGISTER 7 GAMMA CORRECTION REGISTER 8 GAMMA CORRECTION REGISTER 9 GAMMA CORRECTION REGISTER 10 GAMMA CORRECTION REGISTER 11 GAMMA CORRECTION REGISTER 12 GAMMA CORRECTION REGISTER 13 BRIGHTNESS DETECT REGISTER OUTPUT C LOCK REGISTER RESERVED RESERVED RESERVED RESERVED MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER 0 1 2 3 Figure 52 . Subaddress Register for the ADV7192 39 REV. Pr F Preliminary Technical Data ADV7192 Luma Filter Select MODE REGISTER 0 MR0 (MR07-MR00) (Address (SR4-SR0) = 00H) Figure 53 shows the various operations under the control of Mode Register 0. Chroma Filter Select (MR05-MR07): These bits select the chrominance filter. A low pass filter can be selected with a choice of cut-off frequencies (0.65MHz, 1.0MHz, 1.3MHz , 2MHz or 3Mhz) along with a choice of CIF or QCIF filters. MR0 BIT DESCRIPTION Output Video Standard Selection (MR00-MR01): These bits are used to setup the encoder mode. The ADV7192 can be set up to output NTSC, PAL (B,D,G,H,I) , PAL M or PAL N standard video. MR07 MR06 MR05 MR04 MR03 0 1 0 1 0 1 0 1 MR00 OUTPUT VIDEO STANDARD SELECTION MR01 MR00 MR07 MR06 MR05 0 0 1 1 0 0 1 1 MR01 MR02 CHROMA FIL TE R SE LE C T 0 0 0 0 1 1 1 1 (MR02-MR04): These bits specify which luma filter is to be selected. The filter selection is made independent of whether PAL or NTSC is selected. Y R A IN AL M IC I L N E H A R T P EC A T D 0 0 1 1 1.3 MHz LOW PA SS FILTER 0.65 MHz LOW PASS FILTER 1.0 MHz LOW PA SS FILTER 2.0 MHz LOW PA SS FILTER RESER ED CI QCI 3 MHz LO PASS FILTER 0 1 0 1 NTSC PAL (B, D G, H, I) PAL (M) PAL (N) LUMA FIL TE R S E LEC T MR04 MR03 MR02 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 1 1 0 1 LOW PASS FILTER (NTSC LOW PASS FILTER (PAL) NOTCH FILTER (NTSC) NOTCH FILTER (PAL EXTENDED MOD E CI QCI RESERVED Figure 53. Mode Register 0 (MR0) MODE REGISTER 1 MR1 (MR17-MR10) (Address (SR4-SR0) = 01H) 4XOversampling Control (MR16): To enable 4xOversampling this bit has to be set to '1'. When enabled, the data is output at a frequency of 54 MHz. Note that 'PLL Enable' Control has to be enabled (MR61 = "0") in 4xOversampling mode. An external Vref can not be used in 4xOversampling Mode. Figure 54 shows the various operations under the control of Mode Register 1. MR1 BIT DESCRIPTION Reserved (MR17) DAC Control (MR10-MR15): A logical " 0" must be written to this bit. Bits MR15-MR10 can be used to power down the DACs. This is in order to reduce the power consumption of the ADV7192 or if any of the DACs are not required in the application. M R1 7 M R1 6 PO W E R D O W N NO RM A L 0 1 M R1 6 DAC F D A C C O NT RO L M R1 2 0 1 M R1 0 PO W E R D O W N NO RM A L DAC C D A C C O NT RO L M R1 3 2 x O VE R SA M PL ING 4 x O VE R SA M PL ING 0 1 0 1 PO W E R D O W N NO RM A L DAC E D A C C O NT RO L M R1 2 PO W E R D O W N NO RM A L 0 1 PO W E R D O W N NO RM A L Figure 54. Mode Register 1 (MR1) REV. Pr F M R1 0 M R1 1 DAC D D A C C O NT RO L PO W E R D O W N NO RM A L 4 x O VE R SA M PL ING C O NT RO L 0 1 M R1 2 DAC B D A C C O NT RO L M R1 4 M R1 5 0 1 M R1 3 M R1 4 DAC A D A C C O NT RO L MR17 Z e ro m us t be w ritten to this b it M R1 5 40 ADV7192 Preliminary Technical Data MODE REGISTER 2 MR2 (MR27-MR20) (Address (SR4-SR0) = 02H) DAC Output Mode Register 2 is a 8-Bit wide register. Figure 55 shows the various operations under the control of Mode Register 2. MR2 BIT DESCRIPTION- RGB/YUV Control Control (MR21): This bit controls the output from DACs A,B, and C. When this bit is set to "1" Composite, Luma and Chroma Signals are output from DACs A, B and C (respectively).When this bit is set to "0", RGB or YUV may be output from these DACs. SCART Enable Control (MR22): This bit is used to switch the DAC outputs from SCART to a EUROSCART configuration. A complete table of all DAC output configurations is shown below. (MR20): This bit enables the output from the DACs to be set to YUV or RGB output video standard. Table II. DAC Output configuration M R22 M R21 M R20 DAC A SCART DAC O /P RG B/ YUV 0 DAC C DAC B 0 0 G (Y) B 0 0 1 Y (Y ) U (Pb ) 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 (P b ) DAC D DAC E R (P r ) CVBS LUM A CHROM A V (P r) CVBS LUM A CHROM A DAC F Y R A IN AL M IC I L N E H A R T P EC A T D CVBS LUM A CHROM A G (Y) B (Pb ) R (P r ) CVBS LUM A CHROM A Y (Y ) U (Pb ) V (P r ) CVBS B (Pb ) R (P r ) G (Y) LUM A CHROM A CVBS U (Pb ) V (P r) Y (Y ) LUM A CHROM A CVBS LUM A CHROM A G (Y) B (Pb ) R (P r ) CVBS LUM A CHROM A Y (Y ) U (Pb ) V (P r ) Note: In Progressive Scan Mode (MR80, '1') the DAC output configuration is stated in the brackets. Pedestal Control (MR23): Master Mode timing. When this bit is set to "1" by the user (via the I2C), pixel data passes to the pins and the encoder reverts to the timing mode defined by Timing Register 0. This bit specifies whether a pedestal is to be generated on the NTSC composite video signal. This bit is invalid when the device is configured in PAL mode. Square Pixel Control (MR24) (MR24): Sleep Mode Control (MR27): This bit is used to setup square pixel mode. This is available in Slave Mode only. For NTSC, a 24.5454MHz clock must be supplied. For PAL, a 29.5MHz clock must be supplied. Square pixel operation is not available in 4xOversampling mode. When this bit is set ("1"), Sleep Mode is enabled. With this mode enabled the ADV7192 current consumption is reduced to typically 0.1 µA. The I2C registers can be written to and read from when the ADV7192 is in Sleep Mode. Standard I2C Control (MR25): When the device is in Sleep Mode and "0" is written to MR27, the ADV7192 will come out of Sleep Mode and resume normal operation. Also, if a RESET is applied during Sleep Mode the ADV7192 will come out of Sleep Mode and resume normal operation. This bit controls the video standard used by the ADV7192. When this bit is set to "1" the video standard is as programmed in Mode Register 0 ('Output Video Standard Selection'). When it is set to "0", the ADV7192 is forced into the standard selected by the NTSC_PAL pin. When NTSC_PAL is low the standard is NTSC, when the NTSC_PAL pin is high, the standard is PAL. For this to operate, 'Power up in Sleep Mode' control has to be enabled ( MR60 = "1"), otherwise Sleep Mode is controlled by the PAL_NTSC and SCRESET/RTC/TR pins. Pixel DataValid Control (MR26): After resetting the device this bit has the value "0" and the pixel data input to the encoder is blanked such that a black screen is output from the DACs. The ADV7192 will be set to M R27 M R26 M R25 PIX EL D A T A VA L ID CO NT RO L SLE EP M OD E CO NT RO L M R27 0 1 0 1 D IS A B L E E NA B L E S T A N D A R D I2 C CO NT RO L 0 1 0 1 0 1 R G B O U T PU T YU V O U T P U T D A C O UT PU T CO NT RO L M R21 PE D ES T A L O F F PE D E S T A L O N Figure 55. Mode Register 2 (MR2) 41 R G B / YU VM R 2 3 CO NT RO L M R20 D IS A B L E E NA B L E PE D ES T A L CO NT RO L 0 1 M R20 S C A RT E N A B L E CO NT RO L M R23 D IS A B L E E NA B L E M R21 M R22 M R22 M R24 D IS A B L E E NA B L E M R25 D IS A B L E E NA B L E M R23 S Q U A R E P IX E L CO NT RO L M R26 0 1 M R24 0 1 R G B / YU V /C O M P C O M P/L U M A /C H R O M A REV. Pr F Preliminary Technical Data ADV7192 MODE REGISTER 3 MR3 (MR37-MR30) (Address (SR4-SR0) = 03H) Teletext Mode Register 3 is a 8-Bit wide register. Figure 56 shows the various operations under the control of Mode Register 3. MR3 BIT DESCRIPTION Revision Code (MR30 - MR31): Teletext Bit Request Mode Control (MR34): This bit enables switching of the teletext request signal from a continuous high signal (MR34 = "0") to a bitwise request signal (MR34 = "1"). Closed Captioning Field Selection (MR35-MR36) These bits control the fields that closed captioning data is displayed on, closed captioning information can be displayed on an odd field, even field or both fields. This bit is read only and indicates the revision of the device. VBI Open Enable (MR33): This bit must be set to "1" to enable teletext data insertion on the TTX pin. Note: TTX functionality is shared with VSO and CLAMP on pin 62. CLAMP/ VSO Select (MR77) and TTX Input/CLAMPVSO Output Control (MR76) have to be set accordingly. (MR32): This bit determines whether or not data in the Vertical Blanking Interval (VBI) is output to the analog outputs or blanked. Note that this condition is also valid in Timing Slave Mode 0. For further information see page 29. Reserved (MR37): A logic '0' must be written to this bit. M R3 7 Y R A IN AL M IC I L N E H A R T P EC A T D M R3 6 M R3 5 M R3 4 M R3 3 T T X BIT R E Q U E ST M O D E C O N T RO L M R3 7 0 1 V B I_ O P E N M R3 2 0 1 D IS A BL E E NA BL E D IS A BL E E NA B L E M R3 0 M R3 1 M R3 0 RE S E RV E D F O R RE V IS IO N C O D E T E L ET EX T E NA BL E C L O S ED C A PT IO NIN G F IEL D SE L E C T IO N M R3 3 M R3 6 M R3 5 0 1 0 1 M R3 1 M R3 4 Z E R O M US T BE W RIT T E N T O T HIS BIT 0 0 1 1 M R3 2 0 1 NO D A T A O UT O D D F IE L D O N L Y E VE N F IE L D O N L Y D A T A O UT (BO T H F IEL D S) D IS A BL E E NA B L E Figure 56. Mode Register 3 (MR3) MODE REGISTER 4 MR4 (MR47-MR40) (Address (SR4-SR0) = 04H) Mode Register 4 is a 8-Bit wide register. Figure 57 shows the various operations under the control of Mode Register 4. MR4 BIT DESCRIPTION VSYNC_3H Control (MR40): When this bit is enabled ("1") in Slave Mode , it is possible to drive the VSYNC input low for 2.5 lines in PAL mode and 3 lines in NTSC mode. When this bit is enabled in Master Mode the ADV7192 outputs an active low VSYNC signal for 3 lines in NTSC mode and 2.5 lines in PAL mode. Genlock Selection (MR41-MR42) These bits control the genlock feature and timing reset of the ADV7192. Setting MR41 and MR42 to logic "0" disables the SCRESET/RTC/TR pin and allows the ADV7192 to operate in normal mode. (a) By setting MR41 to "0" and MR42 to "1" a timing reset is applied, resetting the horizontal and vertical counters. This has the effect of resetting the Field Count to Field 0. If the SCRESET/RTC/TR pin is held high, the counters will remain reset. Once the pin is released the counters will commence counting again. For correct counter reset, the SCRESET/RTC/TR pin has to remain high for at least 37ns REV. Pr F 42 (1clock cycle at 27MHz). (b) If MR41 is set to "1" and MR42 is set to "0", the SCRESET/RTC/TR pin is configured as a subcarrier reset input and the subcarrier phase will reset to Field 0 whenever a low to high transition is detected on the SCRESET/RTC/TR pin (SCH phase resets at the start of the next Field). (c) If MR41 is set to "1" and MR42 is set to "1", the SCRESET/RTC/TR pin is configured as a real time control input and the ADV7192 can be used to lock to an external video source working in RTC mode. See also page 28. Active Video Line Duration (MR43) This bit switches between two active video line durations. A "0" selects CCIR Rec.601 (720 pixels PAL/NTSC) and a "1" selects ITU-R BT.470 standard for active video duration (710 pixels NTSC, 702 pixels PAL). Chrominance Control (MR44) This bit enables the color information to be switched on and off the chroma, composite and color component outputs. Burst Control (MR45) This bit enables the color burst to be switched on and off the chroma and composite signals. ADV7192 Preliminary Technical Data configured in a Master Timing mode. The output pins VSYNC, HSYNC and BLANK are tri-state during color bar mode. Color Bar Control (MR46): This bit can be used to generate and output an internal color bar test pattern. The color bar configuration is 100/7.5/75/ 7.5 for NTSC and 100/0/75/0 for PAL. It is important to note that when color bars are enabled the ADV7192 is M R47 M R46 M R45 COLOR BAR C O NT RO L M R44 M R43 0 1 M R42 M R41 0 0 0 1 1 1 0 1 ENA BLE C O LO R D IS A B L E C O L O R IN T E R L A C E D N O N - IN T E R L A C E D 0 1 D IS A B L E G E N L O C K E N A B L E S U B C A R R IE R R E S E T P IN T IM IN G R E S E T E N A B L E R T C P IN A C T IV E V ID E O L IN E D U R A T IO N VSYNC _3 H C ONT ROL M R40 M R43 M R45 M R40 G E N L O C K S E L E C T IO N BU R S T C O NT RO L M R47 M R41 M R42 M R44 D IS A B L E ENABLE IN T E R L A C E D M O D E C O NT RO L 0 1 This bit is used to setup the output to interlaced or noninterlaced mode. C H R O M IN A N C E C O NT RO L M R46 0 1 Interlaced Mode Control (MR47): ENA BL E B URST D IS A B L E B U R S T 0 1 0 1 7 2 0 P IX E L S 7 1 0 P IX E L S / 7 0 2 P IX E L S D IS A B L E ENAB LE Y R A IN AL M IC I L N E H A R T P EC A T D Figure 57. Mode Register 4 (MR4) MODE REGISTER 5 MR5 (MR57-MR50) (Address (SR4-SR0) = 05H) RGB Sync Mode Register 5 is a 8-Bit wide register. Figure 58 shows the various operations under the control of Mode Register 5. MR5 BIT DESCRIPTION Y-Level Control (MR50): (MR53): This bit is used to set up the RGB outputs with the sync information encoded on all RGB outputs. Clamp Delay (MR54-MR55): These bits control the delay or advance of the CLAMP signal in the front or back porch of the ADV7192. It is possible to delay or advance the pulse by 0, 1, 2 or 3 clock cycles. This bit controls the component Y output level on the ADV7192. If this bit is set ("0"), the encoder outputs Betacam levels when configured in PAL or NTSC mode. If this bit is set ("1"), the encoder outputs SMPTE levels when configured in PAL or NTSC mode. Note: TTX functionality is shared with VSO and CLAMP on pin 62. CLAMP/VSO Output Control (MR77) and TTX Input/CLAMPVSO Output Control (MR76) have to be set accordingly. UV-Level Control (MR51-MR52): Clamp Delay Direction (MR56): These bits control the color component U and V output levels on the ADV7192. It is possible to have UV levels with a peak-peak amplitude of either 700mV (MR52+MR51 = "01") or 1000mV (MR52 + MR51 = "10") in NTSC and PAL. It is also possible to have default values of 934mV for NTSC and 700mV for PAL (MR52+ MR51 = "00"). M R57 M R56 M R55 This bit controls a positive or negative delay in the CLAMP signal. If this bit is set ("1"), the delay is negative . If it is set ("0"), the delay is positive. Clamp Position (MR57): This bit controls the position of the CLAMP signal. If this bit is set ("1"), the CLAMP signal is located in the back porch position. If this bit is set ("0"), the CLAMP signal is located in the front porch position. M R54 CLAM P DELAY D IR E C T IO N M R52 RG B S YN C 0 1 PO S IT IV E NE G A T IV E M R56 M R55 M R50 Y L E V E L C O NT R O L M R50 D IS A BL E E NA B L E 0 1 D IS A BL E E NA B L E UV L E V E L C O NT RO L CLAM P DELAY C L A M P P O S IT IO N M R51 M R53 M R56 0 1 M R53 M R52 M R51 M R57 0 1 F R O N T P O RC H BA C K P O R C H 0 0 0 1 NO DELA Y 1 X PC L K 1 1 0 1 2 X PC L K 3 X PC L K 0 0 1 1 0 1 0 1 D E F A UL T L E V E L S 700 m V 1000m V R ESERVED Figure 58. Mode Register 5 (MR5) 43 REV. Pr F Preliminary Technical Data ADV7192 MODE REGISTER 6 MR6 (MR67-MR60) (Address (SR4-SR0) = 06H) Reserved (MR62, MR63, MR64) A logical "0" must be written to these bits. Mode Register 6 is a 8-Bit wide register. Figure 59 shows the various operations under the control of Mode Register 6. Field Counter (MR65, MR66, MR67): MR6 BIT DESCRIPTION Power Up Sleep Mode Control (MR60): After RESET is applied this control is enabled (MR60=0) if both SCRESET/RTC/TR and NTSC_PAL pins are tied high. The ADV7192 will then power up in Sleep Mode to faciliate low power consumption before the I2C is initialised. When this control is disabled (MR60=1, via the I2C) Sleep Mode control passes to 'Sleep Mode Control', MR27. These three bits are read only bits. The Field count can be read back over the I2C interface. In NTSC mode the Field count goes from 0 - 3, in PAL mode from 0 - 7. PPL Enable Control (MR61): The PLL control should be enabled (MR61 = '0') when '4xOversampling' is enabled (MR16 = '1'). M R6 7 Y R A IN AL M IC I L N E H A R T P EC A T D M R6 6 M R6 7 M R6 6 M R65 F IE L D C O UNT E R M R6 5 M R6 4 M R6 3 M R6 2 M R6 1 PL L E NA BL E C O NT RO L M R6 4 M R6 3 M R62 Z E RO M U S T B E W RIT T E N T O T HE S E BIT S M R6 1 0 1 ENABL ED D IS A B L E D M R6 0 PO W E R - U P S L E E P M OD E C ONT RO L M R6 0 0 1 E NA B L E D D IS A B L E D Figure 59. Mode Register 6 (MR6) MODE REGISTER 7 MR7 (MR77-MR70) (Address (SR4-SR0) = 07H) Hue Adjust Control (MR72): This bit is used to enable hue adjustment on the composite and chroma output signals of the ADV7192. When this bit is set ("1"), the hue of the color is adjusted by the phase offset described in the Hue Adjust Control Register. When this bit is set ("0"), hue adjustment is disabled. Mode Register 7 is a 8-Bit wide register. Figure 60 shows the various operations under the control of Mode Register 7. MR7 BIT DESCRIPTION Color Control Enable (MR70): Brightness Enable Control (MR73): This bit is used to enable control of contrast and saturation of color (Y-Scale, U-Scale, V-Scale). If this bit is set ("1") color controls are enabled. If this bit is set ("0"), the color control features are disabled. Luma Saturation Control (MR71): When this bit is set ("1"), the luma signal will be clipped if it reaches a limit that corresponds to an input luma value of 255 (after scaling by the Contrast Control Register). This prevents the chrominance component of the composite video signal being clipped if the amplitude of the luma is too high. When this bit is set ("0"), this control is disabled. REV. Pr F This bit is used to enable brightness control on the ADV7192. The actual brightness level is programmed in the Brightness Control Register. This value or 'set up' level is added to the scaled Y data. When this bit is set ("1"), brightness control is enabled. When this bit is set ("0"), brightness control is disabled. 44 ADV7192 Preliminary Technical Data Sharpness Filter Enable (MR74): This bit is used to enable the sharpness control of the luminance signal on the ADV7192 ('Luma Filter Select' has to be set to 'Extended', MR04-MR02 = "100"). The various responses of the filter are determined by the Sharpness Control Register. When this bit is set ("1") the luma response is altered by the amount described in the Sharpness Control Register. When this bit is set ("0"), the sharpness control is disabled. See figues 13, 14, 15 for luma signal responses. CSO_HSO Output Control (MR75): This bit is used to determine whether HSO or CSO M R77 M R75 M R76 MR 7 6 M R74 T T X INPUT C L AM P/V SO OUT PUT M R72 0 1 VSO OU T PU T C L AM P OUT PUT C SO _H SO O UT PUT C O NT RO L 0 1 0 1 BRIG HT N ESS ENA BL E C O NT RO L M R73 M R65 C OL OR C ON T ROL ENABL E M R70 M R72 D ISA BL E ENAB L E 0 1 HS O O UT C SO O UT D ISA BL E ENABL E M R70 M R71 HUE AD JUST C O NT RO L Y R A IN AL M IC I L N E H A R T P EC A T D C L AM P/VSO OUT PUT C O NT RO L M R77 0 1 M R73 SHA RPNES S F IL T E R ENAB L E T T X INPUT /CL A M P-V SO OUT PUT C ONT R OL 0 1 M R74 TTL output signal is output at the CSO_HSO pin. If this bit is set ("1"), then the CSO TTL signal is output. If this bit is set ("0"), then the HSO TTL signal is output. TTX Input/ CLAMP-VSO Output Control (MR76): This bit controls whether pin 62 is configured as an output or as an input pin. A '1' selects pin 62 to be an output for CLAMP or VSO functionality. A '0' selects this pin as a TTX input pin. CLAMP/VSO Output Control (MR77): This bit is used to select the functionality of pin 62. Setting this bit to "1" selects CLAMP as the output signal. A "0" selects VSO as the output signal. Since this pin is also shared with the TTX functionality, 'TTX Input/ CLAMP-VSO Output' Control has to be set accordingly (MR76). D ISA BL E ENAB L E 0 1 D ISA BL E ENAB L E L UM A SA T URA T ION C ON T ROL M R71 0 1 D ISA BL E ENABL E Figure 60. Mode Register 7 (MR7) MODE REGISTER 8 MR8 (MR87-MR80) (Address (SR4-SR0) = 08H) Mode Register 8 is a 8-Bit wide register. Figure 61 shows the various operations under the control of Mode Register 8. 16-Bit Pixel Port Control (MR83): This bit controls whether the ADV7192 is operated in 16bit mode or 8-bit mode. In 8-bit mode the input data will be set up on Pins P0-P7. Unused input pins should be grounded. MR8 BIT DESCRIPTION Progressive Scan Control (MR80): This control enables the progressive scan inputs, Y0-9, Cb0Cb9 and Cr0-Cr9. To enable this control MR80 has to be set to '1'. It is assumed that the incoming Y data contains all necessary sync information. Note: Simultaneous progressive scan input and 16-bit pixel input is not possible. Reserved (MR84): A logical '0' must be written to this bit. DNR Enable Control (MR85): To enable the DNR process this bit has to be set to '1'. If this bit is set to '0' the DNR processing is bypassed. For further information on DNR controls see pages 55-57. Gamma Enable Control (MR86): To enable the programmable gamma correction this bit has to be set to enabled (MR86 = '1'). For further information on Gamma Correction controls see page58. Reserved (MR 81): A '0' must be written to this bit. Double Buffer Control (MR82): Double Buffering can be enabled or disabled on the Contrast Control Register, U Scale Register, V Scale Register, Hue Adjust Control Register, Closed Captioning Register, Brightness Control Register, Gamma Curve Select Bit. Double Buffering is not available in Master Mode. Gamma Curve Select Control (MR87): This bit selects which of the two programmable gamma curves is to be used. When setting MR87 to '0' the gamma correction curve selected is curve A. Otherwise curve B is selected. Each curve will have to be programmed by the user. For further information on Gamma Correction controls see page 58. 45 REV. Pr F Preliminary Technical Data ADV7192 M R87 M R85 M R86 G A M M A E NABL E C O NT RO L M R85 D ISA BL E ENA B L E 0 1 G A M M A C URVE SE L E C T C O NT R O L M R85 0 1 M R84 M R83 1 0 BIT PIX EL PO RT C O NT RO L M R84 0 1 D N R E NA B L E C O NT RO L M R80 M R82 0 1 0 1 D ISA BL E ENA B L E D ISA BL E ENA B L E M R81 Z ER O M UST BE W RIT T EN T O T HIS BIT M R83 D ISA BL E ENA B L E 0 1 M R80 PR O G RE S S IV E SC A N C O NT R O L 2 0 /1 6 BIT PIXE L PO RT C O NT RO L D ISA BL E ENA B L E 0 1 M R81 D O U BL E BU F F ER C O N T R O L D ISA BL E ENA B L E M R85 C URV E A C URV E B M R82 Figure 61. Mode Register 8 (MR8) MODE REGISTER 9 MR9 (MR97-MR90) (Address (SR4-SR0) = 09H) 3 .5 8 M h z C o lo r b u rs t (9 cy c le s ) 2 0 IR E Mode Register 9 is a 8-Bit wide register. Figure 63 shows the various operations under the control of Mode Register 9. 0 IR E Y R A IN AL M IC I L N E H A R T P EC A T D - 2 0 IR E - 4 0 IR E MR9 BIT DESCRIPTION Undershoot Limiter (MR90 -MR91): MR92 MR93 MR95 P A L B la c k B u rs t s ig n a l ) 0 IR E - 4 3 IR E Figure 62 Black Burst signals for PAL and NTSC standards MR20). This signal can be useful for locking two video sources together using professional video equipment. See also page 26. Chroma Delay Control (MR94-MR95): The Chroma signal can be delayed by up to 8clock cycles at 27MHz using MR95-97. For further information see also page 26. Reserved (MR96 - MR97): A '0' must be written to these bits. MR94 CHROMA DELAY CONTROL ZERO MUST BE WRIT- MR96 MR94 TEN TO THESE BITS 0 ns DELAY 0 0 148 ns DELAY 0 1 296 ns DELAY 1 0 RESERVED 1 1 MR93 MR92 BLACK BURST LUMA DAC DISABLE ENABLE BLACK BURST Y-DAC 0 1 UNDERSHOOT LIMITER 0 0 1 1 DISABLE ENABLE Figure 63. Mode Register 9 (MR9) 46 MR90 MR91 MR90 MR93 0 1 MR91 MR92 REV. Pr F (1 0 c yc le s - 2 1 . 5 IR E Black Burst Y-DAC (MR92): It is possible to output a Black Burst signal from the DAC which is selected to be the Luma DAC (MR22, MR21, MR20). This signal can be useful for locking two video sources together using professional video equipment. See also page 26. Black Burst Luma-DAC (MR93): It is possible to output a Black Burst signal from the DAC which is selected to be the Y-DAC (MR22, MR21, MR96 4 .4 3 M h z C o lo r b u rs t 2 1 . 5 IR E This control ensures that no luma video data will go below a programmable level. This prevents any synchronisation problems due to the luma signals going below the blanking level. Available limit levels are - 1.5 IRE, -6 IRE, -11 IRE. Note that this facility is only available in 4xOversampling mode (MR16 = '1'). When the device is operated in 2xOversampling mode (MR16 = '0') or RGB outputs without RGB sync are selected in 4xOversampling, the minimum luma level is set in Timing Register 0, TR06 ('Min Luma' Control). MR97 N T S C B la c k B u r s t s ig n a l 0 1 0 1 DISABLED - 11 IRE IRE - 1. IRE ADV7192 Preliminary Technical Data input is disabled regardless of the register setting. It therefore should be tied low (to Ground) to allow control over the I2C register. TIMING REGISTER 0 (TR07-TR00) (Address (SR4-SR0) = 0AH) Figure 64 shows the various operations under the control of Timing Register 0. This register can be read from as well as written to. Luma Delay (TR04-TR05): The Luma signal can be delayed by up to 222ns (or 6 clock cycles at 27MHz) using TR04-05. For further information see page 26. - TR0 BIT DESCRIPTION - Min Luma Control (TR06): Master/Slave Control (TR00): This bit is used to control the minimum luma output value by the ADV7192. When this bit is set to a logic ("1"), the luma is limited to 7IRE below the blank level. When this bit is set to ("0"), the luma value can be as low as the sync bottom level. This minimum luma value is available in 2xOversampling and 4xOversampling. This bit controls whether the ADV7192 is in master or slave mode. Timing Mode Selection (TR01-TR02): These bits control the timing mode of the ADV7192. These modes are described in more detail on pages 3137. BLANK Timing Register Reset (TR07): Input Control (TR03) (TR03):: Toggling TR07 from low to high and low again resets the internal timing counters. This bit should be toggled after power-up, reset or changing to a new timing mode. This bit controls whether the BLANK input is used to accept blank signals or whether blank signals are internally generated. Note: When this input pin is is tied high (to +5V), the Y R A IN AL M IC I L N E H A R T P EC A T D -- T R0 7 T R0 5 T R0 6 T R0 3 T R0 4 T IM ING RE G IS T E R R E S E T T R0 2 M A S T ER /SL A VE C O N T RO L BL A NK INP UT C O NT RO L T R0 0 T R0 3 T R0 7 T R0 0 T R0 1 0 1 E NA B L E D IS A BL E 0 1 S L A V E T IM ING M A S T ER T IM IN G M IN LU M A C O N TR O L T IM ING M O D E S EL E C T IO N L UM A D E L A Y T R0 6 0 LU M A M IN = SY N C BO TTO M 1 LU M A M IN = BLA N K - 7 .5 IR E T R0 5 T R0 4 0 0 1 1 0 1 0 1 0 ns D EL A Y 7 4 ns D EL A Y 1 4 8 ns D E L A Y 22 2 n s D E L A Y T R0 2 T R0 1 0 0 1 1 0 1 0 1 M OD E M OD E M OD E M OD E 0 1 2 3 Figure 64. Timing Register 0 47 REV. Pr F Preliminary Technical Data ADV7192 TPCLK = one clock cycle at 27MHz. TIMING REGISTER 1 (TR17-TR10) (Address (SR4-SR0) = 0BH) HSYNC to Pixel Data Adjust (TR16-TR17): This enables the HSYNC to be adjusted with respect to the pixel data. This allows the Cr and Cb components to be swapped. This adjustment is available in both master and slave timing modes. TPCLK = one clock cycle at 27MHz. Timing Register 1 is a 8-Bit wide register. Figure 65 shows the various operations under the control of Timing Register 1. This register can be read from as well written to. This register can be used to adjust the width and position of the master mode timing signals. TR1 BIT DESCRIPTION HSYNC Width (TR10-TR11): These bits adjust the HSYNC pulse width. TPCLK = one clock cycle at 27MHz. HSYNC to VSYNC Delay (TR13-TR12): These bits adjust the position of the HSYNC output relative to the VSYNC output. TPCLK = one clock cycle at 27MHz. Y R A IN AL M IC I L N E H A R T P EC A T D HSYNC to VSYN C Rising Edge Delay (TR14TR15): When the ADV7192 is in timing mode 1, these bits adjust the position of the HSYNC output relative to the VSYNC output rising edge. TPCLK = one clock cycle at 27MHz. VSYNC Width (TR14-TR15): When the ADV7192 is configured in timing mode 2, these bits adjust the VSYNC pulse width. T R1 7 T R1 6 T R1 5 H S Y N C TO PIXEL DATA ADJUST T R14 TR 13 H S Y N C TO V S Y N C RISING EDGE DE LA Y (M O DE 1 O NL Y ) T R17 T R16 T R1 2 H S Y N C TO V SY NC DELAY T R13 T R 12 0 0 0 x T PC L K 0 1 1 0 1 x T PC L K 2 x T PC L K 1 1 3 x T PC L K TC T R1 5 T R1 4 T R1 1 T R1 0 H S Y N C WIDTH TA TR 11 TR 10 TB 0 0 1 x T PCL K 0 0 0 x T PC L K 0 1 4 x T PCL K x 0 TB 0 1 1 0 x 1 T B + 32 µs 1 0 4 x T PC L K 8 x T PC L K 1 1 16 x T PC L K 128 x T P C L K 1 1 16 x T PCL K V SY N C WIDTH (M ODE 2 ONLY) T R 15 T R1 4 0 0 0 1 1 0 1 1 1 x T PC LK 4 x T PC LK 16 x T PC L K 128 x T P C L K TIM ING M OD E 1 (M AS TE R/P AL) LINE 1 HSYNC LINE 3 13 TA TC TB V SY N C Figure 65. Timing Register 1 REV. Pr F 48 LINE 314 ADV7192 Preliminary Technical Data SUB-CARRIER FREQUENCY REGISTERS 3-0 (FSC3-FSC0) Sub-Carrier Frequency Value These 8-Bit wide registers are used to set up the Sub-Carrier Frequency. The value of these registers are calculated by (232-1) x 3.5795454x106 using the following equation: 27 x 106 Sub-Carrier Frequency Register = ( 232 - 1) * FSCF = (Address (SR4-SR0) = 0CH-0FH) FCLK Example: Sub-Carrier Register Value NTSC Mode, FCLK = 27 MHz, FSCF = 3.5795454 MHz = 21F07C16 HEX Figure 66 shows how the frequency is set up by the four registers. SU BC A R R IER F R EQ UENCY REG 3 F SC 3 1 F SC 3 0 F SC 2 9 F SC 2 8 F SC 2 7 F SC 2 6 F SC 2 5 F SC 2 4 SU BC A R R IER F R EQ UENCY REG 2 F SC2 3 F SC 2 2 F SC 2 1 F SC 2 0 F SC 1 9 F SC 1 8 F SC 1 7 F SC 1 6 SU BC A R R IER F R EQ UENCY REG 1 F SC 1 5 F SC 1 4 F SC 1 3 F SC 1 2 F SC 1 1 F SC 1 0 F SC 9 F SC 8 SU BC A R R IER F R EQ UENCY REG 0 F SC 7 F SC 6 F SC 5 F SC 4 F SC 3 F SC 2 F SC 1 F SC 0 Y R A IN AL M IC I L N E H A R T P EC A T D Figure 66. Sub Carrier Frequency Registers SUB-CARRIER PHASE REGISTER (FP7-FP0): (Address (SR4-SR0) = 10H) This 8-Bit wide register is used to set up the Sub-Carrier Phase. Each bit represents 1.41o. For normal operation this register is set to 00Hex. SUB C A R RIE R PH A S E RE G IST ER FP H 7 FP H 6 F P H 4 FP H 5 FP H 3 FP H 2 F P H 1 CLOSED CAPTIONING ODD FIELD DATA REGISTER 1-0 (CCD15-CCD00) (Subaddress (SR4-SR0) = 13-14H) These 8-Bit wide registers are used to set up the closed captioning data bytes on Odd Fields. Figure 69 shows how the high and low bytes are set up in the registers. FP H 0 BYTE 1 BYTE 0 Figure 67. Subcarrier Phase Register CLOSED CAPTIONING EVEN FIELD DATA REGISTER 1-0 (CED15-CED00) (Address (SR4-SR0) = 11-12H) C ED 15 C E D 7 C ED 1 4 C E D 6 C ED 1 3 C E D 5 C ED 1 2 C E D 4 C ED 1 1 C E D 3 C ED 1 0 C E D 2 C E D 9 C E D 1 C E D 8 C E D 0 Figure 69. Closed Captioning Data Register These 8-Bit wide registers are used to set up the closed captioning extended data bytes on Even Fields. Figure 68 shows how the high and low bytes are set up in the registers. BYT E 1 BYT E 0 C C D 15 C C D 7 C CD 14 C C D 6 C C D 13 C C D 5 C CD 12 C C D 4 C C D 11 C C D 3 C C D 10 C C D 2 C C D 9 C C D 1 C C D 8 C C D 0 Figure 68. Closed Captioning Extended Data Register 49 REV. Pr F Preliminary Technical Data ADV7192 NTSC PEDESTAL / PAL TELETEXT CONTROL REGISTERS 3-0 (PCE15-0, PCO15-0)/ (TXE15-0, TXO15-0) (Subaddress (SR4-SR0) = 15-18H) These 8-Bit wide registers are used to enable the NTSC pedestal/ PAL Teletext on a line by line basis in the vertical blanking interval for both odd and even fields. Figure 70/71 show the four control registers. A logic "1" in any of the bits of these registers has the effect of turning the Pedestal OFF on the equivalent line when used in NTSC. A logic "1" in any of the bits of these registers has the effect of turning Teletext ON on the equivalent line when used in PAL . LIN E 17 LIN E 16 F IE LD 1/3 PC O 7 PC O 6 LIN E 25 LIN E 24 F IE LD 1/3 PC O 15 PC O 14 LIN E 15 LIN E 14 LIN E 13 LIN E 12 LIN E 11 LIN E 10 PC O 5 PC O 4 PC O 3 PC O 2 PC O 1 PC O 0 LIN E 14 LIN E 13 LIN E 12 LIN E 11 LIN E 10 F IE L D 1/3 TX O 7 LIN E 23 LIN E 22 LIN E 21 LIN E 20 LIN E 19 LIN E 18 PC O 13 PC O 12 P C O 11 PC O 10 PC O 9 P C O 8 P C E 7 PC E 6 PC E 5 PC E 4 PC E 3 PC E 2 P C E 1 PC E 0 TXO 15 PC E 15 PC E 14 PC E 13 PC E 12 PC E 11 TXO 14 TX E 7 TXO 13 P C E 9 PC E 8 (TC00-TC03) TC05 TC04 TX E 6 TX E 5 TX E 4 TX O 11 TX O 1 TXO 10 LIN E 10 LIN E 9 TX E 3 TX E 15 TX E 14 TX E 13 TX E 12 TX E 11 T TXREQ Rising Edge Control LIN E 7 TX O 0 TX E 2 TX O 9 TX O 8 LIN E 8 LIN E 7 TX E 1 TX E 0 TXE 10 TX E 9 TX E 8 (TC04-TC07): These bits control the position of the rising edge of TTXREQ. It can be programmed from zero clock cycles to a max of 15 clock cycles. PCLK = clock cycle at 27MHz. TC03 TTXR EQ R ising Edge C on trol TC07 TC 06 TC05 TC 04 LIN E 8 TX O 2 TC03 are 00Hex when Bits TC04-TC07 are changed then the falling egde of TTREQ will track that of the rising edge (i.e. the time between the falling and rising edge remains constant). PCLK = clock cycle at 27MHz. These bits control the position of the falling edge of TTXREQ. It can be programmed from zero clock cycles to a max of 15 clock cycles. This controls the active window for Teletext data. Increasing this value reduces the amount of Teletext bits below the default of 360. If Bits TC00- TC06 LIN E 9 Figure 71. Teletext Control Registers Teletext Control Register is a 8-bit wide register. See Figure 72 TTXREQ FALLING EDGE CONTROL TX O 3 LIN E 22 LIN E 21 LIN E 20 LIN E 19 LIN E 18 LIN E 17 LIN E 16 LIN E 15 F IE L D 2/4 TELETEXT REQUEST CONTROL REGISTER TC07 (TC07-TC00) (Address (SR4-SR0) = 1CH) TC02 TC01 TC00 TTXR EQ F alling Edge C ontrol TC03 TC 02 TC01 TC 00 0 0 0 0 0 PCLK 0 0 0 0 0 PCLK 0 0 0 1 1 PCLK 0 0 0 1 1 PCLK " 1 " 1 " 1 " 0 " PC LK 14 PC LK " 1 " 1 " 1 " 0 1 1 1 1 15 PC LK 1 1 1 1 " PC LK 14 PC LK 15 PC LK Figure 72 . Teletext Request Control Register REV. Pr F TXO 12 Y R A IN AL M IC I L N E H A R T P EC A T D PC E 10 Figure 70. Pedestal Control Registers TC07 TX O 4 LIN E 14 LIN E 13 LIN E 12 LIN E 11 F IE L D 2/4 LIN E 25 LIN E 24 LIN E 23 LIN E 22 LIN E 21 LIN E 20 LIN E 19 LIN E 18 F IE LD 2/4 TX O 5 LIN E 22 LIN E 21 LIN E 20 LIN E 19 LIN E 18 LIN E 17 LIN E 16 LIN E 15 F IE L D 1/3 LIN E 17 LIN E 16 LIN E 15 LIN E 14 LIN E 13 LIN E 12 LIN E 11 LIN E 10 F IE LD 2/4 TX O 6 50 ADV7192 Preliminary Technical Data the ADV7192. If this bit is disabled ("0") the CRC values in the register are output to the CGMS data stream. CGMS_WSS REGISTER 0 C/W0 (C/W07-C/W00) (Address (SR4-SR0) = 19H) CGMS_WSS register 0 is an 8-bit wide register. Figure 73 shows the operations under control of this register. CGMS Odd Field Control -C/W0 BIT DESCRIPTION- CGMS Even Field Control (C/W06) : CGMS Data (C/W00-C/W03) : These four data bits are the final four bits of CGMS data output stream. Note it is CGMS data ONLY in these bit positions i.e. WSS data does not share this location. When this bit is set ("1") CGMS is enabled for even fields. Note this is only valid in NTSC mode. Wide Screen Signal When this bit is enabled ("1"), the last six bits of the CGMS data i.e. the CRC check sequence is calculated internally by C /W 0 6 C /W 0 5 W ID E S C R EE N S IG N A L C O N T RO L 0 1 C /W 0 4 C /W 03 C /W 0 2 C G M S O D D F IEL D CON TROL C /W 0 7 Control (C/W07) : When this bit is set ("1"), wide screen signalling is enabled. Note this is only valid in PAL mode. CGMS CRC Check Control (C/W04) : C /W 0 7 (C/W05) : When this bit is set ("1") CGMS is enabled for odd fields. Note this is only valid in NTSC mode. C /W 0 1 C /W 00 C /W 0 3 - C /W 0 0 C /W 0 5 CGM S DATA Y R A IN AL M IC I L N E H A R T P EC A T D D IS A B L E ENA BLE 0 1 D IS A B L E ENA BLE C G M S E V E N F IEL D CON TROL C /W 0 6 0 1 C G M S C R C C H EC K CON TROL C /W 0 4 D IS A B L E ENA BLE 0 1 D IS A B L E ENA BLE Figure 73. CGMS_WSS Register 0 CGMS_WSS REGISTER 1 C/W1 (C/W17-C/W10) (Address (SR4-SR0) = 1AH) CGMS_WSS register 1 is an 8-bit wide register. Figure 74 shows the operations under control of this register. -C/W1 BIT DESCRIPTIONCGMS/WSS Data (C/W10-C/W15) : These bit locations are shared by CGMS data and WSS data. In NTSC mode these bits are CGMS data. In PAL mode these bits are WSS data. CGMS Data CGMS_WSS REGISTER 2 C/W1 (C/W27-C/W20) (Address (SR4-SR0) = 1BH) CGMS_WSS register 2 is an 8-bit wide register.Figure 75 shows the operations under control of this register. -C/W2 BIT DESCRIPTIONCGMS/WSS Data (C/W20-C/W27) : These bit locations are shared by CGMS data and WSS data. In NTSC mode these bits are CGMS data. In PAL mode these bits are WSS data. (C/W16-C/W17) : These bits are CGMS data bits only. C /W 1 7 C /W 1 6 C /W 1 5 C /W 1 4 C /W 1 3 C /W 1 2 C /W 1 1 C /W 1 0 C /W 1 5 - C /W 1 0 C /W 1 7 C /W 1 6 C G M S /W S S D A T A CGM S DATA Figure 74. CGMS_WSS Register 1 C /W 2 7 C /W 2 6 C /W 2 5 C /W 2 4 C /W 2 3 C /W 2 2 C /W 2 1 C /W 2 0 C /W 2 7 - C /W 2 0 C G M S/W S S D A T A Figure 75. CGMS_WSS Register 2 51 REV. Pr F Preliminary Technical Data ADV7192 Example: CONTRAST CONTROL REGISTER (CC00-CC07) (Address (SR4-SR0) = 1DH) Scale factor = 1.18 Y Y Y Y The contrast control register is an 8-bit wide register used to scale the Y output levels. Figure 76 shows the operation under control of this register. Scale Value = 1.18 * 128 = 151.04 Scale Value= 151 (rounded to the nearest integer) Scale Value = 10010111b Scale Value = 97h Y Scale Value (CC00-CC07) : These eight bits represent the value required to scale the Y pixel data from 0.0 to 1.5 of its initial level. The value of these eight bits is calculated using the following equation: Y Scale Value = Scale factor * 128 CC07 CC06 CC05 CC04 CC03 CC02 CC01 CC00 CC07-CC00 Y R A IN AL M IC I L N E H A R T P EC A T D Y SCALE VALUE Figure 76. Contrast Control Register COLOUR CONTROL REGISTERS 1-2 (CC1-CC2) (Address (SR4-SR0) = 1EH-1FH) The colour control registers are 8-bit wide registers used to scale the U and V output levels. Figure 77 shows the operations under control of these registers. U U U U -CC1 BIT DESCRIPTIONU Scale Value (CC10-CC17) : -CC2 BIT DESCRIPTION- These eight bits represent the value required to scale the U level from 0.0 to 2.0 of its initial level. The value of these eight bits is calculated using the following equation: U Scalar Value = Scale factor * 128 Example: Scale factor = 1.18 V Scale Value (CC20-CC27) : These eight bits represent the value required to scale the V pixel data from 0.0 to 2.0 of its initial level. The value of these eight bits is calculated using the following equation: Example: Scale factor = 1.18 V V V V CC17 CC16 Scale Value = 1.18 * 128 = 151.04 Scale Value= 151 (rounded to the nearest integer) Scale Value = 10010111b Scale Value = 97h CC15 CC14 CC13 CC12 CC11 Scale Value = 1.18 * 128 = 151.04 Scale Value= 151 (rounded to the nearest integer) Scale Value = 10010111b Scale Value = 97 h CC27 CC10 CC26 CC25 CC23 V SCALE VALUE U SCALE VALUE Figure 77.Color Control Registers REV. Pr F CC24 52 CC22 CC21 CC20 ADV7192 Preliminary Technical Data HUE ADJUST CONTROL REGISTER (HCR) (Address (SR5-SR0) = 20H) (Hue Adjust) [o] = 0.17578125o x( HCRd -128) , for positive Hue Adjust Value. The hue control register is an 8-bit wide register used to adjust the hue on the composite and chroma outputs. Figure 78 shows the operation under control of this register. -HCR BIT DESCRIPTIONHue Adjust Value (HCR0-HCR7) : EXAMPLE To adjust the hue by +4o write 97h to the Hue Control Register: These eight bits represent the value required to vary the hue of the video data i.e. the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the colorburst. The ADV7192 provides a range of +/22.5o increments of 0.17578125o. For normal operation (zero adjustment) this register is set to 80Hex. FFHex and 00Hex represent the upper and lower limit (respectively) of adjustment attainable. HC R7 HC R6 HC R5 HC R4 (4 / 0.17578125) + 128 = 151d* = 97h * rounded to the nearest integer To adjust the hue by -4o write 69h to the Hue Control Register: (- 4 / 0.17578125) + 128 = 105d* = 69h * rounded to the nearest integer HC R3 HC R2 HC R1 HC R0 Y R A IN AL M IC I L N E H A R T P EC A T D HU E A D JU S T V A L U E Figure 78. Hue Adjust Control Register 53 REV. Pr F Preliminary Technical Data ADV7192 BRIGHTNESS CONTROL REGISTER (BCR) (Address (SR5-SR0) = 21H) The brightness control register is an 8-bit wide register which allows brightness control. Figure 79 shows the operation under control of this register. EXAMPLE: Standard: NTSC with Pedestal. To add +20IRE brightness level write 28H into the Brightness Control Register: -BCR BIT DESCRIPTIONBrightness Value (BCR0-BCR6) : Seven bits of this 8-bit wide register are used to control the brightness level. The brightness is controlled by adding a programmable setup level onto the scaled Y data. This brightness level can be a positive or negative value. The programmable brightness levels in NTSC without Pedestal and PAL are maximum +15IRE and minimum -7.5IRE, in NTSC with Pedestal maximum 22.5 IRE and minimum 0IRE. Standard: PAL. To add -7 IRE brightness level write 72H into the Brightness Control Register: S E T -U P L E V E L IN N T S C W IT H PEDESTA L S E T -U P L E V E L IN NTSC NO PEDESTA L [Brightness Control Register Value]H = [IRE Value *2.015631]H = [20 *2.015631]H = [40.31262]H = 28H [|IRE Value| *2.015631] = [7 *2.015631] = [14.109417] = 0001110B [0001110] into 2's complement = [1110010]B = 72H Y R A IN AL M IC I L N E H A R T P EC A T D B R IG H T N E S S CO NTRO L R E G IS T E R VALUE S E T -U P LEVEL IN P A L 2 2 .5 IR E 1 5 IR E 1 5 IR E 1 5 IR E 7 . 5 IR E 7 . 5 IR E 7 . 5 IR E 0 IR E 0 IR E 0 IR E - 7 .5 IR E - 7 .5 IR E NT SC w i th o ut pede stal + 7. 5 IRE 10 0 IR E 1E h 0F h 0 IR E 00 h - 7. 5 IRE 71 h No s et up valu e ad ded Pos itive setup valu e a dded Ne gative setup valu e added Figure 79. Possible output levels for given Brightness Control register values BC R7 BC R6 BC R5 BC R4 BC R3 BC R2 BC R 7 Z ER O M US T B E W RIT T EN T O T HIS BIT BC R1 Figure 81. Adding a positve or negative Brightness Value to an unscaled Y signal BC R0 BR IG H T NE S S V A L U E Figure 80. Brightness Control Register SHARPNESS CONTROL REGISTER (PR) (Address (SR5-SR0) = 22H) while the value 0 (0000) corresponds to -4dB. For normal operation these four bits are set to 6 (0110).Note: 'Luma Filter Select' has to be set to 'Extended Mode' and 'Sharpness Filter Enable' Control has to be enabled for settings in the Sharpness Control Register to take effect ( MR02-04 = '100' ; MR74 = '1' ). Refer to figures 12-15 for the filter responses. The sharpness response register is an 8-bit wide register. The four MSBs are set to "0". The four LSBs are written to in order to select a desired filter response. Figure 82 shows the operation under control of this register. -PR BIT DESCRIPTIONSharpness Response Value (PR3-PR0) : These four bits are used to select the desired luma filter response. The option of twelve responses is given supporting a gain boost/attenuation in the range -4dB to +4dB. The value 12 (1100) written to these four bits corresponds to a boost of +4dB PR7 PR6 PR 7 PR5 PR4 A logical "0" must be written to these bits. PR2 PR1 PR0 PR 6 PR5 PR 4 Z ER O M UST BE W RIT T EN T O T HE SE BIT S REV. Pr F PR3 Reserved (PR4-PR7) : SH A R PN ES S RE SPO N SE V A L U E Figure 82. Sharpness Control Register 54 ADV7192 Preliminary Technical Data DNR REGISTERS 2 -0 (DNR 2 - DNR 0) (Address (SR5-SR0) = 23H - 25H) Coring Gain Data (DNR04-DNR07) : These four bits are assigned to the gain factor applied to the luma data inside the MPEG pixel block. In DNR Mode the range of gain values is 0 - 1, in increments of 1/8. This factor is applied to the DNR filter output which lies below the set threshold range. The result is then subtracted from the original signal. In DNR Sharpness Mode the range of gain values is 0 0.5, in increments of 1/16. This factor is applied to the DNR filter output which lies above the threshold range. The result is added to the original signal. Figure 83, 84 show the various operations under the control of DNR Register 0. The Digital Noise Reduction Registers are three 8-bit wide register. They are used to control the DNR processing. See also page 27. Coring Gain Border (DNR00-DNR03) : These four bits are assigned to the gain factor applied to border areas . In DNR Mode the range of gain values is 0 - 1, in increments of 1/8. This factor is applied to the DNR filter output which lies below the set threshold range. The result is then subtracted from the original signal. In DNR Sharpness Mode the range of gain values is 0 0.5, in increments of 1/16. This factor is applied to the DNR filter output which lies above the threshold range. The result is added to the original signal. D NR 07 D NR 05 D NR 06 D NR 04 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 + + + + + + + + 0 0 0 0 0 0 0 0 1 1/ 16 2/ 16 3/ 16 4/ 16 5/ 16 6/ 16 7/ 16 8/ 16 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 DNR04 DNR03 + + + + + + + + 0 0 0 0 0 0 0 0 1 1/ 16 2/ 16 3/ 16 4/ 16 5/ 16 6/ 16 7/ 16 8/ 16 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 C o r i n g G a i n B o rd e r - 0 1 /8 2 /8 3 /8 4 /8 5 /8 6 /8 7 /8 1 BL O C K SIZ E C O NT RO L D NR 17 0 1 8 PIX EL S 16 PIX EL S 0 1 2 PIX EL S 4 PIX EL S 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 - 0 1 /8 2 /8 3 /8 4 /8 5 /8 6 /8 7 /8 1 2 PIX E L B O R D E R D AT A 8 x 8 PIX E L B L O C K Figure 85. MPEG Block diagram D NR 13 BO R D ER A RE A D NR 16 0 0 0 0 1 1 1 1 0 8 x 8 PIX E L B L O C K Block size control (DNR17): This bit is used to select the size of the data blocks to be processed (see figure 82). Setting the block size control function to a logic '1' defines a 16x16 pixel data block, a logic '0' defines an 8x8 pixel data block, where 1 pixel refers to 2 clock cycles at 27 MHz. D NR 14 0 0 0 0 0 0 0 0 1 7 2 0 X 4 8 5 PIX E L S (N T S C ) Border Area (DNR16): In setting DNR16 to a logic '1' the block transistion area can be defined to consist of 4 pixels. If this bit is set to a logic '0' the border transition area consists of 2 pixels, where 1 pixel refers to 2 clock cycles at 27MHz. D NR 15 DNR00 Figure84. DNR Register 0 in DNR Mode These 6 bits are used to define the threshold value in the range of 0 to 63. The range is an absolute value. D NR 16 DNR01 D NR D NR DNR D NR 03 02 01 00 DNR Threshold (DNR10 - DNR 15): D NR 17 DNR02 C o r i n g G a i n Da ta D NR D NR DNR D NR 07 06 05 04 Figure 83. DNR Register 0 in DNR Sharpness Mode DNR1 BIT DESCRIPTION- DNR05 DNR06 DNR07 D NR 00 D NR 01 D N R D NR D NR D NR 03 02 01 00 D NR D N R D N R D N R 07 06 05 04 0 0 0 0 1 1 1 1 0 D NR 02 C oring G ain Border C oring G ain Data 0 0 0 0 0 0 0 0 1 Y R A IN AL M IC I L N E H A R T P EC A T D D NR 03 D NR 12 D NR 11 D NR 10 D N R T H RE SH O L D D NR DNR 15 14 0 0 0 0 . . . . . . 1 1 1 1 DNR 13 0 0 . . . 1 1 D NR 12 0 0 . . . 1 1 D NR 11 0 0 . . . 1 1 DNR 10 0 1 . . . 0 1 0 1 . . . 62 63 Figure 86 DNR Register 1 55 REV. Pr F Preliminary Technical Data ADV7192 DNR2 BIT DESCRIPTION- In DNR mode, it is possible to subtract a fraction of the signal which lies below the set threshold, assumed to be noise, from the original signal. The threshold is set in DNR Register 1. DNR Input Select Control (DNR20-DNR22): Three bits are assigned to select the filter which is applied to the incoming Y data.The signal which lies in the passband of the selected filter is the signal which will be DNR processed. The figure below show the filter responses selectable with this control. DNR Mode Control (DNR23): This bit controls the DNR mode selected. A logic '0' selects DNR mode, a logic '1' selects DNR Sharpness mode. DNR works on the principle of defining low amplitude, high frequency signals as probable noise and subtracting this noise from the original signal. When DNR Sharpness mode is enabled it is possible to add a fraction of the signal which lies above the set threshold to the original signal, since this data is assumed to be valid data and not noise. The overall effect being that the signal will be boosted (similar to using Extended SSAFTM filter) . 1 Ma g nitud e 0.8 0.6 0.4 Y R A IN AL M IC I L N E H A R T P EC A T D F ilte r D 0.2 0 0 F ilte r C 1 F ilter B F ilte r A 2 3 4 5 6 Frequency (Hz) x 10 6 Figure 87. Filter Response of filters selectable DNR M ode D N R C O N TR OL B lo ck s iz e c o n t ro l B o rd e r a r e a B lo c k o ffs e t G AI N C o rin g G a in D a ta C o ri n g G ai n Bo rd e r N O IS E S IG N AL PA T H Sub tract sig n al in T h resh o ld rang e fro m orig inal sig nal IN P U T F IL T E R BL O CK Y D a ta IN P U T F IL T E R O U T PU T < T H R ES H O L D ? F IL T E R O U T P U T > THRESH OLD M A IN SIG N A L P AT H D N R Sharpness M o de + Σ DN R OU T D N R C O NTR OL B lo ck siz e co n tro l B o rd e r a r e a B lo c k o ff s e t G AI N C o rin g G a in D a ta C o rin g G a in Bo rd e r N O IS E S IG N AL P AT H Y D a ta IN P U T IN P U T F IL T E R BLO CK Ad d sig n al ab o ve T h resh o ld ran ge to orig inal sig nal F IL T E R O U T PU T > T H R ES H O L D ? F IL T E R O U T P U T < THRESH OL D + + M AIN S IG N AL P AT H Σ DNR OUT Figure 88 Block diagram for DNR Mode and DNR Sharpness Mode REV. Pr F 56 ADV7192 Preliminary Technical Data Block Offset Control (DNR24- DNR27): Four bits are assigned to this control which allows a shift of the data block of 15 pixels maximum. Consider the coring gain positions fixed. The block offset 'shifts' the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data. DNR26 DNR27 BLOCK OFFSET CONTROL DNR DNR DNRDNR 27 26 25 24 0 0 0 . . . 1 1 1 0 0 0 . . . 1 1 1 0 0 1 . . . 0 1 1 0 1 0 . . . 1 0 1 DNR24 DNR25 DNR23 DNR22 DNR21 DNR INPUT SELECT CONTROL DNR MODE CONTROL Y R A IN AL M IC I L N E H A R T P EC A T D DNR DNR DNR 22 21 20 DNR23 0 PIXEL OFFSET 1 PIXEL OFFSET 2 PIXEL OFFSET . . . 13 PIXEL OFFSET 14 PIXEL OFFSET 15 PIXEL OFFSET 0 1 DNR20 DNR MODE DNR SHARPNESS MODE 0 0 0 1 0 1 1 0 1 0 1 0 FILTERA FILTERB FILTERC FILTERD Figure 89. DNR Register 2 AP P LY BO R DE R CO RIN G GA IN AP PL Y D AT A CO R IN G GA IN O X X X X X X O O X X X X X X O O X X X X X X O O X X X X X X O DN R 27 -D N R2 4 = 01 HE X OF FS ET CA US ED BY VA RIAT IO NS IN INPU T TIMING O X X X X X X O O X X X X X X O FIGURE 90 DNR 27-24, BLOCK OFFSET CONTROL 57 REV. Pr F Preliminary Technical Data ADV7192 GAMMA CORRECTION REGISTERS (GAMMA 0-13) (Address (SR5-SR0) = 26H -33H) 0- 13 EXAMPLE: y32 = [ (16 / 224)0.5 x 224] + 16 = 76* y64 = [ (48 / 224)0.5 x 224] + 16 =120* The Gamma Correction Registers are fourteen 8-bit wide register. They are used to program the gamma correction curves A and B. Generally gamma correction is applied to compensate for the non linear relationship between signal input and brightness level output (as perceived on the CRT). It can also be applied wherever non-linear processing is used. y96 = [ (80 / 224)0.5 x 224] + 16 = 150* y128 = [ (112 / 224)0.5 x 224] + 16 = 174* * rounded to the nearest integer The above will result in a gamma curve shown below, assuming a ramp signal as an input. Gamma correction uses the function : SignalOUT = (Signal IN )γ where δ = gamma power factor G am m a C orr ection B lo ck O utput to a R am p Input Gamma correction is performed on the luma data only. The user has the choice to use two different curves, curve A or curve B. At any one time only one of these curves can be used. The response of the curve is programmed at 7 predefined locations. In changing the values at these locations the gamma curve can be modified. Between these points linear interpolation is used to generate intermediate values. Considering the curve to have a total length of 256 points, the seven locations are at: 32, 64, 96, 128, 160, 192, 224. 25 0 G a m m a C o rr ec tio n Blo ck O utput to a R am p In p ut fo r v ariou s G am m a V alues 30 0 Y R A IN AL M IC I L N E H A R T P EC A T D 20 0 where 10 0 0.5 20 0 15 0 10 0 50 50 0 For the length of 16 to 240 the gamma correction curve has to be calculated as below: γ 15 0 Gam ma Co rre cted Am plitud e Gam m a C or rec ted A m plitude 25 0 Location 0, 16, 240 and 255 are fixed and can not be changed. y=x S ign a l O utput S ign a l Inp ut 50 10 0 150 2 00 2 50 Loc atio n Figure 91 Signal Input (Ramp) and Signal Output for Gamma 0.5 G a mm a C orre ctio n B lock O u tpu t to a Ram p In pu t f or va rio us G a mm a V a lu es y = gamma corrected output x = linear input signal 2 50 G am m a C orrecti n B lock Outpu t to a R a m p Input for arious G am m a V alues γ = gamma power factor G am m a C orrected Am p litude 2 00 To program the gamma correction registers, the 7 values for y have to be calculated using the following formulare: yn = [ x(n-16) / (240 - 16) ]γ x (240-16) + 16 0.5 1.5 1 50 1.8 1 00 Si where x(n-16) = Value for x along x-axis at points n = 32, 64, 96, 128, 160, 192 or 224 = Value for y along the y-axis, which has yn to be written into the gamma correction register . gn al In pu t 50 50 1 00 1 50 2 00 2 50 L ocation Figure 92 Signal Input (Ramp) and selectable Gamma Output curves The gamma curves shown above are examples only, any user defined curve is acceptable in the range of 16 - 240. REV. Pr F 58 ADV7192 Preliminary Technical Data BRIGHTNESS DETECT REGISTER (Address (SR5-SR0) = 34H) The Brightness Detect Register is a 8-bit wide register used only to read back data in order to monitor the brightness/darkness of the incoming video data on a field-by-field basis. The brightness information is read from the I2C and based on this information, the color controls or the gamma correction controls may be adjusted. The luma data is monitored in the active video area only. The average brightness I2C register is updated on the fallling edge of every VSYNC signal. OUTPUT CLOCK REGISTER ((OCR OCR 9-0) (Address (SR4-SR0) = 35H) The Output Clock Register is a 8-Bit wide register. Figure 93 shows the various operations under the control of this register. OCR Reserved (OCR02): A logic '0' must be written to this bit. Reserved (OCR03-06): BIT DESCRIPTION Y R A IN AL M IC I L N E H A R T P EC A T D A logic '1' must be written to these bits. Reserved (OCR00): A logic '0' must be written to this bit. Reserved (OCR07): CLKOUT pin Control (OCR01): This bit enables the CLKOUT pin when set to '1' and therefore outputs a 54MHz clock generated by the internal PLL. The PLL and 4xOversampling have to be enabled for this control to take effect, (MR61 = ' 0' ; MR16 = '1' ). OCR07 OCR 07 Z E R O M US T BE W R IT T E N T O T H IS BIT OCR06 OCR05 OCR 04 A logic '0' must be written to this bit. OCR03 O C R 0 6 - O C R4 OCR03 -OCR0 2 O N E M US T B E W RIT T E N T O T H E S E BIT S Z E R O M US T BE W R IT T E N T O T H E S E S B IT S OCR02 OCR01 OCR00 C L K O U T PIN C O N T R O L OCR00 OCR01 Z E R O M US T BE W R IT T E N T O T H IS BIT 0 1 E NA B L E D D IS A B L E D Figure 93. Output Clock Register 59 REV. Pr F Preliminary Technical Data ADV7192 APPENDIX 1 BOARD DESIGN AND LAYOUT CONSIDERATIONS The ADV7192 is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. It is imperative that these same design and layout techniques be applied to the system level design such that high speed, accurate performance is achieved. The Recommended Analog Circuit Layout shows the analog interface between the device and monitor. The layout should be optimized for lowest noise on the ADV7192 power and ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and GND pins should by minimized so as to minimize inductive ringing. Ground Planes For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. Best performance is obtained with 0.1 µF ceramic capacitor decoupling. Each group of VAA pins on the ADV7192 must have at least one 0.1 µF decoupling capacitor to GND. These capacitors should be placed as close as possible to the device. It is important to note that while the ADV7192 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise and consider using a three- terminal voltage regulator for supplying power to the analog power plane. Y R A IN AL M IC I L N E H A R T P EC A T D The ground plane should encompass all ADV7192 ground pins, voltage reference circuitry, power supply bypass circuitry for the ADV7192, the analog output traces, and all the digital signal traces leading up to the ADV7192. This should be as substantial as possible to maximize heat spreading and power dissipation on the board. Power Planes Supply Decoupling The ADV7192 and any associated analog circuitry should have its own power plane, referred to as the analog power plane (VAA). This power plane should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead. This bead should be located within three inches of the ADV7192. The metallization gap separating device power plane and board power plane should be as narrow as possible to minimise the obstruction to the flow of heat from the device into the general board. Digital Signal Interconnect The digital inputs to the ADV7192 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane. Due to the high clock rates involved, long clock lines to the ADV7192 should be avoided to reduce noise pickup. Any active termination resistors for the digital inputs should be connected to the regular PCB power plane (VCC), and not the analog power plane. Analog Signal Interconnect The ADV7192 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. The video output signals should overlay the ground plane, and not the analog power plane, to maximize the high frequency power supply rejection. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7192 power pins and voltage reference circuitry. Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane, unless they can be arranged such that the plane-to-plane noise is common-mode. Digital inputs, especially pixel data inputs and clocking signals should never overlay any of the analog signal circuitry and should be kept as far away as possible. For best performance, the outputs should each have a 300ohm load resistor connected to GND. These resistors should be placed as close as possible to the ADV7192 so as to minimize reflections. The ADV7192 should have no inputs left floating. Any inputs that are not required should be tied to ground. REV. Pr F 60 ADV7192 Preliminary Technical Data P O W E R S U P P L Y D E C O U P L IN G FO R EACH PO W ER SUPPLY G RO UP + 5 V (V A A ) + 5 V (V A A) + 5 V (V A A ) + 0 .1 µ F 10µF 0 .1 µ F 0 .1 µ F + 5 V (VD D ) + 10µF 0 .1 µ F 53, 48, 38 45 7 9 , 6 8 , 3 4 ,2 1 56 COMP 2 57 V R EF VAA COMP 1 VDD AD V7192 C b 0 -C b 9 C r0 - C r 9 DAC A 55 300R Y 0 /P 8 - Y 7 /P 15 Y 8- Y 9 DAC B 54 300R P 7 -P 0 DAC C "U N U SE D IN P U TS S HO UL D B E G RO UN DE D " 51 Y R A IN AL M IC I L N E H A R T P EC A T D 61 C SO _H S O 62 300R V S O /T T X /C L A M P DAC D 50 300R 59 PAL_N TS C 41 S C R E S E T /R T C / T R D AC E 47 23 HSYNC 24 VSYN C 25 BLAN K 30 0 R + 5 V (V A A) D AC F 46 + 5 V (V A A ) 4k7 + 60 4 .7 u F 6 .3 V 300R RESE T 32 TTXR E Q 36 27M Hz CLO CK (S A M E C L O C K A S U S E D B Y M PEG 2 DECO DER) + 5 V (V A A ) C L K IN ALSB SCL 39 SD ATA 40 RSET 2 44 RSET 1 58 5k + 5 V (V A A) 5k 100R 100R M PU BUS 1K2 1K2 AG ND DGND 42 80, 69, 43 33, 22, 4k7 52, 49, 35 Figure 94. Recommended Analog Circuit Layout 61 REV. Pr F Preliminary Technical Data ADV7192 APPENDIX 2 CLOSED CAPTIONING The ADV7192 supports closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of even fields. Closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase locked to the caption data. After the clock run-in signal, the blanking level is held for two data bits and is followed by a logic level "1" start bit. 16 bits of data follow the start bit. These consist of two 8-bit bytes, seven data bits and one odd parity bit. The data for these bytes is stored in Closed Captioning Data Registers 0 and 1. The ADV7192 also supports the extended closed captioning operation which is active during even fields and is encoded on Scan Line 284. The data for this operation is stored in Closed Captioning Extended Data Registers 0 and 1. All clock run-in signals and timing to support Closed Captioning on Lines 21 and 284 are generated automatically by the ADV7192. All pixels inputs are ignored during Lines 21 and 284 if closed captioning is enabled. FCC Code of Federal Regulations (CFR) 47 section 15.119 and EIA608 describe the closed captioning information for Lines 21 and 284. Y R A IN AL M IC I L N E H A R T P EC A T D The ADV7192 uses a single buffering method. This means that the closed captioning buffer is only one byte deep, therefore there will be no frame delay in outputting the closed captioning data unlike other two byte deep buffering systems. The data must be loaded one line before (Line 20 or Line 283) it is outputted on Line 21 and Line 284. A typical implementation of this method is to use VSYNC to interrupt a microprocessor, which in turn will load the new data (two bytes) every field. If no new data is required for transmission, "0"es must be inserted in both data registers, this is called NULLING. It is also important to load 'control codes' all of which are double bytes on Line 21 or a TV will not recognize them. If there is a message like "Hello World" which has an odd number of characters, it is important to pad it out to even in order to get "end of caption" 2-byte control code to land in the same field. 10 .5 +/-0.2 5µs 12 .91µ s 7 C YCL ES O F 0.5 035 M H z (CL O CKRU N -IN ) TW O 7-B IT + PA R ITY ASCII C H AR AC T ER S (DATA) S T A R T 50 IR E P A R I T Y D 0 -D 6 B yt e 0 40 IR E R EF ER EN C E C O LO R BU R S T (9 C YC LES) F REQ U EN CY = F SC = 3 .579 545 M H z AM PLITUD E = 4 0 IRE 10 .003 µs 33 .764 µs 27 .382 µs Figure 95. Closed Captioning Waveform (NTSC) REV. Pr F 62 D 0 -D 6 Byte 1 P A R I T Y ADV7192 Preliminary Technical Data APPENDIX 3 COPY GENERATION MANAGEMENT SYSTEM (CGMS) The ADV7192 supports Copy Generation Management System (CGMS) conforming to the standard. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields. Bits C/W05 and C/W06 control whether or not CGMS data is outputed on ODD and EVEN fields. CGMS data can only be transmitted when the ADV7192 is configured in NTSC mode. The CGMS data is 20 bits long, the function of each of these bits is as shown below. The CGMS data is preceeded by a reference pulse of the same amplitude and duration as a CGMS bit, see figure below. These bits are outputed from the configuration registers in the following order: C/W00 = C16, C/W01= C17, C/W02 = C18, C/W03 = C19, C/W10 = C8 , C/W11 = C9, C/W12 = C10, C/W13 = C11, C/W14 = C12, C/W15 = C13, C/ W16 = C14 , C/W17 = C15 , C/W20 = C0 , C/W21 = C1, C/W22 = C2, C/W23 = C3, C/W24 = C4, C/W25 = C5, C/W26 = C6, C/W27= C7. If the bit C/W04 is set to a logic "1", the last six bits C19-C14 which comprise the 6-bit CRC check sequence are calculated automatically on the ADV7192 based on the lower 14 bits (C0-C13) of the data in the data registers and output with the remaining 14-bits to form the complete 20-bits of the CGMS data. The calculation of the CRC sequence is based on the polynomial X6 + X + 1 with a preset value of 111111. If C/W04 is set to a logic "0" then all 20-bits (C0-C19) are output directly from the CGMS registers (no CRC calculated, must be calculated by the user). Function of CGMS bits: WORD 0 - 6 BITS WORD 1 - 4 BITS WORD 2 - 6 BITS CRC - 6 BITS WORD 0 B1 Aspect ratio B2 Display format B3 Undefined Y R A IN AL M IC I L N E H A R T P EC A T D CRC polynomial = X6 + X + 1 (preset to 111111) 1 0 16:9 4:3 Letterbox Normal WORD 0 B4,B5,B6 Identification information about video and other signals (e.g. audio) WORD 1 B7,B8,B9,B10 Identification signal incidental to Word 0 WORD 2 B11,B12,B13,B14 Identification signal and information incidental to Word 0 100 IRE CRC Sequence REF 70 IRE C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 0 IRE -40 IRE 49.1µs±0.5µS 11.2µs 2.235µs±20nS Figure 96. CGMS Waveform diagram 63 REV. Pr F Preliminary Technical Data ADV7192 APPENDIX 4 WIDE SCREEN SIGNALLING The ADV7192 supports Wide Screen Signalling (WSS) conforming to the standard. WSS data is transmitted on line 23. WSS data can only be transmitted when the ADV7192 is configured in PAL mode. The WSS data is 14-bits long, the function of each of these bits is as shown below. The WSS data is preceeded by a run-in sequence and a Start Code, see figure below. The bits are output from the configuration registers in the following order: C/W20 = W0, C/ W21= W1, C/W22 = W2, C/W23 = W3, C/W24 = W4 , C/W25 = W5, C/W26 = W6, C/W27 = W7, C/W10 = W8, C/ W11 = W9, C/W12 = W10 , C/W13 = W11 , C/W14 = W12 , C/W15 = W13 . If the bit C/W07 is set to a logic "1" it enables the WSS data to be transmitted on Line 23. The latter portion of Line 23 (42.5µs from the falling edge of HSYNC) is available for the insertion of video. Function of CGMS bits: Bit 0 - Bit 2 Bit 3 Aspect Ratio / Format / Position is odd parity check of Bit 0 -Bit 2 B0, B1, B2,B3 0 0 0 1 1 0 0 0 0 1 0 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 1 1 1 1 0 Aspect Ratio 4:3 14:9 14:9 16:9 16:9 >16:9 14:9 16:9 Format Full Format Letterbox Letterbox Letterbox Letterbox Letterbox Full Format non-applicable Position non-applicable centre top centre top centre centre non-applicable Y R A IN AL M IC I L N E H A R T P EC A T D B4 0 1 Camera Mode Film Mode B5 0 1 Standard coding Motion Adaptive Colour Plus B6 0 1 No Helper Modulated Helper B7 RESERVED B9 0 1 0 1 B10 0 0 1 1 No open subtitles Subtitles in active image area Subtitles out of active image area Reserved B11 0 1 No surround sound information Surround sound mode B12 B13 RESERVED RESERVED 500m V W 0 W 1 W 2 W 3 W 4 W 5 W 6 W 7 W 8 W 9 W 1 0 W 11 W 12 W 13 Run-in Sequ en ce Start Code 11.0µs 38.4µs 42.5µs Figure 97. WSS Waveform diagram REV. Pr F 64 ACT IV E VID EO ADV7192 Preliminary Technical Data APPENDIX 5 Teletext Insertion Time TPD is the time needed by the ADV7192 to interpolate input data on TTX and insert it onto the CVBS or Y outputs, such that it appears TsynTxtOut = 10.2µs after the leading edge of the horizontal signal. Time TxtDel is the pipeline delay time by the source that is gated by the TTREQ signal in order to deliver TTX data. With the programability that is offered with TTXREQ signal on the Rising/Falling edges, the TTX data is always inserted at the correct position of 10.2µs after the leading edge of Horizontal Sync pulse, thus this enables a source interface with variable pipeline delays. The width of the TTXREQ signal must always be maintained such that it allows the insertion of 360 (in order to comply with the Teletext Standard "PAL-WST") teletext bits at a text data rate of 6.9375Mbits/s, this is achieved by setting TC03TC00 to "0". The insertion window is not open if the Teletext Enable bit (MR34) is set to "0". Teletext Protocol The relationship between the TTX bit clock (6.9375MHz) and the system CLOCK (27MHz) for 50Hz follows: (27MHz / 4 ) = 6.75MHz (6.9375 X 106 / 6.75 X 106 = 1.027777 is given as Thus 37 TTX bits correspond to 144 clocks (27MHz), each bit has a width of almost 4 clock cycles. The ADV7192/93 uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a bandlimited signal which can be output on the CVBS and Y outputs. Y R A IN AL M IC I L N E H A R T P EC A T D At the TTX input the bit duration scheme repeats after every 37 TTX bits or 144 clock cycles. The protocol requires that TTX Bits 10, 19, 28, 37 are carried by three clock cycles, all other bits by four clock cycles. After 37 TTX bits, the next bits with three clock cycles are Bits 47, 56, 65 and 74. This scheme holds for all following cycles of 37 TTX bits, until all 360 TTX bits are completed. All teletext lines are implemented in the same way. Individual control of teletext lines are controlled by Teletext Setup Registers. 4 5 byte s (3 6 0 bi ts ) - PA L T E L E T E X T V B I L IN E A D D R ES S & D A T A R U N -IN C L O C K Figure 98. Teletext VBI Line tS Y N TX TO U T CV BS /Y tPD HSYNC tP D 10.2 µ s TX T D A T A TX T D E L TX T R E Q TX T S T P R O G R A M M A B LE P U LS E E D G E S t S YNT X TO U T = 10.2 µ s t P D = PIPELINE DELAY THROUG H ADV7192 TX T DE L = TTXREQ TO TTX (PROG RAM M ABLE RANG E = 4 B ITS [0-15 CLOCK CY CLE S ]) Figure 99. Teletext Functionality Diagram 65 REV. Pr F Preliminary Technical Data ADV7192 APPENDIX 6 OPTIONAL OUTPUT FILTER If an output filter is required for the CVBS, Y, UV, Chroma and RGB outputs of the ADV7192, the filter in Figure 100 can be used in 2xOversampling Mode. In4xOversampling Mode the filter in Figure 101 is recommended. The plot of the filter characteristics are shown in Figure 102 and 103. An output filter is not required if the outputs of the ADV7192 are connected to most analog monitors or TVs, however if the output signals are applied to a system where sampling is used (eg. Digital TVs) then a filter is required to prevent aliasing. Filter I/P Filter I/P Filter O /P 2.2 uH Filter O /P 0.82 uH 2.5 u H 47 0pF 470pF Y R A IN AL M IC I L N E H A R T P EC A T D Figure 100. Output Filter for 2xOversampling Mode Figure 101. Output Filter for 4xOversampling Mode 20 50 0 0 -20 -40 -50 -60 -10 0 -80 -15 0 1 00 K Hz 1 .0 M Hz 1 0M H z 1 00 M Hz -10 0 1 00 KH z 1 .0G H z 1 .0 MH z 10 MH z 1 00 MH z F re q u e n c y [M H z ] Figure 103 Output Filter Plot for 4xOversampling filter Figure 102. Output Filter Plot for 2xOversampling filter 2X Filter Requirements 0 dB 4X Filter Requirements - 3 0 dB 6.75M Hz 13.5M Hz 27.0M Hz 40.5M Hz 54.0M Hz Figure 104. Output Filter Requirements in 4xOversampling Mode REV. Pr F 1 .0 GHz F re qu en cy [M H z] 66 ADV7192 Preliminary Technical Data APPENDIX 7 DAC BUFFERING External buffering is needed on the ADV7192 DAC outputs. The configuration in Figure 105/106 is recommended. . When calculating absolute output full scale current and voltage use the following equations: VOUT = IOUT * RLOAD IOUT = (VREF * K )/ RSET K= 4.2146 constant, VREF = 1.235V VA A ADV 71 92 VREF OUTPUT BUFFER DA C A Y R A IN AL M IC I L N E H A R T P EC A T D RSET1 1K2 P IX E L POR T DAC B OUTP UT BUFFER LU M A DAC C OUTPUT BU FFER CHROM A DA C D OUTPUT BUFFER G DA C E OUTPUT BUFFER B DAC F OUTPUT BU FFER R D IG IT A L CORE RSET2 1K2 CV BS Figure 105. Output DAC Buffering Configuration VCC+ 4 5 - AD 805 1 IN PU T/ O P T IO N A L FILT ER O /P 3 + 2 1 O U T P U T TO TV M O NIT O R VCC - Figure 106. Recommended DAC Output Buffer using an OP-amp 67 REV. Pr F Preliminary Technical Data ADV7192 APPENDIX 8 RECOMMENDED REGISTER VALUES The ADV7192 registers can be set depending on the user standard required. The following examples give the various register formats for several video standards. Y R A IN AL M IC I L N E H A R T P EC A T D REV. Pr F 68 ADV7192 Preliminary Technical Data NTSC Address 00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex 23Hex 24Hex 25Hex 35Hex PAL B, D, G, H, I (Fsc = 4.43361875MHz) Address 00Hex Mode Register 0 01Hex Mode Register 1 02Hex Mode Register 2 03Hex Mode Register 3 04Hex Mode Register 4 05Hex Mode Register 5 06Hex Mode Register 6 07Hex Mode Register 7 08Hex Mode Register 8 09Hex Mode Register 9 0AHex Timing Register 0 0BHex Timing Register 1 0CHex Subcarrier Frequency Register 0 0DHex Subcarrier Frequency Register 1 0EHex Subcarrier Frequency Register 2 0FHex Subcarrier Frequency Register 3 10Hex Subcarrier Phase Register 11Hex Closed Captioning Ext Register 0 12Hex Closed Captioning Ext Register 1 13Hex Closed Captioning Register 0 14Hex Closed Captioning Register 1 15Hex Pedestal Control Register 0 16Hex Pedestal Control Register 1 17Hex Pedestal Control Register 2 18Hex Pedestal Control Register 3 19Hex CGMS_WSS Reg 0 1AHex CGMS_WSS Reg 1 1BHex CGMS_WSS Reg 2 1CHex Teletext Control Register 1DHex Contrast Control Register 1EHex Color Control Register 1 1FHex Color Control Register 2 20Hex Hue Control Register 21Hex Brightness Control Register 22Hex Sharpness Response Register 23Hex DNR0 24Hex DNR1 25Hex DNR2 35Hex Output Clock Register (Fsc = 3.5795454MHz) Data Mode Register 0 10Hex Mode Register 1 3FHex Mode Register 2 62Hex Mode Register 3 00Hex Mode Register 4 00Hex Mode Register 5 00Hex Mode Register 6 00Hex Mode Register 7 00Hex Mode Register 8 04Hex Mode Register 9 00Hex Timing Register 0 08Hex Timing Register 1 00Hex Subcarrier Frequency Register 0 16Hex Subcarrier Frequency Register 1 7CHex Subcarrier Frequency Register 2 F0Hex Subcarrier Frequency Register 3 21Hex Subcarrier Phase Register 00Hex Closed Captioning Ext Register 0 00Hex Closed Captioning Ext Register 1 00Hex Closed Captioning Register 0 00Hex Closed Captioning Register 1 00Hex Pedestal Control Register 0 00Hex Pedestal Control Register 1 00Hex Pedestal Control Register 2 00Hex Pedestal Control Register 3 00Hex CGMS_WSS Reg 0 00Hex CGMS_WSS Reg 1 00Hex CGMS_WSS Reg 2 00Hex Teletext Control Register 00Hex Contrast Control Register 00Hex Color Control Register 1 00Hex Color Control Register 2 00Hex Hue Control Register 00Hex Brightness Control Register 00Hex Sharpness Response Register 00Hex DNR 0 44Hex DNR 1 20Hex DNR 2 00Hex Output Clock Register 70Hex Y R A IN AL M IC I L N E H A R T P EC A T D 69 Data 11Hex 3FHex 62Hex 00Hex 00Hex 00Hex 00Hex 00Hex 04Hex 00Hex 08Hex 00Hex CBHex 8AHex 09Hex 2AHex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 44Hex 20Hex 00Hex 70Hex REV. Pr F Preliminary Technical Data ADV7192 PAL N (Fsc = 4.43361875MHz) Address 00Hex Mode Register 0 01Hex Mode Register 1 02Hex Mode Register 2 03Hex Mode Register 3 04Hex Mode Register 4 05Hex Mode Register 5 06Hex Mode Register 6 07Hex Mode Register 7 08Hex Mode Register 8 09Hex Mode Register 9 0AHex Timing Register 0 0BHex Timing Register 1 0CHex Subcarrier Frequency Register 0 0DHex Subcarrier Frequency Register 1 0EHex Subcarrier Frequency Register 2 0FHex Subcarrier Frequency Register 3 10Hex Subcarrier Phase Register 11Hex Closed Captioning Ext Register 0 12Hex Closed Captioning Ext Register 1 13Hex Closed Captioning Register 0 14Hex Closed Captioning Register 1 15Hex Pedestal Control Register 0 16Hex Pedestal Control Register 1 17Hex Pedestal Control Register 2 18Hex Pedestal Control Register 3 19Hex CGMS_WSS Reg 0 1AHex CGMS_WSS Reg 1 1BHex CGMS_WSS Reg 2 1CHex Teletext Control Register 1DHex Contrast Control Register 1EHex Color Control Register 1 1FHex Color Control Register 2 20Hex Hue Control Register 21Hex Brightness Control Register 22Hex Sharpness Response Register 23Hex DNR0 24Hex DNR1 25Hex DNR2 35Hex Output Clock Register Data 13Hex 3FHex 62Hex 00Hex 00Hex 00Hex 00Hex 00Hex 04Hex 00Hex 08Hex 00Hex CBHex 8AHex 09Hex 2AHex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 44Hex 20Hex 00Hex 70Hex PAL 60 (Fsc = 4.43361875MHz) Address 00Hex Mode Register 0 01Hex Mode Register 1 02Hex Mode Register 2 03Hex Mode Register 3 04Hex Mode Register 4 05Hex Mode Register 5 06Hex Mode Register 6 07Hex Mode Register 7 08Hex Mode Register 8 09Hex Mode Register 9 0AHex Timing Register 0 0BHex Timing Register 1 0CHex Subcarrier Frequency Register 0 0DHex Subcarrier Frequency Register 1 0EHex Subcarrier Frequency Register 2 0FHex Subcarrier Frequency Register 3 10Hex Subcarrier Phase Register 11Hex Closed Captioning Ext Register 0 12Hex Closed Captioning Ext Register 1 13Hex Closed Captioning Register 0 14Hex Closed Captioning Register 1 15Hex Pedestal Control Register 0 16Hex Pedestal Control Register 1 17Hex Pedestal Control Register 2 18Hex Pedestal Control Register 3 19Hex CGMS_WSS Reg 0 1AHex CGMS_WSS Reg 1 1BHex CGMS_WSS Reg 2 1CHex Teletext Control Register 1DHex Contrast Control Register 1EHex Color Control Register 1 1FHex Color Control Register 2 20Hex Hue Control Register 21Hex Brightness Control Register 22Hex Sharpness Response Register 23Hex DNR0 24Hex DNR1 25Hex DNR2 35Hex Output Clock Register Y R A IN AL M IC I L N E H A R T P EC A T D REV. Pr F 70 Data 12Hex 3FHex 62Hex 00Hex 00Hex 00Hex 00Hex 00Hex 04Hex 00Hex 08Hex 00Hex CBHex 8AHex 09Hex 2AHex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 44Hex 20Hex 00Hex 70Hex - ADV7192 Preliminary Technical Data POWER ON RESET REG VALUES (PAL_NTSC=0, NTSC selected Address 00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex 23Hex 24Hex 25Hex 26Hex 27Hex 28Hex 29Hex 2AHex 2BHex 2CHex 2DHex 2EHex 2FHex 30Hex 31Hex 32Hex 33Hex 34Hex 35Hex Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Mode Register 8 Mode Register 9 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 Teletext Control Register Contrast Control Register Color Control Register 1 Color Control Register 2 Hue Control Register Brightness Control Register Sharpness Response Register DNR0 DNR1 DNR2 Gamma 0 Gamma 1 Gamma 2 Gamma 3 Gamma 4 Gamma 5 Gamma 6 Gamma 7 Gamma 8 Gamma 9 Gamma 10 Gamma 11 Gamma 12 Gamma 13 Brightness Detect Register Output Clock Register POWER ON RESET REG VALUES (PAL_NTSC=1, PAL selected Data 00Hex 07Hex 08Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 08Hex 00Hex 16Hex 7CHex F0Hex 21Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex 72Hex Address 00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex 23Hex 24Hex 25Hex 26Hex 27Hex 28Hex 29Hex 2AHex 2BHex 2CHex 2DHex 2EHex 2FHex 30Hex 31Hex 32Hex 33Hex 34Hex 35Hex Y R A IN AL M IC I L N E H A R T P EC A T D 71 Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Mode Register 8 Mode Register 9 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 Teletext Control Register Contrast Control Register Color Control Register 1 Color Control Register 2 Hue Control Register Brightness Control Register Sharpness Response Register DNR0 DNR1 DNR2 Gamma 0 Gamma 1 Gamma 2 Gamma 3 Gamma 4 Gamma 5 Gamma 6 Gamma 7 Gamma 8 Gamma 9 Gamma 10 Gamma 11 Gamma 12 Gamma 13 Brightness Detect Register Output Clock Register Data 01Hex 07Hex 08Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 08Hex 00Hex CBHex 8AHex 09Hex 2AHex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex 72Hex REV. Pr F Preliminary Technical Data ADV7192 APPENDIX 9 NTSC WAVEFORMS (WITH PEDESTAL) 130 .8 IR E P E A K C O M P O S ITE 126 8.1m V 100 IR E R E F W H ITE 104 8.4m V 714 .2m V 7.5 IR E 0 IR E BLAC K LEV E L BLAN K LEV E L -40 IR E SYN C LEVEL 387 .6m V 334 .2m V 48.3 m V Figure 107. NTSC Composite Video Levels 100 IR E Y R A IN AL M IC I L N E H A R T P EC A T D R E F W H ITE 104 8.4m V 714 .2m V 7.5 IR E 0 IR E -40 IR E BLAC K LEV E L BLAN K LEV E L SYN C LEVEL 387 .6m V 334 .2m V 48.3m V Figure 108. NTSC Luma Video Levels PEAK C HROM A 106 7.7m V 835 m V (pk-pk) 286 m V (pk-pk) B LA N K /B LA C K LE V E L 650 m V PEAK C HROM A 232 .2m V 0m V Figure 109. NTSC Chroma Video Levels 100 IR E R E F W H ITE 105 2.2m V 720 .8m V 7.5 IR E 0 IR E BLAC K LEV E L BLAN K LEV E L -40 IR E SYN C LEVEL Figure 110. NTSC RGB Video Levels REV. Pr F 72 387 .5m V 331 .4m V 45.9m V ADV7192 Preliminary Technical Data NTSC WAVEFORMS (WITHOUT PEDESTAL) 130 .8 IR E P E A K C O M P O S ITE 128 9.8m V 100 IR E R E F W H ITE 105 2.2m V 714 .2m V BLAN K/BLA C K LE VEL 0 IR E SYN C LEVEL Ð 40 IRE 338 m V 52.1 m V Figure 111. NTSC Composite Video Levels 100 IR E Y R A IN AL M IC I L N E H A R T P EC A T D R E F W H ITE 105 2.2m V 714 .2m V 0 IR E -40 IR E BLAN K /B LA C K LE VEL SYN C LEVEL 338 m V 52.1m V Figure 112. NTSC Luma Video Levels PEAK C HROM A 110 1.6m V 903 .2m V (pk-pk) 307 m V (pk-pk) B LA N K /B LA C K LE V E L 650 m V PEAK C HROM A 198 .4m V 0m V Figure 113. NTSC Chroma Video Levels 100 IR E R E F W H ITE 105 2.2m V 715 .7m V BLAN K/BLA C K LE VEL 0 IR E SYN C LEVEL -40 IR E 336 .5m V 51m V Figure 114. NTSC RGB Video Levels 73 REV. Pr F Preliminary Technical Data ADV7192 PAL WAVEFORMS P E A K C O M P O S ITE 128 4.2m V 104 7.1m V R E F W H ITE 696 .4m V 350 .7m V BLAN K/BLA C K LE VEL 50.8 m V SYN C LEVEL Figure 115. PAL Composite Video Levels 104 7m V 350 .7m V 50.8m V Y R A IN AL M IC I L N E H A R T P EC A T D R E F W H ITE 696 .4m V BLAN K/BLA C K LE VEL SYN C LEVEL Figure 116. PAL Luma Video Levels 109 2.5m V PEAK C HROM A 885 m V (pk-pk) 300 m V (pk-pk) B LA N K /B LA C K LE V E L 650 m V PEAK C HROM A 207 .5m V 0m V Figure 117. PAL Chroma Video Levels 105 0.2m V R E F W H ITE 698 .4m V 351 .8m V BLAN K /B LA C K LE VEL SYN C LEVEL 51m V Figure 118. PAL RGB Video Levels REV. Pr F 74 ADV7192 Preliminary Technical Data ColorBar (NTSC) Wfm Wfm --> --> FCC Color Bar Field = 1 Line = 21 Luminance Level (IRE) 99.6 69.0 55.9 48.1 36.3 28.3 15.7 7.7 87.6 81.8 81.8 87.8 62.1 0.0 283.8 240.9 60.8 103.6 347.1 ------- 100.0 50.0 0.0 Chrominance Level (IRE) 0.0 62.1 100.0 50.0 0.0 Chrominance Phase (deg) ------- 167.3 400.0 200.0 0.0 Y R A IN AL M IC I L N E H A R T P EC A T D Gray Average Yellow 32 -> Cyan Green Magenta Red Blue Black 32 Figure 119. NTSC Color Bars Measurement ColourBar (PAL) W fm --> Colour Bar Line = 570 Luminance Level (mV ) 695.7 1000.0 500.0 464.8 366.6 305.7 217.3 156.4 6 1.2 - 0.4 669.1 623.5 624.7 669.6 475.2 0.0 166.7 283.3 240.4 6 0.4 103.2 346.7 ------- Yellow Cyan Green Magenta Red Blue 0 .0 Chrominance Level (mV ) 0.0 474.4 1000.0 500.0 0 .0 Chrominance Phase (deg) ------400.0 300.0 200.0 100.0 0 .0 Gray Average 32 -> Black 32 Figure 120. PAL Color Bars Measurement 75 REV. Pr F Preliminary Technical Data ADV7192 DG DP (NTSC) Wfm --> Field = 1 Line = 21 Differential Gain (%) 2.5 0. 00 0. 21 Wfm -->Wfm ---> min = 0.00 0.02 max = 0.07 0.27 Mod 5 Step p-p/max = 0.27 0. 27 0.08 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 Differential Phase (deg) 2.5 2.0 0. 00 0. 10 min = 0.00 0.12 ma x = 0.15 0.20 pk-pk = 0.13 0. 20 0.10 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 Y R A IN AL M IC I L N E H A R T P EC A T D 1st. Average 32 -> 2nd. 3rd. 4th. 5th. 6th. 32 Figure 121. NTSC Differential Gain and Phase Measurement DG DP (PAL) Wfm --> Mod 5 Step Line = 570 Differential Gain (%) 2.5 0.00 0.30 min = 0.00 0.15 max = 0.24 0.32 pk-pk = 0.32 0.32 0.26 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 Differential Phase (deg) 2.5 0.00 0.09 min = 0.00 max = 0.16 pk-pk = 0.16 0.13 0.16 0.12 0.14 3rd. 4th. 5th. 6th. 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 1st. Average 32 -> 2nd. 32 Figure 122. PAL Differential Gain and Phase Measurement REV. Pr F 76 ADV7192 Preliminary Technical Data Luminance Non Linearity (NTSC) Field = 2 Line = Wfm --> Mod 5 Step 77 Luminance Non Linearity (%) 99.9 99.9 pk-pk = 99.6 0.4 100.0 99.9 111.0 110.0 109.0 108.0 107.0 106.0 105.0 104.0 103.0 102.0 101.0 100.0 99.0 98.0 97.0 96.0 95.0 94.0 93.0 Y R A IN AL M IC I L N E H A R T P EC A T D 92.0 91.0 90.0 89.0 1st. Average 2nd. 32 -> 3rd. 4th. 5th. 32 Figure 123. NTSC Luminance Non-Linearity Luminance Non Linearity (PAL) Wfm --> 5 Step Line = 570 Luminance Non Linearity (%) 99.6 pk-pk = 0.8 99.9 100.0 99.6 99.9 2nd. 3rd. 4th. 5th. 109.0 108.0 107.0 106.0 105.0 104.0 103.0 102.0 101.0 100.0 99.0 98.0 97.0 96.0 95.0 94.0 93.0 92.0 91.0 1st. Average 32 -> 32 Figure 124. PAL Luminance Non-Linearity 77 REV. Pr F Preliminary Technical Data ADV7192 Chrominance Nonlinearity(NTSC) Nonlinearity Wfm Wfm --> --> Field = 2 Line = 217 Chrominance Amplitude Error (%) NTC-7 Combination Ref = 40 IRE Packet 0.5 0.0 -0.3 10.0 0.0 -10.0 Chrominance Phase Error (deg) Ref = 40 IRE Packet -0.0 5.0 0.0 0.0 0.0 -5.0 Chrominance Luminance Intermodulation (% of 714 mV) 0.0 0.1 0.1 0.2 0.1 0.0 -0.1 -0.2 Y R A IN AL M IC I L N E H A R T P EC A T D 20 IRE Average 32 -> 40 IRE 80 IRE 32 Figure 125. NTSC Chrominance Non-Linearity Chrominance Nonlinearity (PAL) Line = 5 72 Chrominance Amplitude Error (%) 0.6 Wfm --> Mod 3 Step Re f = 420 mV P acket 0.0 -0.4 10 .0 0.0 -10.0 Chrominance Phase Error (deg) -0.3 Ref = 420 mV Packet 0.0 -0.3 0.0 -5 .0 Chrominance Luminance Intermodulation ( % of 700 mV) 0.0 0.0 0.1 0.2 0.0 -0 .2 140 mV Average 32 -> 420 mV 32 Figure 126. PAL Chrominance Non-Linearity REV. Pr F 78 700 mV ADV7192 Preliminary Technical Data Chrominance AM PM (NTSC) Wfm W fm --> --> Red Field Field = 2 Line = 217 Band width 10kHz to 100kHz AM Noise -86.5 dB rms -95.0 -90.0 -85.0 -80.0 -75.0 PM Noise -70.0 -65.0 -60.0 dB rms -82.7 dB rms Y R A IN AL M IC I L N E H A R T P EC A T D -95.0 -90.0 -85.0 -80.0 -75.0 -70.0 -65.0 -60.0 dB rms (0 dB = 714 mV p-p with AGC for 100% Chrominance Level) Figure 127. NTSC Chrominance AMPM Chrominance AM PM (PAL) Wfm --> appropriate Line = 572 Band width 10kHz to 100kHz AM Noise -84.2 dB rms -95.0 -90.0 -85.0 -80.0 -75.0 PM Noise -70.0 -65.0 dB rms -80.5 dB rms -95.0 -90.0 -85.0 -80.0 -75.0 -70.0 -65.0 dB rms (0 dB = 700 mV p-p with AGC for 100% Chrominance Level) Average 32 -> 32 Figure 128. PAL Chrominance AMPM 79 REV. Pr F Preliminary Technical Data ADV7192 Noise Spectrum (NTSC) Wfm Wfm--> --> Pedestal Field = 2 Line = 223 Amplitude (0 dB = 714 mV p-p) Band width 10kHz to Noise Level = -79.7 dB rms Full 30 .0 20 .0 10 .0 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 -100.0 Y R A IN AL M IC I L N E H A R T P EC A T D 1.0 2.0 3.0 4.0 5.0 (MHz) Figure 129. NTSC Noise Spectrum - Pedestal Noise Spectrum (PAL) W fm --> Pedestal Line = 511 Amplitude (0 dB = 700 mV p-p) Band width 10kHz to Noise Level = -79.1 dB rms Full 0 .0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 -100.0 1.0 2.0 3.0 4.0 5.0 6.0 (MHz) Figure 130. PAL Noise Spectrum - Pedestal REV. Pr F 80 ADV7192 Preliminary Technical Data Noise Spectrum (NTSC) Field = 2 Line = 217 Amplitude (0 dB = 714 mV p-p) Band width 100kHz to Full 0.0 -5.0 -10.0 -15.0 -20.0 -25.0 -30.0 -35.0 -40.0 -45.0 -50.0 -55.0 -60.0 -65.0 -70.0 -75.0 -80.0 -85.0 -90.0 -95.0 -100.0 Wfm --> Noise Level = (Tilt Null) Ramp -63.1 dB rms Y R A IN AL M IC I L N E H A R T P EC A T D 1.0 2.0 3.0 4.0 5.0 (MHz) Figure 131. NTSC Noise Spectrum - Ramp Noise Spectrum (PAL) Line = 572 Amplitude (0 dB = 700 mV p-p) Band width 100kHz to Full 0.0 Wfm --> Noise Level = (Tilt Null) Ramp -62.3 dB rms -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 -100.0 1.0 2.0 4.0 3.0 6.0 5.0 (MHz) Figure 132. PAL Noise Spectrym - Ramp 81 REV. Pr F 505m V BL A C K BL U E RE D GRE EN C YA N YE L L OW W HIT E BLACK BL UE RED M A G E NT A G R EEN C YA N YEL L O W W H IT E M A G E NT A Preliminary Technical Data ADV7192 5 05 m V 4 23 m V 334m V Be ta C a m L EV E L 171m V 8 2m V BetaC a m LEV EL 0mV 0mV -8 2 m V 0mV 0mV -1 7 1 m V -3 3 4 m V -4 2 3m V -5 0 5m V Y R A IN AL M IC I L N E H A R T P EC A T D BL A C K BL U E 467mV 309m V 158m V RE D GR E EN C YA N W HIT E 467m V M A G E NT A Figure 134. NTSC 100% Color Bars No Pedestal V Levels BL A C K BL U E RE D M A G E NT A GRE EN C YA N W H IT E YE L L O W Figure 133. NTSC 100% Color Bars No Pedestal U Levels YE L L O W -5 0 5 m V 391mV Beta C a m L E V E L Be ta C a m L E V E L 76mV 0mV 0mV 0m V 0m V -7 6 m V -1 5 8 m V -3 0 9 m V -3 9 1 m V -4 6 7 m V -4 6 7 m V BL A C K BL U E RE D M A G E NT A G R E EN 350mV C YA N W HIT E YE L L O W Figure 136. NTSC 100% Color Bars with Pedestal V Levels BL A C K BL U E RE D M A G E NT A G REEN C YA N W HIT E YE L L O W Figure 135. NTSC 100% Color Bars with Pedestal U Levels 350m V 293m V 232mV S M PT E L E V E L 118mV 57m V 0m V 0m V S M PT E L E VE L 0mV -5 7 m V 0mV -1 1 8 m V -2 3 2 m V -2 9 3 m V -3 5 0 m V -3 5 0 m V Figure 138-. PAL 100% Color Bars V Levels Figure 137. PAL 100% Color Bars U Levels REV. Pr F 82 ADV7192 Preliminary Technical Data OUTPUT WAVEFORMS V o lts 0 .6 0 .4 0 .2 0 .0 -0 .2 Y R A IN AL M IC I L N E H A R T P EC A T D L60 8 0 .0 1 0 .0 N o is e re d u c tio n : 0 .0 0 d b A P L = 3 9 .1 % 2 0 .0 3 0 .0 4 0 .0 5 0 .0 S ou n d -In -S y n c O ff P r e c is io n M o d e O ff 6 2 5 lin e P A L 6 0 .0 M ic r o S e c o n d s N o F ilte ring Syn chro nou s S lo w c la m p to 0 .0 0 V a t 6 .7 2 u S S y n c = S o u rc e F r a m e s s e le c te d : 1 2 3 4 Figure 139.100/75% PAL Color Bars Volts 0.5 0.0 L575 0.0 10.0 20.0 30.0 APL needs Sync=Source! 625 line PAL 50.0 40.0 MicroSeconds Precision Mode Off No Filtering Synchronous Slow clamp to 0.00 V at 6.72 uS 60.0 Wait... Sound-In-Sync Off Sync = A Frames selected: Figure 140. 100/75% PAL Color Bars Luminance 83 70.0 No Bruch Signal 1 REV. Pr F Preliminary Technical Data ADV7192 V o lts 0 .5 0 .0 Y R A IN AL M IC I L N E H A R T P EC A T D -0 .5 L575 Figure 141 100/75% PAL Color Bars Chrominance V o lts IR E :F L T 1 0 0 .0 0 .5 5 0 .0 0 .0 0 .0 F1 -5 0 .0 0 .0 L76 1 0 .0 2 0 .0 3 0 .0 4 0 .0 6 0 .0 5 0 .0 M ic ro S e c o n d s A P L = 4 4 .6 % 5 2 5 lin e N T S C P r e c is io n M o d e O ff N o F ilt e rin g Synchrono us S l o w c la m p to 0 .0 0 V a t 6 .7 2 u S REV. Pr F Sync = A F r a m e s s e le c te d : Figure 142. 100/75% NTSC Color Bars 84 1 2 ADV7192 Preliminary Technical Data V o l ts IR E1:F T 0 0L.0 0 .6 0 .4 5 0 .0 0 .2 0 .0 0 .0 Y R A IN AL M IC I L N E H A R T P EC A T D -0 .2 F2 L238 1 0 .0 3 0 .0 2 0 .0 N o is e re d u c tio n : 1 5 .0 5 d b 4 0 .0 5 0 .0 6 0 .0 M ic r o S e c o n d s A P L = 4 4 .7 % P r e c is io n M o d e O ff 5 2 5 lin e N T S C N o F ilt e rin g Synchronou s S lo w c la m p to 0 .0 0 V a t 6 .7 2 u S S y n c = S o u rc e F r a m e s s e le c te d : 2 1 Figure 143. 100/75% NTSC Color Bars Luminance V o lts IR E :F L T 0 .4 5 0 .0 0 .2 0 .0 0 .0 -0 .2 -5 0 .0 -0 .4 F1 L76 0 .0 1 0 .0 2 0 .0 N o is e re d u c tio n : 1 5 .0 5 d b AP L needs S ync=Sou rce! 5 2 5 lin e N T S C 30.0 4 0 .0 5 0 .0 6 0 .0 M ic ro S e c o n d s P r e c is io n M o d e O ff N o F ilte r in g Synchronou s S l o w c la m p to 0 .0 0 V a t 6 .7 2 u S Syn c = B F r a m e s s e le c te d : Figure 144.100/75% NTSC Color Bars Chrominance 85 1 2 REV. Pr F Preliminary Technical Data ADV7192 APPENDIX 10 VECTOR PLOTS V APL = 39.6% SYST EM LIN E L6 08 AN G LE (D EG ) 0. 0 G A IN x 1.000 0.00 0dB 625 LIN E PAL BU R ST F R O M S O URC E D ISPLAY +V & -V cy R g M g 75% 100% YI b Y R A IN AL M IC I L N E H A R T P EC A T D U B yl G Cy m g r SO UN D IN SYN C O F F Figure 145. PAL Vector Plot R -Y A P L = 4 5 .1 % S Y S T E M L IN E L 7 6 F 1 A N G L E (D E G ) 0. 0 G A IN x 1 .0 0 0 0 .0 0 0 d B 5 2 5 L IN E N T S C BURST FRO M SOURCE cy I R M g Q YI b 100% B -Y 75% B G Cy -Q -I S E T U P 7 .5 % Figure 146. NTSC Vector Plot REV. Pr F 86 ADV7192 Preliminary Technical Data APPENDIX 11 PACKAGE OUTLINE DIMENSIONS O U T L IN E D IM E N S IO N S D im e n s io n s s ho w n in in c h e s a n d (m m ). 8 0 -L e a d L Q F P (S T -8 0) 0.64 0 ( 16 .2 5) 0.62 0 ( 15 .7 5) 0.06 3 (1 .60) 0.55 3 ( 14 .0 5) M AX 0.54 9 ( 13 .9 5) 0 . 48 6 (12 .35 ) T Y P 0.03 0 (0 .75) 0.02 0 (0 .50) 41 60 61 40 Y R A IN AL M IC I L N E H A R T P EC A T D SE AT IN G 0. 00 4 80 (0 .1 0) 0.62 0 ( 15 .7 5) 0.5 49 (1 3.9 5 (PIN S D O W N ) 0.64 0 (16 .2 5) TO P VIE W 0.55 3 ( 14 .0 5) 0.4 86 (1 2 .35 ) T Y P PLA N E 21 1 20 M AX 0.00 6 (0 .15) 0.00 2 (0 .05) 0.02 9 (0 .73) 0.01 4 (0 .35) 0.02 2 (0 .57) 0.01 0 (0 .25) 0.05 7 (1 .45) 0.05 3 (1 .35) 87 REV. Pr F

Preliminary Technical Data

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