Transcript
QorIQ™ P1021/P1012 Modular Development System (MDS) The P1021/P1012 Modular Development
P1021/P1012 Processor Board
System is designed for hardware and software
The P1021/P1012 processor board includes
on-board CPLD mapped Board
developers using the P1021/P1012 QorIQ™
a P1021 (dual-core) or P1012 (single-core)
Configuration Registers Set (BCSR)
processor family to accelerate development
processor running up to 800 MHz, along with
and testing, and improve time to market. The
circuitry to utilize the following:
P1021/P1012 MDS enables:
• 3x Gigabit Ethernet (GbE) and dual
• Silicon bring-up/verification • Software/application development and support
asynchronous receiver/transmitter (DUART) • PCI Express® interconnect • Serial RapidIO® technology
• Programmable reconfiguration through
• JTAG interface to host PC The P1021/P1012 MDS processor board’s onboard resources and debugging devices allow developers to upload and run code, set breakpoints, display memory and register and connect proprietary hardware. It can
• Performance benchmarking
• USB 2.0
• Processor evaluation
also be used as a demonstration tool for the
• Double data rate (DDR3 or optional
developer since the developer’s application
The P1021/P1012 MDS consists of multiple boards that provide a comprehensive
DDR2) memory • NAND flash memory
software may be programmed into the flash memory.
development system—a P1021/P1012
• SD/MMC card interface
processor board, a platform I/O board and
• Real-time clock (RTC)
several expansion modules which add support
• Dual I2C interface
for TDM and ATM.
point device. A 4-pin connector is provided
• Serial electrically erasable programmable
to connect to the PC power supply. The PC
read-only memory (EEPROM) • Control switches and LED indicators • Digital/analog regulated core voltage power supply (PS) • Fully controlled onboard power supply subsystem
The P1021/P1012 processor board can be inserted into a PC as a PCI Express end
power supply is not necessary. Other external connections are the same as in the standalone configuration.
P1021/P1012 MDS Processor Board Features
• Debug port access via JTAG/COP
• Supports both the P1021/P1012, running
• 16 MB flash on eSPI interface
up to 800 MHz at 0.95V core voltage in a 689-pin TeBGA 1 mm pitch package • DDR3 SODIMM @ 800 MHz, 512 MB with ECC support • PCI Express adapter to provide root complex mode • Dual 10/100 Mbps Ethernet ports for QUICC Engine™ module • Three additional 10/100/1000 Mbps
PMC Expansion Modules
Ethernet ports from the platform
• PQ-MDS-T1—Supports E1/T1, DS3, T3 I/F with an option of two POTS analog telephone lines • PQ-MDS-QOC3—Supports up to 4x 155 Mbps optical transceivers for evaluating the UTOPIA L2 /POS bus • PQ-MDS-PCI—Single-slot PMC to PCI agent connector to enable additional PCI-based boards for evaluation (actual for MDSs with legacy PCI I/F functionality) • PQ-MDS-PCI Express—Expansion module supporting multiple PCI Express agents
• Dual RS232 transceiver connected to DUART • 2x LYNXx1 modules provide dual Serial RapidIO interface • 4x LYNX connected to PCI Express adapter through PCI Express mux to support host or agent modes: 4x PCI Express edge connector can be plugged in a PC PCI Express adapter slot connector for root complex mode accepts standard (off-the-shelf) PCI Express, up to x4 cards • Local bus I/F Address latch, data (8-bit width) and control buffers to support slow devices on the PMC boards 8-bit 32 MB NAND flash in a socket CPLD BCSR
P1021/P1012 Processor Board Characteristics • Power requirements
Specifications 5V @ 8A external DC power supply
• P1021/P1012 processor
Internal clock runs up to 800 MHz @ 0.95V
• Memory
512 MB (with ECC support) SODIMM DDR3 at up to 800 MHz data rate
• Local bus: flash memory
8-bit 32 MB NAND flash in a socket
• Dimensions
Length 312 mm, width 111 mm, height 50 mm max
connector • Two I2C buses Bus for 256 KB boot EEPROM, 1 KB board related info EEPROM, RTC, SODIMM SPD EEPROM, core voltage POT and UEM configuration • Two operation modes Stand-alone mode PCI Express end point mode—plugged into a PC as standard PC card • QUICC Engine functions supported All QUICC Engine signals are available on PMC0 and PMC1 4x TDM port with the PQ-MDS-T1 card on the MDS (on PMC0 only ) 1x DS3 port with the PQ-MDS-T1 card on the MDS (on PMC0 only) 1x UTOPIA/POS Level 2, 8-bit, multi-PHY multi device with PQ-MDS-QOC3 cards on the MDS (on PMC1 only) 2x 10/100 Mbps RMII Ethernet ports • 3x 1000 Mbps RGMII/RTBI (2x SGMII) Ethernet ports on the PB • RoHS compliant • FCC compliant • CE compliant
CodeWarrior® Development Support
About the QorIQ P1021/P1012 Processor
P1021 processors provide single- and dual-
supporting DUART, local bus, DDR, flash,
Freescale QorIQ communications platforms
performance range, along with advanced
TSEC, I2C, PCI Express (root complex
are the next-generation evolution of our
security and a rich set of interfaces.
and end point) and SPI
leading PowerQUICC® communications
®
• Development Tools Linux OS 2.6,
Typical Applications for the QorIQ P1021/P1012 Processors • Access Gateway (IPv4 forwarding/security) • SMB/SME applications • Multi-service routers • Industrial networking
core solutions for the 533 MHz to 800 MHz
processors. Built using high-performance
The P1012 and P1021 processors are
cores built on Power Architecture® technology,
perfectly suited for multi-service gateways,
QorIQ platforms enable a new era of
Ethernet switch controllers, wireless LAN
networking innovation where the reliability,
access points and high-performance general
security and quality of service for every
purpose control processor applications with
connection matters.
tight thermal constraints.
The QorIQ P1 platform series, which includes
The QorIQ P1012 and P1021 processors are
the P1021 and P1012 communications
pin-compatible with the QorIQ P2 platform
processors, offers the value of extensive
products, offering a four-chip range of cost-
integration and extreme power intelligence
effective solutions. Scaling from a single core
for a wide variety of applications in the
at 533 MHz (P1011) to a dual core at 1.2 GHz
networking, telecom, defense and industrial
per core (P2020), the two QorIQ platforms
markets. Based on 45 nm technology for
deliver an impressive 4.5x aggregate
low-power implementation, the P1012 and
frequency range.
P1021/P1012 MDS Block Diagram P1021/P1012 MDS Processor Board P1021
e500 Core 32 KB 32 KB L1 I-Cache L1 D-Cache
256 KB L2 Cache
e500 Core 32 KB 32 KB L1 I-Cache L1 D-Cache
Coherency Module System Bus DDR2/3 Module or SODIMM Connector
Gigabit Ethernet 1
Ethernet PHY
Gigabit Ethernet 3
Ethernet PHY
Local Bus Controller/ QUICC Engine™ (QE)
USB
USB PHY
GPIO/QE
I2C Controller
I2C EEPROM
DMA2/QE
eSPI
DDR 2/3 Controller RS-232
I2C of Processor TDM
MUX/DEMUX NAND Flash, CPLD
TDM SER UTOPIA
Ethernet PHY
UART Controller 1 USB Connector
MUX/DEMUX
Ethernet PHY I2C
UART Controller 0
eSPI/eSDHC
MUX/DEMUX
DMA1/QE
OSC
IEEE® 1588/IEEE 1588 (QE)
DAC
SPI Flash
SD/MMC Card Socket
eSDHC SERDES
Gigabit Ethernet 2
MUX/DEMUX
Gigabit Ethernet 3
High-Speed Diff MUX
PCI Express® Edge Connector
4 x High-Speed Connectors
Freescale Technology
The devices in these two platforms are
further integrate your design with the same
stashing memory. The integrated security
software compatible, sharing the e500
applications running on each core or serialize
engine supports the cryptographic algorithms
Power Architecture core and peripherals,
your application using the cores for different
commonly used in IPsec, SSL, 3GPP and
as well as being fully software compatible
processing tasks.
other networking and wireless security protocols. The memory controller offers
with the existing PowerQUICC processors. This enables you to create a product with
The P1012 and P1021 processors have an
future-proofing against memory technology
multiple performance points from a single
advanced set of features for ease of use.
migration with support for both DDR2 and
board design. The QorIQ P1020 dual-
The 256 KB L2 cache offers incremental
DDR3. It also supports error correction codes,
core processor supports symmetric and
configuration to partition the cache between
a baseline requirement for any high-reliability
asymmetric processing, enabling you to
the two cores or to configure it as SRAM or
system.
Learn More:
Freescale and the Freescale logo are trademarks or registered trademarks of Freescale Semiconductor, Inc. in the U.S. and other countries. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. © Freescale Semiconductor, Inc. 2009. Document Number: P1021MDSFS REV 0
For current information about Freescale products and documentation, please visit www.freescale.com/QorIQ.
