Transcript
QCP-10G3B4QDR
QSFP+ 40GBASE-LR4 Fiber Transceiver
Preliminary
Features RoHS-6 compliant Hot pluggable QSFP+ form factor 40Gbps aggregate rate 4x10Gb/s CWDM transmitter Compliant to industrial standard SFF-8436 QSFP+ standard Power consumption <3.5W Duplex LC receptacle. I2C standard management interface
Description
Application
The QCP-10G3B4QDR is a 40Gbps, hot pluggable fiber transceivers for 40G Ethernet data transmission. The module support 40Gbps links over single mode fiber for 10km. The module consist 4x10Gbps CWDM LDs and multiplex 4 CWDM signals on a 40Gbps optical transmission, and de-multiplex 40G receiver signals to 4 CWDM signals. 4 receiving data lanes and each lane at data rate up to 10.3125Gbps.
40G Ethernet Proprietary high speed, high density data transmission. Switch and router high speed backplane interconnect High performance computing, server and data storage.
QCP-10G3B4QDR is designed to meet the requirements of high speed, high density and low power consumption for applications in today’s data center. QCP-10G3B4QDR compliant with QSFP+ MSA and IEEE 802.3ba 40Gbase-LR4.
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Revision: Draft 05/20/2013
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QCP-10G3B4QDR 1. 1. Absolute Maximum Ratings Parameter Storage Temperature Storage Ambient Humidity Power Supply Voltage
Symbol Ts HA VCC
Min. -40 5 0
Typ.
Max. 75 85 3.6
Unit ºC % V
Min. 0 5 3.13
Typ.
Max. +70 85 3.47 3.5 10.3125+ 100ppm 10.3125+ 100ppm 10
Note
2. Recommended Operating Conditions Parameter Operating Case Temperature Ambient Humidity Power Supply Voltage Total Power dissipation
Symbol TC HA VCC
3.3
10.312510.3125 100ppm 10.312510.3125 100ppm
Data rate for transmitter per lane Data rate for receiver per lane Transmission Distance
Unit ºC % V W
Note Non-condensing
Gbd Gbd km
3. Specification of Transmitter Parameter Total Average Launched Power Optical Extinction Ratio Lane Center Wavelength(Range) Side Mode Suppression Ratio Transmitter OFF Output Power, each Lane Tx OMA per Lane Average Launched Power,per Lane Transmitter Reflectance Optical Return Loss Tolerance Relative Intensity Noise Output Eye Mask X1,X2,X3,Y1,Y2,Y3
Symbol PO ER λC SMSR
Min. 3.5 1264.5 1284.5 1304.5 1324.5 30
POff TxOMA
-4.0 -7
RIN20OMA
Typ.
1271 1291 1311 1331
Max. +8.3 1277.5 1297.5 1317.5 1337.5
Unit dBm dB
Note Note (1)
nm dB
-30
dBm
3.5 2.3 -12 20 -128
dBm dBm dB dB dB/Hz
Compliant with IEEE 802.3ba (0.25,0.4,0.45,0.25,0.28,0.4)
Note (2)
Note (1). Total launch power consists 4 Channels operating at 10.3125Gbps. Note (2). Transmitter eye mask definition
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QCP-10G3B4QDR
4. Specification of Receiver Parameter Lane Center Wavelength(Range)
Average Receiver Power per Lane Damage Threshold, per lane Receiver Power OMA, per Lane Receiver Sensitivity OMA, per lane Stressed Receiver OMA, per lane Return Loss Stressed Eye jitter, per lane
Symbol λC
Min. 1264.5 1284.5 1304.5 1324.5
PIN
-13.7
Pth RxOMA S SRS
+3.3
Typ. 1271 1291 1311 1331
Max. 1277.5 1297.5 1317.5 1337.5
Unit
Note
+2.3
dBm
Note(1)
3.5 -11.5 -9.6 -26 0.3
dBm dBm dBm dBm dB UI
Note(2)
nm
Note (1).The min. power is informative and not the principal indicator of signal strength. Note (2). Tested with PRBS 231-1, BER 1X10-12
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QCP-10G3B4QDR 5. Electrical Interface Characteristics Parameter Transmitter Total Supply Current Differential line input Impedance Differential Data Input Swing Receiver Total Supply Current Differential Data Output Swing Low speed signal Input Control Voltage LPMode, Reset and modseIL Input Control Voltage LPMode, Reset and modseIL Output Voltage ModPrsL and IntL Output Voltage ModPrsL and IntL
Symbol
Min.
Typ.
Max.
Unit
Note
ICC RIN VDT
100
A 110 800
mA Ohm mVp-p
Note (1)
90 200
ICC VDR
200
B 800
mA mVp-p
Note (1) Note (2)
VIL
0
0.8
V
VIH
2
Vcc+0.3
V
VOL
0
0.4
V
VOH
2
Vcc+0.3
V
Note (2)
Note (1). A (TX)+ B (RX) = 1.1A (Not include termination circuit) Note (2). CML Interface, AC coupled to 100ohm differential Load.
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QCP-10G3B4QDR 6. Pin Description QSFP Module Pad Layout (Top View)
Host PCB Layout (Top View)
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QCP-10G3B4QDR Module Electrical Pin Function Definition Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Logic
Symbol GND CML-I Tx2n CML-I Tx2p GND CML-I Tx4n CML-I Tx4p GND LVTTL-I ModSelL LVTTL-I ResetL Vcc Rx LVCMOS-I/O SCL LVCMOS-I/O SDA GND CML-O Rx3p CML-O Rx3n GND CML-O Rx1p CML-O Rx1n GND GND CML-O Rx2n CML-O Rx2p GND CML-O Rx4n CML-O Rx4p GND LVTTL-O ModPrsL LVTTL-O IntL Vcc Tx Vcc1 LVTTL-I LPMode GND CML-I Tx3p CML-I Tx3n GND CML-I Tx1p CML-I Tx1n GND
Name/Description Ground Transmitter Inverted Data Input Transmitter Non-inverted Data Input Ground Transmitter Inverted Data Input Transmitter Non-inverted Data Input Ground Module Select Module Reset +3.3V Power Supply Receiver 2-Wire Serial Interface Clock 2-Wire Serial Interface Data Ground Receiver Non-Inverted Data Output Receiver Inverted Data Output Ground Receiver Non-Inverted Data Output Receiver Inverted Data Output Ground Ground Receiver Inverted Data Output Receiver Non-Inverted Data Output Ground Receiver Inverted Data Output Receiver Non-Inverted Data Output Ground Module Present Interrupt +3.3V Power Supply Transmitter +3.3V Power Supply Low Power Mode Ground Transmitter Non-inverted Data Input Transmitter Inverted Data Input Ground Transmitter Non-inverted Data Input Transmitter Inverted Data Input Ground
Note [1]
[1]
[1]
[2] [2] [1]
[1]
[1] [1]
[1]
[1] [2] [2]
[1]
[1]
[1]
Notes: 1. Module ground pins GND are isolated from the module case and chassis ground within the module. 2. Shall be pulled up with 4.7K-10Kohms to a voltage between 3.15V and 3.45V on the host board. 3. Please refer to SFF-8436 Fig. 3a for more information on interface circuit and power filtering network. 6 Revision: Draft 05/20/2013 DELTA ELECTRONICS, INC.
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QCP-10G3B4QDR 7. Low Speed Electrical Hardware Pins In addition to 2-wire serial interface, QCP-10G3B4QDR module has the following low speed pins for control and status: ModPrsL, IntL, LPMode, ModSelL, ResetL 7.1 ModPrsL ModPrsL is an output pin. When “low”, indicates the module is present. The ModPrsL is asserted “Low” when inserted and deasserted “High” when the module is physically absent from the host connector. 7.2 IntL IntL is an output pin. When “Low”, it indicates a possible module operational fault or a status critical to the host system. The source of the interrupt could be identified by using the 2-wire serial interface. 7.3 LPMode LPMode is a control pin. When “High”, it could be used to set the module in low power mode (<1.5W). This pin, along with Power_overide bit and Power_set bit in management interface could be used to avoid system power crash. QCP-10G3A4BDR, however consumes less than 1.5W. Therefore this pin takes no effect. 7.4 ModSelL ModSelL is an input signal. When held low by the host, the module responds to two-wire serial communication commands. The ModSelL signal allows multiple QSFP modules to be on a single two-wire interface bus. When the ModSelL signal is “High”, the module will not respond to or acknowledge any two-wire interface communication from the host. The ModSelL signal input pin is biased to a “High” state in the module. In order to avoid conflicts, the host system must not attempt two-wire interface communications within the ModSelL deassert time after any QSFP modules are de-selected. Similarly, the host must wait for the period of the ModSelL assert time before communicating with the newly selected module. The assert and deassert periods of different modules may overlap as long as the above timing requirements are met. 7.5 ResetL The ResetL signal is pulled to Vcc in the QSFP+ module. A logic low level on the ResetL signal for longer than the minimum pulse length (t_Reset_init) initiates a complete module reset, returning all user module settings to their default state. Module Reset Assert Time (t_init) starts on the rising edge after the low level on the ResetL pin is released. During the execution of a reset (t_init) the host will disregard all status bits until the module indicates a completion of the reset interrupt. The module indicates this by posting an IntL signal with the Data_Not_Ready bit negated. Note that on power-up (including hot insertion) the module will post this completion of reset interrupt without requiring a reset. 7 DELTA ELECTRONICS, INC.
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QCP-10G3B4QDR 8. Outline Dimension
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QCP-10G3B4QDR Appendix A. Document Revision Version No. Draft
Date 2013-05-20
Description Preliminary datasheet
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