Transcript
Quad 8-Bit, 65 MSPS, Serial LVDS 3 V A/D Converter AD9289 FEATURES
FUNCTIONAL BLOCK DIAGRAM
Four ADCs in one package Serial LVDS digital output data rates to 520 Mbps (ANSI-644) Data and frame clock outputs SNR = 48 dBc (to Nyquist) Excellent linearity DNL = ±0.2 LSB (typical) INL = ±0.25 LSB (typical) 300 MHz full power analog bandwidth Power dissipation = 112 mW/channel at 65 MSPS 1 Vp-p to 2 Vp-p input voltage range 3.0 V supply operation Power-down mode Digital test pattern enable for timing alignments
AVDD
DFS
PDWN
DTP
DRVDD
DRGND
AD9289 VIN+A VIN–A
SHA
PIPELINE ADC
SHA
PIPELINE ADC
SHA
PIPELINE ADC
SHA
PIPELINE ADC
VIN+B VIN–B VIN+C VIN–C VIN+D VIN–D
8
8
8
8
SERIAL LVDS
D1+A
SERIAL LVDS
D1+B
SERIAL LVDS
D1+C
SERIAL LVDS
D1+D D1–D
FCO– REF SELECT
DATA RATE MULTIPLIER
REFT_B
DCO+ DCO–
REFB_B SHARED_REF
AGND
LVDSBIAS
CML
CLK+
CLK–
03682-001
Tape drives Medical imaging
REFB_A
D1–C
FCO+
0.5V
APPLICATIONS
D1–B
LOCK
VREF SENSE REFT_A
D1–A
Figure 1.
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9289 is a quad 8-bit, 65 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. The product operates at up to a 65 MSPS conversion rate and is optimized for outstanding dynamic performance where a small package size is critical.
1.
Four ADCs are contained in a small, space-saving package.
2.
A data clock out (DCO) is provided, which operates up to 260 MHz and supports double-data rate operation (DDR).
3.
The outputs of each ADC are serialized LVDS with data rates up to 520 Mbps (8 bits × 65 MSPS).
4.
The AD9289 operates from a single 3.0 V power supply.
5.
The internal clock duty cycle stabilizer maintains performance over a wide range of input clock duty cycles.
The ADC requires a single, 3 V power supply and an LVDScompatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) trigger for signaling a new output byte are provided. Power-down is supported. The ADC typically consumes 7 mW when enabled. Fabricated on an advanced CMOS process, the AD9289 is available in a 64-ball mini-BGA package (64-BGA). It is specified over the industrial temperature range of –40°C to +85°C.
Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
AD9289 TABLE OF CONTENTS Specifications..................................................................................... 3
Typical Performance Characteristics ..............................................9
AC Specifications.......................................................................... 4
Terminology .................................................................................... 12
Digital Specifications ................................................................... 4
Theory of Operation ...................................................................... 14
Switching Specifications .............................................................. 5
Analog Input and Reference Overview ................................... 14
Timing Diagrams.......................................................................... 5
Clock Input and Considerations .............................................. 15
Absolute Maximum Ratings............................................................ 6
Evaluation Board ............................................................................ 20
Explanation of Test Levels........................................................... 6
Outline Dimensions ....................................................................... 30
ESD Caution.................................................................................. 6
Ordering Guide .......................................................................... 30
Pin Configuration and Function Descriptions............................. 7 Equivalent Circuits ........................................................................... 8
REVISION HISTORY 10/04—Initial Version: Revision 0
Rev. 0 | Page 2 of 32
AD9289 SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error 1 Gain Matching1 Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference Voltage (VREF = 1 V) REFERENCE Output Voltage Error (VREF = 1 V) Load Regulation @ 1.0 mA (VREF = 1 V) Output Voltage Error (VREF = 0.5 V) Load Regulation @ 0.5 mA (VREF = 0.5 V) Input Resistance COMMON MODE Common-Mode Level Output ANALOG INPUTS Differential Input Voltage Range (VREF = 1 V) Differential Input Voltage Range (VREF = 0.5 V) Common-Mode Voltage Input Capacitance Analog Bandwidth, Full Power POWER SUPPLY AVDD DRVDD IAVDD DRVDD Power Dissipation2 Power-Down Dissipation CROSSTALK 1
2
2
1 2
Temperature
Test Level
Min 8
Full Full Full Full Full 25°C Full 25°C Full
VI VI VI VI VI V VI V VI
Guaranteed ±5 ±12 ±0.5 ±0.2 ±0.2 ±0.2 ±0.25 ±0.25
Full Full Full
V V V
±16 ±40 ±10
Full Full Full Full Full
VI V VI V V
±10 0.7 ±8 0.2 7
±35 ±26
mV mV mV mV kΩ
Full
VI
±1.5
±50
mV
Full Full Full Full Full
VI VI V V V
2 1 1.5 5 300
Full Full Full Full Full Full Full
IV IV VI VI VI VI V
2.7 2.7
Typ
3.0 3.0 150 33 550 7 –75
Max
Unit Bits
±57 ±68 ±2.5 ±0.9
mV mV % FS % FS LSB LSB LSB LSB
±0.6 ±0.6
ppm/°C ppm/°C ppm/°C
V p-p V p-p V pF MHz 3.3 3.3 168 40 625 12
Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.0 V external reference and a 2 V p-p differential analog input). Power dissipation measured with rated encode and 2.4 MHz analog input at –0.5 dBFS.
Rev. 0 | Page 3 of 32
V V mA mA mW mW dB
AD9289 AC SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted. Table 2. Parameter SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz fIN = 10.3 MHz fIN = 35 MHz fIN = 2.4 MHz fIN = 10.3 MHz fIN = 35 MHz fIN = 2.4 MHz fIN = 10.3 MHz fIN = 35 MHz fIN = 2.4 MHz fIN = 10.3 MHz fIN = 35 MHz fIN = 2.4 MHz fIN = 10.3 MHz fIN = 35 MHz fIN = 2.4 MHz fIN = 10.3 MHz fIN = 35 MHz fIN1 = 15 MHz fIN2 = 16 MHz
SIGNAL-TO-NOISE RATIO (SINAD)
EFFECTIVE NUMBER OF BITS (ENOB)
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
WORST HARMONIC (Second or Third)
WORST OTHER (Excluding Second or Third)
TWO TONE INTERMOD DISTORTION (IMD) AIN1 and AIN2 = –7.0 dBFS
Temperature Full 25°C Full Full 25°C Full Full 25°C Full Full 25°C Full Full 25°C Full Full 25°C Full 25°C
Test Level IV V VI IV V VI IV V VI IV V VI IV V VI IV V VI V
Min 47.7 46.7 47.6 46.2 7.6 7.4 61.0 54.0
Typ 49.0 48.5 48.0 48.9 48.4 47.5 7.8 7.7 7.6 70.0 68.0 65.0 –75.0 –70.0 –65.0 –70.0 –68.0 –65.0 –72.0
Max
–61.0 –54.0 –61.0 –57.5
Unit dB dB dB dB dB dB Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
DIGITAL SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted. Table 3. Parameter CLOCK INPUTS1 (CLK+, CLK–) Logic Compliance Differential Input Voltage High Level Input Current Low Level Input Current Input Common-Mode Voltage Input Resistance Input Capacitance LOGIC INPUTS (DFS, PDWN, SHARED_REF) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUTS (LOCK) Logic 1 Voltage Logic 0 Voltage DIGITAL OUTPUTS (D1+, D1–) Logic Compliance Differential Output Voltage Output Offset Voltage Output Coding
1
Temperature
Test Level
Full Full Full Full 25°C 25°C
IV VI VI IV V V
Full Full 25°C 25°C
IV IV V V
2.0
Full Full
IV IV
2.45
Full Full Full
VI VI VI
Clock inputs are LVDS-compatible. They require external dc bias and cannot be ac-coupled. Rev. 0 | Page 4 of 32
Min LVDS 250
1.125
Typ
Max
Unit
350 30 30 1.25 100 2
450 75 75 1.375
mV p-p µA µA V kΩ pF
0.8 30 4
0.05 LVDS 260 1.15
350 440 1.25 1.35 Twos complement or binary
V V kΩ pF V V
mV V
AD9289 SWITCHING SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted. Table 4. Parameter CLOCK Maximum Clock Rate Minimum Clock Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) OUTPUT PARAMETERS Valid Time (tV)1 Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) FCO Propagation Delay (tFCO) DCO Propagation Delay (tCPD) DCO-to-Data Delay (tDATA) DCO-to-FCO Delay (tFRAME) Data-to-Data Skew (tDATA-MAX – tDATA-MIN) PLL Lock Time (tLOCK) Wake-Up Time Pipeline Latency APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter) OUT-OF-RANGE RECOVERY TIME
1
Temp
Test Level
Min
Full Full Full Full
VI IV VI VI
65
Full Full Full Full Full Full Full Full Full 25°C 25°C Full
IV VI V V V V VI VI IV V V IV
25°C 25°C 25°C
V V V
Typ
Max
12 6.9 6.9 0.5 6.9
7.7 7.7
9.0 250 250 9.0 9.0 ±100 ±100 ±100 1.8 7 6
<1.5 11.6
±550 ±500 ±250
4.5 <1 1
TIMING DIAGRAMS N-1 AIN N
tEH
CLK–
tEL
CLK+
tCPD DCO– STATIC
STATIC DCO+
tFRAME
tFCO FCO– STATIC
STATIC
FCO+
tPD D1– STATIC
INVALID
D1+
tDATA MSB D6 D5 D4 D3 D2 D1 LSB MSB (N-7) (N-7) (N-7) (N-7) (N-7) (N-7) (N-7) (N-7) (N-6)
STATIC
03682-003
LOCK
tV
Figure 2. Timing Diagram
Rev. 0 | Page 5 of 32
MSPS MSPS ns ns CLK cycles ns ps ps ns ns ps ps ps µs ms CLK cycles ns ps rms CLK cycles
Actual valid time is dependent on the moment when LOCK goes low.
tA
Unit
AD9289 ABSOLUTE MAXIMUM RATINGS Table 5.
Parameter ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs (D1+, D1–, DCO+, DCO–, FCO+, FCO–)
LOCK, LVDSBIAS CLK+, CLK– VIN+, VIN– PDWN, DFS, DTP REFT, REFB, SHARED_REF, CML VREF, SENSE ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) Thermal Impedance1
EXPLANATION OF TEST LEVELS With Respect To
Min
Max
Unit
AGND DRGND DRGND DRVDD DRGND
–0.3 –0.3 –0.3 –3.9 –0.3
+3.9 +3.9 +0.3 +3.9
V V V V V
DRGND AGND AGND AGND AGND
–0.3 –0.3 –0.3 –0.3 –0.3
DRVDD
AVDD AVDD AVDD AVDD
V V V V V
AGND
–0.3
AVDD
V
–40
+85
°C
150
°C
300
°C
+150
°C
40
°C/W
I. 100% production tested.
DRVDD
II. 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only.
–65
VI. 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1
θJA for a 4-layer PCB with solid ground plane in still air.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 6 of 32
AD9289 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8
03682-005
A B C D E F G H
Figure 3. BGA Top View (Looking Through)
Table 6. Pin Function Descriptions Pin No. A1 B1 C1
Mnemonic D1–A D1+A FCO+
D1 E1 F1 G1 H1 A2 B2 C2
DNC AGND VIN–A VIN+A LVDSBIAS1 DNC DNC FCO–
D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4
DNC AGND AVDD AGND VIN+B D1–B D1+B DRVDD DRGND AGND CML SHARED_REF3 VIN–B DNC DNC DCO+
LOCK
Description ADC A Complement Digital Output ADC A True Digital Output Frame Clock Output (MSB Indicator) True Output Do Not Connect Analog Ground ADC A Analog Input—Complement ADC A Analog Input—True LVDS Output Bias Pin Do Not Connect Do Not Connect Frame Clock Output (MSB Indicator) Complement Output Do Not Connect Analog Ground Analog Supply Analog Ground ADC B Analog Input—True ADC B Complement Digital Output ADC B True Digital Output Digital Supply Digital Ground Analog Ground Common Mode Level Output ( = AVDD/2) Shared Reference Control Bit ADC B Analog Input—Complement Do Not Connect Do Not Connect Data Clock Output—True PLL Lock Output
E4 F4 G4 H4 A5 B5 C5
AVDD REFT_A REFB_A SENSE D1–C D1+C DCO–
Analog Supply Reference Buffer Decoupling (Positive) Reference Buffer Decoupling (Negative) Reference Mode Selection ADC C Complement Digital Output ADC C True Digital Output Data Clock Output—Complement
Pin No. D5 E5 F5 G5 H5 A6 B6 C6 D6 E6 F6 G6 H6 A7 B7 C7 D7 E7 F7 G7 H7 A8 B8 C8 D8 E8 F8 G8 H8
1
Mnemonic AGND AGND REFT_B REFB_B VREF DNC DNC DRVDD DRGND AVDD AGND AGND VIN–C D1–D D1+D DFS2 AGND AGND AVDD AGND VIN+C DNC DNC CLK+ CLK– PDWN3 VIN–D VIN+D DTP3, 4
Description Analog Ground Analog Ground Reference Buffer Decoupling (Positive) Reference Buffer Decoupling (Negative) Voltage Reference Input/Output Do Not Connect Do Not Connect Digital Supply Digital Ground Analog Supply Analog Ground Analog Ground ADC C Analog Input—Complement ADC D Complement Digital Output ADC D True Digital Output Data Format Select Analog Ground Analog Ground Analog Supply Analog Ground ADC C Analog Input—True Do Not Connect Do Not Connect Input Clock—True Input Clock—Complement Power Down Selection ADC D Analog Input—Complement ADC D Analog Input—True Digital Test Pattern
LVDSBIAS use a 3.9 kΩ resistor-to-analog ground to set the LVDS output differential swing of 350 mV p-p. DFS has an internal on-chip pull-down resistor and defaults to offset binary output coding if untied. If twos complement output coding is desired then tie this pin to AVDD. 3 To enable, tie this pin to AVDD. To disable, tie this pin to AGND. 4 DTP has an internal on-chip pull-down resistor. 2
Rev. 0 | Page 7 of 32
AD9289 EQUIVALENT CIRCUITS AVDD
DRVDD
VIN+, VIN–
V
V
AGND
D1+ V
V
DRGND
Figure 4. Equivalent Analog Input Circuit
Figure 7. Equivalent Digital Output Circuit
DRVDD
AVDD
LOCK
CLK+, CLK–
03682-007
AGND
DRGND
Figure 8. Equivalent LOCK Output Circuit
Figure 5. Equivalent Clock Input Circuit
DRVDD
03682-008
375Ω
DRGND
03682-010
25Ω
375Ω
DFS, PDWN, SHARED_REF
03682-009
03682-006
D1–
Figure 6. Equivalent Digital Input Circuit
Rev. 0 | Page 8 of 32
AD9289 TYPICAL PERFORMANCE CHARACTERISTICS 0
75 AIN = –0.5dBFS SNR = 49.08dB ENOB = 7.86 BITS SFDR = 70.55dBc
1V p-p, SFDR (dBc) 65
–40 60
–60 55
03682-014
–100 0.0
2V p-p, SNR (dB)
50
4.1
8.1
12.2 16.3 20.3 FREQUENCY (MHz)
24.4
28.4
03682-017
–80
1V p-p, SNR (dB) 45 10
32.5
Figure 9. Single-Tone 32k FFT With fIN = 2.4 MHz, fSAMPLE = 65 MSPS
20
30
40 50 ENCODE (MSPS)
60
70
Figure 12. SNR/SFDR vs. fSAMPLE, fIN = 2.4 MHz
0
75 AIN = –0.5dBFS SNR = 48.93dB ENOB = 7.83 BITS SFDR = 71.45dBc
–20
70
2V p-p, SFDR (dBc) 1V p-p, SFDR (dBc)
AIN = –0.5dBFS
65 –40 dB
60
–60 55 –80 03682-015
–100 0.0
4.1
8.1
12.2 16.3 20.3 FREQUENCY (MHz)
24.4
28.4
1V p-p, SNR (dB) 45 10
32.5
Figure 10. Single-Tone 32k FFT With fIN = 10.3 MHz, fSAMPLE = 65 MSPS
20
30
40 50 ENCODE (MSPS)
60
70
Figure 13. SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz
0
–20
2V p-p, SNR (dB)
50
03682-018
AMPLITUDE (dBFS)
AIN = –0.5dBFS
70
dB
AMPLITUDE (dBFS)
–20
2V p-p, SFDR (dBc)
75 2V p-p, SFDR (dBc)
AIN = –0.5dBFS SNR = 48.8dB ENOB = 7.8 BITS SFDR = 68.5dBc
AIN = –0.5dBFS
70
dB
–40 60
–60 55
–100 0.0
2V p-p, SNR (dB)
50
4.1
8.1
12.2 16.3 20.3 FREQUENCY (MHz)
24.4
28.4
03682-019
–80 03682-016
AMPLITUDE (dBFS)
1V p-p, SFDR (dBc) 65
1V p-p, SNR (dB) 45 10
32.5
Figure 11. Single-Tone 32k FFT With fIN = 35 MHz, fSAMPLE = 65 MSP
20
30
40 50 ENCODE (MSPS)
60
Figure 14. SNR/SFDR vs. fSAMPLE, fIN = 35 MHz
Rev. 0 | Page 9 of 32
70
AD9289 75
75
60
70dB REFERENCE LINE
70 SFDR (dBc)
50
2V p-p, SNR (dB)
1V p-p, SFDR (dBc)
65
dB
dB
40
30
60
1V p-p, SNR (dB) 55
20
–35
03682-020
0 –40
50
2V p-p, SFDR (dBc)
–30 –25 –20 –15 –10 ANALOG INPUT LEVEL (dBFS)
–5
SNR (dB) 45 0.1
0
Figure 15. SNR/SFDR vs. Analog Input Level, fSAMPLE = 65 MSPS, fIN = 2.4 MHz
1
10 FREQUENCY (MHz)
100
Figure 18. SNR/SFDR vs. fIN, fSAMPLE = 65 MHz
0
75
60
AIN1 AND AIN2 = –7.0dBFS SFDR = 69.9dBc IMD2 = 74.9dBc IMD3 = 72.9dBc
70dB REFERENCE LINE –20 2V p-p, SNR (dB)
1V p-p, SFDR (dBc)
AMPLITUDE (dBFS)
50
03682-023
10
dB
40
30
1V p-p, SNR (dB)
–40
–60
20
–35
03682-021
0 –40
2V p-p, SFDR (dBc)
–30 –25 –20 –15 –10 ANALOG INPUT LEVEL (dBFS)
–5
–100 0.0
0
Figure 16. SNR/SFDR vs. Analog Input Level, fSAMPLE = 65 MSPS, fIN = 10.3 MHz
4.1
8.1
12.2 16.3 20.3 FREQUENCY (MHz)
24.4
28.4
32.5
Figure 19. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz, fSAMPLE = 65 MSPS
75
80
60
50
03682-024
–80 10
70
70dB REFERENCE LINE 1V p-p, SFDR (dBc)
60
2V p-p, SNR (dB)
70dB REFERENCE LINE 50 dB
dB
40
30
40
1V p-p, SNR (dB)
SFDR (dBc)
30 20
20 2V p-p, SFDR (dBc)
–35
–30 –25 –20 –15 –10 ANALOG INPUT LEVEL (dBFS)
–5
Figure 17. SNR/SFDR vs. Analog Input Level, fSAMPLE = 65 MSPS, fIN = 35 MHz
0 –40
0
03682-025
0 –40
10
03682-022
10
–35
–30 –25 –20 –15 –10 ANALOG INPUT LEVEL (dBFS)
–5
0
Figure 20. Two-Tone SFDR vs. Analog Input Level with fIN1 = 15 MHz and fIN2 = 16 MHz, fSAMPLE = 65 MSPS
Rev. 0 | Page 10 of 32
AD9289 0.5
75 2V p-p, SFDR (dBc)
0.4
70
0.3
1V p-p, SFDR (dBc)
0.2 DNL (LSB)
60
55
0 –0.1 –0.2 –0.3
03682-026
2V p-p, SINAD (dB)
50
1V p-p, SINAD (dB) 45 –40
0.1
–20
0
20 49 TEMPERATURE (°C)
60
03682-028
dB
65
–0.4 –0.5 0
80
Figure 21. SINAD/SFDR vs. Temperature, fSAMPLE = 65 MSPS, fIN 10.3 MHz
32
64
96
128 CODE
160
192
224
256
Figure 23. Typical DNL, fIN = 2.4 MHz, fSAMPLE = 65 MSPS
0.5
15
0.4 0.3 0.2
5 INL (LSB)
SHARED REF MODE (PIN TIED HIGH) 0
–5
0.1 0 –0.1 –0.2
SHARED REF MODE (PIN TIED LOW)
–0.3
–15 –40
–20
0
20 49 TEMPERATURE (°C)
60
03682-029
–10 03682-027
GAIN ERROR (ppm/°C)
10
–0.4 –0.5 0
80
32
64
96
128 CODE
160
192
224
Figure 24. Typical INL, fIN = 2.4 MHz, fSAMPLE = 65 MSPS
Figure 22. Gain vs. Temperature
Rev. 0 | Page 11 of 32
256
AD9289 TERMINOLOGY Analog Bandwidth
Effective Number of Bits (ENOB)
Analog Bandwidth is the analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB from full scale.
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, it is possible to obtain a measure of performance expressed as N, the effective number of bits:
Aperture Delay
N = (SINAD – 1.76)/6.02
Aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and is measured from the 50% point rising edge of the clock input to the time at which the input signal is held for conversion.
Thus, the effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD.
Aperture Uncertainty (Jitter)
Gain Error
Aperture jitter is the variation in aperture delay for successive samples and can be manifested as frequency-dependent noise on the ADC input.
The largest gain error is specified and is considered the difference between the measured and ideal full-scale input voltage range.
Clock Pulse Width and Duty Cycle
Gain Matching
Pulse width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve a rated performance. Pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle.
Expressed in %FSR. Computed using the following equation:
Crosstalk
where FSRMAX is the most positive gain error of the ADCs, and FSRMIN is the most negative gain error of the ADCs.
Crosstalk is defined as the coupling of a channel when all channels are driven by a full-scale signal.
GainMatching =
FSR max − FSR min × 100% max + FSR min ⎞ FSR ⎛ ⎜ ⎟ 2 ⎝ ⎠
Second and Third Harmonic Distortion
Differential Analog Input Capacitance The complex impedance simulated at each analog input port.
The ratio of the rms signal amplitude to the rms value of the second or third harmonic component, reported in dBc. Integral Nonlinearity (INL)
Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a pin and subtracting the voltage from a second pin that is 180° out of phase. Peak-to-peak differential is computed by rotating the input phase 180° and taking the peak measurement again. The difference is computed between both peak measurements. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to an 8-bit resolution indicates that all 256 codes, respectively, must be present over all operating ranges.
INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Offset Error The largest offset error is specified and is considered the difference between the measured and ideal voltage at the analog input that produces the midscale code at the outputs.
Rev. 0 | Page 12 of 32
AD9289 Offset Matching
Signal-to Noise and Distortion (SINAD) Ratio
Expressed in mV. Computed using the following equation:
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels.
OffsetMatching = OFFMAX − OFFMIN where OFFMAX is the most positive offset error and OFFMIN is the most negative offset error. Out-of-Range Recovery Time Out-of-range recovery time is the time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. Output Propagation Delay The delay between the clock logic threshold and the time when all bits are within valid logic levels.
Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. Temperature Drift The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value at TMIN or TMAX. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. It may be reported in dBc (i.e., degrades as signal levels are lowered) or in dBFS (always related back to converter full scale).
Rev. 0 | Page 13 of 32
AD9289 THEORY OF OPERATION
The input stage contains a differential SHA that can be configured as ac- or dc-coupled in differential or single-ended modes. The output-staging block aligns the data and carries out the error correction. The data is serialized and aligned to the frame, output clock, and lock detection circuitry.
The analog inputs of the AD9289 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device functions over a wider range with reasonable performance (see Figure 26 and Figure 27). 75 2V p-p, SFDR (dBc) 70
60 55 2V p-p, SNR (dB)
50
1V p-p, SNR (dB)
45 40 35
ANALOG INPUT AND REFERENCE OVERVIEW
0
The analog input to the AD9289 is a differential-switched capacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA input can support a wide common-mode range and maintain excellent performance, as shown in Figure 26 sand Figure 27. An input common-mode voltage of midsupply minimizes signal dependent errors and provides optimum performance.
0.5 1.0 1.5 2.0 2.5 ANALOG INPUT COMMON-MODE VOLTAGE (V)
3.0
Figure 26. SNR, SFDR vs. Common-Mode Voltage, fIN = 2.4 MHz, fSAMPLE = 65 MSPS 75 2V p-p, SFDR (dBc)
70 65 60 dB
H
S
1V p-p, SFDR (dBc)
65
03682-030
Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor digitalto-analog converter (DAC) and interstage residue amplifier (MDAC). The MDAC magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC.
of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. Also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC’s input; therefore, the precise values are dependent on the application.
dB
Each A/D converter in the AD9289 architecture consists of a front send sample-and-hold amplifier (SHA) followed by a pipe-lined, switched capacitor ADC. The pipelined ADC is divided into two sections, consisting of six 1.5-bit stages and a final 2-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined into a final 8-bit result in the digital correc-tion logic. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock.
1V p-p, SFDR (dBc)
55
S
2V p-p, SNR (dB)
50
VIN+ CPAR
1V p-p, SNR (dB)
45
03682-031
40
S
35
VIN– 03682-051
0 CPAR
S
The clock signal alternately switches the SHA between sample mode and hold mode (see Figure 25). When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half
3.0
Figure 27. SNR, SFDR vs. Common-Mode Voltage, fIN = 35 MHz, fSAMPLE = 65 MSPS
H
Figure 25. Switched-Capacitor SHA Input UPDATE
0.5 1.0 1.5 2.0 2.5 ANALOG INPUT COMMON-MODE VOLTAGE (V)
For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC.
Rev. 0 | Page 14 of 32
AD9289 AVDD
R 2V p-p
VIN+
49.9Ω
C R
AVDD
VIN– AGND
1kΩ
REFT = 1/2 (AVDD + VREF) REFB = 1/2 (AVDD − VREF) Span = 2 × (REFT − REFB) = 2 × VREF
AD9289 03682-053
An internal reference buffer creates the positive and negative reference voltages, REFT and REFB, respectively, that defines the span of the ADC core. The output common-mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as
1kΩ 0.1µF
It can be seen from the equations above that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage. The internal voltage reference can be pin-strapped to fixed values of 0.5 V or 1.0 V or adjusted within the same range, as discussed in the Internal Reference Connection section. Maximum SNR performance is achieved by setting the AD9289 to the largest input span of 2 V p-p.
Figure 29. Differential Transformer-Coupled Configuration
Single-Ended Input Configuration A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, there is a degradation in SFDR and distortion performance due to the large input common-mode swing. However, if the source impedances on each input are matched, there should be little effect on SNR performance. Figure 30 details a typical singleended input configuration.
The SHA should be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined in Figure 26 and Figure 27.
10µF 1kΩ 2V p-p
49.9Ω
R
0.1µF 1kΩ
Differential Input Configurations
C
AVDD VIN+
AD9289
Optimum performance is achieved by driving the AD9289 in a differential input configuration. For baseband applications, the AD8351 differential driver provides excellent performance and a flexible interface to the ADC (see Figure 28). 1kΩ
25Ω
1kΩ
GP1
VIN–
PWUP
AD8351
25Ω
AVDD
0.1µF R
VCM
GP2 1V p-p 50Ω
0.1µF
VIN– AGND
1kΩ
Figure 30. Single-Ended Input Configuration
R
0.1µF 10Ω
1.2kΩ
AD9289
C 0.1µF
CLOCK INPUT AND CONSIDERATIONS
1kΩ
1kΩ
VIN+ AGND
1kΩ
AVDD
03682-054
0.1µF 10Ω
10µF
10kΩ
1kΩ
0.1µF
R
1kΩ
03682-052
AVDD
Figure 28. Differential Input Configuration Using the AD8351
However, the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9289. For applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example of this is shown in Figure 29.
Typical high speed ADCs use both clock edges to generate a variety of internal timing signals, and as a result may be sensitive to clock duty cycle. Typically, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9289 has a self-contained clock duty cycle stabilizer that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9289. An on-board phase-locked loop (PLL) multiplies the input clock rate for the purpose of shifting the serial data out. As a result, any change to the sampling frequency requires a minimum of 100 clock periods to allow the PLL to reacquire and lock to the new rate.
In any configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed.
Rev. 0 | Page 15 of 32
AD9289 High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (fA) due only to aperture jitter (tA) can be calculated with the following equation: SNR degradation = 20 × log10 [1/2 × π × fA × tA] In the equation, the rms aperture jitter, tA, represents the root sum square of all jitter sources, which include the clock input, analog input signal, and ADC aperture jitter specification. Applications that require undersampling are particularly sensitive to jitter. The LVDS clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9289. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. The AD9289 can also support a single-ended CMOS clock. Refer to the evaluation board schematics to enable this feature.
Power Dissipation and Standby Mode As shown in Figure 31, the power dissipated by the AD9289 is proportional to its sample rate. The digital power dissipation does not vary because it is determined primarily by the strength of the digital drivers and the load on each output bit. Digital power consumption can be minimized by reducing the capacitive load presented to the output drivers. The data in Figure 31 was collected while a 5 pF load was placed on each output driver. The analog circuitry of the AD9289 is optimally biased to achieve excellent performance while affording reduced power consumption. 600
180 160
550
500 100 POWER
80
450
CURRENT (mA)
120
60
Digital Outputs The AD9289’s differential outputs conform to the ANSI-644 LVDS standard. To set the LVDS bias current place a resistor (RSET is nominally equal to 3.9 kΩ) to ground at the LVDSBIAS pin. The RSET resistor current is derived on-chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal ±350 mV swing at the receiver. To adjust the differential signal swing, simply change the resistor to a different value, as shown in Table 7. Table 7. LVDSBIAS Pin Configuration RSET 3.6k 3.9k (Default) 4.3k
IDRVDD
20 0
20
30
40 50 ENCODE (MSPS)
Differential Output Swing 375 mV p-p 350 mV p-p 325mV p-p
The AD9289’s LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 Ω termination resistor placed as close to the receiver as possible. It is recommended to keep the trace length no longer than 12 inches and to keep differential output traces close together and at equal lengths. The format of the output data can be selected as offset binary or twos complement. A quick example of each output coding format can be found in Table 8. The DFS pin is used to set the format (see Table 9). Table 8. Digital Output Coding
40
400
60
70
Figure 31. Supply Current vs. fSAMPLE for fIN = 10.3 MHz
03682-032
POWER (mW)
In standby mode, low power dissipation is achieved by shutting down the reference, reference buffer, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering standby mode and then must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in standby mode, and shorter standby cycles result in proportionally shorter wake-up times. With the recommended 0.1 µF and 10 µF decoupling capacitors on REFT and REFB, it takes approximately 1 s to fully discharge the reference buffer decoupling capacitors and 7 ms to restore full operation.
140
IAVDD
350 10
By asserting the PDWN pin high, the AD9289 is placed in standby mode. In this state, the ADC typically dissipates 7 mW. During standby the LVDS output drivers are placed in a high impedance state. Reasserting the PDWN pin low returns the AD9289 into its normal operational mode.
Code 255 128 127 0
Rev. 0 | Page 16 of 32
VIN+ − VIN− Input Span = 2 V p-p (V) 1.000 0 −0.00781 −1.00
VIN+ − VIN− Input Span = 1 V p-p (V) 0.500 0 −0.00391 −0.5000
Digital Output Offset Binary (D7...D0) 1111 1111 1000 0000 0111 1111 0000 0000
Digital Output Twos Complement (D7...D0) 0111 1111 0000 0000 1111 1111 1000 0000
AD9289 Table 9. Data Format Configuration
Voltage Reference
DFS Mode AVDD AGND
A stable and accurate 0.5 V voltage reference is built into the AD9289. The input range can be adjusted by varying the reference voltage applied to the AD9289, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly.
Data Format Twos complement Offset binary
Timing Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to eight bits times the sample clock rate, with a maximum of 520 MHz (8 bits x 65 MSPS = 520 MHz). The lowest typical conversion rate is 12 MSPS. Two output clocks are provided to assist in capturing data from the AD9289. The DCO is used to clock the output data and is equal to four times the sampling clock (CLK) rate. Data is clocked out of the AD9289 and can be captured on the rising and falling edges of the DCO that supports double-data rate operation (DDR). The frame clock out (FCO) signals the start of a new output byte and is equal to the sampling clock rate. See the timing diagram shown in Figure 2 for more information.
The shared reference mode (see Figure 32) allows the user to externally connect the reference buffers from the quad ADC for better gain and offset matching performance. If the ADCs are to function independently, the reference decoupling can be treated independently and can provide better isolation between the four channels. To enable shared reference mode, the SHARED_REF pin must be tied high and external reference buffer decoupling pins must be externally shorted. (REFT_A must be externally shorted to REFT_B and REFB_A must be shorted to REFB_B.) Note that Channels A and B are referenced to REFT_A and REFB_A and Channels C and D are referenced to REFT_B and REFB_B. Table 10. Reference Settings
LOCK Pin The AD9289 contains an internal PLL that is used to generate the DCO. When the PLL is locked, the LOCK signal will be low, indicating valid data on the outputs. If for any reason the PLL loses lock, the LOCK signal goes high as soon as the lock circuitry detects an unlocked condition. While the PLL is unlocked, the data outputs and DCO remains in the last known state. If the LOCK signal goes high in the middle of a byte, no data or DCO signals will be available for the rest of the byte. It takes at least 1.8 µs at 65 MSPS to regain lock once it is lost. Note that regaining lock is sample ratedependent and takes at least 100 input periods after the PLL acquires the input clock. Once the PLL regains lock the DCO starts. The first valid data byte is indicated by the FCO signal. The FCO rising edge occurs 0.5 to <1.5 input clock periods after LOCK goes low.
CML Pin A common-mode level output is available at Pin F3. This output self biases to AVDD/2. This is a relatively high impedance output (2.5k nominal), which may need to be considered when used as a reference.
Selected Mode External Reference Internal, 1 V p-p FSR Programmable Internal, 2 V p-p FSR
Resulting VREF (V) N/A
VREF
0.5
0.2 V to VREF AGND to 0.2 V
0.5 × (1 + R2/R1) 1.0
Resulting Differential Span (V p-p) 2 × External Reference 1.0 2 × VREF 2.0
Internal Reference Connection A comparator within the AD9289 detects the potential at the SENSE pin and configures the reference into four possible states, which are summarized in Table 10. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 33), setting VREF to 1 V. Connecting the SENSE pin to the VREF pin switches the amplifier output to the SENSE pin, configuring the internal op amp circuit as a voltage follower and providing a 0.5 V reference output. If an external resistor divider is connected as shown in Figure 34 the switch is again set to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as
R2 ⎞ VREF = 0.5 × ⎛⎜1 + ⎟ R1 ⎠ ⎝
DTP Pin When the digital test pattern (DTP) pin is enabled (pulled to AVDD), all of the ADC channel outputs shift out the following pattern: 11000000. The FCO and DCO outputs still work as usual while all channels shift out the test pattern. This pattern allows the user to perform timing alignment adjustments between the DCO and the output data.
SENSE Voltage AVDD
In all reference configurations, REFT_A and REFT_B and REFB_A and REFB_B establish their input span of the ADC core. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference.
Rev. 0 | Page 17 of 32
AD9289 VIN+A (+B)
VIN+A (+B)
VIN–A (–B)
VIN–A (–B)
REFT_A A CORE B CORE
0.1µF
+
VREF
0.1µF
A CORE B CORE
10µF
REFB_A
0.1µF
10µF
0.1µF R2
SELECT LOGIC
10µF
0.1µF
VREF
0.1µF
+
REFB_A
VREF
0.1µF
VREF 10µF
0.1µF
REFT_A
SELECT LOGIC
SENSE SENSE R1 0.5V
0.5V
VIN+C (+D)
VIN+C (+D)
VIN–C (–D)
VIN–C (–D)
REFT_B
VREF C CORE D CORE
0.1µF 0.1µF
+
0.1µF
C CORE D CORE
10µF
0.1µF
03682-011
CONTROL
SHARED_REF
Figure 32. Shared Reference Mode Enabled
REFT_A 0.1µF 0.1µF
CONTROL
Figure 34. Programmable Reference Configuration
VIN+A (+B)
A CORE B CORE
10µF
REFB_B
SHARED_REF
VIN–A (–B)
+
03682-013
REFB_B
AVDD
+
10µF
If the internal reference of the AD9289 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 35 depicts how the internal reference voltage is affected by loading.
REFB_A
VREF
0.05
0.1µF
VREF
0
0.1µF
–0.05 VREF ERROR (%)
SELECT LOGIC SENSE
0.5V
VREF = 0.5V
–0.10 –0.15 –0.20 VREF = 1.0V
–0.25
VIN+C (+D) –0.30
VIN–C (–D)
–0.35
C CORE D CORE
0.1µF 0.1µF
+
10µF
REFB_B SHARED_REF
03682-033
REFT_B
VREF
CONTROL
03682-012
10µF
REFT_B
VREF
Figure 33. Internal Reference Configuration
Rev. 0 | Page 18 of 32
–0.40 0
0.5
1.0 1.5 ILOAD (mA)
Figure 35. VREF Accuracy vs. Load
2.0
2.5
AD9289 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 36 shows the typical drift characteristics of the internal shared reference in both 1 V and 0.5 V modes. 0.15 VREF = 0.5V
0.10
Power and Ground Recommendations VREF = 1.0V
0 –0.05 –0.10 –0.15 –0.20
03682-034
VREF ERROR (%)
0.05
–0.25 –40
When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7 kΩ load. The internal buffer still generates the positive and negative full-scale references, REFT_A and REFT_B and REFB_A and REFB_B , for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1 V.
–20
0
20 40 TEMPERATURE (°C)
Figure 36. Typical VREF Drift
60
80
When connecting power to the AD9289, it is recommended that two separate 3.0 V supplies be used. One for analog (AVDD) and one for digital (DRVDD). If only one supply is available then it should be routed to the AVDD first and tapped off and isolated with a ferrite bead or filter choke with decoupling capacitors proceeding. One may want to use several different decoupling capacitors to cover both high and low frequencies. These should be located close the point of entry at the pc board level as well as close to the parts with minimal trace length. A single pc board ground plane should be sufficient when using the AD9289. With proper decoupling and smart partitioning of the pc board’s analog, digital, and clock sections, optimum performance is easily achieved.
Rev. 0 | Page 19 of 32
AD9289 EVALUATION BOARD the signal sources that are used have very low phase noise (< 1 ps rms jitter) to realize the ultimate performance of the converter. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance.
The AD9289 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially through a transformer (default) or the AD8351 driver. Provisions have also been made to drive the ADC single-ended. Separate power pins are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (refer to the schematics). Figure 37 shows the typical bench characterization setup used to evaluate the ac performance of the AD9289. It is critical that
XFMR INPUT
–
+
DUT_DRVDD
GND
BRD_AVDD
3.3V +
AD9289 EVALUATION BOARD
ROHDE AND SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER
CLK
HSC-ADC-FPGA HIGH-SPEED DE-SERIALIZATION BOARD
HSC-ADC-EVAL-DC FIFO DATA CAPTURE BOARD
2 CH 8-BIT PARALLEL CMOS
USB CONNECTION
CHA–CHD 8-BIT SERIAL LVDS
Figure 37. Evaluation Board Connections
Rev. 0 | Page 20 of 32
PC RUNNING ADC ANALYZER
03682-002
BAND-PASS FILTER
3.0V –
GND
ROHDE AND SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER
3.0V +
DUT_AVDD
–
See Figure 37 to Figure 47 for complete schematics and layout plots, which demonstrate the routing and grounding techniques that should be applied at the system level.
03682-048
CLOCK INPUT
NC
R41 50 Ω
2
V–
1
C7 0.1 µF
TP4
R109 1kΩ
R110 1kΩ
BRD_AVDD
R43 1k Ω
R40 1k Ω
1
4
3
2
1
RB DNP
U1 13
U1
JP35
R70 1kΩ
R29 1kΩ JP9
R73 100 Ω
5 V REF = 1V
TP2 JP1
R37 10k Ω
DUT_AVDD
TP1
TP3
DUT_AVDD
DUT_AVDD
VREF
SHARED_REF
H8
E6
F6
G6
E3
F5
G5
F4
G4
G7
F7
H5
H4
G3
F3
R76 3.9k Ω H1
6 V REF = 0.5V (1 + RA/RB)
4
8 V REF = 0.5V 7 V REF = EXTERNAL
3
2
1
U17
BRD_AVDD
R71 0Ω
R102 22Ω
5
6
7
JP5
R66 0Ω
SINGLE-ENDED CLOCK DRIVER OPTION
2 12
DNC
DNC
DOUT+
8
C600 0.1 µF
JP3
C35 0.1 µF
C36 0.1 µF
VREF
BRD_AVDD
DOUT –
C80 0.1 µF
C100 10 µF
C44 0.1 µF
C120 10µF
FIN1017M
GND
DNC
DIN
VCC
U2
BRD_AVDD
C250 0.1 µF
CX 10 µF
RA DNP
REMOVE CX WHEN USING EXTERNAL V REF U6
C47 0.1 µF
JP2
C1 0.1 µF
C53 0.1 µF
R1 1k Ω
BRD_AVDD
V+
C6 0.1 µF
ADR510
TRIM/NC
P5
3
U6
DTP
AVDD
AGND
AGND
AGND
REFT_B
REFB_B
REFT_A
REFB_A
AGND
AVDD
VREF
SENSE
SHARED_REF
CML
LVDSBIAS
AGND E5
BRD_AVDD
F2 E4
VIN_B H2
AD9289 EXTERNAL REFERENCE OPTION
VIN_B H6
AVDD
E2
SHARED_REF
DUT_AVDD
AD9289
VIN_A R75 10k Ω
R72 10k Ω
FCO C1
VOLTAGE REFERENCE CIRCUITRY
G2 AGND
DUT_AVDD AVDD
H3 VIN –B VIN –C VIN_C
VIN+B VIN+C H7 VIN_C
AGND
E1 D7
AGND E7
AGND AGND
G1 G8
VIN_A F1 F8
VIN+A
D1 DNC DFS C7
VIN –D VIN_D
VIN+D VIN_D
VIN –A
D2 DNC CLK – D8
FCO+
C2 E8
CLK+ C8
FCO R32 10k Ω
FCO –
CHA A8
PDWN
B1 D1+A DNC
CHA A1 D1 –A
B2
DRGND
DRVDD
DNC
DNC
D1 –C
D1+C
AGND
DCO –
DCO+
LOCK
DNC
DNC
D1 –B
D1+B
DRGND
DRVDD
D1 –D A7
DNC B8
DNC
A2 DNC 5 4
6 2 3
D3
C6
A6
B6
A5
B5
D5
C5
C4
D4
A4
B4
A3
B3
D6
C3
CHD
CHC
CHB
CHA
FCO
DCO
DUT_DRVDD
CHC
CHC
DCO
DCO
TP9
CHB
CHB
DUT_DRVDD
46 45
6
25
24
23
22
21
26
27
28
29
30
31
32 20
33
34
35
36
37
38
39
40
41
19
R4 DNP
R3 DNP
R2 DNP
R67 DNP
42
43
18
17
16
15
14
13
12
11
10
9
8
44
47
5
R25 DNP
48
4
7
49
3
R26 DNP
50
2
U5 1
CHD
CHC
CHB
CHA
FCO
DCO
** PLACE ONLY WHEN USING THE AD8351 AS INPUT. SEE DATASHEET FOR DETAILS. DNP = DO NOT POPULATE = GND
BRD_AVDD 1
J6
D1+D
Rev. 0 | Page 21 of 32
B7
Figure 38. Evaluation Board Schematic, DUT, VREF, and Clock Inputs CHD
U7 CHD
DIGITAL LVDS OUTPUTS
AD9289
Figure 39. Evaluation Board Schematic, DUT Analog Input
03682-047
ANALOG INPUT CHANNEL D
ANALOG INPUT CHANNELC
P4
P3
ANALOG P2 INPUT CHANNEL B
ANALOG P1 INPUT CHANNEL A JP20 JP26
JP18 JP21 JP24 JP25 JP27
Rev. 0 | Page 22 of 32 JP28
JP19 JP29
R42 50Ω
R21 1kΩ
CM4
C5 0.1µF
AVDD
R65** DNP
AMP_IN4
R83 50Ω
R13 1kΩ
CM2
C3 0.1µF
AVDD
R64** DNP
AMP_IN3
R30 50Ω
R63** DNP
AMP_IN2
R15 50Ω
R62** DNP
AMP_IN1
C20 0.1µF
4
3
R24 1kΩ
5
T4
6
2
1
C28 DNP
C15 0.1µF
4
3
R16 1kΩ
5
T2
6
2
1
C24 DNP
R84** DNP
CM4
R82** DNP
R74** DNP
CM2
R69** DNP
CH_D
CH_D
CH_B
CH_B
L13 120nH
L28 120nH
L27 120nH
L10 120nH
L9 120nH
L20 120nH
L19 120nH
L6 120nH
R11 33Ω
C4 0.1µF
AVDD
C9 DNP
R14 33Ω
R23 33Ω
C17 DNP
R27 33Ω
AVDD
CM1
VIN_D C13 DNP
C10 20pF
R77** DNP
CM3
R80** DNP
R59** DNP
CM1
R68** DNP
CH_C
CH_C
CH_A
CH_A
L11 120nH
L22 120nH
L21 120nH
L12 120nH
L4 120nH
L1 120nH
L2 120nH
L3 120nH
R44 33Ω
C42 DNP
R47 33Ω
R34 33Ω
C31 DNP
R31 33Ω
VIN_C C43 DNP
C41 20pF
VIN_C
VIN_A C23 DNP
C30 20pF
VIN_A
** PLACE ONLY WHEN USING THE AD8351 AS INPUT. SEE DATASHEET FOR DETAILS. DNP = DO NOT POPULATE = GND
C18 0.1µF
6 1
4
5
T3
C25 DNP
2
3
R19 1kΩ
VIN_D
R18 1kΩ
CM3
VIN_B C22 DNP
C21 20pF
C16 0.1µF
6
1
4
5
T1
C19 DNP
2
3
R20 1kΩ
VIN_B
R12 1kΩ
C2 0.1µF
AD9289
Figure 40. Evaluation Board Schematic, Optional DUT Analog Input Drive R8 10Ω
C64 R9 0.1µF 10Ω R92 R79 25Ω 25Ω
C65 0.1µF
R90 10kΩ
C50 R7 0.1µF 10Ω R49 R22 25Ω 25Ω
R5 10Ω
5
4
3
2
1
RGP2
INLO
INHI
RGP1
PWUP
U9
R78* DNP
R50 1kΩ
R35 1.2kΩ
R93 1kΩ
R81 1.2kΩ
OPLO
03682-049
OPHI
VPOS
R94 1kΩ
6
7
8
9
10
COMM
OPLO
OPHI
VPOS
VOCM
6
7
8
9
10
C63 0.1µF
COMM
C62 0.1µF
R45 1kΩ C49 0.1µF
VOCM
C48 0.1µF
BRD_AVDD
RGP2
INLO
INHI
RGP1
PWUP
U7
FOR PWDN PLACE R78
5
4
3
2
1
R6* DNP
FOR PWDN PLACE R6
* TO ENABLE THE POWER DOWN OPTION ON THE AD8351, PLACE A 0Ω RESISTOR IN THIS PLACE HOLDER.
R91 50Ω
AMP_IN3
R38 50Ω
AMP_IN1
C54 0.1µF
R36 10kΩ
BRD_AVDD
CH_A
CH_A
CH_C
CH_C
R106 25Ω
AMP_IN4
R99 C67 0Ω 0.1µF
R98 C66 0Ω 0.1µF
R55 25Ω
AMP_IN2
R48 C51 0Ω 0.1µF
R48 C52 0Ω 0.1µF
R10 10Ω
R33 10Ω
C70 R39 0.1µF 10Ω R107 R101 50Ω 25Ω
C71 0.1µF
R104 10kΩ
C58 R17 0.1µF 10Ω R56 R52 50Ω 25Ω
C59 0.1µF
R54 10kΩ
5
4
3
2
RGP2
INLO
INHI
RGP1
PWUP
U10
R100* DNP
1
R57 1kΩ
R53 1.2kΩ
R58 1kΩ
R103 1.2kΩ
COMM
OPLO
OPHI
VPOS
6
7
8
9
10
C69 0.1µF
R108 1kΩ
VOCM
R111 1kΩ
6
7
8
9
C68 0.1µF
COMM
OPLO
OPHI
VPOS
10
C57 0.1µF
VOCM
C55 0.1µF
BRD_AVDD
RGP2
INLO
INHI
RGP1
PWUP
U8
FOR PWDN PLACE R100
5
4
3
2
1
R51* DNP
FOR PWDN PLACE R51
BRD_AVDD
AD8351
AD8351 AD8351
Rev. 0 | Page 23 of 32
AD8351
AD8351 ANALOG INPUT DRIVER OPTION
R114 C73 0Ω 0.1µF
R113 C72 0Ω 0.1µF
R61 C61 0Ω 0.1µF
R60 C60 0Ω 0.1µF
CH_D
CH_D
CH_B
CH_B
AD9289
P6
P5
P4
P3
P2
P1
P6
Figure 41. Evaluation Board Schematic, Power, and Decoupling 03682-050
C14 0.1µF
DUT_AVDD
+3.0V
+3.0V
+3.3V
6
5
4
3
2
1
C12 0.1µF
C37 0.1µF
C171 10µF
L8 10µH
C176 10µF
L7 10µH
C170 10µF
C29 0.1µF
BRD_AVDD
DECOUPLING CAPS
+
+
+
C25 0.1µF
JP2
C11 0.1µF
11
9
5
3
10
8
6
4
GROUND TEST POINTS
U1
U1
U1
U1
** PLACE ONLY WHEN USING THE AD8351 AS INPUT. SEE DATASHEET FOR DETAILS. DNP = DO NOT POPULATE = GND
C40 0.1µF
DUT_DRVDD
DUT_DRVDD C110 0.1µF
DUT_AVDD C183 0.1µF
BRD_AVDD C108 0.1µF
TP14
JP1 JP4
UNUSED GATES
TP15
L5 10µH
TP16
Rev. 0 | Page 24 of 32
TP18
POWER CONNECTIONS
AD9289
03682-036
AD9289
03682-038
Figure 42. Evaluation Board Layout, Primary Side
Figure 43. Evaluation Board Layout, Primary Side (With Ground Copper Pour)
Rev. 0 | Page 25 of 32
03682-039
AD9289
03682-040
Figure 44. Evaluation Board Layout, Ground Plane
Figure 45. Evaluation Board Layout, Power Plane
Rev. 0 | Page 26 of 32
03682-045
AD9289
03682-041
Figure 46. Evaluation Board Layout, Secondary Side
Figure 47. Evaluation Board Layout, Secondary Side (With Ground Copper Pour)
Rev. 0 | Page 27 of 32
AD9289 Table 11. Evaluation Board Bill of Materials (BOM)
Item 1
Qnty. per Board 1
2 3
1 8
4
8
5
8
6
8
7 8 9
4 1 8
10 11
4 13
12
6
13 14
1 5
15
23
16 17 18
2 4 36
19
17
20 21 22
3 3 16
23 24
3 1
REFDES AD9289 BGA REVA/PCB Assembly R46, R48, R60, R61, R98, R99, R113, R114 R5, R7, R8, R9, R10, R17, R33, R39 R22,R49, R52, R55, R79, R92, R101, R106 R11,R14, R23, R27, R31, R34, R44, R47 R38, R56, R91, R107 R73 R45, R50, R57, R58, R93, R94, R108, R111 R35, R53, R81, R103 R6, R32, R36, R51, R54, R72, R75, R78, R90, R100, R104, R37, R76 R62, R63, R64, R65, R66, R71 R102 R15, R30, R41, R42, R83 R1, R12, R13, R16, R18, R19, R20, R21, R24, R29, R40, R43, R59, R68, R69, R70, R74, R77, R80, R82, R84, R109, R110 R96, R97 C10, C21, C30, C41 C1, C35, C44, C47, C80, C250, C600, C11, C12, C14, C37, C40, C48, C63, C64, C65, C66, C67, C68, C69, C70, C71, C72, C73 C2, C3, C4, C5, C6, C7, C15, C16, C18, C20, C25, C29, C36, C53, C108, C110, C183 C100, C120, C163 C170, C171, C176 L1, L2 ,L3, L4, L6, L9, L10, L11, L12, L13, L19, L20, L21, L22, L27, L28 L5,L7,L8 P6
Device PCB
Package PCB
Value PCB
Manufacturing PCSM
Mfg. Part Number PCSM
RES_402
402
0
Protronics Yageo America
Protronics 9C04021A0R00JLHF3
RES_402
402
10
Susumu Co Ltd
RR0510R-100-D
RES_402
402
25
Susumu Co Ltd
RR0510R-240-D
RES_402
402
33
Susumu Co Ltd
RR0510R-330-D
RES_402 RES_402 RES_402
402 402 402
50 100 1K
Panasonic-ECG Yageo America Panasonic-ECG
ERJ-L14KF50MU 9C04021A1000FLHF3 ERJ-2GEJ102X
RES_402 RES_402
402 402
1.2K 10K
Panasonic-ECG Susumu Co Ltd
ERJ-2GEJ122X RR0510P-103-D
BRES603
603
0
Panasonic-ECG
ERJ-3GEY0R00V
BRES603 BRES603
603 603
22 50
Susumu Co Ltd Susumu Co Ltd
RR0816Q-220-D RR0816Q-49R9-D-68R
BRES603
603
1K
Susumu Co Ltd
RR0816P-102-D
BRES603 CAP402 CAP402
603 402 402
XXX 20PF 1UF
Kemet Panasonic-ECG
C0402C220J5GACTU ECJ-0EF1C104Z
BYPASSCAP
603
0.1UF
Kemet
C0603C104Z3VACTU
TANTALUMB TANTALUMB INDUCTOR_6
805 T491B06K01 603
10UF 10UF 120NH
Panasonic-ECG Kemet Murata
ECJ-2FB0J106M T491B106K016AS BLM18BB750SN1D
IND1210 PTMICRO6
1210 PTMICRO6
10UH 6-Pole PCB Header
Panasonic-ECG Wieland
ELJ-SA100KF Z5.531.3625.0
Rev. 0 | Page 28 of 32
AD9289 Item
Qnty. per Board 1
REFDES
Device
Package
25
5
P1, P2, P3, P4, P5
SMBMST
SMB
26 27
4 1
T1, T2, T3, T4 U17
ADT1-1WT HEADER
CD542_X65 2MMSMT-872
28 29
1 1
U5 J6
DIFF_CONN MINIJMPR3
FCN_268M01 2MMSMT-872
ADT1-1WT WM18158ND DIFF_CONN MINIJMPR3
30 31
2 2
JP1, JP2
SGLJMPR NYLON
87267-0850 1/4" 6-32
32 33
2 1
U1
SGLJMPR 11/4" STANDOFF 6-32NUTS 74VHC04MTC
NYLON TSSOP-14
6-32 74VHC04
34
1
U2
FIN1017M
MO8A_(SOIC)
FIN1017M
35
1
U4
9289BGA
36 37
1 4
U6 U7, U8, U9, U10
AD9289BBC65 ADR510 AD8351ARM
SOT23 MSOP010
Value 6-Pole PCB Connector SMBMST
Manufacturing Wieland
Mfg. Part Number 25.600.5653.0
Amphenol-RF Division Minicircuits Molex/Waldom Electronics Corp Fujitsu Molex/Waldom Electronics Corp Samtec RAF
901-144-8RFX ADT1-1WT 87267-0850 FCN-268M012-G/1D 87267-0850 TSW-120-07-G-S 4040-632-N
9289BGA
RAF Fairchild Semiconductor Fairchild Semiconductor ADI
AD9289BBC-65
ADR510 AD8351
ADI ADI
ADR510 AD8351ARM
Rev. 0 | Page 29 of 32
3058-N 74VHC04MTC FIN1017M
AD9289 OUTLINE DIMENSIONS A1 CORNER INDEX AREA
8.00 BSC SQ
8
7
6
5
4
3
2
1 A
BALL A1 INDICATOR TOP VIEW
B C
5.60 BSC SQ
D
0.80 BSC
E F G H
BOTTOM VIEW 1.70 1.55 1.35
DETAIL A
DETAIL A 0.34 NOM 0.25 MIN
1.31 1.21 1.10
COPLANARITY 0.55 0.12 SEATING 0.50 PLANE 0.45 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-205-BA
Figure 48. 64-Lead Chip Scale Package Ball Grid Array [CSP_BGA] (BC-64-1) Dimensions shown in millimeters
ORDERING GUIDE Model AD9289BBC AD9289-65EB
Temperature Range –40°C to +85°C
Package Description 64-Lead Chip Scale Package Ball Grid Array [CSP_BGA] Evaluation Board
Rev. 0 | Page 30 of 32
Package Option BC-64-1
AD9289 NOTES
Rev. 0 | Page 31 of 32
AD9289 NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03682-0-10/04(0)
Rev. 0 | Page 32 of 32
