Transcript
RAD5545™ SpaceVPX single-board computer Multi-core single-board computer SpaceVPX connector
The RAD5545 SpaceVPX singleboard computer (SBC) integrates either the RAD5515™ or RAD5545 system-on-chip (SoC) processor with volatile and non-volatile memory on a 6U-220 format module compliant to the ANSI/ VITA 78.00 SpaceVPX standard. It includes up to 16 GBytes of DDR3
The SBC is designed to support operation as either a payload or system controller in a SpaceVPX backplane. Based on BAE Systems’ RAD5545 or RAD5515 QorIQ® Power Architecture® radiation-hardened SoC processor, the SBC offers both high performance and high I/O throughput.
™
RAD5545 SoC with heat pipe
DDR3 DRAM memory DIMM
SDRAM with error correction at 800 MTransfers/second and up to 8 GBytes of triple modular redundant non-volatile flash memory. Up to four RapidIO ports at 16 Gbits/second each and 12 SpaceWire links at 320 Mbits/second each are provided to the SpaceVPX backplane. An optional daughter card with PCI, RapidIO, and/ or SpaceWire interfaces can be used to personalize the SBC for unique needs.
Point-of-Load (POL) converters
Key
FPGA
I/O
Power Supply
Processor module
Power module
SpaceUM module
FPGA
RADNET™ 1848-PS ASSP
RADNET™ 1616-XP ASSP
FPGA
RADNET™ SpW-RB4 ASSP
Payload module
Switch module
Controller module
Payload module
Peripheral module
Payload module
DDR3 DRAM
DDR3 DRAM
RAD5515™ processor
RAD5545™ processor
RADNET™ SpW-EP ASSP
RADNET™ SRIO-EP ASSP
DDR3 DRAM
DDR3 DRAM
RAD5545™ processor
RADNET™ SRIO-EP ASSP
RapidIO SpaceWire Possible small systems solution
Data Control Utility Expansion
I/O
RADNET™ 1616-XP ASSP
RADNET™ 1848-PS ASSP
XAUI Representative SpaceVPX network (redundant modules not shown)
www.baesystems.com
RADNET™ SpW-RB4 ASSP I/O Heritage compact PCI module
Utility plane: I2C + Data plane: Utility plane RapidIO 4 fat pipes
SE P0/J0 S E Diff P1/J1
Utility plane
S E Diff P1/J1
User defined
S Diff E P2/J2
User defined
S Diff E P2/J2
S Diff E P3/J3
Control plane SpaceWire 12 thin pipes, 4 reserved
S Diff E P3/J3
Key
User defined RapidIO SpaceWire I2C PCI
SE P0/J0
S Diff E P4/J4
S Diff E P5/J5
S Diff
User defined Utility plane: I2C + 16 pairs
To E P6/J6 SpaceUM 8 pairs Key Controller with data plane
User defined
S Diff E P4/J4
S Diff E P5/J5
Key Utility plane: I2C + Data plane: RapidIO 4 fat pipes Expansion plane – User defined Key User defined Control plane SpaceWire 2 thin pipes User defined
S Diff E P6/J6
Key Payload
Key features and benefits
Specifications
• Processor throughput of up to 5.6 giga-operations per second/3.7 giga-floating-point operations per second offers more than 10 times the performance of the fastest RAD750® processor
SpaceVPX
• Memory bandwidth of up to 51 Gb/s and I/O throughput of up to 64 Gb/s provide balance to prevent bottlenecks to or from the processor cores • Dual in-line memory module mounting supports ease of memory replacement or upgrade • Optional user-personalized daughter card with parallel peripheral component interconnect, RapidIO, and/or SpaceWire interfaces supports mission-specific SBC personalization • Designed for insertion into the SpaceVPX backplane, supporting the RapidIO data plane, SpaceWire control plane, and system management inter-integrated circuit utility plane for interoperability with other SpaceVPX-compliant boards • Multiple levels of on-die cache and high-performance DDR3 main memory all with error correction provide maximum effective throughput and reliability • Triple modular redundant (TMR) flash memory enables highdensity, non-volatile storage with high reliability • Trust architecture security infrastructure provides secure boot, integrity code testing, data encryption, and partitioning of the system to minimize the likelihood of corruption due to intentional or environmental-based intrusion • Up to four RapidIO ports with integrated message managers support high-performance data streaming and messaging and support system architectures based on either mesh or switchbased backplanes
Hardware block diagram 8 GB DDR3 SDRAM
4 GB flash
Daughter card connector
PCI 32-bit RTAX FPGA
Utility plane (x5) (x1 on P0 x4 on P6)
Memory, test, & low speed interfaces
Test
RAD5545™ processor
RapidIO (on P1) 3 (or 4 optional) at 16 Gbps
SpaceWire 4 at 320 Mbps
1.5V 2.5V 3.3V 3.3V AUX +12V -12V RapidIO 1 (optional) at 16 Gbps
Oscillators 125 MHz 66 MHz 25 MHz
0.75V 0.95V 1.5V 2.5V 3.3V Point of load converters
SpaceWire (on P3 and P4) 12 at 320 Mbps 3.3V AUX
For more information contact: BAE Systems 9300 Wellington Road Manassas , Virginia 20110-4122 T: 571 364 7777 E:
[email protected] W: www.baesystems.com/spaceproducts Cleared for open publication on 03/17 BAE Systems | RAD5545™ SpaceVPX single board computer
Slot profiles: payload, system controller with data plane Module profiles: Payload: MOD6-PAY-4F1Q2T-12.2.1-5-22 Controller:MOD6-CON-4F12T12U-12.6.1-2-22 Mechanical size: 6U-220 Card pitch: 1.2 inches Cooling: Conduction Power profile (no daughter card) 5.0 V (+/- 10 percent): 6.7 Amps 3.3 V AUX: <1.0 Amps User-defined I/O: Differential Temperature Operating at -55 to +125 degrees Celsius RadiationTotal ionizing dose: 100 Krad (Si) hardness Single event upset: 1e-3 upsets/card-day Latchup immune Power 35 Watts at 95 degrees Celsius and +5 dissipation percent voltage with all dissipation interfaces operational (no daughter card) Interfaces Up to four 4-lane RapidIO ports up to 5 Gbaud/lane (also supports 3.125, 2.5, and 1.25 Gbaud/lane) Up to 12 SpaceWire serial links to the backplane up to 320 Mb/s each I2C and related utility plane control signals JTAG test and debug Aurora high speed trace debug Up to 4 SpaceWire links Daughter card One RapidIO port (the RapidIO port is mutually interfaces exclusive with the 4th RapidIO port to the backplane) 32-bit parallel PCI
5V
+/-12V AUX
Disclaimer and copyright This document gives only a general description of the product(s) and service(s) and, except where expressly provided otherwise, shall not form any part of any contract. From time to time, changes may be made in the products or the conditions of supply. BAE SYSTEMS is a registered trademark of BAE Systems plc. ©2017 BAE Systems. All rights reserved. CS-17-C09
