Remote Terminal Unit Callisto - Scada Help Desk

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Callisto Remote Terminal Unit T EC HNICA L G U IDE ©2012 DAQ Electronics, LLC. All rights reserved. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, without the prior written permission of DAQ Electronics, LLC. Part #P03-07066 Revised January 2012 262B Old New Brunswick Road Piscataway, NJ 08854 USA T 732.981.0050 F 732.981.0058 www.daq.net DAQ Electronics, LLC Callisto RTU Technical Guide ► Important Document Notes ► General This equipment guide covers the major components of the DAQ Callisto series of RTUs (Remote Terminal Units). Included in the document are general overviews, board drawings, and technical descriptions related to the overall Callisto system and individual modules. In addition, a trouble-shooting section provides useful information to help users correct or avoid the most common technical problems. ► Software Documentation Configuration of Callisto RTUs is accomplished via DAQ CallistoView software. A separate user’s guide for this software package is available in the form of extensive Help files that cover all stages of RTU configuration, from initial setup to the fine-tuning of specific parameters. These interactive files are included with the latest version of CallistoView and are also available for download from www.daq.net. i DAQ Electronics, LLC Callisto RTU Technical Guide Table of Contents ► Introduction……………………………………………………………………………………………................ 1 General Description…………………………………………………………………………………….…… 1 Architecture………………………………………………………………………………………................. 1 Local Area Network………………………………………………………………………………................2 Voyager…………………………………………………………………………………………………........ 2 Processing Nodes…………………………………………………………………………………………... 3 IoA1 Analog Input Processing Node………………………………………………………................ 3 IoC1 Command Output Processing Node………………………………………………………….... 4 IoD1 Status Input Processing Node………………………………………………………………...... 4 IoE1 Serial Communication Processing Node……………………………………………............... 4 IoE2 Serial Communication Processing Node……………………………………………............... 5 IoP1 Parallel Data Processing Node………………………………………………………................5 Operating System…………………………………………………………………………………...............5 Configuration………………………………………………………………………………………............... 5 Industry Standard Interfaces……………………………………………………………………………….. 6 Power System Calculations……………………………………………………………………….............. 6 ► Hardware…………………………………………………………………………………………………………... 8 Motherboards………………………………………………………………………………………….…...... 8 General Description……………………………………………………………………………………..8 Links……………………………………………………………………………………………………… 8 DXC10………………………………………………………………………………………………. 8 DXC15………………………………………………………………………………………………. 9 DXC21………………………………………………………………………………………………. 9 Connections……………………………………………………………………………………………...10 DXC10………………………………………………………………………………………………. 10 DXC15………………………………………………………………………………………………. 11 DXC21…………………………………………………………………………..………………….. 12 I/O Interface……………………………………………………………………………………..………. 14 Board Drawing List……………………………………………………………………………………... 14 Technical Description…………………………………………………………………………………...14 Environmental Specifications…………………………………………………………………….. 14 Construction………………………………………………………………………………..………. 14 IoA1…………………………………………………………………………………………………………… 15 General Description……………………………………………………………………………………..15 Links……………………………………………………………………………………………………… 16 Connections………………………………………………………………… ………………………….. 17 Termination Board I/O Interface………………………………………………………………………. 17 LEDs……………………………………………………………………………………………………... 18 Board Drawing List……………………………………………………………………………………... 19 Technical Description…………………………………………………………………………………...19 80C188 Processor………………………………………………………………………………….19 Reset Circuit………………………………………………………………………………………... 19 Watchdog Circuit…………………………………………………………………………………... 20 Memory……………………………………………………………………………………………... 20 Input Point Capabilities……………………………………………………………………………. 20 Power Requirements…………………………………………………………………………….... 20 Analog to Digital Conversion……………………………………………………………………... 21 Operating System………………………………………………………………………………….. 21 ii DAQ Electronics, LLC Callisto RTU Technical Guide Local Area Network………………………………………………………………………………... 21 Environmental Specifications…………………………………………………………………….. 21 Configuration……………………………………………………………………………………….. 21 Construction………………………………………………………………………………………... 21 IoC1…………………………………………………………………………………………………………… 22 General Description……………………………………………………………………………………..22 Links……………………………………………………………………………………………………… 23 Connections………………………………………………………………… ………………………….. 24 Termination Board I/O Interface………………………………………………………………………. 24 LEDs……………………………………………………………………………………………………... 25 Board Drawing List……………………………………………………………………………………... 26 Technical Description…………………………………………………………………........................ 26 80C188 Processor………………………………………………………………………………….26 Reset Circuit………………………………………………………………………………………... 26 Watchdog Circuit…………………………………………………………………………………... 26 Memory……………………………………………………………………………………………... 26 Communications Port……………………………………………………………………………… 28 Outputs……………………………………………………………………………………………… 28 Power Requirements……………………………………………………………………………… 29 Operating System………………………………………………………………………………….. 29 Local Area Network………………………………………………………………………………... 29 Environmental Specifications…………………………………………………………………….. 29 Configuration……………………………………………………………………………………….. 29 Construction………………………………………………………………………………………... 29 IoD1…………………………………………………………………………………………………………… 30 General Description……………………………………………………………………………………..30 Links……………………………………………………………………………………………………… 31 Connections……………………………………………………………………………………………...31 Termination Board I/O Interface………………………………………………………………………. 31 LEDs……………………………………………………………………………………………………... 32 Board Drawing List……………………………………………………………………………………... 32 Technical Description…………………………………………………….……………………………..33 80C188 Processor………………………………………………………………………………….33 Reset Circuit………………………………………………………………………………………... 33 Watchdog Circuit…………………………………………………………………………………... 33 Memory……………………………………………………………………………………………... 33 Communications Port……………………………………………………………………………… 35 Inputs………………………………………………………………………………………………... 35 Power Requirements……………………………………………………………………………… 35 Operating System………………………………………………………………………………….. 36 Local Area Network………………………………………………………………………………... 36 Environmental Specifications………………………………………………………………….…. 36 Configuration……………………………………………………………………………………….. 36 Construction………………………………………………………………………………………... 36 IoE1…………………………………………………………………………………………………………… 37 General Description……………………………………………………………………………………..37 Links……………………………………………………………………………………………………… 39 Connections……………………………………………………………………………………………...39 Termination Board I/O Interface………………………………………………………………………. 39 LEDs……………………………………………………………………………………………………... 40 Board Drawing List……………………………………………………………………………………... 41 Technical Description…………………………………………………………………………………...41 80C188 Processor………………………………………………………………………………….41 iii DAQ Electronics, LLC Callisto RTU Technical Guide Reset Circuit………………………………………………………………………………………... 42 Watchdog Circuit…………………………………………………………………………………... 42 Memory……………………………………………………………………………………………... 42 Z8530 Serial Communications Controller……………………………………………………….. 44 Communications Ports……………………………………………………………………………. 44 Adjustments………………………………………………………………………………………… 45 Serial Input/Output………………………………………………………………………………… 45 Power Requirements……………………………………………………………………………… 46 Real Time Clock…………………………………………………………………………………… 46 Operating System………………………………………………………………………………….. 46 Local Area Network………………………………………………………………………………... 46 Environmental Specifications…………………………………………………………………….. 47 Configuration……………………………………………………………………………………….. 47 Construction………………………………………………………………………………………... 47 IoE2…………………………………………………………………………………………………………… 48 General Description…………………………………………………………………………………..... 48 Links……………………………………………………………………………………………………… 50 Connections……………………………………………………………………………………………...50 Termination Board I/O Interface………………………………………………………………………. 51 LEDs……………………………………………………………………………………………………... 51 Board Drawing List……………………………………………………………………………………... 52 Technical Description…………………………………………………………………………………...52 Processor…………………………………………………………………………………………… 52 Real Time Clock………………………………………………………………………………….... 54 Reset Registers ……………………………………………………………………………………. 54 EPLD………………………………………………………………………………………………... 55 Buffers………………………………………………………………………………………………. 56 Disk-On-Chip……………………………………………………………………………………..... 56 Flash………………………………………………………………………………………………… 56 SRAM……………………………………………………………………………………………….. 56 Buffers………………………………………………………………………………………………. 57 Switching Power Regulator……………………………………………………………………….. 57 Serial Ports…………………………………………………………………………………………. 57 ArcNET……………………………………………………………………………………………... 58 Ethernet…………………………………………………………………………………………….. 58 Modem……………………………………………………………………………………………… 58 Memory Maps……………………………………………………………………………………… 59 Environmental Specifications………………………………………………………………..…… 62 Configuration……………………………………………………………………………………….. 62 Construction………………………………………………………………………………………... 62 IoP1…………………………………………………………………………………………………………… 63 General Description……………………………………………………………………………………..63 Links……………………………………………………………………………………………………… 63 Connections………………………………………………………………… ………………………….. 63 Termination Board I/O Interface………………………………………………………………………. 63 LEDs……………………………………………………………………………………………………... 63 Board Drawing List……………………………………………………………………………………... 64 Technical Description…………………………………………………………………………………...64 80C188 Processor………………………………………………………………………………….64 Reset Circuit………………………………………………………………………………………... 65 Watchdog Circuit…………………………………………………………………………………... 65 Memory……………………………………………………………………………………………... 65 Communications Port……………………………………………………………………………… 65 Inputs………………………………………………………………………………………………... 65 iv DAQ Electronics, LLC Callisto RTU Technical Guide Power Requirements……………………………………………………………………………… 65 Operating System………………………………………………………………………………….. 66 Local Area Network………………………………………………………………………………... 66 Environmental Specifications…………………………………………………………………….. 66 Configuration……………………………………………………………………………………….. 66 Construction………………………………………………………………………………………... 66 Polaris………………………………………………………………………………………………………… 67 General Description……………………………………………………………………………………..67 Links……………………………………………………………………………………………………… 69 I/O Interface……………………………………………………………………………………………... 70 LEDs……………………………………………………………………………………………………... 71 Board Drawing List……………………………………………………………………………………... 72 Technical Description…………………………………………………………………………………...73 80C188 Processor………………………………………………………………………………….73 Reset Circuit………………………………………………………………………………………... 73 Watchdog Circuit…………………………………………………………………………………... 73 Memory……………………………………………………………………………………………... 73 Communications Ports……………………………………………………………………………. 75 Serial Input/Output………………………………………………………………………………… 76 Power Requirements……………………………………………………………………………… 76 Operating System………………………………………………………………………………….. 76 Protocol…………………………………………………………………....................................... 76 Local Area Network………………………………………………………………………………... 77 Environmental Specifications…………………………………………………………………….. 77 Configuration……………………………………………………………………………………….. 77 Construction………………………………………………………………………………………... 77 Fiber Optic Transceivers…………………………………………………………………………………….78 General Description……………………………………………………………………………………..78 Links……………………………………………………………………………………………………… 78 1 Port Fiber Optic Transceiver…………………………………………………………………… 78 4 Port Fiber Optic Transceiver…………………………………………………………………… 78 Connections………………………………………………………………… ………………………….. 79 1 Port Fiber Optic Transceiver…………………………………………………………………… 79 4 Port Fiber Optic Transceiver…………………………………………………………………… 79 LEDs……………………………………………………………………………………………………...80 1 Port Fiber Optic Transceiver…………………………………………………………………… 80 4 Port Fiber Optic Transceiver…………………………………………………………………… 80 Board Drawing List……………………………………………………………………………………... 80 Technical Description…………………………………………………………………………………...81 Power Requirements……………………………………………………………………………… 81 Environmental Specifications…………………………………………………………………….. 81 Construction………………………………………………………………………………………... 81 IRIG-B Demodulator………………………………………………………………………………………… 82 General Description……………………………………………………………………………………..82 Board Drawing List……………………………………………………………………………………... 83 Technical Description…………………………………………………………………………………...83 Adjustments………………………………………………………………………………………… 83 Connections………………………………………………………………………………………... 83 Specialty Boards…...………………………………………………………………………………………...84 TBI3 Analog Interface Board………………..……………………………………………………….... 84 Board Drawing List……………………………………………………………………………….... 84 TBI1 Status Interface Board………………..………………………………………………………..... 84 v DAQ Electronics, LLC Callisto RTU Technical Guide Board Drawing List……………………………………………………………………………….... 85 L5T Analog Termination Board……………………………………………………………………...... 85 Board Drawing List……………………………………………………………………………….... 85 Polaris Memory Expansion Daughter Board…………………………………………………........... 85 Board Drawing List……………………………………………………………………………….... 86 Capacitor Bank Controller Option…………………………………………………………………...... 86 Capacitor Bank Controller Board………………………………………………………………… 86 Board Drawing List………………………………………………………………………....... 87 Capacitor Bank Driver Board……………………………………………………………………... 87 Board Drawing List………………………………………………………………………....... 87 Power Filter Board…………….………………………………………………………………….......... 88 Isolation……………………………………………………………………………………………... 88 Environmental Specifications…………………………………………………………………….. 88 Construction…………………………………………………………………………………………88 Board Drawing List……………………………………………………………………………….... 88 ► Maintenance and Troubleshooting………………………………………………………………………..….. 89 Determining Network Health……………………………………………………………………………….. 89 Communication Problems………………………………………………………………………………...... 89 Incorrect Protocol Selected in Firmware………………………………………………………….….. 90 Incorrect Communications Parameter in Configuration……………………………………………..90 Incorrect Station Address……………………………………………………………………………… 90 Crystal OSC1 Not Installed……………………………………………………………………………. 90 Bad IoE1 or Polaris Module…………………………………………………………………………… 90 Other Communication Problems……………………………………………………………………… 90 Control Outputs Not Operating…………………………………………………………………………….. 91 Command Inhibit Switch……………………………………………………………………………….. 91 Incorrect Configuration………………………………………………………………………………….91 Bad IoC1………………………………………………………………………………………………… 91 Bad IoCT or Ribbon Cable…………………………………………………………………………….. 91 Status Inputs Not Operating………………………………………………………………………………...92 Analog Inputs Not Operating………………………………………………………………………………..92 Analogs Not Reporting…………………………………………………………………………………. 92 Incorrect Values Reported for Physical Inputs………………………………………………………. 93 Calculated Analog Point Values Are Incorrect…………………………………………………………… 93 Configuration Will Not Download………………………………………………………………………….. 94 Customer Service Information……………………………………………………………………………... 94 Limited Equipment Warranty………………………………………………………………………….. 94 Service Warranty……………………………………………………………………………………….. 94 Instructions for Obtaining Equipment Service……………………………………………………….. 94 Field Service…………………………………………………………………………………………….. 95 vi DAQ Electronics, LLC Callisto RTU Technical Guide DAQ Board Drawings ► Board Diagrams………………………………………………………………………………………………….. 96 Motherboards…………………………………………………………………………………………………96 DXC21 Motherboard Assembly Diagram, DAQ DWG: #16915………………………………….... 96 DXC21 Motherboard Schematic Diagram, DAQ DWG: #16912…………………………………... 97 DXC10 Motherboard Assembly Diagram, DAQ DWG: #17032………………………………........99 DXC10 Motherboard Schematic Diagram, DAQ DWG: #17029…………………………………... 100 Analog Processing…………………………………………………………………………………………...101 IoA1 Assembly Diagram, DAQ DWG: #16846………………………………………………………. 101 IoA1 Schematic Diagram, DAQ DWG: #16843………………………………………………………102 IoAT1 Assembly Diagram, DAQ DWG: #16851…………………………………………………….. 107 IoAT1 Schematic Diagram, DAQ DWG: #16848……………………………………………………. 108 IoAT2 Assembly Diagram, DAQ DWG: #17027…………………………………………………….. 109 IoAT2 Schematic Diagram, DAQ DWG: #17024……………………………………………………. 110 Command Processing………………………………………………………………………………………. 111 IoC1 Assembly Diagram, DAQ DWG: #16900……………………………………………………….111 IoC1 Schematic Diagram, DAQ DWG: #16897……………………………………………………... 112 IoCT2 Assembly Diagram, DAQ DWG: #16895…………………………………………………….. 118 IoCT2 Schematic Diagram, DAQ DWG: #16892……………………………………………………. 119 IoCT3 Assembly Diagram, DAQ DWG: #A20042……………………………………………………120 IoCT3 Schematic Diagram, DAQ DWG: #A20043………………………………………………….. 121 IoCT5 Assembly Diagram, DAQ DWG: #B23485…………………………………..………….…… 122 IoCT5 Schematic Diagram, DAQ DWG: #B23484………………………………………………….. 123 Status Processing…………………………………………………………………………………………… 125 IoD1 Assembly Diagram, DAQ DWG: #16905……………………………………………………….125 IoD1 Schematic Diagram, DAQ DWG: #16902……………………………………………………... 126 IoDT1 Assembly Diagram, DAQ DWG: #16890…………………………………………………….. 132 IoDT1 Schematic Diagram, DAQ DWG: #16887……………………………………………………. 133 IoDT2 Assembly Diagram, DAQ DWG: #A24406…………………………………………………... 134 IoDT2 Schematic Diagram, DAQ DWG: #A24405………………………………………………….. 135 Communication Processing…………………………………………………………………………………136 IoE1 Assembly Diagram, DAQ DWG: #16910………………………………………………………. 136 IoE1 Schematic Diagram, DAQ DWG: #16907………………………………………………………137 IoE2 Assembly Diagram, DAQ DWG: #001-2900…………………………………………………... 143 IoE2 Schematic Diagram, DAQ DWG: #A24249……………………………………………………. 144 IoET1 Assembly Diagram, DAQ DWG: #17007…………………………………………………….. 154 IoET1 Schematic Diagram, DAQ DWG: #17004……………………………………………………. 155 Parallel Processing………………………………………………………………………………………….. 156 IoP1 Assembly Diagram, DAQ DWG: #17176………………………………………………………. 156 IoP1 Schematic Diagram, DAQ DWG: #17173………………………………………………………157 IoPT1 Assembly Diagram, DAQ DWG: #18544…………………………………………………….. 163 IoPT1 Schematic Diagram, DAQ DWG: #18541……………………………………………………. 164 Single Board Communication, Status, Command Processing…………………………………………. 165 Polaris Assembly Diagram, DAQ DWG: #16841……………………………………………………. 165 Polaris Schematic Diagram, DAQ DWG: #16838……………………………………………………166 Polaris Termination Assembly Diagram, DAQ DWG: #16965…………………………………….. 176 Polaris Termination Schematic Diagram, DAQ DWG: #16962……………………………………. 177 vii DAQ Electronics, LLC Callisto RTU Technical Guide Fiber Optic Transceivers…………………………………………………………………………………….181 1 Port Fiber Optic Transceiver Assembly Diagram, DAQ DWG: #17151………………………… 181 1 Port Fiber Optic Transceiver Schematic Diagram, DAQ DWG: #17148……………………….. 182 4 Port Fiber Optic Transceiver Assembly Diagram, DAQ DWG: #17156…………………………183 4 Port Fiber Optic Transceiver Schematic Diagram, DAQ DWG: #17153……………………….. 184 Real Time Interface…………………………………………………………………………………………. 185 IRIG-B Demodulator Assembly Diagram, DAQ DWG: #19948…………………………………….185 IRIG-B Demodulator Schematic Diagram, DAQ DWG: #19949……………………………………186 Specialty Boards…...………………………………………………………………………………………...187 TBI3 Analog Interface Board Schematic Diagram, DAQ DWG: #17019……………………........ 187 TBI1 Status Interface Board Assembly Diagram, DAQ DWG: #17012………………………....... 188 TBI1 Status Interface Board Schematic Diagram, DAQ DWG: #17009……………………......... 189 L5T Analog Termination Board Assembly Diagram, DAQ DWG: #A20106………………........... 190 L5T Analog Termination Board Schematic Diagram, DAQ DWG: #A20107…………………...... 191 Polaris Memory Expansion Assembly Diagram, DAQ DWG: #A20472…………………............. 193 Polaris Memory Expansion Schematic Diagram, DAQ DWG: #A20473…………………............ 194 Capacitor Bank Controller Option…………………………………………………………………...... 195 Capacitor Bank Controller Board Assembly Diagram, DAQ DWG: #19550………………… 195 Capacitor Bank Controller Board Schematic Diagram, DAQ DWG: #19547………………...196 Capacitor Bank Driver Board Assembly Diagram, DAQ DWG: #19698…………………...... 199 Capacitor Bank Driver Board Schematic Diagram, DAQ DWG: #19699……………….........200 Power Filter Board, Assembly Diagram, DAQ DWG: #ACB-08510………………………............ 201 Power Filter Board, Schematic Diagram, DAQ DWG: #A24340…………………………............. 202 viii DAQ Electronics, LLC Callisto RTU Technical Guide ► Introduction ► General Description DAQ’s Callisto series of RTUs is driven by the requirements for advanced applications in Supervisory Control and Data Acquisition (SCADA), Distribution Automation, and Load Monitoring in the electric utility industry. Features include:  Distributed LAN-based multiprocessor architecture  Advanced power system measurements  Flexible packaging  Extensive user configuration capabilities  Modular, expandable design  Truly detachable protocols  Industry standard interfaces  Time tagged sequence of events with a resolution to 1 millisecond  GPS interface for system-wide time base  Real-time, multi-tasking operating system  Remote diagnostic facilities  Local Windows MMI option Emerging substation automation projects mandate an advanced programmable logic capability, which has been incorporated into the Callisto remote system. Additionally, the unit is capable of importing executable code written off-line in "C" for higher-level applications. In addition to supporting "conventional" SCADA inputs and directly coupled analog inputs, Callisto readily supports serial data exchanges from a wide range of intelligent devices at the remote station location. ► Architecture Callisto can be viewed as a combination of closely coupled processing nodes residing on an industry standard ArcNET LAN and loosely coupled nodes connected through LAN resident serial processing nodes. Callisto processing nodes include:  IoA1 - analog input  IoC1 - command output  IoD1 - status input  IoE1 - communication 1 DAQ Electronics, LLC Callisto RTU Technical Guide  IoE2 - communication  IoP1 - parallel data These processing nodes are packaged to mount in an industry standard card bin. Each node is built with two 64 pin DIN connectors. The boards slide into the card bin and their upper 64 pin DIN connector (P1) connects to a common motherboard. The motherboard distributes power and allows for interboard communications. Each node interfaces to field device input and output signals through their second 64 pin DIN connector. This signal interface connection is via the processing node’s termination board(s). The IoE1 / IoE2 termination board (IoET1) is mounted onto the card bin and the P2 connector of the IoE1 / IoE2 plugs directly into the termination board. The termination boards for all other processing nodes are mounted separate from the card bin and interfaced to their processing nodes via a 64 pin ribbon cable. The Polaris processing node is used for small point count applications, such as pole top RTUs. It combines communications, status inputs, and command outputs into a single node. Unlike the other processing nodes, the Polaris does not mount in a card bin; it is meant to be panel mounted. The Polaris plugs directly into its termination board, the Polaris Termination board. An IoA1 processing node can be added if analog inputs are needed. The Polaris Termination board is equipped to handle nine analog input points. Callisto processing nodes or complete RTUs can be networked together in a point-to-point or star configuration and connected via RS-485 cabling or fiber optics. This allows a “host“ RTU to communicate with “slave” RTUs. ► Local Area Network The Callisto LAN system (ArcNET) provides a number of advantages:  Flexible transmission media, providing for combinations of simple "backplane" and distributed RS485 or fiber optic operation  High-speed operation at 2.5 Mbit/sec  Deterministic token passing protocol  Availability of cost effective VLSI LAN module with in-built micro controller interface  Availability of PC connectivity modules  Automatic network reconfiguration where nodes are added or removed Deterministic LAN performance is a pre-requisite for distributed electric utility SCADA applications that call for 1 millisecond resolution of system events across network resident processing nodes. ► Voyager Callisto nodes residing on the ArcNET LAN communicate via DAQ Voyager protocol, which has been specifically designed to support advanced SCADA data acquisition/commands, configuration, and diagnostic exchanges across node resident processors. 2 DAQ Electronics, LLC Callisto RTU Technical Guide ► Processing Nodes The Callisto series of remotes consists of a family of processing node boards, which communicate with each other over a high-speed local area network (LAN). Each processing node has different functionality and can be interfaced to up to four termination boards that allow for interfacing to field devices. Each board carries a highly integrated 16 bit 80C188 embedded processor. Input signal conditioning, processing, and initial data storage occurs at the local processing node level. Each board provides for 4 Kbits EPROM, 32 Kbytes EPROM, 128 Kbytes Flash memory, and 128 Kbytes RAM. The generic names of the various Callisto processing node and associated termination boards are shown in the table below. Different board build options are available and are indicated by a dash number after the part number of the board. Processing Node Board IoA1 IoC1 IoD1 IoE1 IoE2 IoP1 Polaris Processing Nodes Termination Board IoAT1, IoAT2 IoCT2, IoCT3 IoDT1 IoET1 IoET1 IoPT1 Polaris Termination Function Analog inputs Control outputs Digital inputs Communication interface Communication interface Parallel I/O *(9) Analog & (16) Digital inputs, (4) Control outputs, (4) Communication ports *to accommodate analog input points, the IoA1 board must be combined with the Polaris and Polaris Termination boards. ■ IoA1 Analog Input Processing Node The IoA1 supports up to 32 analog inputs, which may originate from conventional DC instrumentation sources or directly coupled AC power system devices. A dynamic dead band software filter is incorporated for each input to avoid "nuisance" signal swings, while maintaining instant reporting of limit excursions. A 50 MHz DSP and two high-speed, signed 12 bit A/D converters enable directly coupled AC inputs to be continuously sampled at a rate of 32 readings per cycle. True RMS values at 0.2% accuracy are computed for:  Voltage per phase  Current per phase  Neutral current  Power per phase and 3-phase  Reactive power per phase and 3-phase  Apparent power per phase and 3-phase  Power factor per phase and 3-phase An FFT algorithm is used to compute the harmonic content of each AC input on a periodic basis to provide each of the 2nd through 15th harmonic for all of the physically presented AC inputs at the node. KWHr and KVAHr values are computed for each input circuit on a phase and 3-Phase basis. 3 DAQ Electronics, LLC Callisto RTU Technical Guide Limited digital fault recording capability is provided for each current input. A 50 cycle register containing 16 samples per cycle is maintained in a circular buffer. A processed or external trigger initiates a pre-defined "runon" period for the data, thus permitting a pre and post trigger history on the input waveform. Additionally, an analog limit excursion algorithm is provided to identify timed peak and duration excursions outside user-defined bands. The IoA1 processing node also runs fault detection/fault direction algorithms. Specific algorithms are written offline and downloaded to the node via Voyager LAN protocol. Full functionality of the IoA1 module restricts the number of directly coupled AC inputs to 24 currents (8 feeders) and 6 voltages to allow for split voltage feeder rows. The current inputs may be utilized for dual range processing, with the second range providing up to 20 times full load. For such requirements, the number of physical current connections is limited to 12 (4 feeders), again with up to 6 associated voltages. ■ IoC1 Command Output Processing Node The IoC1 supports up to 32 command relay outputs. These outputs are configurable for 16 on/off pairs with select-check-execute protection or as 32 direct operate commands. Direct operate commands may be controlled individually or in parallel blocks, as required. Command pulse durations are user definable on a per point basis. Direct operate commands can also be utilized for Raise/Lower controls with the output relay operate time loaded as part of the command message. ■ IoD1 Status Input Processing Node The IoD1 supports up to 32 status/alarm inputs with 1 millisecond time tagged sequence of events recording. User-definable debounce, anti-toggle filtering, and multiple change detection are incorporated on each module. Any status points may be configured to be an accumulator input point. However, Form-C accumulators must be configured on consecutive status input points with the first of those points being an even numbered point (zero being the first point on the RTU). ■ IoE1 Serial Communication Processing Node The IoE1 can be equipped with up to four communication ports. These data ports may be physically presented as either RS-232, RS-485, 202T modem or a dial-up modem channel. The IoE1 is used for data exchange with master stations, intelligent meters, instruments or relays, or other intelligent electronic devices (IEDs) distributed across the Callisto system. Other applications for the IoE1 include:  Multi-port communications with master station(s) using differing protocols  Communication with remotely sited satellite RTUs (outside plant) over modem lines, radio, fiber, packet radio, or dial-up networks  Support of a local station printer for alarm logging and SOE recording  Interface to a Real Time Clock or Global Positioning System (GPS) 4 DAQ Electronics, LLC Callisto RTU Technical Guide ■ IoE2 Serial Communication Processing Node As the second generation serial processing node for the Callisto series of remotes, the IoE2 carries four serial data ports, and an IP Ethernet connection. Serial ports may be physically presented as either RS-485 or RS-232 circuits. Communications options supported include both byte and bit oriented protocols. When used to replace or upgrade an IoE1, a Bell 202 modem may be plugged into port 1. The IoE2 may be utilized for serial data exchange with master station(s), intelligent meters, relays, or other intelligent electronic devices (IEDs) distributed across the Callisto system. Like all Callisto boards, the IoE2 utilizes ArcNET technology and DAQ Voyager protocol to interface to the internal high speed LAN. Other applications for the IoE2 include:  Multi-port and IP communications with master station(s) using differing protocols  Communication with remotely sited satellite RTUs over modem lines, radio, fiber, packet radio, or dial-up networks  Support of a local station printer for alarm logging and SOE recording  Interface to a Real Time Clock or Global Positioning System (GPS)  Historical File Storage for retrieval using FTP (File Transfer Protocol) ■ IoP1 Parallel Data Processing Node The IoP1 provides for a general purpose 32-way parallel digital signal plant interface, which is user-assignable for inputs or outputs in blocks of 8 points. Signal conditioning is implemented on the termination modules for TTL, CMOS, or relay isolation input/outputs with an additional output option for Darlington drivers. Typical IoP1 applications include unit controller interfaces, transformer tap changer interfaces, as well as an input/output facility for local display/control panels. ► Operating System The Callisto series of processing nodes all operate under the industry standard, preemptive Nucleus time-sliced real time multitasking operating system. This allows for integration of any algorithms or applications that are created under the Nucleus guidelines. Users may simply write their own "C" code off-line with the operating system, and download it to the RTU. Because the operating system is present on all modules, porting of any Callisto application from one unit to another is transparent. ► Configuration CallistoView (CALVIEW), DAQ’s Windows based PC editor, provides for extensive user configurability of the Callisto RTU. The configuration data that is created can be downloaded to the Callisto RTU via a RS-232 serial port. Configuration functions are entered via a series of dialog boxes from which users are able to create and edit RTU parameters, point descriptors, logic applications, and math functions. In addition to an extensive range of Boolean constructs, the logic editor supports a library of macro functions, such as breaker Recloser, Volt/VAR control, etc., which may be called up as editable applications without recourse to the lower logic module levels. Arithmetic computations can be declared using double precision 32 integer math conforming to IEEE floating point standards. 5 DAQ Electronics, LLC Callisto RTU Technical Guide ► Industry Standard Interfaces The entire family of Callisto processing nodes is designed around industrial grade double EuroCard modules with highly reliable 64 pin DIN plug and socket connectors. ► Power System Calculations The gathering of analog data on the IoA1 card is controlled by an ADDS 2101 DSP processor. The card accepts 32 analog inputs. However, currents can generate two inputs each: one normal current and one over current. In such configurations, the system provides a capacity of four 3-phase circuits, having a maximum of 12 phase currents, and 12 over currents. These are combined with the appropriate voltages to yield 24 volt/current pairs, or 48 measurements, in total. In addition, one phantom input pair is included, making a total of 50 measurements. Upon timer interrupt, the 2101 acquires the current readings from two A/D converters, then supplies the analog mux address latches with the addresses of the supra-next points to be converted. Loading the first latch of a cascaded pair of latches starts the conversion cycle. When the A/D converters complete their sampling phase, the A/D "start conversion" signal causes the supra-next addresses to fall into the second latches of the cascaded latch pairs. The 2101 uses an internal timer to generate the interrupts. The A/D completion interrupt is not used. The 2101 takes 25 pairs of read-ins, as described above, 32 times each AC cycle, for a total of 1600 readings. The buffer for these readings is 3200 words in length, and can thus hold two full cycles of data. The two parts of the buffer are "ping-ponged", with new data being written into one half, while calculations occur in the other half. Calculations are done in eight segments, with each segment producing the results for the 3-phases of one feeder. Each segment consists of 13 passes through the data. The first six passes do the time alignment of the data for voltage and current of each of 3-phases. These passes correct for the fact that the 3-phase voltages and currents are not sampled simultaneously. If the sampling is done in ABC order, for example, then at the time the phase C readings are taken, the phase A readings are 41.6 microseconds old, and the phase B readings are 20.8 microseconds old. Thus, the phase C readings need to be "backed up" by 41.6 microseconds. This is accomplished by adding 41.6/520.8 or the previous phase C reading (taken 520.8 microseconds earlier) and 489.2/520.8 or the current reading. Phase B is similarly corrected. This is simple linear interpolation. However, the worst case error (near 90 degrees) is only 0.15 percent, and the average error is 0.08 percent, compared to an average error of 0.17 percent when no correction is applied. Note that the correction is independent of frequency. Also, during this operation, amplitude and phase corrections are applied to each input, and the corrected outputs for each phase are developed. The integrated and double integrated inputs are also computed. The phase correction is accomplished by summing A * previous reading + B * current reading + C * integrated value + D * double integrated reading. The constants A, B, C, and D are individually computed for each input. This is done by the compiler program in the laptop, and permits entry of the line post manufacturer's calibration data. The algorithm is capable of correcting for two cascaded zeros. The corrected currents are also summed to obtain the neutral current. This operation generates 192 intermediate results. The next seven passes produce the 1-cycle results for each phase. The outputs are: 1. Summation voltage squared 2. Summation current squared 3. Summation current * voltage (watts) 4. Fundamental voltage, real part 5. Fundamental voltage, quadrature part 6 DAQ Electronics, LLC Callisto RTU Technical Guide 6. Fundamental current, real part 7. Fundamental current, quadrature part. The in phase and quadrature components of the fundamental E and I are measured with respect to a fictitious, invariant sine wave. The same fictitious wave is used for all three phases, so that the exact angles between phases can computed, if desired. 7 DAQ Electronics, LLC Callisto RTU Technical Guide ► Hardware ► Motherboards ■ General Description The Callisto series of processing node boards communicate with each other and their host node over an ArcNET network. The IoX processing nodes (IoA1, IoC1, etc.) within a single, physical RTU interface to the LAN and their power source via a motherboard. There are three Callisto motherboards: the DXC10, which is capable of directly interfacing 10 IoX processing node boards, the DXC15, which can accommodate a total of 15 boards, and the DXC21, which can accommodate 21. Motherboards are mounted to the rear back plane of a standard EuroCard bin of 10, 15, and 21 positions, respectively. The IoX processing node boards slide into the card bin and interface to the installed motherboard. Motherboards accomplish three basic functions: 1. Distribute DC voltages for Callisto processing node boards 2. Provide ArcNET communication connections between processing node boards 3. Achieve a packaged installation for implementing processing node boards within a Callisto RTU ■ Links The Node, Group, and Station jumper links have a binary weighted value that achieves the desired address (1, 2, 4, 8, 16, 32, 64, 128). These addresses are equal to the sum of the decimal values associated with the installed jumpers on each LK link. For example, if LK2 has jumpers installed across positions 2, 8 and 32, the board plugged into motherboard position 2 will have a node address of 42 (2 + 8 + 32 = 42). DXC10 The DXC10 has 18 jumper links numbered LK1 through LK18, as defined below: Connector Location P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 Node Link # LK1 LK2 LK3 LK4 LK5 LK6 LK7 LK8 LK9 LK10 DXC10 Links Group Link # N/A LK11 N/A LK12 N/A LK13 N/A LK14 N/A N/A 8 Station Link # N/A LK15 N/A LK16 N/A LK17 N/A LK18 N/A N/A DAQ Electronics, LLC Callisto RTU Technical Guide DXC15 The DXC15 has 23 jumper links numbered LK1 through LK 15 and LK22 through LK29, as defined below: Connector Location P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 Node Link # LK1 LK2 LK3 LK4 LK5 LK6 LK7 LK8 LK9 LK10 LK11 LK12 LK13 LK14 LK15 DXC15 Links Group Link # N/A LK22 N/A LK23 N/A LK24 N/A LK25 N/A N/A N/A N/A N/A N/A N/A Station Link # N/A LK26 N/A LK27 N/A LK28 N/A LK29 N/A N/A N/A N/A N/A N/A N/A DXC21 The DXC21 has 29 jumper links numbered LK1 through LK29, as defined below: Connector Location P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 Node Link # LK1 LK2 LK3 LK4 LK5 LK6 LK7 LK8 LK9 LK10 LK11 LK12 LK13 LK14 LK15 LK16 LK17 LK18 LK19 LK20 LK21 DXC21 Links Group Link # N/A LK22 N/A LK23 N/A LK24 N/A LK25 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 9 Station Link # N/A LK26 N/A LK27 N/A LK28 N/A LK29 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A DAQ Electronics, LLC Callisto RTU Technical Guide ■ Connections The DXC10, DXC15, and DXC21 interface to the IoX processing node boards via 64 pin connector sockets located on the front of the motherboard (note that the Polaris board does not interface with a motherboard, but directly interfaces with its own termination board). These connectors are identified as P1 through P10 for the DXC10, P1 through P15 for the DXC15, and P1 through P21 for the DXC21. Node designation jumper links set the physical node assignment for each processor. This node assignment address will be used to configure the overall Callisto RTU. Provisions to designate Group and Station numbers for IoE1 serial processing nodes are available for four of the connector sockets (locations P2, P4, P6, and P8). If an RTU contains several IoE1 boards that will communicate with a master station, they must be installed into one of these connector slots. IoE1 nodes that communicate with slave devices such as IEDs, meters, or serial printers may be installed in any connector slot. Note that an IoE1 board will occupy not only its slot within the card bin but also half of the slot to its right and left. This is due to the physical size of the IoE1 termination board, the IoET1. DXC10 There are a total of four terminal blocks (TB1 - TB4) and one connector (P11) located on the rear of the DXC10 motherboard, as defined below: Terminal blocks TB1 and TB2 are used for input power and are located at opposite ends of the motherboard for convenience. These terminal blocks allow connection of the DC voltages (0V, +5V, -12V, +12V) produced by external power supplies, thus powering the Callisto boards located within the card bin. Voltage connections can be routed to either terminal block. TB1 and TB2 Terminal Position 1 2 3 4 Voltage GND (0 VDC) +5 VDC -12 VDC +12 VDC Terminal block TB3 allows for an external ArcNET connection to one or more motherboards, providing communication to other Callisto processing node boards housed in additional EuroCard bins. The signals available on this terminal block include: TB3 Terminal Position 1 2 3 4 Signal ArcArc+ Txend 0 VDC Terminal block TB4 is used for Command Enable/Inhibit and allows an external switch to be connected to the DXC10. Using this switch, the user can enable or disable command outputs from IoC1 boards located on the ArcNET network. 10 DAQ Electronics, LLC Callisto RTU Technical Guide TB4 Terminal Position 1 2 Signal CMD INH +12 VDC A DB9-F nine-pin female connector, P11, is installed to accommodate an additional connection scheme to the ArcNET signals. A fiber-optic card, either one-port or four-ports, can be interfaced at this location. Connection to a fiber-optic board will allow extension of the ArcNET LAN to remotely located Callisto-based RTUs. P11 Connector Pin 1 2 3 4 5 6 7 8 9 Signal Txend Arc+ ArcNo connection No connection +12 VDC -12 VDC +5 VDC 0 VDC Each DXC10 Motherboard has an 820 ohm ArcNET pull-up resistor (R2) and an 820 ohm pull-down resistor (R1), which requires LK20 and LK19, respectively, to be installed. DXC15 There are a total of six terminal blocks and one connector (DB1) located on the rear of the DXC15 motherboard, as defined below: Terminal blocks TB1 through TB4 are used for input power. These terminal blocks allow connection of the DC voltages (0V, +5V, -12V, +12V) produced by external power supplies, thus powering the Callisto boards located within the card bin. Voltage connections can be routed to any of these terminal blocks. TB1 through TB4 Terminal Position 1 2 3 4 Voltage GND (0 VDC) +5 VDC -12 VDC +12 VDC The TB6 terminal block allows for an external ArcNET connection to one or more motherboards, providing communication to other Callisto processing node boards housed in additional EuroCard bins. The signals available on these terminal blocks include: 11 DAQ Electronics, LLC Callisto RTU Technical Guide TB6 Terminal Position 1 2 3 4 Signal ArcArc+ Txend 0 VDC The TB8 terminal block is used for Command Enable/Inhibit and allows an external switch to be connected to the DXC15. Using this switch, the user can enable or disable command outputs from IoC1 boards located on the ArcNET network. TB8 Terminal Position 1 2 Signal CMD INH +12 VDC A nine-pin female connector, DB1, is installed to accommodate an additional connection scheme to the ArcNET signals. A fiber-optic card, either one-port or four-ports can be interfaced at this location. Connection to a fiber-optic board will allow extension of the ArcNET LAN to remotely located Callisto based RTUs. DB1 Connector Pin 1 2 3 4 5 6 7 8 9 Signal Txend Arc+ ArcNo connection No connection +12 VDC -12 VDC +5 VDC 0 VDC Each DXC15 motherboard has an 820 ohm ArcNET pull-up resistor and an 820 ohm pull-down resistor installed on the rear of the PCB. DXC21 There are a total of nine terminal blocks (TB1 - TB9) and one connector (DB1) located on the rear of the DXC21 motherboard, as defined below: Terminal blocks TB1 through TB5 are used for input power. These terminal blocks allow connection of the DC voltages (0V, +5V, -12V, +12V) produced by external power supplies, thus powering the Callisto boards located within the card bin. Voltage connections can be routed to any of these terminal blocks. 12 DAQ Electronics, LLC Callisto RTU Technical Guide TB1 through TB5 Terminal Position 1 2 3 4 Voltage GND (0 VDC) +5 VDC -12 VDC +12 VDC Terminal blocks TB6 and TB7 allow for an external ArcNET connection to one or more motherboards, providing communication to other Callisto processing node boards housed in additional EuroCard bins. The signals available on these terminal blocks include: TB6 and TB7 Terminal Position 1 2 3 4 Signal ArcArc+ Txend 0 VDC Terminal blocks TB8 and TB9 are used for Command Enable/Inhibit and allow an external switch to be connected to the DXC21. Using this switch, the user can enable or disable command outputs from IoC1 boards located on the ArcNET network. TB8 and TB9 Terminal Position 1 2 Signal CMD INH +12 VDC A nine-pin female connector, DB1, is installed to accommodate an additional connection scheme to the ArcNET signals. A fiber-optic card, either one-port or four-ports can be interfaced at this location. Connection to a fiber-optic board will allow extension of the ArcNET LAN to remotely located Callisto based RTUs. DB1 Connector Pin 1 2 3 4 5 6 7 8 9 Signal Txend Arc+ ArcNo connection No connection +12 VDC -12 VDC +5 VDC 0 VDC Each DXC21 motherboard has an 820 ohm ArcNET pull-up resistor (R2) and an 820 ohm pull-down resistor (R1) installed on the rear of the PCB. 13 DAQ Electronics, LLC Callisto RTU Technical Guide ■ I/O Interface The DXC10, DXC15, and DXC21 motherboards do not directly interface to input or output points. Each processing node board that plugs into a motherboard will interface to its associated termination board via its own P2 connector, which is physically located below the P1 connector that interfaces to the motherboard. P2 connectors on the IoA1, IoC1, and IoD1 interface to termination boards via a 64 pin ribbon cable, while the P2 connector on the IoE1 interfaces directly into the termination board. ■ Board Drawing List The following motherboard drawings are included in this manual for reference purposes: Board Name DXC10 DXC21 DXC10 and DXC21 Drawings Assembly Diagram DAQ Drawing #17032 DAQ Drawing #16915 ■ Technical Description Environmental Specifications Operating range: Storage range: Relative humidity: Vibration: -20 to +70°C -20 to +70°C 5 to 95% non-condensing 5 to 65Hz Construction DXC10: DXC15: DXC21: 7.925” x 5.10” 11.75” x 5.10” 16.725” x 5.10” 14 Schematic Diagram DAQ Drawing #17029 DAQ Drawing #16912 DAQ Electronics, LLC Callisto RTU Technical Guide ► IoA1 ■ General Description As the analog processing node for the Callisto series of remotes, the IoA1 multiplexes up to 32 analog inputs from termination boards. These inputs may be from conventional DC instrumentation sources, directly coupled AC power system devices, or line post sensors. A 50 MHz DSP processes the AC inputs to provide true RMS power system measurements at 0.2% accuracy for:  Voltage per phase  Current per phase  Power per phase and three phase  Reactive power per phase and three phase  Apparent power per phase and three phase  Power factor per phase and three phase  Neutral current Dual high speed, signed 12 bit A/D converters allow for simultaneous sampling of both voltage and current, thus eliminating the skew associated with single A/D converter designs. Directly coupled AC inputs are continuously sampled at a rate of 32 readings per cycle and an FFT algorithm is used to compute the harmonic content of each AC input on a periodic basis. This provides harmonic content and RMS calculation accuracy through the 15th harmonic on all AC inputs physically presented at the node. KWHr and KVAHr values are computed for each input circuit on a phase and three phase basis. Limited digital fault recording capability is provided for each current input. A 50 cycle register containing 16 samples per cycle is maintained in a circular buffer. A processed or external trigger initiates a pre-defined "runon" period for the data, thus permitting a pre and post trigger history of the input waveform. Additionally, an analog limit excursion algorithm is provided to identify timed peak and duration excursions outside user-defined bands. Like all Callisto modules, the IoA1 utilizes ArcNET technology and DAQ's Voyager protocol to interface to the high speed LAN. Additionally, the industry standard Nucleus real-time, multi-tasking operating system allows for user-defined applications and algorithms to be easily incorporated into the unit. The IoA1 processing node also runs fault detection/fault direction algorithms. Specific algorithms are written off-line and downloaded to the node via the Voyager LAN protocol under the guidelines of Nucleus. 15 DAQ Electronics, LLC Callisto RTU Technical Guide LAN ArcNET Memory IoA 80188 Additional Callisto Modules DSP I/O 32 Analog Inputs Full functionality of the IoA1 module restricts the number of directly coupled AC inputs to 24 currents (8 feeders) and 6 voltages to allow for split voltage feeder rows. The current inputs may be utilized for dual range processing with the second range up to 20 times full load. For such requirements, the number of physical current connections is limited to 12 (4 feeders), again with up to 6 associated voltages. +5, +12, -12 VDC P1 IoA Address ArcNET Interface FIFO DSP and Support Latch RAM CPU and Support A/D 32 Input Mux P2 Memory A/D 32 Input Mux ■ Links The Watchdog circuit is always installed unless debugging with emulator. LK2 enables/disables the Watchdog timer as follows: In = Enabled Out = Disabled 16 DAQ Electronics, LLC Callisto RTU Technical Guide ■ Connections P1: 64 Pin DIN connector supporting power and ArcNET connections P2: 64 Pin DIN connector supporting 32 analog input signals via analog termination boards ■ Termination Board I/O Interface There are two types of Callisto series analog termination boards, the IoAT1 and the IoAT2. Both boards interface with the IoA1 via a ribbon cable (note that the same IoA1 analog processing node can not interface with both IoAT1 and IoAT2 boards). The IoAT1 accepts both AC and DC input signals and handles up to nine inputs per termination board. The IoAT2 accepts only DC input signals and handles up to eight inputs per termination board. For information on connecting SLD-type terminal blocks to IoAT boards, see “TBI3 Analog Interface Board” in the Specialty Board section of this manual. For information on grounding unused IoA1 inputs, see “L5T Analog Termination Board” also in the Specialty Board section of this manual. The IoA1 P2 connector interfaces with up to four IoAT1 or IoAT2 termination boards. The termination boards condition the analog inputs and pass the signals through the P2 connector to the IoA1 multiplexors. The IoA1 can measure a variety of analog input types. When interfaced to an IoAT1 termination board, the IoA1 can measure either DC or AC inputs. The IoAT1 board can interface to nine points per board. The inputs may originate from current transformers (CT), potential transformers (PT), current or voltage line post sensors, DC transducers, or other AC/DC output sources. The IoAT1 is equipped with a removable platform assembly for each input point (the assembly is referred to as an analog termination configuration platform assembly). The configuration and components on the platform varies depending upon the desired input point to be measured. The IoAT2 allows for the measuring of eight DC analog signals per board. Specifically, it can measure +/- 1 mA DC, 4-20 mA DC, or 0-5 VDC. Like the IoAT1, the IoAT2 allows for different input point types on a per point basis. The following table summarizes the input point signal capability of both the IoAT1 and IoAT2 boards. In addition to those listed, other special case input signals may be measured (consult DAQ for confirmation of your specific requirements). 17 DAQ Electronics, LLC Callisto RTU Technical Guide Input Point Signal Capability IoAT1 0-69 VAC 0-150 VAC 0-220 VAC 0-5 A AC 0-15 mV DC 0-30 mV DC 0-1 VDC +/- 1 VDC 0-5 VDC 0-10 VDC 0-15 VDC 0-30 VDC 0-48 VDC 0-150 VDC +/- 1 mA DC 1-5 mA DC 4-20 mA DC Square D Current or Voltage Line Post Sensor Lindsey Current or Voltage Line Post Sensor S & C Current or Voltage Line Post Sensor IoAT2 0-1 mA DC +/- 1 mA DC 4-20 mA DC 0-5 VDC ■ LEDs There are 10 LEDs that protrude through the front panel indicating the operational status of the unit. The 10segment LED is called “LED9”. LED9 contains eight software driven LEDs and two hardware-driven LEDs. LED 9 1 - Heartbeat 2 - DSP running 3 - On-board reconfiguration 4 - Reconfiguration by another board 5 - Fault detected 6 - Future use 7 - Future use 8 - Future use 9 - ArcNET interrupt 10 - ArcNET transmit enable 18 DAQ Electronics, LLC Callisto RTU Technical Guide IoA1 LEDs LED # 1 Description Heartbeat 2 3 4 5 6 7 8 9 10 DSP running ArcNET reconfigurations by this board ArcNET reconfigurations by another board Future use Future use Future use Future use ArcNET interrupts TX enable hardware signals Normal Operation Toggles once per second - meaning program running Always on Toggles when reconfiguration occurs Toggles when reconfiguration occurs Always off Always off Always off Always off Flashes approximately once per second Always on ■ Board Drawing List The following analog sub-system board drawings are included in this manual for reference purposes: Board Name IoA1 IoAT1 IoAT2 IoA Drawings Assembly Diagram DAQ Drawing #16846 DAQ Drawing #16851 DAQ Drawing #17027 Schematic Diagram DAQ Drawing #16843 DAQ Drawing #16848 DAQ Drawing #17024 ■ Technical Description 80C188 Processor The processor for the IoA1 board is the Intel 80C188 microcontroller (U30) providing:  8-bit data bus  20-bit address bus  2 DMA channels  Direct addressing to 1 MByte memory and 64 KBytes I/O  50 MHz Digital Signal Processor (DSP) The CMOS N80C188-16 is a 16-bit microprocessor with an 8-bit external data bus, which operates at speeds up to 16 MHz. On the IoA1, this microprocessor operates at 12.288 MHz using a 24.576 MHz crystal and can directly address up to 1 MByte of memory and 64 KBytes of I/O. The microprocessor package is the 68 pins Plastic Leaded Chip Carrier (PLCC). Reset Circuit A manual reset is provided via a switch (S1) located on the front panel of the board. Power-up reset and brownout protection is provided by a watchdog chip (U2). 19 DAQ Electronics, LLC Callisto RTU Technical Guide Watchdog Circuit LK2 enables/disables the Watchdog timer, which is located in U2. In = Enabled Out = Disabled Memory 128Kx8 Flash Memory 1Kx1 Serial EEPROM (3) 32Kx8 High Speed RAM 128Kx8 EPROM 128Kx8 RAM (U41) (U15) (U43, U44, and U45) (U31) (U36) Input Point Capabilities Each IoA1 node can measure up to 32 analog input points via up to four termination boards. The following are typical analog input signal types measured by the IoA1. Other special case input signals may be measured (consult DAQ for confirmation of your specific requirements). DC Sources Unipolar Voltage: 0-15 mV 0-30 mV 0-1V 0-5 V 0-10 V 0-15 V 0-30 V 0-48 V 0-150 V Unipolar Current: 0-1 mA 1-5 mA 4-20 mA Bipolar Voltage: +/- 1 V Bipolar Current: +/- 1 mA Analog Input Signal Types AC Sources Current: 0-5 A CT, via DAQ SPCT1 Single Phase Current Transformer Voltage: 0-69 V PT 0-150 V PT 0-220 V PT Power Requirements 410 mA @ 5 VDC 25 mA @ 12 VDC 35 mA @ -12 VDC 20 Line Post Sensors Lindsey Voltage or Current Square D Voltage or Current S & C Electric Voltage or Current DAQ Electronics, LLC Callisto RTU Technical Guide Analog to Digital Conversion Employs dual, high speed A/D Converters Resolution: Accuracy: Conversion time: Sample rate: 12 bit plus sign bit 0.2% full scale (0 to 60 degrees C) 17 microseconds / channel All inputs sampled 32 times per AC waveform @ 50Hz, 60Hz Com. mode rejection: Differential mode: Input impedance: > 80 dB > 50 dB > 1M ohm Operating System The IoA1 operating system is the industry standard Nucleus RTX real-time, multi-tasking OS allowing for simple integration of user-defined applications and algorithms. Local Area Network The LAN protocol is DAQ Voyager protocol operating over a standard ArcNET Local Area Network at speeds up to 2.5 megabits per second. Environmental Specifications Operating range: Storage range: Relative humidity: Vibration: -20 to +70°C -20 to +70°C 5 to 95% non-condensing 5 to 65Hz Configuration IoA1 configuration is accomplished through its Callisto host node using DAQ CallistoView (or CALVIEW) Windows configuration utility. Construction Standard 4 layer Double EuroCard printed circuit board (PCB) 6.25" x 9.25" (160 mm x 235 mm) 21 DAQ Electronics, LLC Callisto RTU Technical Guide ► IoC1 ■ General Description As the command processing node for the Callisto series of remotes, the IoC1 controls up to 32 command relay outputs, which are configurable for 16 on/off pairs with select-check-execute protection, 16 latch/reset relays, or as 32 direct operate commands. Direct operate command output points may be controlled individually or in four parallel blocks. Momentary command pulse durations are user-definable on a per point basis. Controls can also be utilized for a Raise/Lower function, with the output relay operate time loaded as part of the command message. Relays may be mounted on the IoC1 board or on an IoCT command termination board. The switching capacity of the output relay contacts varies depending upon the build option selected. The following relay output contact ratings are available as standard options. In addition to those listed, other special case relays may be utilized (consult DAQ for confirmation of your specific requirements). Relay Output Contact Ratings Momentary Outputs Latching Outputs 5 A @ 30 VDC/240 VAC (1 Form “C”) 10 A @ 28 VDC/240 VAC (1 Form “C”) 10 A @ 120 VAC (1 Form “C”) 10 A @ 150 VDC (1 Form “A”) - Like all Callisto processing node boards, the IoC1 utilizes ArcNET technology and DAQ Voyager protocol to interface to the high-speed LAN. Additionally, the industry standard Nucleus real-time, multi-tasking operating system allows for user-defined applications and algorithms to be easily incorporated into the unit. There are two ways an IoC1 can be configured. Relays can be installed on the board to provide a single Form “A” or Form “B” contact output per point. These relays have a resistive load contact rating of 5A @ 250 VAC or 30 VDC and an inductive load contact rating of 2A @ 250 VAC or 30 VDC. Alternatively, the IoC1 can be configured to directly drive external relay coils located on IoCT command output termination boards. The transistors, which either provide these voltages or drive the on-board relays, are monitored to provide selectcheck capability. An 80C188 is used as the main processor of the board. 22 DAQ Electronics, LLC Callisto RTU Technical Guide LAN ArcNET Memory IoC 80188 Additional Callisto Modules DSP I/O 16 Trip/Close Pairs +5, +12, -12 VDC Command Inhibit CI P1 IoC Address 0-3 Latch 0-3 Outputs 0 3 Buffer ArcNET Interface CI 4-7 Latch CPU and Support 4-7 Outputs 4-7 Buffer P2 CI Memory 8 - 11 Latch 8 - 11 Outputs 8 - 11 Buffer CI 12 - 15 Latch 12 - 15 Outputs 12 - 15 Buffer ■ Links The Watchdog circuit is always installed unless debugging with emulator. LK2 enables/disables the Watchdog timer as follows: In = Enabled Out = Disabled 23 DAQ Electronics, LLC Callisto RTU Technical Guide ■ Connections P1: 64 Pin DIN connector carrying power and ArcNET signals P2: 64 Pin DIN connector interfacing to 32 control output relays ■ Termination Board I/O Interface Currently, there are five types of Callisto series control output termination boards, the IoCT2 through IoCT6. All boards interface with the IoC1 via a ribbon cable (note that the same IoC1 control output processing node can interface with each type of IoCT board). The IoCT2, IoCT4, and IoCT6 boards provide momentary output relays only. The IoCT3 and IoCT5 boards can support either momentary or latching relays. Other differences between IoCT boards are related to board dimensions and mounting options. Each IoC1 node can interface with up to four termination boards. A 2 x 16 matrix is used to drive the 16 trip/close control outputs on the IoC1. The 16 point outputs (software points 0 - 15) are generated via four identical circuits, with each circuit consisting of a hex D-type latch, an octal buffer, four open collector drivers, and four PNP transistors. The hex D-type latch is used to latch the four bits that control the four related points. A "1" being latched indicates an "on" condition while a "0" being latched represents an "off" condition. The four least significant bits of the latch are used for this purpose. The four latched outputs drive the inputs of the four open collector drivers, which in turn drive the bases of the four PNP transistors. An "on" written to the latch will turn a transistor on while an "off" will turn a transistor off. Each transistor has +12 VDC connected to its emitter via the P1 connector. When a transistor is turned on, the +12 VDC is essentially switched to the collector (minus the collect-emitter drop). This is the positive voltage used for one side of a relay coil, either internally or externally. The collector output of each transistor is also divided down by a resistor combination of 6.8K and 4.7K (12 VDC to 5 VDC) and fed into the four least significant bits of the octal latch. This allows the software to directly monitor the relay coil voltage and provide check back capability. The circuit identifiers for each control section are shown in the following control circuits table: Component Hex D-type latch Open collector driver PNP transistors Octal buffer Control Circuits Pts 0 - 3 Pts 4 - 7 U9 U12 U16A - U16D U16E - U16H Q3 - Q6 Q7 - Q10 U7 U20 Pts 8 -11 U22 U27A - U27D Q11 - Q14 U21 Pts 12 - 15 U26 U27E - U27H Q15 - Q18 U25 The two control outputs are used to select the "trip" or "close" command; 16 of the relays are used for the trip command and 16 are used for the close command (thus, the 2 x 16 matrix). Two NPN transistors (Q1 and Q2) are used to drive the other sides of the 16 pairs of relays. Q1 pertains to the "close" command while Q2 pertains to the "trip" command. The bases of these transistors are driven by outputs from PAL U5. The PAL inputs consist of the collector voltages for the first eight points, two signals from PAL U24, and two bits from the U9 hex D-type latch. These two bits are the trip/close selections. The U24 PAL is responsible for monitoring the collector voltages for the last eight points. The PALs are programmed to insure that only a single point and a single command is selected before enabling the trip/close outputs. Each relay also has a pair or 1N914 diodes associated with it for inductive spike suppression and blocking point selections from feeding back through non-selected points. The IoC1 may be equipped with on-board relays or interfaced to an IoCT command termination board. The IoC1 on-board relays are momentary type, with 1-Form “C” contact rated 5 A @ 30 VDC or 240 VAC. As mentioned, there are five IoCT command termination boards. The IoCT2, IoCT4, and IoCT6 can be equipped with up to 24 DAQ Electronics, LLC Callisto RTU Technical Guide eight momentary relays, which may be 1-Form “C” contact rated 10 A @ 120 VAC or 1-Form “A” contact rated 10A @ 150 VDC. The IoCT3 and IoCT5 may be equipped with either momentary or latching relays. A latching relay replaces two momentary relays; there is a maximum capability of four latching relays per board. The IoCT3 and IoCT5 can handle the same relays as the IoCT2, IoCT4, and IoCT6 boards as well as latching relays with 1-Form “C” contact rated 10 A @ 28 VDC or 240 VAC. In addition, the IoC1 can interface to other special relays (contact DAQ to discuss your specific requirements). An external command inhibit switch can be used to enable /disable IoC1 command outputs. This switch is put in series with the +12 VDC relay coil power source, thereby allowing enabling or disabling of all commands. ■ LEDs There are 10 LEDs protruding through the front panel indicating the operational status of the board. The 10segment LED is called “LED1”. LED1 contains eight software driven LEDs and two hardware-driven LEDs. LED 1 1 - Heartbeat 2 - Point selected 3 - On-board reconfiguration 4 - Reconfiguration by another board 5 - Future use 6 - Future use 7 - Future use 8 - Future use 9 - ArcNET interrupt 10 - ArcNET transmit enable IoC1 LEDs LED # 1 Description Heartbeat 2 Point selected 3 4 5 6 7 8 9 10 ArcNET reconfigurations by this board ArcNET reconfigurations by another board Future use Future use Future use Future use ArcNET interrupts TX enable hardware signals 25 Normal Operation Toggles once per second - meaning program running Toggles once per second when a control point is selected Toggles when reconfiguration occurs Toggles when reconfiguration occurs Always off Always off Always off Always off Flashes approximately once per second Always on DAQ Electronics, LLC Callisto RTU Technical Guide ■ Board Drawing List The following command output sub-system board drawings are included in this manual for reference purposes: IoC Drawings Assembly Diagram DAQ Drawing #16900 DAQ Drawing #16895 DAQ Drawing #A20042 DAQ Drawing #B23485 Board Name IoC1 IoCT2 IoCT3 IoCT5 Schematic Diagram DAQ Drawing #16897 DAQ Drawing #16892 DAQ Drawing #A20043 DAQ Drawing #B23484 ■ Technical Description 80C188 Processor The processor for the IoC1 board is the Intel 80C188 microcontroller providing:  8-bit data bus  20-bit address bus  2 DMA channels  Direct addressing to 1 MByte memory and 64 KBytes I/O The CMOS N80C188-16 is a 16-bit microprocessor with an 8-bit external data bus, which operates at speeds up to 16 MHz. On the IoC1, this microprocessor operates at 12.288 MHz using a 24.576 MHz crystal. It can directly address up to 1 MByte of memory and 64 KBytes of I/O. The microprocessor package is the 68 pin Plastic Leaded Chip Carrier (PLCC). Reset Circuit Manual reset is provided for the IoC1 board via a switch (SW1) located on the front panel of the board. Powerup reset and brownout protection is provided by a watchdog timer chip (U28). Watchdog Circuit LK2 enables/disables the Watchdog timer, which is located in U28. In = Enabled Out = Disabled Memory 128Kx8 Flash Memory 1Kx1 Serial EEPROM 64Kx8 EPROM 128Kx8 RAM (U8) (U11) (U14) (U10) 26 DAQ Electronics, LLC Callisto RTU Technical Guide The microprocessor on the IoC1 is the 80C188 (U17). This CMOS high integration microprocessor has twenty address bits that can directly access 1 MByte of memory and 64 Kbytes of I/O. Octal D-type latches, U6 and U19, are used to latch twelve of the twenty address bits on the low-going edge of the Address Latch Enable (ALE) signal. The 80C188 also has seven peripheral and six memory chip selects built in, as defined below: Peripheral Chip Select PCS0 PCS1 PCS2 PCS3 PCS4 PCS5 PCS6 Chip Select Definitions Hardware Memory Chip Select ArcNET interface LCS Watchdog timer MCS0 Node address and LEDs MCS1 Serial EEPROM MCS2 Control outputs MCS3 Not used UCS Not used Hardware RAM Not used Not used Flash memory Flash memory EPROM Two NAND gates in U15 are used to "OR" the MCS2-MCS3 chip selects together to obtain the chip select for the FLASH memory (U8). The EPROM socket, U14, can accept either a 64x8 Kbytes or 128x8 Kbytes EPROM. The RAM (U10) and the Flash memory are 128 KBytes each. The serial EEPROM, U11, is 512 Bytes. Interfacing to the EEPROM is done via PAL U13. The 1 MByte of memory space is divided up as shown in the following IoC1 Memory Map Table: 64x8 KByte EPROM Address Range Description 00000 - 1FFFF RAM 20000 - 5FFFF Not used 60000 - 7FFFF Flash 80000 - EFFFF Not used F0000 - FFFFF EPROM 128x8 KByte EPROM Address Range Description 00000 - 1FFFF RAM 20000 - 5FFFF Not used 60000 - 7FFFF Flash 80000 - DFFFF Not used E0000 - FFFFF EPROM The 64x8 Kbytes of I/O space consists of seven programmable hardware chip selects and a 256 byte block of internal reserved registers. The I/O space is shown in the IoC1 I/O Map table and the PSC0 - PSC6 chip selects are divided as shown in the External Hardware table. The addresses shown are the actual hardware addresses used. Address Range 0000 - 007F 0080 - 00FF 0100 - 017F 0180 - 01FF Description PSC0 PSC1 PSC2 PSC3 I/O Map Address Range 0200 - 027F 0280 - 02FF 0300 - 037F FF20 - FFFF 27 Description PSC4 PSC5 PSC6 Internal registers DAQ Electronics, LLC Address 0000 0000 0001 0001 0002 0003 0004 0006 0007 0007 0007 0007 0080 0100 0100 0183 0184 0200 0200 0201 0201 0202 0202 0203 0203 Callisto RTU Technical Guide External Hardware Description I/O Name ArcNET status STATUS_REG ArcNET interrupt mask INT_MASK_REG ArcNET diagnostic status DIAG_STATUS_REG ArcNET command COMMAND_REG ArcNET high address ADDR_HIGH_REG ArcNET low address ADDR_LOW_REG ArcNET data DATA_REG ArcNET configuration CONFIG_REG ArcNET tentative ID TENTID_REG ArcNET node ID NODEID_REG ArcNET setup SETUP_REG ArcNET next ID NEXTID_REG Watchdog timer WATCHDOG_TIMER Node HRDWR_NODE Software LEDs LEDS Serial EEPROM EEPROM_IN Serial EEPROM EEPROM_OUT Control outputs 0-3, T/C WCN1 Control checkback 0-3, T/C RCN1 Control outputs 4–7 WCN2 Control checkback 4-7 RCN2 Control outputs 8-11 WCN3 Control checkback 8-11 RCN3 Control outputs 12-15 WCN4 Control checkback 12-15 RCN4 R/W R W R W R/W R/W R/W R/W R/W R/W R/W R W R W R W W R W R W R W R Communications Port Communications with other Callisto boards is accomplished via the ArcNET LAN. The ArcNET controller (U4) has a RS-485 interface. Outputs Up to 32 command outputs using on-board relays or via IoCT command termination cards. Configurations: 16 on/off pairs or 16 latched/reset outputs with Select/Check/Execute security or 32 direct operate relays Momentary Relay Types: 5 A @ 30 VDC/240 VAC (1 Form “C”) 10 A @ 150 VDC (1 Form “A”) 10 A @ 120 VAC (1 Form “C”) Latching Relay Types: 10 A @ 28 VDC/240 VAC (1 Form “C”) 28 DAQ Electronics, LLC Callisto RTU Technical Guide Note that other special case relays may be used (consult DAQ for confirmation of your specific requirements). Pulse Durations: Configurable per point between 20 millisecond and 10 minutes Operate Time: 3 ms with on-board relay Release Time: 1 ms with on-board relay Power Requirements 290 mA @ 5 VDC 1.5 mA @ 12 VDC + 35 mA when command relay energizes (does not include power for external relay(s), if used) Operating System The IoC1 operating system is the industry standard Nucleus RTX real-time, multi-tasking OS allowing for simple integration of user defined applications and algorithms. Local Area Network The LAN protocol is DAQ Voyager protocol operating over a standard ArcNET Local Area Network at speeds up to 2.5 megabits per second. Environmental Specifications Operating range: Storage range: Relative humidity: Vibration: -20 to +70°C -20 to +70°C 5 to 95% non-condensing 5 to 65Hz Configuration IoC1 configuration is accomplished through its Callisto host node using DAQ CallistoView (or CALVIEW) Windows configuration utility. Construction Standard 4 layer Double EuroCard PCB 6.25" x 9.25" (160 mm x 235 mm) 29 DAQ Electronics, LLC Callisto RTU Technical Guide ► IoD1 ■ General Description As the status input processing node for the Callisto series of remotes, the IoD1 can multiplex up to 32 status/alarm inputs with one millisecond time-tagged sequence of events recording. A digital filtering algorithm is utilized to maintain time-tagging accuracy during contact bounce conditions. Debounce time is user-definable in multiples of 10 milliseconds with a 10 millisecond default. Two forms of anti-toggle filtering are provided. Under conditions when a user-definable number of "invalid" state changes occur (where the change does not exceed the debounce time) the point is taken out of service. A "chattering" point that produces an excessive number of valid changes within a user-defined period will be disabled, and the condition will be reported to the master station via a user-defined flag. The IoD1 interfaces to customer input points via IoDT1 or IoDT2 status termination boards. Both IoDT options allow for wet and dry contact input configurations with keying voltages of 12, 24, 48, and 125 VDC. Additionally, any status input point may be configured to be a pulse accumulator input point. Form “C” accumulators must have their first contact inputted on an even numbered input (zero being the first even status input point address). Accumulators are stored in dual 16 bit registers, with one register continuing accumulations during accumulator freeze conditions. After the freeze, the "secondary" register value is added back to the primary register, thus, the actual count is stored in a single location. Rollover is programmable on a per counter basis, with the options for freezing at the maximum value (65,536) or resetting the accumulator to zero and continuing to count. Like all Callisto series boards, the IoD1 utilizes ArcNET technology and DAQ Voyager protocol to interface to the high speed LAN. Additionally, the industry standard Nucleus real-time, multi-tasking operating system allows for user-defined applications and algorithms to be easily incorporated into the unit. The 80C188 processor is used as the board main processor. LAN ArcNET Memory IoD 80188 Additional Callisto Modules DSP I/O 32 Digital Inputs 30 DAQ Electronics, LLC Callisto RTU Technical Guide +5, +12, -12 VDC P1 IoD Address 0-7 Buffer Optical Isolators ArcNET Interface 8 - 15 Buffer Optical Isolators CPU and Support 16 - 23 Buffer Optical Isolators Memory 24 - 31 Buffer P2 Optical Isolators ■ Links The Watchdog circuit is always installed unless debugging with emulator. LK2 enables/disables the Watchdog timer, as follows: In = Enabled Out = Disabled ■ Connections P1: 64 Pin DIN connector carrying power and ArcNET signals P2: 64 Pin DIN connector interfacing to up to 32 status inputs via IoDT1 status termination boards ■ Termination Board I/O Interface The Callisto series status input termination boards, the IoDT1 and IoDT2, interface with the IoD1 via a ribbon cable. Differences between IoDT boards are related to board dimensions and mounting options. For information on connecting SLD-type terminal blocks to IoDT boards, see “TBI1 Status Interface Board” in the Specialty Board section of this manual. Each IoDT board can support up to eight status input points. Each IoD1 node can interface with up to four termination boards, thereby allowing up to 32 status input points per IoD1 node. IoDT boards allow for either wet or dry contact input configurations and support keying voltages of 12, 24, 48, and 125 VDC. Additionally, any status input point may be configured to be a pulse accumulator input point. Both Form “A” and Form “C” type accumulators are supported. Form “C” accumulators must have their first contact inputted on an even numbered input (zero being the first even status input point address). PCS4 and address bits A0-A2 are decoded by PAL U20 to generate the four hardware addresses to read the four status buffers. Four octal D-type latches, U13-U16, are used to read the 32 status inputs from the P2 connector. 31 DAQ Electronics, LLC Callisto RTU Technical Guide ■ LEDs There are 10 LEDs protruding through the front panel indicating the operational status of the board. The 10segment LED is called “LED1”. LED1 contains eight software driven LEDs and two hardware-driven LEDs. LED 1 1 - Heartbeat 2 - Future use 3 - On-board reconfiguration 4 - Reconfiguration by another board 5 - Future use 6 - Future use 7 - Future use 8 - Future use 9 - ArcNET interrupt 10 - ArcNET transmit enable IoD1 LEDs LED # 1 Description Heartbeat 2 3 4 5 6 7 8 9 10 Future use ArcNET reconfigurations by this board ArcNET reconfigurations by another board Future use Future use Future use Future use ArcNET interrupts TX enable hardware signals Normal Operation Toggles once per second - meaning program running Always off Toggles when reconfiguration occurs Toggles when reconfiguration occurs Always off Always off Always off Always off Flashes approximately once per second Always on ■ Board Drawing List The following status input sub-system board drawings are included in this manual for reference purposes: Board Name IoD1 IoDT1 IoDT2 IoD Drawings Assembly Diagram DAQ Drawing #16905 DAQ Drawing #16890 DAQ Drawing #A24406 32 Schematic Diagram DAQ Drawing #16902 DAQ Drawing #16887 DAQ Drawing #A24405 DAQ Electronics, LLC Callisto RTU Technical Guide ■ Technical Description 80C188 Processor Intel 80C188 microcontroller with:  8-bit data bus  20-bit address bus  2 DMA channels  Direct addressing to 1 MByte memory and 64 KBytes I/O The CMOS N80C188-16 is a 16-bit microprocessor with an 8-bit external data bus, which operates at speeds up to 16 MHz. On the IoD1, the microprocessor operates at 12.288 MHz using a 24.576 MHz crystal. It can directly address up to 1 MByte of memory and 64 KBytes of I/O. The microprocessor package is the 68 pin Plastic Leaded Chip Carrier (PLCC). Reset Circuit Manual reset is provided for the IoD1 board via a switch (SW1), which is located on the front panel of the board. Power-up reset and brownout protection is provided by a watchdog timer chip (U29). Watchdog Circuit LK2 enables/disables the Watchdog timer, which is located in U29. In = Enabled Out = Disabled Memory 128Kx8 Flash Memory 1Kx1 Serial EEPROM 64Kx8 EPROM 128Kx8 RAM (U25) (U22) (U17) (U21) The microprocessor on the IoD1 is the 80C188 (U23). This CMOS high integration microprocessor has twenty address bits, which can directly access 1 MByte of memory and 64 KBytes of I/O. Octal D-type latches, U18 and U19, are used to latch twelve of the twenty address bits on the low-going edge of the Address Latch Enable (ALE) signal. The 80C188 also has seven peripheral and six memory chip selects built in, as defined below: 33 DAQ Electronics, LLC Peripheral Chip Select PCS0 PCS1 PCS2 PCS3 PCS4 PCS5 PCS6 Callisto RTU Technical Guide Chip Select Definitions Hardware Memory Chip Select ArcNET interface LCS Watchdog timer MCS0 Node address and LEDs MCS1 Serial EEPROM MCS2 Status inputs MCS3 Not used UCS Not used Hardware RAM Not used Not used Flash memory Flash memory EPROM An AND gate in U27 is used to combine the MCS2 and MCS3 chip select signals to obtain the chip select for the FLASH memory (U25). The EPROM socket, U17, can accept either a 64x8 KByte or 128x8 KByte EPROM. The RAM (U21) and the Flash memory are 128 KBytes each. The serial EEPROM, U22, is 512 Bytes. Interfacing to the EEPROM is done via PAL U24. The 1 MByte of memory space is divided up as defined below: 64x8 KByte EPROM Address Range Description 00000 - 1FFFF RAM 20000 - 5FFFF Not used 60000 - 7FFFF Flash 80000 - EFFFF Not used F0000 - FFFFF EPROM 128x8 KByte EPROM Address Range Description 00000 - 1FFFF RAM 20000 - 5FFFF Not used 60000 - 7FFFF Flash 80000 - DFFFF Not used E0000 - FFFFF EPROM The 64 KBytes of I/O space consists of seven programmable hardware chip selects and a 256 byte block of internal reserved registers. The I/O space is shown in the IoD1 I/O Map table below. The PSC0 - PSC6 chip selects are further divided as shown in the IoD1 External Hardware table. The addresses shown are the actual addresses used. Address Range 0000 - 007F 0080 - 00FF 0100 - 017F 0180 - 01FF Description PSC0 PSC1 PSC2 PSC3 I/O Map Address Range 0200 - 027F 0280 - 02FF 0300 - 037F FF20 - FFFF 34 Description PSC4 PSC5 PSC6 Internal registers DAQ Electronics, LLC Address 0000 0000 0001 0001 0002 0003 0004 0006 0007 0007 0007 0007 0080 0100 0100 0183 0184 0200 0201 0202 0203 Callisto RTU Technical Guide External Hardware Description I/O Name ArcNET status STATUS_REG ArcNET interrupt mask INT_MASK_REG ArcNET diagnostic status DIAG_STATUS_REG ArcNET command COMMAND_REG ArcNET high address ADDR_HIGH_REG ArcNET low address ADDR_LOW_REG ArcNET data DATA_REG ArcNET configuration CONFIG_REG ArcNET tentative ID TENTID_REG ArcNET node ID NODEID_REG ArcNET setup SETUP_REG ArcNET next ID NEXTID_REG Watchdog timer WATCHDOG_TIMER Node HRDWR_NODE Software LEDs LEDS Serial EEPROM EEPROM_IN Serial EEPROM EEPROM_OUT Status inputs 0 - 7 RSLOA Status inputs 8 - 15 RSLOB Status inputs 16 - 23 RSHIA Status inputs 24 - 31 RSHIB R/W R W R W R/W R/W R/W R/W R/W R/W R/W R W R W R W R R R R Communications Port Communications with other Callisto boards is accomplished via the ArcNET LAN. The ArcNET controller, U12, has an RS-485 interface. Inputs 32 digital inputs via termination cards Status: Keying voltages: 12, 24, 48, 125 VDC Scan rate: One scan per millisecond Debounce: Configurable per point from one millisecond to 10 minutes Configurable for any combination of status, Form A, or Form C accumulators Accumulators: Formats: Form A, Form C Pulse Frequency: rates up to 1 change per debounce period Rollover: Definable 16 or 32-bit rollover Power Requirements 265 mA @ 5 VDC 35 DAQ Electronics, LLC Callisto RTU Technical Guide Operating System The IoD1 operating system is the industry standard Nucleus RTX real-time, multi-tasking OS allowing for simple integration of user-defined applications and algorithms. Local Area Network The LAN protocol is DAQ Voyager protocol operating over the a standard ArcNET Local Area Network at speeds up to 2.5 megabits per second. Environmental Specifications Operating range: Storage range: Relative humidity: Vibration: -20 to +70°C -20 to +70°C 5 to 95% non-condensing 5 to 65Hz Configuration IoD1 configuration is accomplished through its Callisto host node using DAQ CallistoView (or CALVIEW) Windows configuration utility. Construction Standard 4 layer Double EuroCard PCB 6.25" x 9.25" (160 mm x 235 mm) 36 DAQ Electronics, LLC Callisto RTU Technical Guide ► IoE1 ■ General Description As the serial processing node for the Callisto series of remotes, the IoE1 carries four serial data ports, which may be physically presented as either RS-485 or RS-232 circuits. Two IoE1 ports may be linked for operation via an on-board Bell 202, 1200-baud modem. Of these ports, one may be optionally configured for operation over the dial-up network. Communications options supported include both synchronous and asynchronous, byte or bit oriented protocols. The IoE1 may be utilized for serial data exchange with master station(s), intelligent meters, relays, or other intelligent electronic devices (IEDs) distributed across the Callisto system. Like all Callisto boards, the IoE1 utilizes ArcNET technology and DAQ Voyager protocol to interface to the high speed LAN. Additionally, the industry standard Nucleus real-time, multi-tasking operating system allows for userdefined applications and algorithms to be easily incorporated into the unit. Other applications for the IoE1 include:  Multi-port communications with master station(s) using differing protocols  Communication with remotely sited satellite RTUs over modem lines, radio, fiber, packet radio, or dial-up networks  Support of a local station printer for alarm logging and SOE recording  Interface to a Real Time Clock or Global Positioning System (GPS) LAN ArcNET Memory IoE 80188 Protocol Driver Protocol Driver Port A Port B Additional Callisto Modules 4 Serial Ports to Intelligent Electronic Devices 37 DAQ Electronics, LLC Callisto RTU Technical Guide Dial-Up Modem +5, +12, -12 VDC P1 IoE Address 202 Modem Serial Port 1 RS-232 ArcNET Interface RS-485 Dial-Up Modem CPU and Support 202 Modem Memory P2 Serial Port 2 RS-232 RS-485 RS-232 Serial Port 3 RS-485 RS-232 Serial Port 4 RS-485 The IoE1 can be configured as either a host or a slave node. A host node IoE1 will contain the database from the slave nodes (IoA1, IoD1, Polaris, etc.) on its network. A host node can communicate with a master station as well as intelligent electronic devices (electronic meters, relaying devices, etc.). In a slave configuration, the IoE1 will only communicate with intelligent electronic devices, maintaining a database of their points and sending this data back to a host node. Each IoE1 can be configured with up to four communication ports. Ports one and two are configurable for RS232, RS-485, an internal Bell 202 modem, or dial-up modem. Ports three and four can be either RS-232 or RS485. All ports can be configured to communicate either asynchronously or synchronously. Port one can also be configured for bit-oriented protocols as well as byte-oriented. An 80C188 is the IoE1 main processor. 38 DAQ Electronics, LLC Callisto RTU Technical Guide ■ Links This section provides a brief summary of links and connections required for installation: IoE1 Links Link LK1 LK2 LK3 LK4 LK5 LK6 1-2 4W 2W PTT PTT 2-3 2W 4W TX Clk TX Clk LK7 LK8 LK9 LK10 LK11 LK12 LK13 LK14 & LK16 Set LK14 & LK16 LK15 LK17 Set XXX Normal XXX Description Port 1-2W or 4W internal modem fitted Port 2-2W or 4W internal modem fitted Port 1 Pin 6 D-Type Port 2 Pin 6 D-Type Not Used Port 1 RX synchronous protocols - Polarity selection for external clocks Port 1 TX synchronous protocols - Polarity selection for external clocks Port 2 RX synchronous protocols - Polarity selection for external clocks Port 2 TX synchronous protocols - Polarity selection for external clocks Port 3 RX synchronous protocols - Polarity selection for external clocks Port 3 TX synchronous protocols - Polarity selection for external clocks Port 4 RX synchronous protocols - Polarity selection for external clocks Port 4 TX synchronous protocols - Polarity selection for external clocks Port 1 Protocol option - Bit oriented (asynchronous or synchronous) Port 1 Protocol option - Byte oriented (asynchronous or synchronous) Polarity of bit oriented protocols Watchdog enable (always fitted) ■ Connections P1: 64 Pin DIN connector carrying power and ArcNET signals P2: 64 Pin DIN connector interfacing to customer communication channels via IoET1 termination board ■ Termination Board I/O Interface The four available communication channels of the IoE1 are presented to the user via the IoET1 termination board. The IoET1 mounts onto the Callisto card bin and is directly interfaced to the IoE1 through its 64 pin DIN connector. Each IoET1 can support up to four communication channels. The user interface to these communication channels is defined below: I/O Interface Communication Port Type Modem, Bell 202T RS-232 RS-485 39 User Physical Interface 4-position terminal block DB9, 9-pin male connector 2-position terminal block DAQ Electronics, LLC Callisto RTU Technical Guide The IoET1 is simply the physical presentation of the communication ports selected on the IoE1 communication processing node. However, the IoET1 must be configured to properly match the desired IoE1 ports. On RTUs whose card bin is mounted in such a way that the rear of the bin is not accessible, the connections on the IoET1 are wired to terminal blocks or connectors located in a more accessible location. ■ LEDs There are 20 LEDs protruding through the front panel indicating the operational status of the board. These 10segment LEDs are called “LED1” and “LED2”. LED1 contains eight software driven LEDs and two hardwaredriven LEDs. The LEDs on LED2 indicate transmit and receive for the four communications ports. LED 1 LED 2 1 - Heartbeat 1 - Port 1 TX 2 - Future use 2 - Port 1 RX 3 - On-board reconfiguration 3 - Port 2 TX 4 - Reconfiguration by another board 4 - Port 2 RX 5 - Port 4 - Good message received 5 - Port 3 TX 6 - Port 3 - Good message received 6 - Port 3 RX 7 - Port 2 - Good message received 7 - Port 4 TX 8 - Port 1 - Good message received 8 - Port 4 RX 9 - ArcNET interrupt 10 - ArcNET transmit enable Two octal D-type latches, U2 and U3, are used to read in the 16 bits worth of remote addressing from the P1 connector. The 8 bits read via octal D-type latch U1 are the IoE1 node address. A third octal D-type latch, U38 drives the first 8 LEDs of LED1. 40 DAQ Electronics, LLC Callisto RTU Technical Guide LED 1 LED # 1 Description Heartbeat 2 3 4 5 Future use ArcNET reconfigurations by this board ArcNET reconfigurations by another board Port 4 - Good message received 6 Port 3 - Good message received 7 Port 2 - Good message received 8 Port 1 - Good message received 9 10 ArcNET interrupts TX enable hardware signals Normal Operation Toggles once per second - meaning program running Always off Toggles when reconfiguration occurs Toggles when reconfiguration occurs Blinks when good message processed on Port 4 Blinks when good message processed on Port 3 Blinks when good message processed on Port 2 Blinks when good message processed on Port 1 Flashes approximately once per second Always on LED 2 Description Port 1 - Transmit Port 1 - Receive Port 2 - Transmit Port 2 - Receive Port 3 - Transmit Port 3 - Receive Port 4 - Transmit Port 4 - Receive PSTN 1 American Implementation PSTN 2 American Implementation LED # 1 2 3 4 5 6 7 8 9 10 Normal Operation Blinks when port 1 transmits Blinks when port 1 receives Blinks when port 2 transmits Blinks when port 2 receives Blinks when port 3 transmits Blinks when port 3 receives Blinks when port 4 transmits Blinks when port 4 receives Not used Not used ■ Board Drawing List The following communications sub-system board drawings are included in this manual for reference purposes: Board Name IoE1 IoET1 IoE Drawings Assembly Diagram DAQ Drawing #16910 DAQ Drawing #17007 ■ Technical Description 80C188 Processor Intel 80C188 microcontroller with:  8-bit data bus  20-bit address bus 41 Schematic Diagram DAQ Drawing #16907 DAQ Drawing #17004 DAQ Electronics, LLC Callisto RTU Technical Guide  2 DMA channels  Direct addressing to 1 MByte memory and 64 KBytes I/O The CMOS N80C188-25 is a 16-bit microprocessor with an 8-bit external data bus, which operates at speeds up to 25 MHz. On the IoE1, the microprocessor operates at 24 MHz using a 48 MHz crystal. It can directly address up to 1 MByte of memory and 64 KBytes of I/O. The microprocessor package is the 68 pin Plastic Leaded Chip Carrier (PLCC). Reset Circuit Manual reset is provided for the IoE1 board via a switch (SW1), which is located on the front panel of the board. Power-up reset and brownout protection is provided by a watchdog timer chip (U41). Watchdog Circuit LK17 enables/disables the Watchdog timer, which is located in U41. In = Enabled Out = Disabled Memory 128Kx8 Flash Memory 64Kx8 EPROM 256Kx8 RAM 1Kx1 Serial EEPROM (U25) (U32) (U30, U31) (U18) The microprocessor on the IoE1 is the 80C188 (U33). This CMOS high integration microprocessor has 20 address bits, which can directly access 1 MByte of memory and 64 KByte of I/O. Octal D-type latches, U10 and U26, are used to latch 12 of the 20 address bits on the low-going edge of the Address Latch Enable (ALE) signal. The 80C188 also has 7 peripheral and 6 memory chip selects built in, as defined below: Peripheral Chip Select PCS0 PCS1 PCS2 PCS3 PCS4 PCS5 PCS6 Chip Select Definitions Hardware Memory Chip Select ArcNET interface LCS Watchdog timer MCS0 RTU/node address, LEDs MCS1 Serial EEPROM MCS2 Miscellaneous communications MCS3 Communications ports 3, 4 UCS Communications ports 1, 2 Hardware RAM RAM RAM Flash memory Flash memory EPROM PCS2, PCS4, and address bits A0-A2 are further decoded by PAL U15 to address three of the hardware sections shown in the table above: RTU/node address, LEDs, and Miscellaneous communications. Two of the AND gates in U40 are used to "OR" the MCS0-MCS3 chip selects together to obtain two chip selects for the upper RAM (U31) and FLASH memory (U25). 42 DAQ Electronics, LLC Callisto RTU Technical Guide The EPROM socket, U32, can accept either a 64 KByte or 128 KByte EPROM. Each RAM and the Flash memory are 128 KBytes. The serial EEPROM, U18, is 512 Bytes. Interfacing to the EEPROM is done via PAL U24. The 1 MByte of memory space is divided up as defined below: 64x8 KByte EPROM Address Range Description 00000 - 1FFFF RAM 20000 - 3FFFF Not used 40000 - 5FFFF RAM 60000 - 7FFFF Flash 80000 - EFFFF Not used F0000 - FFFFF EPROM 128x8 KByte EPROM Address Range Description 00000 - 1FFFF RAM 20000 - 3FFFF Not used 40000 - 5FFFF RAM 60000 - 7FFFF Flash 80000 - DFFFF Not used E0000 - FFFFF EPROM The 64 KBytes of I/O space consists of seven programmable hardware chip selects and a 256 byte block of internal reserved registers. The I/O space is shown in the IoE1 I/O Map table below. The PSC0 - PSC6 chip selects are further divided down as shown in the IoE1 External Hardware table. The addresses shown are the actual addresses used when accessing the hardware. Address Range 0000 - 007F 0080 - 00FF 0100 - 017F 0180 - 01FF Description PSC0 PSC1 PSC2 PSC3 I/O Map Address Range 0200 - 027F 0280 - 02FF 0300 - 037F FF20 - FFFF 43 Description PSC4 PSC5 PSC6 Internal registers DAQ Electronics, LLC Address 0000 0000 0001 0001 0002 0003 0004 0006 0007 0007 0007 0007 0080 0100 0100 0101 0102 0183 0184 0200 0200 0201 0202 0202 0203 0280 0281 0282 0283 0300 0301 0302 0303 Callisto RTU Technical Guide External Hardware Description I/O Name ArcNET status STATUS_REG ArcNET interrupt mask INT_MASK_REG ArcNET diagnostic status DIAG_STATUS_REG ArcNET command COMMAND_REG ArcNET high address ADDR_HIGH_REG ArcNET low address ADDR_LOW_REG ArcNET data DATA_REG ArcNET configuration CONFIG_REG ArcNET tentative ID TENTID_REG ArcNET node ID NODEID_REG ArcNET setup SETUP_REG ArcNET next ID NEXTID_REG Watchdog timer WATCHDOG_TIMER Node HRDWR_NODE Software LEDs LEDS MSByte RTU HRDWR_GROUP LSByte RTU HRDWR_RTU Serial EEPROM EEPROM_IN Serial EEPROM EEPROM_OUT Port 1 misc. comm. signals RCOM1 Port 1 misc. comm. signals WCOM1 Port 1 modem control WMC1 Port 2 misc. comm. signals RCOM2 Port 2 misc. comm. signals WCOM2 Port 2 modem control WMC2 Port 3 85C30 control PORT3_CNTL Port 2 85C30 control PORT2_CNTL Port 3 85C30 data PORT3_DATA Port 2 85C30 data PORT2_DATA Port 1 85C30 control PORT1_CNTL Port 0 85C30 control PORT0_CNTL Port 1 85C30 data PORT1_DATA Port 0 85C30 data PORT0_DATA R/W R W R W R/W R/W R/W R/W R/W R/W R/W R W R W R R R W R W W R R W R/W R/W R/W R/W R/W R/W R/W R/W Z8530 Serial Communications Controller The IoE1 has options for two 85C30 UART chips, each supporting two communications channels. Communications Ports Communications with other Callisto boards is accomplished via the ArcNET LAN, which consists of the ArcNET controller, U5, and the U4 RS-485 interface. There are four other communication ports on the IoE1. Port 1 can be configured to communicate via RS-232, RS-485, Bell 202 modem, or dial-up modem. The communications protocol can be bit or byte oriented, asynchronous or synchronous. For synchronous protocols, U27 inverters, LK5, and LK7 are used to accommodate different polarities for the external clocks. For byte oriented protocols, the 85C30 Dual Serial Communications Controller (U42) is used. One half of this IC interfaces to either an RS-232 interface (U20), a RS-485 interface (U12), a Bell 202 modem (U7), or a dial-up modem (also U7). These are all build options. For bit-oriented protocols, a hex d-type latch (U37) is used to output the RTS and TD signals while an octal 44 DAQ Electronics, LLC Callisto RTU Technical Guide buffer (U14) is used to read the CTS, DCD, and RD signals. These ICs also interface to the RS-232 interface, RS-485, Bell 202 modem, or dial-up modem. LK14 and LK16 are positioned based on the bit or byte-oriented selection, as defined below: Port # RS-232 1 2 3 4 x x x x LK14 and LK16 Connections Onboard RS-485 Bit Byte Modem x x x x x x x x x x x Sync Async x x x x x x x x Port 1 Protocol Options Option Bit oriented Byte oriented LK14 and LK16 1 to 2 2 to 3 A pair of op-amps in U11 buffer the transmit and receive signals when Port 1 is configured for an internal modem. The 10K potentiometer VR2 is used to adjust the transmit level of Port 1 up to +3 dB into a 600 Ohms load. The receive sensitivity can be adjusted by another 10K potentiometer VR2. Port 2 uses the other half of the 85C30 Dual Serial Communications Controller (U42). This port can also be configured to communicate via RS-232, RS-485, Bell 202 modem, or dial-up modem. Unlike Port 1, Ports 2 through 4 can only accommodate byte oriented protocols, either asynchronous or synchronous. For synchronous protocols, U28 inverters, LK8, and LK9 are used to accommodate different polarities for the external clocks. The 85C30 IC interfaces to either an RS-232 interface (U21), an RS-485 interface (U13), a Bell 202 modem (U16), or a dial-up modem (also U16). These are all build options. A second 85C30 Dual Serial Communications Controller (U36) serves as Ports 3 and 4. These ports can be configured for RS-232 or RS-485 and can communicate with byte oriented, asynchronous or synchronous protocols. The RS-232 interfaces for Ports 3 and 4 are U22 and U23, respectively. The RS-485 interfaces for Ports 2 and 3 are U12 and U9, respectively. For synchronous protocols on Port 3, U27 inverters, LK10, and LK11 are used to accommodate different polarities for the external clocks. Similarly, U27 inverters, LK12, and LK13 are used on Port 4. The first eight LEDs on the LED2 bar display indicate transmit and receive for the four communication ports. Adjustments Port 1 can be configured for an internal modem. The transmit level can be adjusted up to +3 dB (into 600 Ohms) by 10K potentiometer VR1. The receive sensitivity can be adjusted by another 10K potentiometer VR2. Port 2 can be configured for an internal modem. The transmit level can be adjusted up to +3 dB (into 600 Ohms) by 10K potentiometer VR4. The receive sensitivity can be adjusted by another 10K potentiometer VR3. Serial Input/Output 4 Independent Serial Communications Ports: Baud Rate: Protocol: Up to 19.2 Kbit/sec individually configurable per port Byte or bit oriented, synchronous or asynchronous 45 DAQ Electronics, LLC Interfaces: Modem: Other Media: Callisto RTU Technical Guide 4 Ports individually configurable as RS-232, RS-485 circuits On board 1200 baud, V21, V23 modem for private circuit operation - external modems are supported for both leased line and/or PSTN circuits Fiber, Radio, Trunked Radio, Packet Radio, plus RS-232 or RS-485 circuits Software: IoE1 is fully programmable and capable of operating in a variety of modes and applications Drivers: Software protocols are independent on each port - a library of protocols is available off-the-shelf or can be written for particular applications Applications:  Serial interface to intelligent instruments, meters, protection relays, etc.  Multi-port communications to host computer(s)  Communications hub for other RTUs  Local printers for alarm and sequence of events recording  An extensive library of protocols for communications with SCADA master stations and distributed substation devices Power Requirements 340 mA @ 5 DC 10 mA @ 12 VDC 25 mA @ -12 VDC Real Time Clock Crystal: Accuracy: Employment: 6.144 MHz Crystal Oscillator 1 ppm (1 ms per 15 minute interval) Provides real time synchronization for all nodes on an ArcNET LAN and maintains 1ms time tagging accuracy for all events on a network Operating System The IoE1 operating system is the industry standard Nucleus RTX real-time, multi-tasking OS allowing for simple integration of user-defined applications and algorithms. Local Area Network DAQ Voyager protocol operating on the Callisto standard ArcNET Local Area Network at speeds up to 2.5 megabits per second 46 DAQ Electronics, LLC Callisto RTU Technical Guide Environmental Specifications Operating range: Storage range: Relative humidity: Vibration: -20 to +70°C -20 to +70°C 5 to 95% non-condensing 5 to 65Hz Configuration IoE1 configuration is accomplished through its Callisto host node using DAQ CallistoView (or CALVIEW) Windows configuration utility. Construction Standard 4 layer Double EuroCard PCB 6.25" x 9.25" (160 mm x 235 mm) 47 DAQ Electronics, LLC Callisto RTU Technical Guide ► IoE2 ■ General Description As the second generation serial processing node for the Callisto series of remotes, the IoE2 carries four serial data ports, and an IP Ethernet connection. Serial ports may be physically presented as either RS-485 or RS-232 circuits. Communications options supported include both byte and bit oriented protocols. When used to replace or upgrade an IoE1, a Bell 202 modem may be plugged into port 1. The IoE2 may be utilized for serial data exchange with master station(s), intelligent meters, relays, or other intelligent electronic devices (IEDs) distributed across the Callisto system. Like all Callisto boards, the IoE2 utilizes ArcNET technology and DAQ Voyager protocol to interface to the internal high speed LAN. Other applications for the IoE2 include:  Multi-port and IP communications with master station(s) using differing protocols  Communication with remotely sited satellite RTUs over modem lines, radio, fiber, packet radio, or dial-up networks  Support of a local station printer for alarm logging and SOE recording  Interface to a Real Time Clock or Global Positioning System (GPS)  Historical File Storage for retrieval using FTP (File Transfer Protocol) 48 DAQ Electronics, LLC Callisto RTU Technical Guide 49 DAQ Electronics, LLC Callisto RTU Technical Guide The IoE2 can be configured as either a host or a slave node. A host node IoE2 will contain the database from the slave nodes (IoA1, IoD1, Polaris, etc.) on its network. A host node can communicate with a master station as well as intelligent electronic devices (electronic meters, relaying devices, etc.). In a slave configuration, the IoE2 will only communicate with the intelligent electronic devices, maintaining a database of their points and sending this data back to a host node. Each IoE2 can be configured with up to four communication ports. All ports are configurable for RS-232, RS-485 and support byte oriented protocols. Port 1 can be configured for bit-oriented protocols as well as byte-oriented. An 80386 is the IoE2 main processor. ■ Links This section provides a brief summary of links and connections required for installation: IoE2 Links Link JP1 1-2 Battery enable JP2 Watchdog enable Pin 1-2 2-wire ArcEN Low JP3 JP4 JP5 JP6 JP7 JP8 JP9 JP10 Port 1 PTT Port 2 PTT Port 3 PTT Port 4 PTT 1-2, 3-4 Port 1 RS485 1-2, 3-4 Port 3 RS485 2-3 Pin 3-4 4-wire ArcEN High Port 1 12V Port 2 12V Port 3 12V Port 4 12V 5-6, 7-8 Port 2 RS485 5-6, 7-8 Port 4 RS485 Description Installed to allow battery to back-up Static Ram - This link is typically shipped uninstalled, and should be installed at time of installation This link should always be installed during normal operation Port 1 Bell 202 Modem 2W/4W operation Arcnet enable signal for driving Fiber-Optic - set as 12 for DAQ transceivers Brings 12 Volts or PTT to pin 8 of J2 Brings 12 Volts or PTT to pin 8 of J3 Brings 12 Volts or PTT to pin 8 of J4 Brings 12 Volts or PTT to pin 8 of J5 Biasing and termination for RS485 lines Biasing and termination for RS485 lines JP11 JP12 JP13 Factory installed based on build option Factory installed based on build option Not used in normal operation ■ Connections P1: 64 Pin DIN connector carrying power, ArcNET, and addressing signals from the motherboard P2: 64 Pin DIN connector interfacing to customer communication channels via IoET1 termination board J2: J3: J4: J5: J6: Port 1 RS232 and RS485 interface Port 2 RS232 and RS485 interface Port 3 RS232 and RS485 interface Port 4 RS232 and RS485 interface Ethernet/IP interface 50 DAQ Electronics, LLC Callisto RTU Technical Guide J2 - J5 Pin 1 2 3 4 5 6 7 8 Signal DCD RX TX RS485GND RS485+ RTS +12V/PTT ■ Termination Board I/O Interface The four available communication channels of the IoE2 are presented to the user via J2-J5 RJ45 connections or via the IoET1 termination board. The IoET1 mounts onto the Callisto card bin and is directly interfaced to the IoE2 through its 64 pin DIN connector. Each IoET1 can support up to four communication channels. The user interface to these communication channels is defined below: I/O Interface Communication Port Type Modem, Bell 202T RS-232 RS-485 User Physical Interface 4-position terminal block DB9, 9-pin male connector 2-position terminal block The IoET1 is simply the physical presentation of the communication ports selected on the IoE2 communication processing node. However, the IoET1 must be configured to properly match the desired IoE2 ports. ■ LEDs There are 20 LEDs protruding through the front panel indicating the operational status of the board. These 10segment LEDs are called “LED1” and “LED2”. LED1 contains eight software driven LEDs and two hardwaredriven LEDs. The first eight LEDs on LED2 indicate transmit and receive for the four communications ports. LED 1 LED 2 1 - Heartbeat 1 - Port 1 TX 2 - Future use 2 - Port 1 RX 3 - On-board reconfiguration 3 - Port 2 TX 4 - Reconfiguration by another board 4 - Port 2 RX 5 - Port 4 - Good message received 5 - Port 3 TX 6 - Port 3 - Good message received 6 - Port 3 RX 7 - Port 2 - Good message received 7 - Port 4 TX 8 - Port 1 - Good message received 8 - Port 4 RX 9 - ArcNET interrupt 9 - ENET 10/100 Mbit 10 - ArcNET transmit enable 10 - ENET half/full duplex 51 DAQ Electronics, LLC Callisto RTU Technical Guide LED 1 LED # 1 Description Heartbeat 2 3 4 5 Future use ArcNET reconfigurations by this board ArcNET reconfigurations by another board Port 4 - Good message received 6 Port 3 - Good message received 7 Port 2 - Good message received 8 Port 1 - Good message received 9 10 ArcNET interrupts TX enable hardware signals LED # 1 2 3 4 5 6 7 8 9 10 Description Port 1 - Transmit Port 1 - Receive Port 2 - Transmit Port 2 - Receive Port 3 - Transmit Port 3 - Receive Port 4 - Transmit Port 4 - Receive Ethernet 10/100 Mbit Ethernet half/full duplex Normal Operation Toggles once per second - meaning program running Always off Toggles when reconfiguration occurs Toggles when reconfiguration occurs Blinks when good message processed on Port 4 Blinks when good message processed on Port 3 Blinks when good message processed on Port 2 Blinks when good message processed on Port 1 Flashes approximately once per second Always on LED 2 Normal Operation Blinks when port 1 transmits Blinks when port 1 receives Blinks when port 2 transmits Blinks when port 2 receives Blinks when port 3 transmits Blinks when port 3 receives Blinks when port 4 transmits Blinks when port 4 receives Off = 10 Mbit, On = 100 Mbit Off = half duplex, On = full duplex ■ Board Drawing List The following communications sub-system board drawings are included in this manual for reference purposes: Board Name IoE2 IoET1 IoE2 Drawings Assembly Diagram DAQ Drawing #001-2900 DAQ Drawing #17007 Schematic Diagram DAQ Drawing #A24249 DAQ Drawing #17004 ■ Technical Description Processor The IoE2 processor is the 80386EX (U34), which controls the address bus and control lines that go to all peripherals. The processor either receives data on the data bus or generates data for other peripherals. The address space of the processor is broken down into memory space and I/O space. In order to determine which space the processor is accessing, the pin M/IO# (pin 29) will be 3.3V high for memory space accesses and 0V 52 DAQ Electronics, LLC Callisto RTU Technical Guide low for I/O space. The processor also has a 16-bit wide data bus to access peripherals (some peripherals only have an 8-bit wide data bus; the processor will access these with D0-D7 of the data bus). When the processor is functioning correctly with a number of other peripherals, flash, SRAM, EPLD, and LEDs, the first LED of front panel LED1 will blink. In order to begin proper functioning, there are several requirements:  The processor must be supplied with 3.3V and Ground on the appropriate pins  The processor RESET pin 119 must be in a low state (if held high, the processor will remain in a reset state)  The processor must be supplied with a clock signal on pin 125 (the clock signal generated for the processor is 50MHz and this frequency should be seen on pin 125)  The JTAG pin TMSRST on the processor (pin 129) must be high With these pins in the correct state, the processor should generate several signals, including a clock out on pin 112. This clock signal should be half of the input clock on pin 125, therefore, a 25MHz clock signal should be seen. The UCS, the Upper Chip Select from the processor, will also be generated on pin 112. This signal should appear 3.3V high with the signal going to 0V a number of times. The signal will look erratic on the scope because it is executing a number of accesses to the flash devices (it will continually generate accesses to read code from the flash device). If the signal remains high, the board should be reset and the signal checked to see if it goes low once. If this is the case, the processor attempted to access the flash device but was unsuccessful in reading the proper data (the processor simply stops). No other accesses will be attempted. This access problem can be caused by a number of areas:  Stuck or unsoldered address lines between the processor and flash  Stuck or unsoldered data lines between the processor and flash  Unsoldered UCS pin to the flash  Stuck or unsoldered control pins from the EPLD to the flash  The EPLD or the EPLD did not decode the UCS properly in generating the appropriate chip select for the flash device (refer to the EPLD section)  The control signal RD#, read signal low, is stuck or unconnected to the flash (note that flash devices have a buffer (U42) between the data bus of the processor and the data bus of the flash device) If the flash device is correctly accessed, the next stage is the SRAM, the actual location where the code for the processor is run. The processor will load all code stored in the flash device into the SRAM device where it will reside. The SRAM is powered by the Real Time Clock controller, which has a supervisor circuit that controls whether a device is powered from battery or the main power supply (refer to RTC section). The SRAM is under this battery backed circuit. The SRAM 3.3V comes from U12 and is labeled as 3.3VQ. For this function to work correctly, the generated chip select for the SRAM coming from the processor (CS0#) goes through the RTC circuit, the EPLD, and then a decode IC before it hits the individual SRAMs. The chain of chip selects is as follows: CS0# -> CS0Q# -> (RSEL0, RSEL1, RSEL2) -> (RCS0#, RCS1#, RCS2#, RCS3#, RCS4#). If the heartbeat LED is not blinking and the flash appears to be accessed correctly, the following aspects should be checked:  SRAM chip selects are active (they are 3.3V high and go 0V low for an access to a device) 53 DAQ Electronics, LLC Callisto RTU Technical Guide  Pins of the SRAM devices are soldered to the board (the address and data lines should be correct since the flash was being accessed)  3.3V and Ground for the SRAM devices After the processor loads code from the flash into the SRAM, it runs the code and attempts to toggle the heartbeat LED. The register for the LED is located in the EPLD (U33). The processor accesses this register in the EPLD through the address bus, data bus, and the IOPORT-CS# signal. If the LED is not blinking, the following aspects should be checked:  Address and data connections on EPLD: determine whether the pins are soldered to the board  IOPORT-CS#: check that the signal is in change state when an access is occurring at the LED register, going from a 3.3V high to a 0V low - also check to see if the pin from the EPLD is soldered to the board  If the heartbeat LED is still not blinking, check the connections to the LEDs The processor has a debug port (PD Remote) for use with some software tools. The internal uart to the processor is connected to U45, a TTL to RS232 converter. A special cable is needed to connect JP11 to a PC. The processor also has a precise oscillator connected to the TMRCLK0 pin (pin 101). The frequency of the clock coming into the processor is 6.144MHz, which is used to maintain an accurate time base for the system. Real Time Clock The RTC (Real Time Clock U12) provides a number of functions, including voltage supervisor, watchdog circuit, and real time clock. The voltage supervisor circuit monitors the 3.3V line and sets a reset signal low to put devices in a reset state if the voltage level drops below a certain threshold. It will also go into battery back up mode. The RTC has a battery attached to the circuit that can be used to power other devices if those devices have a low power mode. In this case, the battery back feature is used to power up to 5 SRAM chips when the board is powered down. The RTC outputs 3.3V on pin VOUT (pin 1) when the board is powered up and a lower voltage when the board is powered down. The VOUT pin (3.3VQ) is connected to the SRAM power. This allows the SRAM to retain all information when no power is on the board. The chip select from the processor (CS0#) for the SRAMs is input into the RTC pin CEIN (pin 26). The chip select signal is then routed out of the RTC at pin CEOUT (pin 25). This allows the RTC to control the state of the pin and prevent any erroneous chip select accesses when power is being shut down, which could corrupt the SRAM. Other devices also powered by the battery can be identified by the 3.3VQ symbol attached to their power lines. The watchdog timer circuit is used to monitor the processor. If the processor does not toggle a signal (WDI pin 23) on the RTC every 3 seconds, the RTC will toggle the reset signal to the processor and other peripherals. This is useful in cases where the processor gets hung up. The function can also be disabled by removing the shorting shunt from JP2. The RTC also keeps time via a crystal input (Y3) of 32.768KHz, which allows the device to keep an internal clock running. The RTC will also generate an interrupt to the processor. Reset Registers Two D flip flops (U35 and U43) retain the condition of the last reset. U35 is used to hold the state of a Watchdog Timer reset and U43 is used to hold the state of the Power Button Reset. 54 DAQ Electronics, LLC Callisto RTU Technical Guide EPLD The EPLD (U33) has multiple functions, including:  Flash device address decode  SRAM address decode  Chip select generation from IOPORT-CS#  LED registers  NMI state machine for bit bang protocol  UART Port1/Modem control  RS232/RS485 port switch Since the EPLD device code is readily available, only a brief description of each function will be provided here (the IoE2 memory maps later in this section provide additional information). The flash address decode takes in the UCS (Upper Memory Chip Select) from the processor (U34) and generates two chip selects (FLSH-CS0# and FLSH-CS1#) based on the addresses (A20, A21, A22, A23) and the header (JP12) settings. JP12 is used to determine the size of the flash devices installed on the board, 1MB or 2MB size devices. If standard 1MB devices are used, the headers are left open. The headers are shorted with a shorting shunt for 2MB devices. FLSH-CS1# is always the active chip select when the processor initially boots. The processor will come out of reset and attempt to read a word from the upper location of memory, which is located in the FLSH-CS1# range. The EPLD handles part of the address decode for the SRAM. This is only one stage in a larger pipeline of stages. The EPLD takes in the CS0Q# from the RTC circuit, which receives the chip select from the processor. The EPLD only partially decodes this logic. This is done due to the desire of the SRAM to be battery backed. The final stage of address decode must be powered by the battery when the power to the board is removed. Otherwise, the EPLD would draw too much current to be powered by the battery, and thus dissipate the battery too quickly. A low power address decode IC (U25) is used as the final stage of decode. The EPLD uses the CS0Q# gated together with the address range A20 to A23 and the jumper settings of JP12 to create the signals required by U25, RSEL0, RSEL1, and RSEL2. The EPLD also generates a number of chip selects for internal registers and external peripherals. These chip selects, whether internal or external, evolve from the IOPORT-CS# signal in combination with addresses A4 through A7. Below, the external chip selects are listed with the devices they go to: ELPD External Chip Selects / Devices Chip Select PORT1-CS# PORT2-CS# PORT3-CS# PORT4-CS# MODEM1-CS# RMODE-REG# RSTATION-REG# RGROUP-REG# RSTATUS-REG# 55 Devices U20 U20 U22 U22 U2 U3 U5 U4 U6 DAQ Electronics, LLC Callisto RTU Technical Guide The EPLD contains internal registers that control whether the LEDs are on or off. These values are written into the registers of the EPLD by the processor, and the outputs of the registers are tied to LED1 and LED2. When the output bit of the register is pulled low (0V) the LED will turn on, and when the output bit is high (3.3V) the LED will turn off. The EPLD also directs where the receive data for port 1 comes from, whether it is the modem chip (U2) or the RS232/RS485 devices (U26/U36). This is accomplished via an internal register setting within the EPLD. In the same way, the EPLD determines where the receive data for all of the ports 1-4 comes from, whether it is the RS232 or RS485 devices. The EPLD takes receive data in and sends the correct receive data out to the uart, according to the register setting. Buffers The data bus coming from the processor is buffered twice by two different buffers (U19 and U42) of the same type, 74VCX16245. These buffers are 16 bit wide bi-directional buffers. The16 bit width of the buffers matches the width of the processor data bus. The directional control of the buffers is determined by either the RD# (read signal), or the WR# (write signal). U42 is a buffer for the flash data bus. It buffers the main data bus from the processor from the flash data bus. The enabling of the buffer is controlled by the UCS# signal, and the direction of the buffer is controlled by the WR# signal. U19 is a buffer that isolates the processor data bus between devices that are mapped into the memory space from the devices that are mapped into the I/O space. The enabling of the buffer is accomplished by the signal from the processor M/IO#. When low (0V), the buffer is enabled and access to the I/O space is being done, and when high (3.3V), the buffer is disabled. The directional control of the buffer is accomplished with the RD# signal, the read signal from the processor. Disk-On-Chip This disk-on-chip device is currently an option on IoE2 boards at location U40. The large, flash-based device allows access to large amounts of memory, through an indirect address scheme, with the capability to perform large amounts of erasing and writing to the device. Flash The IoE2 board is laid out for two flash devices of size 1MB or 2MB. Each device is controlled by a chip select from the EPLD, FLSH-CS0# and FLSH-CS1#. U24 (FLSH-CS1#) is the primary flash device for boot up of the processor. The processor will always access this flash device first to get the information it needs to initiate a correct boot up procedure. JP12 is used to determine what size flash devices are installed on the board, 1MB or 2MB. If standard 1MB devices are used, the headers are left open. The headers are shorted with a shorting shunt for 2MB devices. SRAM The IoE2 is configured to have either 2MB or 5MB of Static RAM, SRAM. For 2MB of SRAM, U23 and U17 will be populated. Otherwise, all of the SRAM devices will be populated. There is a board option to use JP12 to populate larger sized (2MB) SRAM devices (this is currently a future consideration). The SRAM devices are battery backed and have a low power feature, whereby a minimal amount of current is needed to keep the contents or memory stable. This feature of the SRAM allows the devices to be powered by a battery when power to the board is no longer applied. The ability to switch between the battery and board power is controlled by the RTC (U12). 56 DAQ Electronics, LLC Callisto RTU Technical Guide Buffers The IoE2 has three buffers that can read the status of settings on the backplane board: buffer U3 reads the settings of the node headers, buffer U4 reads the settings of the group headers, and buffer U5 reads the settings of the station headers. Buffer U6 reads the values of miscellaneous signals that contain status information needed by the processor. Switching Power Regulator Most of the components on the IoE2 run off of 3.3V, which must be converted from the 5V supplied to the board. This conversion is accomplished via an efficient switching power converter (U1) that will allow up to 3Amps of current to be used. Serial Ports The IoE2 has four asynchronous serial ports controlled by two dual UARTs. UART U20 controls ports 1 and 2, while UART U22 controls ports 3 and 4. All four ports support byte oriented RS232 and RS485 protocols. Port 1 also supports a Bell 202 Modem connection and bit oriented protocols. Port # 1 2 3 4 RS-232 x x x x RS-485 x x x x U20 and U22 202 Modem x Byte x x x x Bit x All of the UARTS are clocked by a 14.7456MHz clock and mapped into the IO space of the processor. The chip select signals for the UARTs are generated by the EPLD. The UARTs also generate interrupts back to the processor. A UART generates a serial transmit data stream which goes to both an RS232 converter and an RS485 converter. The UART also generates an RTS1# signal which goes to the RS232 converter. The UART receives back data from the EPLD which selects whether the port is setup for RS485 or RS232. The UART also receives back a DCD signal from the RS232 converter. The RS232 chip for Port 1 (U26) takes the transmit data signal (TX1) from the UART and converts it into the correct RS232 levels required, which are either > +3V or < -3V (typically, you will see +7V and -7V). The RS232 chip is designed with an internal charge pump configuration, which takes a voltage of 3.3V and generates a larger voltage and a negative voltage. The larger positive voltage can be seen on pin 3 of the device and the negative voltage can be seen on pin 7. The RS232 chip also takes in RTS1# signal from the UART and converts it into the correct RS232 levels. Correspondingly, the RS232 converter chip will take in RS232 level signal and generate the correct 3.3V TTL signals for the UART. This is done for both the receive data and the DCD signal. The receive data is sent to the EPLD before it goes back to the UART, but the DCD signal (DCD1-232) goes directly from the converter to the UART. The RS232 converter is the same for Port 2 (U27), Port 3 (U28), and Port 4 (U29). The RS485 chip for Port 1 (U36) takes the transmit data signal (TX1) from the UART and converts it into the correct RS485 levels required. Since RS485 are bidirectional differential pairs, the TX1 will have a positive version and a negative version based around offset voltages. The RS485 chip will also take in a differential pair and convert it to the correct TTL 3.3V signal. 57 DAQ Electronics, LLC Callisto RTU Technical Guide ArcNET The IoE2 communicates with other boards in the system via the ArcNET interface. The IoE2 processor will send a byte of data to the ArcNET chip (U14) which handles the protocol layer information before sending the data off to the correct board in the system. Data received from other boards is passed into the ArcNET controller and then sent to the processor. The ArcNET controller will send an interrupt (ANET-INT) to the processor, informing it of the data it received. The processor will then do a read of the ArcNET device to obtain the data. The data bus from the processor to the ArcNET device is 8 bits wide and the chip select from the processor is ANET-CS#. The ArcNET chip is located on the IO bus of the processor. The ArcNET is clocked with a 20MHz crystal. Communication between ArcNET devices on different boards is based on RS485 physical interface. The RS485 driver/receiver chip (U15) converts the 3.3V TTL signals to/from RS485 differential levels. The output TXEN (pin 29) is connected to a D flip-flop (U16), which takes the signal and divides it by two; the output drives an LED on the front panel. Ethernet The IoE2 has the added capability of an Ethernet connection. The processor interfaces to the Ethernet device (U30) through a 16 bit wide data bus mapped into the IO space of the processor. The Ethernet device can interrupt the processor (ENET-INT) when it has received new data or is ready to transmit data. The device is clocked by the 25MHz clock (CLKOUT) from the processor. The device also has separate power connection for a digital 3.3V supply and an analog 3.3V supply. This is to ensure that any noise on the digital supply does not get added to the analog signals from the chip. The digital 3.3V is filtered with a pie power filter circuit and supplied to the analog power of U30 (3.3VA). The Ethernet device supplies an analog differential transmit signal and receives an analog differential receive signal. These signals come through a transformer (U41). The Ethernet device also drives two LEDs on the front panel. Modem The IoE2 has an option for a 1200 baud Bell 202 modem. The modem chip (U2) is socketed for this case. All of the mode settings for the chip are setup by the processor writing to register U13, which is mapped into the IO space of the board. All of the transmit data and receive data for the chip along with the control signals for the chip originate from the UART port 1 of U20. When transmitting and receiving data, the analog side of the chip appears like frequency modulation, or FM radio. The modem chip uses both 5V and negative 5V. The negative 5V is generated by a negative linear regulator (U7) using the negative 12V input into the board. The modem can be configured for 2-wire mode and 4-wire mode. In 2-wire mode, only transformer T1 is used and the jumper configuration is set to short out 1 and 3 on JP3. In 4-wire mode, both transformers are used and the jumper settings on JP3 are set to 1 shorted to 2 and 3 shorted to 4. 58 DAQ Electronics, LLC Callisto RTU Technical Guide Memory Maps Memory Space 0x3FF_FFFF Flash Memory U24 and U32 0x3C0_0000 0x3BF_FFFF Reserved 0x200_8000 0x200_07FF Real Time Clock (RTC) U12 0x200_0000 0x1FF_FFFF Reserved 0x100_2000 0x100_1FFF Disk-on-Chip U40 0x100_0000 0x0FF_FFFF SRAM Memory U10, U11, U17, U18, U23 0x00 0000 59 DAQ Electronics, LLC Callisto RTU Technical Guide IO Space 0xFFFF Reserved 0x3400 0x33FF IOPORT-CS# U33 0x3000 0x2FFF Reserved 0x1008 0x1007 ArcNET U14 0x1000 0x0FFF Reserved 0x0400 0x030F Ethernet U30 0x0300 0x02FF Reserved 0x0000 60 DAQ Electronics, LLC Callisto RTU Technical Guide IOPORT-CS# (detailed breakout) 0x33FF Reserved NMI-CTRLREG (internal) 0x30C1 0x30C0 0x30C0 0x30B0 NMI-STATCLR (internal) LEDREG2 (internal) LEDREG1 (internal) RSTATUS-REG# U6 RGROUP-REG# U4 0x30B0 0x30A0 0x30A0 0x3090 0x3090 0x3080 0x3080 0x3070 0x3070 0x3060 RSTATION-REG# U5 RMODE-REG# U3 MODEM-CS# U2 PORT4-CS# U22 0x3060 0x3050 0x3050 0x3040 0x3040 0x3033 0x3030 0x3023 PORT3-CS# U22 0x3020 0x3013 PORT2-CS# U20 PORT1-CS# U20 0x3010 0x3003 0x3000 61 DAQ Electronics, LLC Callisto RTU Technical Guide Environmental Specifications Operating range: Storage range: Relative humidity: Vibration: -20 to +70°C -20 to +70°C 5 to 95% non-condensing 5 to 65Hz Configuration IoE2 configuration is accomplished through its Callisto Host Node via the Callisto Windows configuration utility, CallistoView. Construction Standard 4 layer Double EuroCard PCB 6.25" x 9.25" (160 mm x 235 mm) 62 DAQ Electronics, LLC Callisto RTU Technical Guide ► IoP1 ■ General Description The IoP1 is the parallel processing node board for the Callisto series of remotes and is configurable on a per point basis, allowing for input and output points to exist on the same card. The IoP1 is capable of monitoring or controlling up to 32 points. These points can be combinations of the following:  Command output relays  Binary inputs in 8, 16, 24, and 32 bit format  Binary outputs in 8, 16, 24, and 32 bit format The binary input capability of the IoP1 is limited to a maximum of 32 single-ended negative keyed inputs, and output capability is limited to a maximum of 32 open-collector Darlington drivers used to drive output relays. Those relays may be wired directly to the IoP1 via a DIN termination board or may reside on the IoPT1 termination board. ■ Links The Watchdog circuit is always installed unless debugging with emulator LK2 enables/disables the Watchdog timer as follows: In = Enabled Out = Disabled ■ Connections P1: 64 Pin DIN connector carrying power and ArcNET signals P2: 64 Pin DIN connector interfacing to customer input/output signals via IoPT1 or DIN termination board ■ Termination Board I/O Interface The IoP1 parallel processing node can interface to field I/O via a DIN termination module or the IoPT1 termination board. Termination boards interface with the IoP1 via a 64 conductor ribbon cable. Each IoP1 node can interface with either a single DIN termination board or up to four IoPT1 termination boards. The DIN termination board is used for interfacing with binary input or output points or interfacing with special relays (relays not found on the IoPT1 board). The IoPT1 is an output card for the IoP1 processing node. Each IoPT1 is equipped with 8 individual outputs. The board has eight mercury-wetted relays, which use either a pull up voltage from the IoP1 or an externally supplied voltage. Unlike the IoC1 node, the IoP1 allows for multiple relays to be executed simultaneously. The IoPT1 is link selectable on a per point basis for either Form-A or Form-B relay outputs. ■ LEDs There are 10 LEDs protruding through the front panel indicating the operational status of the board. The 10segment LED is called “LED1”. LED1 contains eight software driven LEDs and two hardware-driven LEDs. 63 DAQ Electronics, LLC Callisto RTU Technical Guide LED 1 1 - Heartbeat 2 - Future use 3 - On-board reconfiguration 4 - Reconfiguration by another board 5 - Future use 6 - Future use 7 - Future use 8 - Future use 9 - ArcNET interrupt 10 - ArcNET transmit enable IoP1 LEDs LED # 1 Description Heartbeat 2 3 4 5 6 7 8 9 10 Future use ArcNET reconfigurations by this board ArcNET reconfigurations by another board Future use Future use Future use Future use ArcNET interrupts TX enable hardware signals Normal Operation Toggles once per second - meaning program running Always off Toggles when reconfiguration occurs Toggles when reconfiguration occurs Always off Always off Always off Always off Flashes approximately once per second Always on ■ Board Drawing List The following board drawings are included in this manual for reference purposes: Board Name IoP1 IoPT1 IoD Drawings Assembly Diagram DAQ Drawing #17176 DAQ Drawing #18544 ■ Technical Description 80C188 Processor Intel 80C188 microcontroller with:  8-bit data bus 64 Schematic Diagram DAQ Drawing #17173 DAQ Drawing #18541 DAQ Electronics, LLC Callisto RTU Technical Guide  20-bit address bus  2 DMA channels  Direct addressing to 1 MByte memory and 64 KBytes I/O The CMOS N80C188-16 is a 16-bit microprocessor with an 8-bit external data bus, which operates at speeds up to 16 MHz. On the IoP1, the microprocessor operates at 12.288 MHz using a 24.576 MHz crystal. It can directly address up to 1 MByte of memory and 64 KBytes of I/O. The microprocessor package is the 68 pin Plastic Leaded Chip Carrier (PLCC). Reset Circuit Manual reset is provided for the IoP1 board via a switch (SW1), which is located on the front panel of the board. Power-up reset and brownout protection is provided by a watchdog timer chip (U28). Watchdog Circuit LK2 enables/disables the Watchdog timer, which is located in U28. In = Enabled Out = Disabled Memory 128Kx8 Flash memory 128Kx8 EPROM 128Kx8 RAM 1Kx1 Serial EEPROM (U25) (U23) (U24) (U9) Communications Port Communications with other Callisto boards is accomplished via the ArcNET LAN. The ArcNET controller (U12) has an RS-485 interface. Inputs 32 command output relays Binary inputs in 8, 16, 24, and 32 bit format Binary outputs in 8, 16, 24, and 32 bit format Power Requirements 290 mA @ 5 VDC 1.5 mA @ 12 VDC + 35 mA when command relay energizes (does not include power for external relay(s), if used) 65 DAQ Electronics, LLC Callisto RTU Technical Guide Operating System The IoP1 operating system is the industry standard Nucleus RTX real-time, multi-tasking OS allowing for simple integration of user-defined applications and algorithms. Local Area Network The LAN protocol is DAQ Voyager protocol operating over the a standard ArcNET Local Area Network at speeds up to 2.5 megabits per second. Environmental Specifications Operating range: Storage range: Relative humidity: Vibration: -20 to +70°C -20 to +70°C 5 to 95% non-condensing 5 to 65Hz Configuration IoP1 configuration is accomplished through its Callisto host node using DAQ CallistoView (or CALVIEW) Windows configuration utility. Construction Standard 4 layer Double EuroCard PCB 6.25" x 9.25" (160 mm x 235 mm) 66 DAQ Electronics, LLC Callisto RTU Technical Guide ► Polaris ■ General Description The Polaris board forms the core of a powerful pole mount or distributed substation RTU for the Callisto series of remotes. Unlike the IoX processor node boards (IoA1, IoC1, etc.), the Polaris does not interface with a motherboard. Instead, the Polaris plugs directly into its own termination board. The Polaris combines the functionality of the IoC1, IoD1, and the IoE1 modules: it is capable of handling 16 status/accumulator inputs, four select/check trip/close control outputs, and up to four communication ports. For information on utilizing the Polaris as a capacitor switch controller, see “Capacitor Bank Controller” in the Specialty Board section of this manual. Communication configurations include RS-232, RS-485, Bell 202 1200 baud modem, and dial-up modem. The Polaris will support options for both synchronous and asynchronous communication, with either bit or byte oriented protocols. Access to both the ArcNET and serial communication ports are via the Polaris termination board. The four communication ports of the Polaris are able to communicate with external devices using different protocols. Port 1, the host port, is configurable for RS-232, an internal Bell 202 1200 baud modem, or dial-up modem. Port 2 is configurable for RS-232 or RS-485, while ports 3 and 4 are RS-232. Communications are byte oriented (port 1 can also be configured for bit oriented protocols). In the byte oriented mode, communications can also be synchronous or asynchronous. The Polaris requires 24 VAC or 24 VDC input power and contains on-board power supplies that convert the 24 volt input power to the +5 VDC and +/-12 VDC required by its own internal logic. The board provides power for its own logic and the following optional equipment: an IoA1 analog processing node, +12 VDC for battery charging, and +12 VDC @ 2.5 amps for radio communications. All Polaris inputs and outputs (I/O) are interfaced through the Polaris termination board, which provides all necessary I/O protection and conditioning. Analog input point capabilities can be added to a Polaris-based RTU with the addition of an IoA1 analog processing node. The Polaris termination board allows for up to nine AC or DC type analog input points (up to 32 analog inputs points can be equipped using the IoAT termination boards). The P3 connector, which is the interface to the IoA1, contains the signals for the ArcNET interface, IoA1 node addressing, and power. P1 and P2 are connections to the Polaris termination board and contain signals for the ArcNET interface and power, as well as the I/O connections and node addresses. The address links for both the Polaris node and the optional IoA1 node are set on the Polaris termination board. LAN ArcNET ArcNET Memory Memory Polaris IoA 80188 80188 DSP I/O I/O I/O 4 Serial Ports 4 Trip/Close Commands 16 Digital Inputs 9 Analog Inputs 67 DAQ Electronics, LLC Callisto RTU Technical Guide +12, +24 VDC Power Supply +-5, -12 VDC 24 VAC Analog Amplifiers IoA Interface ARCNET Interface Status Inputs IoA Address Control Outputs Port 1 202 Modem Serial Port Dial-Up Modem CPU & Support RS-232 Port 2 RS-232 Serial Port RS-485 Memory Port 3 Serial Port RS-232 Serial Port RS-232 Polaris Address Port 4 68 Termination Board Interface DAQ Electronics, LLC Callisto RTU Technical Guide ■ Links This section provides a brief summary of links and connections required for installation. Link LK1 LK2 1-2 LK3 LK4 LK5 LK6 LK7 LK8 LK9 LK10 & LK11 See below LK12 LK13 LK10 Link Position 1-2 2-3 2-3 Link LK1 LK2 LK3 LK4 LK5 LK6 LK7 LK8 Polaris Board Links 2-3 Description Normal Polarity of Bit oriented protocols Port 2 RX synchronous protocols - Polarity selection for external clocks Port 2 TX synchronous protocols - Polarity selection for external clocks Port 3 TX synchronous protocols - Polarity selection for external clocks Port 3 RX synchronous protocols - Polarity selection for external clocks Port 1 RX synchronous protocols - Polarity selection for external clocks Port 4 TX synchronous protocols - Polarity selection for external clocks Port 4 RX synchronous protocols - Polarity selection for external clocks Port 1 TX synchronous protocols - Polarity selection for external clocks See below Port 1 protocol option - Bit oriented (asynchronous or synchronous) Not used N/A Watchdog enable LK10 and LK11 LK11 Link Position 1-2 2-3 1-2 Polaris Termination Board Links 1-2 PTT wired out 2 wire modem See below See below See below Not used See below Not used 69 Mode Port 1 bit Port 1 byte oriented PSTN mode 2-3 PTT strapped high 4 wire modem DAQ Electronics, LLC Callisto RTU Technical Guide LK3 - Node Link Position 1 2 4 8 16 32 64 128 Description IoA1 ArcNET node address with weight of 1 IoA1 ArcNET node address with weight of 2 IoA1 ArcNET node address with weight of 4 IoA1 ArcNET node address with weight of 8 IoA1 ArcNET node address with weight of 16 IoA1 ArcNET node address with weight of 32 IoA1 ArcNET node address with weight of 64 IoA1 ArcNET node address with weight of 128 LK4 - Group Link Position 1 2 4 8 16 32 64 128 RTU/Node Description Address with weight of 1 Address with weight of 2 Address with weight of 4 Address with weight of 8 Address with weight of 16 Address with weight of 32 Address with weight of 64 Address with weight of 128 When out, LK5 represents station address. When in, LK5 represents ArcNET node address of Polaris. Not used - Link Position 1 2 4 8 16 32 64 128 LK5 - RTU/Node (depending upon LK4 - 8) Description RTU/Node Address with weight of 1 RTU/Node Address with weight of 2 RTU/Node Address with weight of 4 RTU/Node Address with weight of 8 RTU/Node Address with weight of 16 RTU/Node Address with weight of 32 RTU/Node Address with weight of 64 RTU/Node Address with weight of 128 LK7 - ArcNET Termination Link Position High Term Low - Installed Installed Installed Not used ■ I/O Interface The status input section of the Polaris board is divided into two identical circuits. Each sub-section handles eight status input points, and each block of eight status inputs can be keyed with either positive or negative voltage, independent of each other. The keying voltage on each block can be 24, 48, or 125 VDC. The polarity and keying voltage options are selected on the Polaris termination board. The field interface to the status input 70 DAQ Electronics, LLC Callisto RTU Technical Guide points is via terminal blocks TB1 and TB2 on the Polaris termination board. External keying voltage is connected to the Polaris via terminal blocks TB11 and TB12 of the Polaris termination board. Each status input point has an optical isolator, which is used to provide isolation and to allow for either keying voltage polarity. Changing from one polarity keying voltage to the opposite is accomplished by reversing the LED5 or LED6 bar displays. LED5 handles points 1 through 8 and LED6 handles points 9 through 16. Octal Dtype latches (U40 and U35) are used to read the outputs from the optical isolators. A 2 x 4 matrix on the Polaris is used to drive the 4-trip/close control output relay pairs that are located on the Polaris termination board. The field interface to these output relays is via terminal blocks TB3 and TB4 of the Polaris termination board. However, the Polaris can drive relays external to the Polaris termination board. In this case, the relays located on the Polaris termination board are bypassed and external relays are driven. Four PNP transistors (Q2 - Q5) are used to drive one side of the four pairs of relays. Each relay pair pertains to a control point. Two NPN transistors (Q6 and Q7) are used to drive the other side of the four pairs of relays. Q6 pertains to the "close" command while Q7 pertains to the "trip" command. A hex D-type latch (U58) is used to latch the point selection as well as the trip or close signal. An octal D-type latch (U44) is used to read the check back from the relay coils. PAL U53 decodes the point selection and the trip/close signals to insure that only a single point and a single command are selected. A command inhibit switch is in series with the emitters on the transistor drivers (Q2 - Q5) to enable or disable controls. Field interface to the analog input points is via terminal blocks TB5 and TB6 of the Polaris termination board. ■ LEDs There are two 10-segment LEDs on the Polaris indicating the operational status of the board, LED7 and LED1. LED7 contains eight software driven LEDs and two hardware-driven LEDs. The first two LEDs on LED1 are reserved for future use and the last eight indicate transmit and receive for the four communications ports. LED 7 LED 1 1 - Heartbeat 1 - Future Use 2 - Future use 2 - Future Use 3 - On-board reconfiguration 3 - Port 4 TX 4 - Reconfiguration by another board 4 - Port 4 RX 5 - Port 4 - Good message received 5 - Port 3 TX 6 - Port 3 - Good message received 6 - Port 3 RX 7 - Port 2 - Good message received 7 - Port 2 TX 8 - Port 1 - Good message received 8 - Port 2 RX 9 - ArcNET interrupt 9 - Port 1 TX 10 - ArcNET transmit enable 10 - Port 1 RX Two octal D-type latches (U41 and U36) are used to read in the 16 bits worth of addressing from the P2 connector. The 8 bits read via U41 can be either the Polaris node address or 8 of the 16 RTU address bits. The 8 bits read via U36 are the remaining 8 bits of the 16 RTU address bits. The meaning of the U41 bits is 71 DAQ Electronics, LLC Callisto RTU Technical Guide determined by the R/N link option, which is read via octal D-type latch U44 in the control section. A third octal Dtype latch (U52) drives the first 8 LEDs of LED bar display LED7. Polaris LED7 LED # 1 Description Heartbeat 2 3 4 5 Future use ArcNET reconfigurations by this board ArcNET reconfigurations by another board Port 4 - Good message received 6 Port 3 - Good message received 7 Port 2 - Good message received 8 Port 1 - Good message received 9 10 ArcNET interrupts being addressed TX enable hardware signals LED # 1 2 3 4 5 6 7 8 9 10 Description Future Use Future use Port 4 - Transmit Port 4 - Receive Port 3 - Transmit Port 3 - Receive Port 2 - Transmit Port 2 - Receive Port 1 - Transmit Port 1 - Receive Normal Operation Toggles once per second - meaning program running Always off Toggles when reconfiguration occurs Toggles when reconfiguration occurs Blinks when good message processed on port 4 Blinks when good message processed on port 3 Blinks when good message processed on port 2 Blinks when good message processed on port 1 Flashes approximately once per second Always on Polaris LED1 Normal Operation Always off Always off Blinks when port 4 transmits Blinks when port 4 receives Blinks when port 3 transmits Blinks when port 3 receives Blinks when port 2 transmits Blinks when port 2 receives Blinks when port 1 transmits Blinks when port 1 receives The Polaris board also features additional LEDs. Two 10-segment LEDs, LED5 and LED6, indicate whether the board status points are connected and operational. LED2 and LED4 serve as power indications. ■ Board Drawing List The following communications sub-system board drawings are included in this manual for reference purposes: Board Name Polaris Polaris termination IoD Drawings Assembly Diagram DAQ Drawing #16841 DAQ Drawing #16965 72 Schematic Diagram DAQ Drawing #16962 DAQ Drawing #16962 DAQ Electronics, LLC Callisto RTU Technical Guide ■ Technical Description 80C188 Processor Intel 80C188 microcontroller with:  8-bit data bus  20-bit address bus  2 DMA channels  Direct addressing to 1 MByte memory and 64 KBytes I/O The CMOS N80C188-25 is a 16-bit microprocessor with an 8-bit external data bus, which operates at speeds up to 25 MHz. On the Polaris, the microprocessor operates at 24 MHz using a 48 MHz crystal. It can directly address up to 1 MByte of memory and 64 KBytes of I/O. The microprocessor package is the 68 pin Plastic Leaded Chip Carrier (PLCC). Reset Circuit Manual reset is provided for the Polaris board via a switch (SW4), which is located on the board. Power-up reset and brownout protection is provided by a watchdog timer chip (U12). Watchdog Circuit LK13 enables/disables the Watchdog timer, which is located in U12. In = Enabled Out = Disabled Memory 128Kx8 Flash Memory 64Kx8 EPROM 256Kx8 RAM 1Kx1 Serial EEPROM (U29) (U33) (U37, U34) (U55) For information on expanding the memory of the Polaris board, see “Polaris Memory Expansion Daughter Board” in the Specialty Board section of this manual. The heart of the Polaris is the 80C188 microprocessor (U23). This CMOS high integration microprocessor has 20 address bits, which can directly access 1 MByte of memory and 64 KByte of I/O. Octal D-type latches (U28 and U43) are used to latch 12 of the 20 address bits on the low-going edge of the Address Latch Enable (ALE) signal. The 80C188 also has seven peripheral and six memory chip selects built in, as defined below: 73 DAQ Electronics, LLC Peripheral Chip Select PCS0 PCS1 PCS2 PCS3 PCS4 PCS5 PCS6 Callisto RTU Technical Guide Chip Select Definitions Hardware Memory Chip Select ArcNET interface LCS Watchdog timer MCS0 RTU/Node address, LEDs MCS1 Serial EEPROM MCS2 Status, controls MCS3 Communications ports 3, 4 UCS Communications ports 1, 2 Hardware RAM RAM RAM Flash memory Flash memory EPROM PCS2, PCS4, and address bits A0-A2 are further decoded by PAL U22 to address the four of the hardware sections shown in the table above (RTU/Node Address, LEDs, Status, Controls). Two of the AND gates in U13 are used to "OR" the MCS0-MCS3 chip selects together to obtain two chip selects for the upper RAM (U37) and FLASH memory (U29). The EPROM socket, U33, can accept either a 64 KByte or 128 KByte EPROM. Each RAM and the Flash memory are 128 KBytes. The serial EEPROM (U55) is 512 Bytes. Interfacing to the EEPROM is accomplished via PAL U48. The 1 MByte of memory space is divided up as shown in the memory map table below: 64x8 KByte EPROM Address Range Description 00000 - 1FFFF RAM 20000 - 3FFFF Not used 40000 - 5FFFF RAM 60000 - 7FFFF Flash 80000 - EFFFF Not used F0000 - FFFFF EPROM Address Range 0000 - 007F 0080 - 00FF 0100 - 017F 0180 - 01FF Description PSC0 PSC1 PSC2 PSC3 128x8 KByte EPROM Address Range Description 00000 - 1FFFF RAM 20000 - 3FFFF Not used 40000 - 5FFFF RAM 60000 - 7FFFF Flash 80000 - DFFFF Not used E0000 - FFFFF EPROM I/O Map Address Range 0200 - 027F 0280 - 02FF 0300 - 037F FF20 - FFFF Description PSC4 PSC5 PSC6 Internal Registers The 64 KBytes of I/O space consists of seven programmable hardware chip selects and a 256 byte block of internal reserved registers. The I/O space is shown in the Polaris I/O Map table. The PSC0 - PSC6 chip selects are further divided down as shown in the Polaris External Hardware table. The addresses shown are the actual addresses used when accessing the hardware. 74 DAQ Electronics, LLC Address 0000 0000 0001 0001 0002 0003 0004 0006 0007 0007 0007 0007 0080 0100 0100 0101 0183 0184 0200 0200 0201 0201 0202 0203 0204 0280 0281 0282 0283 0300 0301 0302 0303 Callisto RTU Technical Guide External Hardware Description I/O Name ArcNET status STATUS_REG ArcNET interrupt mask INT_MASK_REG ArcNET diagnostic status DIAG_STATUS_REG ArcNET command COMMAND_REG ArcNET high address ADDR_HIGH_REG ArcNET low address ADDR_LOW_REG ArcNET data DATA_REG ArcNET configuration CONFIG_REG ArcNET tentative ID TENTID_REG ArcNET node ID NODEID_REG ArcNET setup SETUP_REG ArcNET next ID NEXTID_REG Watchdog timer WATCHDOG_TIMER Node or LSByte RTU HRDWR_NODE Software LEDs LEDS MSByte RTU HRDWR_GROUP Serial EEPROM EEPROM_IN Serial EEPROM EEPROM_OUT Control inputs RCN Control outputs WCN Misc. comm. signals RCOM Misc. comm. signals WCOM Status inputs 0 - 7 RSLO Status inputs 8 - 15 RSHI Port 0 modem control WMC Port 3 85C30 control PORT3_CNTL Port 2 85C30 control PORT2_CNTL Port 3 85C30 data PORT3_DATA Port 2 85C30 data PORT2_DATA Port 1 85C30 control PORT1_CNTL Port 0 85C30 control PORT0_CNTL Port 1 85C30 data PORT1_DATA Port 0 85C30 data PORT0_DATA R/W R W R W R/W R/W R/W R/W R/W R/W R/W R W R W R R W R W R W R R W R/W R/W R/W R/W R/W R/W R/W R/W Communications Ports Communications with other Callisto boards is accomplished via the ArcNET LAN, which consists of ArcNET controller U42 and the U54 RS-485 interface. There are also four other communication ports on the Polaris Board. Port 1, the host port, can be configured to communicate via RS-232, Bell 202 modem, or dial-up modem. The communications protocol can be bit or byte oriented (asynchronous or synchronous). For synchronous protocols, U8 inverters, LK5, and LK9 are used to accommodate different polarities for the external clocks. For byte-oriented protocols, the 85C30 Dual Serial Communications Controller (U21) is used. One half of this IC interfaces to either a RS-232 interface (U26), a Bell 202 modem (U5), or a dial-up modem (also U5). These are all build options. For bit-oriented protocols, a hex d-type latch (U49) is used to output the RTS and TD signals while an octal buffer (U10) is used to read the CTS, DCD, and RD signals. These ICs also interface to the previously mentioned RS-232 interface, Bell 202 modem, or dial-up modem. LK10 and LK11 are positioned based on the bit or byte oriented selection. The connections for LK10 and LK11 are shown in the following table: 75 DAQ Electronics, LLC Callisto RTU Technical Guide LK10 and LK11 Port 1 Protocol Options Option LK10 and LK11 Bit oriented 1 to 2 Byte oriented 2 to 3 A pair of op-amps in U19 buffer the transmit and receive signals when port 1 is configured for an internal modem. The transmit level can be adjusted up to +3 dB (into 600 Ohms) by 10K potentiometer VR1. The receive sensitivity can be adjusted by another 10K potentiometer VR2. Port 2 uses the other half of the 85C30 Dual Serial Communications Controller (U21). This port can be configured to communicate via RS-232 or RS-485. The RS-232 configuration can communicate with byteoriented asynchronous or synchronous protocols. For synchronous protocols, U8 inverters, LK2, and LK3 are used to accommodate different polarities for the external clocks. RS-232 driver (U4) is installed when Port 2 is configured for RS-232 while RS-485 driver (U45) is installed when port 2 is configured for RS-485. A second 85C30 Dual Serial Communications Controller (U20) serves as ports 3 and 4. These ports are RS232 ports, which can communicate with byte oriented asynchronous or synchronous protocols. For synchronous protocols on Port 3, U25 inverters, LK4, and LK5 are used to accommodate different polarities for the external clocks. Similarly, U25 inverters, LK7, and LK8 are used on port 4. Serial Input/Output 4 Independent Serial Communications Ports Baud Rate: Protocol: Interfaces: Modem: Other media: Up to 19.2 Kbit/sec. individually configurable per port Byte or bit-oriented, synchronous or asynchronous 4 Ports individually configurable as RS-232, RS-485 circuits On board 1200 baud, V21, V23 modem for private circuit operation - external modems are supported for both leased line and/or PSTN circuits Fiber, Radio, Packet Radio, plus RS-232 or RS-485 circuits Power Requirements 24 VAC or DC Operating System The industry standard Nucleus RTX real-time, multi-tasking operating system allowing for simple integration of user-defined applications and algorithms Protocol An extensive library of protocols for communications with SCADA master stations and distributed substation devices. 76 DAQ Electronics, LLC Callisto RTU Technical Guide Local Area Network DAQ Voyager protocol operating on the Callisto standard ArcNET Local Area Network at speeds up to 2.5 megabits per second. Environmental Specifications Operating range: Storage range: Relative humidity: Vibration: -20 to +70°C -20 to +70°C 5 to 95% non-condensing 5 to 65Hz Configuration Polaris configuration is accomplished through its Callisto host node using DAQ CallistoView (or CALVIEW) Windows configuration utility. Construction Standard 4 layer Double EuroCard PCB 7 7/8" x 10 3/8" (200 mm x 265 mm) 77 DAQ Electronics, LLC Callisto RTU Technical Guide ► Fiber Optic Transceivers ■ General Description Callisto processing nodes or full RTUs can be networked together in a point-to-point or star configuration. The nodes/RTUs can be connected via RS-485 cabling or fiber optics, allowing a host RTU to communicate with slave RTUs. There are two Callisto fiber optic transceivers, the 1 Port Fiber Optic Transceiver and the 4 Port Fiber Optic Transceiver. Both boards are interfaced to the RTU via RS-485 ArcNET signals. The outgoing signal is converted to light by the transceiver. Typically a “host” will have a 4 Port Fiber Optic Transceiver, thereby allowing it to communicate with four “slaves”. If necessary, up to three 4 Port Fiber Optic Transceivers can be connected together to allow communication with more than four slaves. If a host intends to communicate with only one slave, the host can be equipped with a 1 Port Fiber Optic Transceiver instead of the four port unit. Both transceiver boards transmit data at speeds up to 2.5 Mbps at distances up to .75 miles (1.2 Km) and operate in a half duplex and asynchronous mode. These units can interface with an RS-485 port of an RTU using a twisted pair cable. Data transmitted via fiber optics is not susceptible to any form of external frequency related interference. Since fiber optic drivers use a light-based transmission medium, they are completely immune to electronic noise and ideal for utility environments. Callisto fiber optic boards operate with an 820 nm wavelength. Fiber optic connectors are industry standard ST type. These units will operate with fiber sizes: 50/125um, 62.5/125um, 100/140um and 200um. However, DAQ recommends the use of 62.5/125um fiber cable. ■ Links 1 Port Fiber Optic Transceiver LK1: Provides RS-485 data direction control 1-2: Non-inverted data 2-3: Inverted data LK2: RS-485 120 ohm termination resistor Not Installed: RS-485 120 ohm termination resistor not provided 1-2: Provides RS-485 120 ohm termination resistor 4 Port Fiber Optic Transceiver LK1: Provides RS-485 data direction control 1-2: Non-inverted data 2-3: Inverted data LK2: RS-485 120 ohm termination resistor Not Installed: RS-485 120 ohm termination resistor not provided 1-2: Provides RS-485 120 ohm termination resistor LK3: Cascade 1-2: 1W Cascading selected (note: this option is no longer applicable) 78 DAQ Electronics, LLC Callisto RTU Technical Guide 2-3: 4W Cascading selected JP1: Enable external power input +5VDC via DB9 connector JP2: Enable external power input +12VDC via DB9 connector ■ Connections 1 Port Fiber Optic Transceiver DB9 Female Connector Pin # 1 2 3 6 8 9 Signal TXEND + +12V +5V GND Description RS-485 direction control Negative RS-485 Positive RS-485 Power input Power input Ground Optical Connectors FOTX1 FORX1 Optical transmit Optical receive Terminal Block TB1 Pin # 1 2 Signal +12V 0V Description Input power Input power 4 Port Fiber Optic Transceiver DB9 Female Connector Pin # 1 2 3 6 8 9 Signal TXEND + +12V +5V GND Description RS-485 direction control Negative RS-485 Positive RS-485 Power input Power input Ground 79 DAQ Electronics, LLC Callisto RTU Technical Guide Optical Connectors FOTX1 FORX1 FOTX2 FORX2 FOTX3 FORX3 FOTX4 FORX4 Optical transmit port 1 Optical receive port 1 Optical transmit port 2 Optical receive port 2 Optical transmit port 3 Optical receive port 3 Optical transmit port 4 Optical receive port 4 Terminal Block TB1 Pin # 1 2 3 4 5 6 7 8 Signal +12V 0V +5V U REC U TX L REC L TX 1W Description Input power Input power Power input Upper receiver, 4W cascade Upper transmitter, 4W cascade Lower receiver, 4W cascade Lower transmitter, 4W cascade Cascade selected (note: this option is no longer applicable) ■ LEDs 1 Port Fiber Optic Transceiver: LED # 1 2 1 Port Fiber Optic Transceiver LED Description Normal Operation RD Receive data TD Transmit data 4 Port Fiber Optic Transceiver LED # 1 2 4 Port Fiber Optic Transceiver LED Description Normal Operation LOC Local data EXT External data coming from upper/lower 4W cascade ■ Board Drawing List The following board drawings are included in this manual for reference purposes: Board Name 1 port fiber optic transceiver 4 port fiber optic transceiver IoD Drawings Assembly Diagram DAQ Drawing #17151 DAQ Drawing #17156 80 Schematic Diagram DAQ Drawing #17148 DAQ Drawing #17153 DAQ Electronics, LLC Callisto RTU Technical Guide ■ Technical Description Power Requirements 1 Port Fiber Optic Transceiver: From TB1 terminal bock option 12 VDC@ 180 ma From DB9 option 12 VDC@ 100 mA 5 VDC@ 80 mA 4 Port Fiber Optic Transceiver: From TB1 terminal bock option 12 VDC@ 480 ma From DB9 option 12 VDC@ 400 mA 5 VDC@ 80 mA Environmental Specifications Operating range: -20 to +70°C Storage range: -20 to +70°C Relative humidity: 5 to 95% non-condensing Vibration: 5 to 65Hz Construction 1 Port Fiber Optic Transceiver: Standard 2-sided PCB 2.75” x 2.75” (70 mm x 70 mm) 4 Port Fiber Optic Transceiver: Standard 2-sided PCB 5.5” x 2.75” (140 mm x 70 mm) 81 DAQ Electronics, LLC Callisto RTU Technical Guide ► IRIG-B Demodulator ■ General Description The IRIG Demodulator module accepts an amplitude-modulated IRIG-B input signal and converts it to an RS232 compatible digital data stream, which can be interpreted by a Callisto computer. The IRIG signal conveys accurate time information that may be used for a time reference at a remote location. The amplitude-modulated signal uses a higher amplitude to represent a logic one bit and a lower level to represent a zero. The fundamental frequency is 1 kHz and the amplitude changes only at the zero crossings. Every 10 milliseconds, the amplitude begins at a high level. Some time into the 10-millisecond period, the amplitude switches low. The time duration of the high level conveys information that the computer decodes. The input signal is connected to either the J1 BNC connector or to terminals 1 and 2 of TB1. The gas tube (GT1) is used to shunt surges to earth ground and transformer T1 isolates the IRIG signal from the electronics. R1 is the input to an op amp circuit U1-A. It presents a fixed impedance to the IRIG source. CR1 and CR2 are used for protection to clamp any high level surges to common. R2 and R3 set the gain of the amplifier. The modulated IRIG signal has a nominal 10-to-3 ratio of high-to-low level. The circuitry around Q1 is designed to illuminate LED1 when the gain is set too high. When U1-1 goes negative by about one base-emitter drop below -6 volts, Q1 conducts, which lights LED1. U1-C and resistors R5 through R8 and CR3 and CR4 act as a slicer. U1-8 will go high any time the output of the first amplifier goes above 3.37 volts or goes below –3.37 volts. The gain potentiometer (R3) should be set so that with high amplitude input bits, the output at U1-8 switches high because with each half wave, the signal at U1-1 exceeds the + -3.37-volt slicing level during a portion of the half sine wave. However, the peak amplitude of the logic 0, or low input wave, should never reach the 3.37-volt threshold. Thus, with high level input, U1-8 switches up for a portion of every half wave, but with low level input, U1-8 never switches. The output of U1-C at pin 8 is connected via R9 and R10 to the D input of U3-A at pin 5. R9, R10 and CR5 are used to clamp the signal into U3 to a safe voltage and limit current out of U1-C. The clock input to U3-A at pin 3 is timed to sample the state of U1-C output precisely at the positive and negative peaks of the 1 kHz IRIG signal. The Q output of U3-A at pin 1 will then be a high if the IRIG signal is high, and will be a low if the IRIG signal is low. The voltage at pin 1 remains stable between sample times. The purpose of U3-B and U4-A is to delay the output from U3-A. U3-A pin 1 can change 1/4 of a cycle after the IRIG sine wave crosses 0. The output at U4-1 is the same as that at U3-1, except it is delayed by 3/4 of a cycle, or exactly 1 millisecond from when the IRIG signal crossed zero (remembering that the input signal frequency is 1 kHz). U6 converts the logic signal to an RS232 level signal. R23, R24 and CR8 limit the voltage at U6 input pin 2 to a safe voltage below its rated maximum. U1-B is meant to square up the output of U1-1, which has a sinusoidal shape. When U1-1 goes low, CR6 is reverse biased and there is nothing to prevent the output of U1-7 from saturating at the op amps most positive output level. However, when U1-1 goes positive, current flows through CR6 in the forward direction and the output of U1-7 only drops to -.7 volts. The output at U1-7 is then a square wave switching between -.7 volts and approximately 10 volts. The output of U1-B at pin 1 is the signal input to the phase-locked loop integrated circuit U5. U2, sections A and B, form a divide-by-four circuit that is fed back to pin 3 of the phase-locked-loop. R19, R20 and C7 are the components that determine U5 VCO output frequency. R21, R22 and C4 set the oscillator stability and capture 82 DAQ Electronics, LLC Callisto RTU Technical Guide speed. When the phase-locked-loop is locked onto the input frequency, the VCO output is 4 kHz. U2 is wired in such a way that U2-2 goes high every half cycle of the input frequency at exactly the positive and negative peaks. ■ Board Drawing List The following board drawings are included in Section 5 of this manual for reference purposes: Board Name IRIG-B demodulator IRIG-B Drawings Assembly Diagram DAQ Drawing #19948 Schematic Diagram DAQ Drawing #19949 ■ Technical Description Adjustments The only adjustment is R3, the gain potentiometer. Its final setting must be determined after installation in the field. With the IRIG-B signal connected to the input, this pot should be adjusted clockwise (increasing gain) until both LEDs illuminate and then backed off, or turned counterclockwise, until LED1 goes out. Connections The IRIG-B signal is connected to either TB1 terminals 1 and 2 with twisted pair cable or to J1 using coaxial cable with a BNC connector at the end. The output, either at J2 pin 2 or at TB1 terminal 8 is connected to the receive data input of a serial port. Power, is connected to TB1: +12 volts to terminal 5, -12 volts to terminal 6 and common to terminal 7. 83 DAQ Electronics, LLC Callisto RTU Technical Guide ► Specialty Boards ■ TBI3 Analog Interface Board The TBI3 Analog Interface board is used to create a physical electrical connection from an SLD (Sliding Link Disconnect) terminal block to an IoAT2 Analog Termination board utilizing 5/8” stud spacing. The TBI3 board is primarily used in retrofit RTU applications in which the wiring from monitored analog points is terminated to an SLD terminal block. These blocks are mounted inside an enclosure, adjacent to corresponding IoAT2 boards. Manufacturers of this type of terminal block include States and Poweright. The TBI3 board resembles a comb, with the backbone providing placement for two 16-pin Berg-type connectors, P1 and P2. Only one of these connectors is installed on the board, depending on the left or right side positioning of the IoAT2 boards with respect to the SLD terminal block. Eight finger-like protrusions are milled into the board, with a 0.210” diameter hole at the end of each protrusion. The electrical paths on the board provide connection from the pins of the Berg connector to the land at the end of the appropriate protrusion. The TBI3 board is installed on the SLD terminal block by positioning the holes at the end of the TBI3 protrusions over the corresponding threaded studs of the terminal block and sliding the board down to the base of the block. The TBI3 is then secured to the terminal block with #10-32 UNF nuts and lockwashers. A short length of ribbon cable with 16-position female Berg connectors at each end is used to electrically connect the TBI3 board to the IoAT2 board. Board Drawing List The following board drawings are included in this manual for reference purposes: Board Name TBI3 Analog Interface TBI3 Drawings Schematic Diagram DAQ Drawing #17019 ■ TBI1 Status Interface Board The TBI3 Status Interface board is used to create a physical electrical connection from an SLD (Sliding Link Disconnect) terminal block to an IoDT1 Digital Termination board utilizing 5/8” stud spacing. The TBI1 board is primarily used in retrofit RTU applications in which the wiring from monitored status points is terminated to an SLD terminal block. These blocks are mounted inside an enclosure, adjacent to corresponding IoDT1 boards. Manufacturers of this type of terminal block include States and Poweright. The TBI1 board resembles a comb, with the backbone providing placement for two 16-pin Berg-type connectors, P1 and P2. Only one of these connectors is installed on the board, depending on the left or right side positioning of the IoDT1 boards with respect to the SLD terminal block. Eight finger-like protrusions are milled into the board, with a 0.210” diameter hole at the end of each protrusion. The electrical paths on the board provide connection from the pins of the Berg connector to the land at the end of the appropriate protrusion. 84 DAQ Electronics, LLC Callisto RTU Technical Guide The TBI1 board is installed on the SLD terminal block by positioning the holes at the end of the TBI1 protrusions over the corresponding threaded studs of the terminal block and sliding the board down to the base of the block. The TBI1 is then secured to the terminal block with #10-32 UNF nuts and lockwashers. A short length of ribbon cable with 16-position female Berg connectors at each end is used to electrically connect the TBI1 board to the IoDT1 board. Board Drawing List The following board drawings are included in this manual for reference purposes: Board Name TBI1 Status Interface TBI1 Drawings Assembly Diagram DAQ Drawing #17012 Schematic Diagram DAQ Drawing #17009 ■ L5T Analog Termination Board L5T Analog Termination boards are used to ground any unused inputs of the IoA1 Analog Processing Module. This keeps unwanted noise that may be picked up through the input ribbon cables from affecting the adjacent input points. The L5T is available in two configurations. The L5T-1 option is used to ground the unused analog inputs on the fourth IoAT1. The L5T-2 option is used to ground the unused analog inputs on the second and third IoAT1 and any IoAT2 board location. Construction: single-sided board, 2.75” x 1.5” Board Drawing List The following board drawings are included in this manual for reference purposes: Board Name L5T Analog Termination L5T Drawings Assembly Diagram DAQ Drawing #A20106 Schematic Diagram DAQ Drawing #A20107 ■ Polaris Memory Expansion Daughter Board The Polaris Memory Expansion Daughter Board is a plug-in module that provides the Polaris main processor board with additional RAM and flash memory. This memory expansion is necessary for Polaris RTU configurations that run many applications concurrently. Depending on the option specified, the daughter board can support up to 512 KB of flash memory and 256 KB of RAM (128 KB volatile RAM, plus 128 KB batterybacked RAM). With the daughter board installed, the amount of available RAM is equal to 256 KB (the total of RAM chips U34 and U37 on the main processor board), plus an additional 128 KB or 256 KB, depending on the selected daughter board option. The 128 KB option can be provided as volatile RAM or battery-backed RAM. The battery-backed RAM option is useful in situations where data loss upon power failure is unacceptable, such as event recording or data archiving. The 256 KB option provides 128 KB of volatile RAM and 128 KB of batterybacked RAM. 85 DAQ Electronics, LLC Callisto RTU Technical Guide The amount of flash memory available with the daughter board installed is either 384 KB or 512 KB, depending on the option selected. Without the daughter board, the amount of available flash memory on the main processor board is 128 KB. The daughter board is easily installed in the Polaris main processor: 1. Remove the boot EPROM (U33), flash memory chip (U29), and octal latch (U28) from the board 2. Orient the daughter board so that the pins at the bottom of the board line up with the sockets left vacant from step one above 3. Gently push down on the daughter board until it bottoms in the sockets Board Drawing List The following board drawings are included in this manual for reference purposes: Board Name Polaris Memory Expansion Daughter Board Drawings Assembly Diagram DAQ Drawing #A20472 Schematic Diagram DAQ Drawing #A20473 ■ Capacitor Bank Controller Option The function of the Capacitor Bank Controller is to allow capacitor switches to open or close with as little disturbance on the power line as possible. To do this, the switch must close at the voltage zero crossing and open at the current zero crossing. The controller consists of three printed circuit boards: a controller board containing the logic and manual control panel, a switch driver board providing the high power drivers required to drive the solenoid, and a suppression assembly to protect the controller and driver board from any transients that could affect status feedback and the output drivers from any inductive spikes from relay coils. Capacitor Bank Controller Board The controller card contains a micro-controller, a zero crossing detector, three disturbance detectors, and three open/close output pairs. The controller can operate each phase independently, or all phases together (each switch opening/closing at zero crossing of its associated phase). The dedicated micro-controller makes all of the timing and correction calculations, by observing the disturbance on line as the switch closes or opens. It detects the zero crossing of the voltage and, after waiting a calculated amount of time, will output the command to the switch. The wait time is the amount required by the control circuits plus the actual switch operate time, subtracted from one or more full cycle times (the mechanical delays may be more than one cycle). The time delay is actually an anticipation time, so that the completion of the switch operation will occur exactly at the next zero crossing. Each time the switch operates, the line is monitored for a disturbance. If a disturbance is detected, the time of the disturbance is measured from the actual zero crossing, and a new time delay is calculated and stored in non-volatile memory. Six times are stored, one for close and one for open for each of the three phase switches. 86 DAQ Electronics, LLC Callisto RTU Technical Guide Each one of the three disturbance detectors consists of a high pass filter with a cutoff frequency of 2 KHz, and an adjustable comparator. If the amplitude of the disturbance is below the limit of the comparator, it is assumed that the closure/opening was at, or very close to, the zero crossing, and that the current timing values are correct. If a disturbance is detected, the time of the disturbance is recorded, and a new anticipation time is calculated. This value is then stored for use in the next switch operation. A local panel allows selection of the controller mode (automatic or manual), individual control of each (open/close), and selection of supervisory operation from a remote master location. Ultra-bright LED displays (for sunlight viewing) on the panel provide indication of the mode (automatic/manual) and status (open/closed) of each switch. The control panel allows an operator to select either automatic or manual mode of operation. The mode may also be changed via a command from a master station. The mode is stored in a magnetic latching relay to prevent loss in case power is interrupted. When in manual mode, each of the switches may be operated individually from either location. The master may also send an “all” command, which will command all three switches to operate within the appropriate three-phase cycle. When operating in automatic mode, or via the master station, all switch operations are synchronous. When operating any of the switches from the local panel in the manual mode, they will operate in a non-synchronous manner, without regard for the zero crossing. This is so that in the event of a failure of the controller board, a local operator will still be able to open or close the switches. A supervisory cutout switch is provided on the panel. When placed in the cutout position, the switch will prevent any commands from being accepted from the master station. Board Drawing List The following board drawings are included in this manual for reference purposes: Board Name Capacitor Bank Controller Capacitor Bank Drawings Assembly Diagram DAQ Drawing #19550 Schematic Diagram DAQ Drawing #19547 Capacitor Bank Driver Board The switch is operated on DC power. By using a regulated 160 VDC, the switch operating timing is maintained at very consistent values. The switch driver module contains the regulated 160 VDC, the switch driver triacs, and a delay circuit to allow the triacs to recover after firing. The energy to power the switch is stored in three large 4700F capacitors (one per switch) mounted separately. Three neon lamps indicate that the capacitors are charged above 90 volts, but do not indicate whether the capacitors are fully charged. Each lamp will go out when its associated switch is commanded. Whenever a triac is fired, the capacitor is completely discharged, and the triac recovers control due to loss of holding current. To ensure that the current will go to zero, a timer cuts off drive to the triac and also shuts down supply power for two seconds after each operation. It takes approximately 45 seconds for a single capacitor to recharge, and may take up to two minutes for a complete recovery during an “all phase” command, where all three are discharged, or from a power up condition. 87 DAQ Electronics, LLC Callisto RTU Technical Guide ■ Power Filter Board The Power Filter board is utilized to protect the circuitry within any DC input, multi-card RTU. The board protects the input power supplies by using a Pi section filter to block voltage spikes that may have an affect on the power supplies or status inputs. Isolation Electrical interference: Insulation/isolation: IEC 255-5 High frequency disturbance: IEC 255-22-1 Fast transient/burst: IEC 801-4 Electrostatic discharge: IEC 801-2 Environmental Specifications Operating range: -20 to +70°C Storage range: -20 to +70°C Relative humidity: 5 to 95% non-condensing Vibration: 5 to 65Hz Construction Double-sided printed circuit board 2.75” x 4.5” Board Drawing List The following board drawings are included in this manual for reference purposes: Board Name Power Filter Power Filter Board Drawings Assembly Diagram DAQ Drawing #ACB-08510 88 Schematic Diagram DAQ Drawing #A24340 DAQ Electronics, LLC Callisto RTU Technical Guide ► Maintenance and Troubleshooting In addition to the information provided in the following sections, extensive technical FAQs and downloads are available from the technical support section of the DAQ website (www.daq.net). Please make careful notes of all steps performed while troubleshooting, as these notes may prove to be helpful in fixing the problem. ► Determining Network Health When looking at any RTU that is not working properly, the first step is to determine the health of the network. This can be accomplished by looking at the third and fourth LEDs on each of the processor node boards. These LEDs may be either ON or OFF but it is important to observe if they are toggling. If the third or fourth LED is toggling on the boards, determine which modules are toggling their third LED and which are toggling their fourth. Most likely, only one module will be toggling its third, while all others will be toggling their fourth. If this is the case, remove the board that is toggling the third LED (or hold down its reset button), and see if the toggling stops on all of the other modules. If it does, either the module is bad, or the strapping of the node address is incorrect. First, check the node addressing (assure that it is not a duplicate with another node’s address) and then try replacing the module. If there is more than one module toggling its third LED, the RTU has split into separate networks. This will only happen in a distributed RTU. If this has happened, it implies that there is probably a bad fiber-optic modem, as well as a bad module, which should be diagnosed as above. Once the health of the network is verified (third and fourth LEDs not toggling on any modules) it is much easier to troubleshoot the network. ► Communication Problems The communication sub-system consists of several parts that may have a problem:  Master station or test box  Radio or modem  Cable interfacing to communications port:  DAQ provided cable connecting DB9 on front panel to DB9 on IoET1  IoET1 or Polaris Termination  IoE1 or Polaris The first step in troubleshooting communications is to look at the communication LEDs. These are the first and second LEDs on the second bank of the IoE1/IoE2 and the ninth and tenth LEDs on the second bank of the Polaris. The second and ninth, respectively, represent receive data. When a poll is sent to the master, this receive data light should blink (“OFF” on the IoE1 and “ON” on the Polaris). If this is happening, it verifies that all of the ribbon cables and connectors leading to the IoE1 or Polaris are working. If this LED is not blinking, the problem is likely in the hardware external to the RTU (ribbon cables, connectors, laptops, etc), or the build option/links on the IoE1/IoE2 are incorrect. Once the determination is made that the receive data LED is blinking, the next place to look is the Good Station LED. This is the eighth LED on the first bank for the IoE1, IoE2, and Polaris. This light blinks ON when the board processes a message that was intended for it. If this light is not blinking ON, the problem may be: 89 DAQ Electronics, LLC Callisto RTU Technical Guide  Incorrect protocol in the firmware (using an EPROM intended for a different protocol than the system is using)  Incorrect communications parameters in the configuration  Incorrect station address  Crystal OSC1 not working / not installed  Bad IoE1/IoE2 module/Polaris module ■ Incorrect Protocol Selected in Firmware If using an EPROM configured at the factory, verify with DAQ that the correct files have been sent to you. If using firmware that supports the configuration program, verify that the protocol and board for the EPROM is correct (i.e. SESPOL.HEX on a system with a Polaris communicating SES-92 protocol or RPIIOE.HEX for a system using an IoE1/IoE2 communicating with DAQ RPI protocol). ■ Incorrect Communications Parameter in Configuration Verify that the communications parameters entered in the CALVIEW program are correct. Also, re-verify that the configuration has downloaded successfully. ■ Incorrect Station Address Verify that the Group and Station links are correctly set up on the Motherboard or Polaris Termination board. These links must agree with the station address being sent from the master station or the protocol test set. ■ Crystal OSC1 Not Installed Verify that Crystal OSC1 is installed in the IoE1, IoE2, or Polaris board. ■ Bad IoE1 or Polaris Module This is easy to test by trying a known working IoE1, IoE2, or Polaris in place of the board in question. If the new board works, there is a hardware problem. If it does not, the problem is elsewhere. ■ Other Communication Problems If the Good Station LED is blinking (eighth LED), the next thing to look at is the Transmit LED. This is the first LED on the second bank of the IoE1/IoE2, which should blink OFF, and the ninth LED on the second bank of the Polaris which should blink ON. If these LEDs are blinking, it means that the IoE1, IoE2, or Polaris is responding to the request, but the test box or master is not hearing it. Once again, this implies that there is a problem with the ribbon cables, connectors, test box, etc. If these lights are not blinking, there is potentially a problem with the -12 volts in the RTU. This should be verified as good or bad and replaced accordingly. If all of these steps fail, contact the factory for additional assistance. 90 DAQ Electronics, LLC Callisto RTU Technical Guide ► Control Outputs Not Operating Note: when troubleshooting control outputs, be certain to open all disconnect links or disconnect the IoCT plug-in terminal blocks to avoid inadvertent operation of field devices. If you are attempting to issue a control output and it does not function properly it can be due to:  Command Inhibit Switch  Incorrect configuration  Bad IoC1  Bad IoCT  Bad ribbon cables When determining the cause of a control output problem, it is important to focus on the manner in which the control outputs are separated: there are 16 control pairs per IoC1, and 4 control pairs per IoCT. The first step is to determine which control output(s) are not working. If it is a single group of 16 points, the problem lies within the configuration or hardware of a single IoC1. If a group of 4 points is not working, it is likely a single IoCT. If all of the points in the remote are not working, the Command Inhibit Switch may be the problem. ■ Command Inhibit Switch Verify that the Command Inhibit Switch is in the enabled position. If it is not, switch it to the enabled position. If any control outputs in the RTU are functioning, the Command Inhibit is not the problem. ■ Incorrect Configuration First, determine if messages are being sent to the IoC1 by observing the ninth LED on the IoC1 board. When controls are not being sent, this LED will not be toggling, or it will be toggling at a rate of once per second. When a control message is sent from the master or test box, the ninth LED should register an extra blink. If this blink is occurring, the problem is not in the configuration. If the blink is not occurring, there is likely a configuration problem. There can only be one configuration problem associated with control outputs: the node addresses in the configuration do not match the node addresses strapped for the IoC1 board. Verify that the strapped node addresses match those assigned in CallistoView (CALVIEW) or those assigned by DAQ. ■ Bad IoC1 Replace the current IoC1 with an IoC1 that is known to be working correctly. If this fixes the problem, there is a hardware problem on the IoC1. If it does not, the problem lies elsewhere in the RTU. ■ Bad IoCT or Ribbon Cable This can be verified by trying a different IoCT or moving the ribbon cables around within the RTU. For example, try moving the ribbon cable labeled X1 (X being any letter) into the slot currently occupied by X2. The controls for X1 (the first four points on this IoC1 board) are now being directed to a different IoCT. If the controls work, 91 DAQ Electronics, LLC Callisto RTU Technical Guide the problem is the first IoCT board. Alternately, if the points that are not working follow a specific piece of the ribbon cable (i.e. location X1), the problem is in the ribbon, and it will need to be replaced (please contact DAQ). ► Status Inputs Not Operating As with control outputs, it is important to determine which point(s) are not working. Groups of 32 points tend to imply a whole IoD1 is malfunctioning, while groups of 8 points imply a single IoDT module has malfunctioned. There are three common situations that may be found with status problems: 1. The LED indications never light, either with the field contacts or a clip lead. This situation implies a hardware problem in the IoD1, IoDT, or ribbon cable. The source of the problem can often be discovered by swapping out the IoD1 or IoDT with a board that is known to be working. Additionally, moving ribbon cables and boards may also help. For example, try moving the ribbon cable labeled X1 (X being any letter) into the slot currently occupied by X2. The status for X1 (the first eight points on this IoD1 board) are now being directed to a different IoDT. If the status point now work, the problem is the first IoDT board. Alternately, if the points that are not working follow a specific piece of the ribbon cable (i.e. location X1), the problem is in the ribbon, and it will need to be replaced (please contact DAQ). 2. The LED indication works properly with a clip lead, but not with the field contacts. This situation implies a problem with the operation or wiring of the field contacts. This is a problem external to the RTU and should be handled accordingly. 3. The LED indications always light correctly, both with the field contacts and a clip lead. This situation implies a problem in the configuration. It is likely that the node addresses are not correct: the node addresses in the configuration do not match the node addresses strapped on the boards. Verify that the strapped node addresses match those assigned in CallistoView (CALVIEW), or those assigned by DAQ. If all of these steps fail, contact DAQ for additional assistance. ► Analog Inputs Not Operating Several problems may arise depending upon the use of EPROM-based configurations provided by DAQ or CallistoView (CALVIEW) generated configurations. ■ Analogs Not Reporting Verify that the ninth LED on the IoA1 board is toggling on and off, implying that the IoA1 is sending data. If it is not toggling, there is likely an IoA1 hardware problem. If it is toggling, the problem is either an incorrect DAQ prom configuration or mismatched node addresses. Verify that the strapped node addresses match those assigned in CallistoView or those assigned by DAQ. If the node addresses are correct and the configuration was burned in the EPROM by DAQ, please contact the factory for assistance. 92 DAQ Electronics, LLC Callisto RTU Technical Guide ■ Incorrect Values Reported for Physical Inputs If the values being reported for the inputs physically present at the terminations are incorrect:  Verify that the configuration is correct: the points being reported/mapped are in the correct order.  Verify that one side of the SPCT-1 inputs are grounded.  Verify that all unused inputs are shorted.  Measure the input at the termination card. Consult the following table for expected values. If the values are incorrect at the terminal block, something is wired incorrectly external to the RTU. Input Type 0-150 Volt PT 0-150 Volt PT 0-5 Amp CT Lindsey/SquareD Current 12 KV Lindsey/SquareD Voltage 12 KV Lindsey/SquareD Voltage 22 KV Lindsey/SquareD Voltage 22 KV Lindsey/SquareD Voltage 34 KV Lindsey/SquareD Voltage 34 KV Lindsey/SquareD Voltage Expected Values Engineering Value Output to Amplifier 2.331 VAC 2.9143 VAC .333 VAC .34635 VAC 0.7217 VAC Counts 120 VAC 150 VAC 1200 Amps for 1200:5 CT 1200 Amps 120 VAC Input to Board 120 VAC 150 VAC .333 VAC 12 VAC 0.7217 VAC 150 VAC 0.9021 VAC 0.9021 VAC 2047 120 VAC 1.299 VAC 1.299 VAC 1638 150 VAC 1.624 VAC 1.624 VAC 2047 120 VAC 1.991 VAC 1.991 VAC 1638 150 VAC 2.488 VAC 2.488 VAC 2047 1638 2047 2047 2047 1638  If the values at the terminal blocks are correct, measure the analog value coming out of the amplifier. The amplifiers for a particular point are directly across from the associated field wiring. With a volt meter, place the ground/common lead on pin 5 of the amplifier. Then place the hot lead on pin 6 of the amplifier. The measured signal should correspond with the chart above. If the values are incorrect, the termination platform may be incorrect, or the amplifier on the board is bad and should be changed.  If the all of the above check correctly, there is probably a bad IoA1 card. This can be checked by substituting a known working card into the slot and verifying the results. ► Calculated Analog Point Values Are Incorrect If the calculated analog point values are incorrect, and all of the physical inputs are reporting correctly, there can be one of three problems. 1. If using a PROM where DAQ has done the configuration in the EPROM, the configuration may be incorrect. 2. If using a configuration done in CallistoView, it may be incorrect. Verify the types of metering used and that the right points have been selected for reporting. Also, check that the mapping is in the expected order. 93 DAQ Electronics, LLC Callisto RTU Technical Guide 3. There is a phasing problem on the inputs from the field. Verify that the voltage and current pairs are presented to the terminal blocks in the correct order, and that Phase A Current is paired with Phase A Voltage, Phase B with Phase B, etc. for all pairs. It is extremely unlikely that there is a hardware problem if the physical inputs are all reporting correctly. ► Configuration Will Not Download Verify that the cable is plugged into the correct location. This would be P5 on a Polaris, P2 on the back of an IoET1, or its location on front of the bin.  Verify that the correct communication port is identified in CallistoView.  Verify that you are using the correct version of firmware.  Verify that the IoE1/IoE2 is set up correctly. U21 should be installed, and U7 should not be installed. If all of this appears correct, try another known working IoE1/IoE2 card. ► Customer Service Information ■ Limited Equipment Warranty DAQ Electronics, LLC warrants that our products are free from defects in workmanship and material for a period of one (1) year from date of delivery. DAQ ‘s sole obligation under this warranty shall be limited to correcting, without charge at its factory, any part or parts therefore which shall be returned transportation prepaid. This warranty does not apply to any DAQ equipment that has been subject to neglect, misuse, improper installation, or accident. DAQ shall not be liable for loss or damage other than above stated, whether ordinary or exemplary, caused either directly or indirectly by users of this product. This warranty supersedes and is in lieu of all other warranties expressed or implied. No other liabilities may be assumed unless expressly authorized in writing by DAQ Electronics, LLC. ■ Service Warranty It is the policy of DAQ Electronics, LLC, to repair, without charge, any DAQ manufactured equipment returned to the factory during the warranty period. DAQ will repair all equipment as quickly as possible with priority being given to the most critical equipment. In emergency situations, DAQ can ship replacement units on a 24-hour notice, providing stock of the particular equipment exists. ■ Instructions for Obtaining Equipment Service Telephone DAQ Electronics, LLC, using the following number: (732)981-0050. DAQ’s hours of operation are 9:00 a.m. to 5:00 p.m. E. S. T. Monday through Friday. DAQ recognizes national holidays. 94 DAQ Electronics, LLC Callisto RTU Technical Guide Please have the following information available:  Your name and phone number  The name of your company  Purchase order number (if out of warranty)  Billing and shipping instructions  A brief description of the problem you are experiencing. A return authorization (RA) number will be assigned. Please mark the packing list with the number and return the equipment to: DAQ Electronics, LLC 262B Old New Brunswick Road Piscataway, N.J. 08854-3756 Attn: Service Department ■ Field Service The service of a qualified service engineer is available from DAQ in the event of system failure or mis-operation. Before any field service is supplied, DAQ will attempt to correct any problems over the phone, avoiding costly service calls to the customer. Cost for field service is based on the individual system. Please consult with the Customer Service Department at DAQ for pricing and availability of personnel. 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho hoho hoho ho ho ho ho ho ho ho ho ho ho ho ho hoho hoho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho hoho ho hoho ho hho oho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho 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ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho ho hohohoho hohohoho hohohoho hohohoho ho ho PAGE 2 PAGE 3 CPU D[0..15] D[0..15] RST-CLR# PORT1-INT PORT2-INT PORT3-INT PORT4-INT ENET-INT ANET-INT NMI-OUT TMROUT0 ANET-CS# ENET-CS# IOPORT-CS# DOC-CS# TCK TDO TDO_0 TMS UART-CLK CS0# CS0Q# CS0Q# RCS0# RCS1# RCS2# RCS3# RCS4# UCS# CS0# CS0# FLSH-CS0# FLSH-CS1# RTC-RST# UCS# UCS# PB-RST PB-RST NMI-START NMI-EDGE NMI-TIMER CLKOUT RTC-RST# RTC-RST# ARC+ ARCARCEN NMI-START NMI-EDGE NMI-TIMER FLSH0-BSY# FLSH1-BSY# PB-RST RST-CLR# PB-RST ENET-1 ENET-2 ENET-3 ENET-4 FLSH0-BSY# LED-RSV2# RST-CLR# TX3 RX3 RX1-232 RX1-485 RX1-MODEM RX1 TX1-UART TX1 DCD1-232 DCD1-MODEM DCD1-UART TX1 RX1 ANET-CS# WR# RD# TX2 RX2 TX3 RX3 BLE# TX4 RX4 RX1-232 RX1-485 RX1-MODEM RX1 RX4-232 RX4-485 RX4 TX1-UART TX1 RX3-232 RX3-485 RX3 DCD1-232 DCD1-MODEM DCD1-UART RX2-232 RX2-485 RX2 ENET-LEDA# ENET-LEDB# CLKOUT ENET-INT RESET ENET-CS# W/R# WR# RD# ADS# BHE# BLE# ANET-CS# WR# RD# W/R# WR# RD# ADS# BHE# BLE# BLE# A[1..15] A[1..2] D[8..15] IOD[0..7] IOPORT PORT1-CS# PORT2-CS# PORT3-CS# PORT4-CS# MODEM1-CS# ENET-LEDA# ENET-LEDB# IOD[0..15] IOD[0..7] IOPORT-CS# DOC-CS# TCK TDO TDO_0 TMS RTC-RST# ENET-CS# TX4 RX4 IOD[0..15] ANET-INT RESET TX2 RX2 ENET-LEDA# ENET-LEDB# NMI-OUT TMROUT0 TCK TDO TDO_0 TMS ANET-INT ENET-INT LED-RSV2# ENET-LEDA# ENET-LEDB# ANET-CS# ENET-CS# IOPORT-CS# RST-CLR# ENET-5 ENET-6 ENET-7 ENET-8 CLKOUT TX1 RX1 NMI-OUT TMROUT0 ENET-5 ENET-6 ENET-7 ENET-8 TXEN-LED# LED-HBEAT# LED-RSV1# LED-LANETCFG# LED-SANETCFG# LED-GDMSG4# LED-GDMSG3# LED-GDMSG2# LED-GDMSG1# RST-CLR# ENET-1 ENET-2 ENET-3 ENET-4 FLSH1-BSY# RTC-RST# LED-HBEAT# LED-RSV1# LED-LANETCFG# LED-SANETCFG# LED-GDMSG4# LED-GDMSG3# LED-GDMSG2# LED-GDMSG1# LED-RSV2# PORT1-INT PORT2-INT PORT3-INT PORT4-INT ENET-INT ANET-INT RST-CLR# RCS0# RCS1# RCS2# RCS3# RCS4# LED-HBEAT# LED-RSV1# LED-LANETCFG# LED-SANETCFG# LED-GDMSG4# LED-GDMSG3# LED-GDMSG2# LED-GDMSG1# RESET UART-CLK ARC+ ARCARCEN FLSH-CS0# FLSH-CS1# CS0Q# WD-RST ENET WD-RST TXEN-LED# CLKOUT CLKOUT RESET RMODE-REG# RSTATION-REG# RGROUP-REG# RSTATUS-REG# WD-RST M/IO# BLE# BHE# ADS# RD# WR# PAGE 9 ARCNET W/R# W/R# WD-RST RMODE-REG# RSTATION-REG# RGROUP-REG# RSTATUS-REG# A[1..24] M/IO# BLE# BHE# ADS# RD# WR# M/IO# BLE# BHE# ADS# RD# WR# PAGE 8 IOPORT D[0..15] A[1..24] A[1..24] CPU PAGE 5 DECODE ARCNET PORT1-CS# PORT2-CS# PORT3-CS# PORT4-CS# MODEM1-CS# ENET IOD[0..15] RX4-232 RX4-485 RX4 RX3-232 RX3-485 RX3 RX2-232 RX2-485 RX2 DECODE A[1..24] D[0..15] PAGE 10 PAGE 4 MODEM PAGE 6 MEMORY PAGE 7 PORT12 D[0..15] A[1..20] BLE# BHE# RD# WR# D[0..15] PORT34 IOD[0..7] A[1..20] BLE# RD# WR# PORT1-CS# PORT2-CS# BLE# BHE# RD# WR# RESET UCS# FLSH-CS0# FLSH-CS1# IOD[0..7] MODEM1-CS# RESET RTC-RST# RCS0# RCS1# RCS2# RCS3# RCS4# MODEM1-CS# RESET RTC-RST# RTC-RST# TX1 RX1-MODEM DCD1-MODEM RTS1# MODEM-2WA MODEM-2WB MODEM-4WA MODEM-4WB MODEM FLSH0-BSY# TX1 FLSH1-BSY# RX1-MODEM DCD1-MODEM UCS# FLSH-CS0# FLSH-CS1# TX1 RX1 RX1-232 RX1-485 DCD1-232 DCD1-UART RTS1# RCS0# RCS1# RCS2# RCS3# RCS4# TX2 RX2 RX2-232 RX2-485 RTC-RST# PORT1-INT PORT2-INT FLSH0-BSY# FLSH1-BSY# ENET-1 ENET-2 ENET-3 ENET-4 RTS1# ENET-5 ENET-6 ENET-7 ENET-8 MODEM-2WA MODEM-2WB MODEM-2WA MODEM-2WB MODEM-4WA MODEM-4WB MODEM-4WA MODEM-4WB MEMORY IOD[0..7] A[1..2] TX1-UART ENET-1 ENET-2 ENET-3 ENET-4 ENET-5 ENET-6 ENET-7 ENET-8 MODEM-2WA MODEM-2WB MODEM-4WA MODEM-4WB UART-CLK A[1..2] BLE# RD# WR# PORT1-CS# PORT2-CS# BLE# RD# WR# PORT3-CS# PORT4-CS# PORT3-CS# PORT4-CS# RESET RESET TX1 RX1 RX1-232 RX1-485 DCD1-232 DCD1-UART RTS1# TX3 RX3 RX3-232 RX3-485 TX2 RX2 RX2-232 RX2-485 TX4 RX4 RX4-232 RX4-485 PORT1-INT PORT2-INT RESET TX3 RX3 RX3-232 RX3-485 TX4 RX4 RX4-232 RX4-485 PORT3-INT PORT4-INT PORT3-INT PORT4-INT TX1-UART UART-CLK UART-CLK RS485-3A RS485-3B PTT3 RTS3 TXD3 RXD3 DCD3 RS485-3A RS485-3B PTT3 RTS3 TXD3 RXD3 DCD3 RS485-4A RS485-4B PTT4 RTS4 TXD4 RXD4 DCD4 RS485-4A RS485-4B PTT4 RTS4 TXD4 RXD4 DCD4 PORT12 PORT34 DAQ ELECTRONICS, INC. PISCATAWAY CORPORATION CENTER 262B OLD NEW BRUNSWICK ROAD PISCATAWAY, NJ 08854-3756 144 Size C Document Number Date: Friday, April 29, 2005 Rev D A24249 Sheet 1 of 10 ALTERA ISP PROGRAMMING INTERFACE BIT BLASTER CONNECTOR JTAG CONNECTOR 3.3V J1 JP13 3 3 TCK 3 TDO TMS TCK TDO TMS 1 3 5 7 9 TDI HEADER 5X2 3 TMS TDI TDO TCK TMSRST 1 2 3 4 5 6 7 8 9 10 2 4 6 8 10 TDO_0 3.3V 3.3V PIN 8 KEYED +5V HEADER 10 3.3V 1 HEADER5X2 R16 1.00K D[0..15] 3.3V 3.3V HEADER10X1 L3 2 600 OHM PORT2-INT PORT3-INT RESET_UP 44 NA# 98 NMI 79 130 SMI# SMIACT# 119 RESET GND OUT 3 138 WDTOUT 125 CLK2 3 11 18 24 33 36 39 47 TEMPERATURE COMPENSATED SG-615 HIGH PRECISION TIMER 28 R767 16 15 14 13 12 11 10 9 A9 A10 A11 A12 A13 A14 A15 A16 VCC CEIN BC NVRAM RTC WDI 5 X1 2 X2 3 VOUT 1 +5V D1 MMBD1501A HEADER2X1 Y3 32.768KHZ C35 27PF VSS 1 2 3 4 5 6 7 8 VBATT VSS RP7 26 24 INT WDI 2 1 JUMPER WDO# R8 SOT-23 332 C32 27PF VBATT SX1555 20 118 95 88 77 65 51 41 30 131 VCC VCC VCC VCC VCC VCC VCC VCC VCC 16 TRST# 124 VSS VSS VSS VSS VSS VSS VSS VSS S8002JA-PCM-50.00 129 CS0# 4 C0805 3.3VQ R0805 C0805 JP1 JUMPER 3.3VQ WOIC/28 3.3VQ 47 R67 4.75K RP6 1 2 3 4 5 6 7 8 R767 16 15 14 13 12 11 10 9 A17 A18 A19 A20 A21 A22 A23 A24 RTC-INT 2 U44A HEADER2X1 BT1 BATTERY 1 R0805 74LVX04 CS0# ANET-CS# ENET-CS# IOPORT-CS# RTC-CS# DOC-CS# M/IO# BLE# BHE# ADS# UCS# W/R# RD# WR# BS8# READY# D/C# LBA# 29 40 42 43 1 32 37 38 35 34 31 4 M/IO# BLE# BHE# ADS# UCS# W/R# RD# WR# CLKOUT 112 CLKOUT CS0# ANET-CS# ENET-CS# IOPORT-CS# V150H/3 INSTALL JP15 TO ENABLE BATTERY BACKUP OF SRAM 3 8 9 3 SOIC/14 3 DOC-CS# D[0..15] R767 3 3,4,5,6,7,8,9 3,4,9 3,9 3,4 9 3,4,6,7,8,9 3,4,6,7,8,9 3,4,5,6,7,8,9 A[1..24] 3.3V U35 5 WD-RST WD-RST 3.3VQ CLKOUT 3,4,9 D[0..15] A[1..24] M/IO# BLE# BHE# ADS# UCS# W/R# RD# WR# 3,9 4 5 2 D 3 VCC CP 1 GND CLR 6 Q U44B 4 3 74LVX04 RST-CLR# 5 NC7SZ175 VSS VSS VSS VSS VSS VSS VSS VSS 4 47 133 134 135 136 137 139 2 FA80386EXTB25 105 108 109 120 126 132 141 144 VCC VSS VSS VSS VSS VSS VSS VSS VSS 2 OE 50 60 69 72 75 83 90 97 TMSRST Y6 1 D0 D1 D2 D3 D4 D5 D6 D7 23 3 CS0Q# 47 P2.0/CS0# P2.1/CS1# P2.2/CS2# P2.3/CS3# P2.3/CS4# DACK0#/CS5# REFRESH#/CS6# 3.3V 11 12 13 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7 WDI WDO 3,4,5,8,10 RTC-RST# JP2 3 NMI-OUT NMI-OUT DACK1#/TXD1 DRQ1/RXD1 DRQ0/DCD1# EOP#/CTS1# DSR1#/STXCLK RTS1#/SSIOTX FLT# RI1/SSIORX DTR1#/SRXCLK CS OE WE CS0Q# 2 3 122 128 127 123 106 86 107 85 84 INT4/TMRCLK0 INT5/TMRGATE0 INT6/TMRCLK1 INT7/TMRGATE1 ERROR#/TMROUT0 BUSY#/TMRGATE2 PEREQ/TMRCLK2 21 22 27 RTC-RST# 25 1 RX6 101 102 103 104 99 100 96 P3.0/TMROUT0/IN P3.1/TMROUT1/IN P3.2/INT0 P3.3/INT1 P3.4/INT2 P3.5/INT3 P3.6/PWRDOWN P3.7/COMCLK RTC-CS# RD# WR# A1 A2 A3 A4 A5 A6 A7 A8 6 CEOUT RST C0805 1 PREC_CLK PORT2-INT PORT3-INT RTC-INT 45 46 48 49 52 53 54 55 56 57 58 59 61 62 63 64 66 67 68 70 71 73 74 76 78 16 15 14 13 12 11 10 9 A0 A1 A2 A3 14 UART-CLK UART-CLK A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16/CAS0 A17/CAS1 A18/CAS2 A19 A20 A21 A22 A23 A24 A25 1 2 3 4 5 6 7 8 10 9 8 7 7 6,7 6 7 P2.5/RXD0 P2.6/TXD0 P2.7/CTS0# RP8 BLE# L0805 A1 A2 A3 14 8 6 7 9 80 81 87 89 91 92 93 94 TMROUT1 ANET-INT PORT1-INT PORT4-INT ENET-INT TMROUT1 ANET-INT PORT1-INT PORT4-INT ENET-INT 140 142 143 P1.0/DCDO# P1.1/RTS0# P1.2/DTR0# P1.3/DSRO# P1.4/RIO# P1.5/LOCK# P1.6/HOLD P1.7/HLDA NOTE: PULL JP2 WHEN WHEN RUNNING IN DEBUG MODE 3 RX5 TX5 VCC 9 WDI VCC 110 111 113 114 115 116 117 121 VCC DCD5# RTS5# TMS TDI TDO TCK D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 1 28 27 26 82 5 6 7 8 10 12 13 14 15 17 19 20 21 22 23 25 1 TMSRST TMS TDI TDO_0 TCK U12 BQ4802LY U34 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D2 LED R0805 C40 0.1UF 2 3 4 5 6 7 8 9 10 SIP/10 2 R72 4.75K R12 1.00K R0805 3.3V 3.3V SOIC/14 Microprocessor - 80C386EX 5 3.3V PB-RST PB-RST 4 U43 SC70/6 Q 5 VCC D 3 CP 1 CLR 6 S1 TQFP/144 3.3V VCC GND OUT 2 3 12.288MHZ D KST221J 1 CLK 6 7 R PR 2 VCC OE U31 4 Q 5 Q 3 GND PREC_CLK NC7SZ175 R66 4.75K R63 1.00K SC70/6 RTC-RST# U44C 4 CK8125 TEST PANEL SERIAL INTERFACE GND 2 3.3VQ 8 Y5 1 NC7SZ74 R0805 6,7,9,10 CRYDIP14 C110 .1UF U44E C106 .1UF C0805 10 2 C1+ 4 C1- 5 C2+ 11 6 74LVX04 TX5 RTS5# C0805 RX5 DCD5# U44F 12 13 SOIC/14 74LVX04 6 5 T1IN T2IN 10 13 R1OUT R2OUT EN# 1 R62 4.75K SOIC/14 74LVX04 C111 V+ 3 V- 7 R0805 3 1 Q6 MMBT2222LT1 U44D .1UF C105 2 RESET_UP TEST PANEL 8 9 SOIC/14 .1UF C2- 11 12 AM3222 145 RESET RS232 Transceiver U45 UNUSED GATES RESET T1OUT T2OUT 8 15 TXD5 C0805 RTS5 R1IN R2IN 9 14 RXD5 DCD5 C0805 VCC 17 SD# GND 18 16 3.3V JP11 74LVX04 1 2 3 4 5 SOIC/14 HEADER 5 R51 1.00K SOT-23 R0805 DAQ ELECTRONICS, INC. PISCATAWAY CORPORATION CENTER 262B OLD NEW BRUNSWICK ROAD PISCATAWAY, NJ 08854-3756 HEADER5X1 Size C Document Number Date: Friday, April 29, 2005 Rev D A24249 R0805 WOIC/18 Sheet 2 of 10 3.3VQ 2,3,9 2,4,5,10 CLKOUT RTC-RST# U25 16 TMROUT1 RSEL0 RSEL1 RSEL2 A7 A6 2 CS0Q# 1 2 3 A B C 6 4 5 G1 G2A G2B VCC A23 A22 A21 A20 A[20..23] GND 2 2,4,5,6,7,8,9 15 14 13 12 11 10 9 7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 MEMORY OPTION JUMPER SELECTIONS 4 RCS0#4 RCS1#4 RCS2#4 RCS3#4 RCS4# RCS0# RCS1# RCS2# RCS3# RCS4# 74LVX138 8 RMODE-REG# RSTATION-REG# RGROUP-REG# IOD3 IOD2 2 TDO_0 2 TMS 2 TCK 2 6 TDO TX1-UART IOD1 IOD0 TDO_0 TMS TCK TDO TX1-UART I/O I/O I/O I/O(TMS) I/O I/O 100 81 4 15 62 73 78 I/O I/O I/O(TDI) I/O(TMS) I/O(TCK) I/O(TDO) I/O EPLD 5,6,10 TX1 7 13 10 42 41 45 I/O I/O I/O I/O I/O I/O I/O I/O I/O 6 8 9 90 89 88 87 SOIC/16 5 RMODE-REG# 5 RSTATION-REG# 5 RGROUP-REG# I/O 40 RSTATUS-REG# I/O I/O I/O I/O I/O I/O I/O 35 36 27 19 37 16 17 PORT1-CS# PORT2-CS# PORT3-CS# PORT4-CS# MODEM1-CS# LED-HBEAT# LED-RSV1# I/O I/O I/O I/O I/O I/O 20 21 22 23 24 25 LED-LANETCFG# LED-SANETCFG# LED-GDMSG4# LED-GDMSG3# LED-GDMSG2# LED-GDMSG1# I/O I/O I/O I/O I/O I/O I/O 30 29 28 31 32 94 1 RSTATUS-REG# PORT1-CS# PORT2-CS# PORT3-CS# PORT4-CS# MODEM1-CS# LED-HBEAT# LED-RSV1# LED-LANETCFG# LED-SANETCFG# LED-GDMSG4# LED-GDMSG3# LED-GDMSG2# LED-GDMSG1# DB-CTRL-CS1 DB-CTRL-CS2 LED-RSV2# RST-CLR# DB-STATUS-CS1 NMI-OUT 5 6 6 7 7 10 5 5 DB-CTRL-CS1 DB-CTRL-CS25 LED-RSV2#5 RST-CLR# DB-STATUS-CS1 5 NMI-OUT5 5 5 5 5 5 5 5 DISC ON CHIP SURFACE MOUNT TO DIP SOCKET 3.3V 2 2 2,4,5,6,7,8,9 A[8..12] A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 BLE# DAQ-EPM7128AETC100-10 TX1 TQFP/100 7 7 RX4-232 RX4-485 5,7 RX4 7 7 RX3-232 RX3-485 5,7 RX3 6 6 RX2-232 RX2-485 5,6 RX2 6 6 RX1-232 10 RX1-485 RX1-MODEM 5,6 RX1 6 10 DCD1-232 6 DCD1-MODEM DCD1-UART DOC-CS# COD-CS# 4 25 23 26 27 5 6 7 8 9 10 11 12 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 22 CE RD# 24 OE WR# 31 WE 16 2 U40 32 IOPORT-CS# 61 58 80 84 12 14 4 4 I/O I/O I/O I/O I/O I/O I/O CS0# F-1MBYTE R-1MBYTE I/O I/O I/O I/O I/O I/O I/O FLSH-CS0# FLSH-CS1# U33 97 69 65 98 52 99 96 R0805 I/O I/O 55 56 79 50 92 85 60 33 77 54 46 63 68 47 5 D7 D6 D5 D4 D3 D2 D1 D0 21 20 19 18 17 15 14 13 NC NC NC NC NC NC 1 2 3 28 29 30 5 5 D7 D6 D5 D4 D3 D2 D1 D0 2 DOC2000 WOIC/32 3.3V RD# 2,4,9 D[0..15] 2 M/IO# D[0..15] 31 42 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1 24 A1>B1 A2>B2 OE1 OE2 48 25 16bit Bidirectional Buffer 5,6,7,8,9,10 IOD[0..15] RP5 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 M/IO# IOD[0..15] 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 IOD15 IOD14 IOD13 IOD12 IOD11 IOD10 IOD9 IOD8 9 10 11 12 13 14 15 16 IOD7 IOD6 IOD5 IOD4 IOD3 IOD2 IOD1 IOD0 47 RP4 8 7 6 5 4 3 2 1 R767 47 GND GND GND GND GND GND GND GND D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCC VCC VCC VCC 7 18 U19 74VCX16245 4 10 15 21 28 34 39 45 2 BLE# RD# 2WR# UCS# 2 CS0# 48 57 I/O I/O I/O 2,4,6,7,8,9 2,4,6,7,8,9 2,4,6,7,8,9 R0805 HEADER2X2 93 83 70 A5 A4 A3 A2 A1 BLE# RD# WR# UCS# I/GCLK2 I/GCLR# I/OE1 I/GCLK1 4.75K I/O I/O I/O 4.75K R65 49 75 2 HEADER 2X2 I/O I/O I/O 2 4 67 64 44 1 3 3.3V R64 71 5 53 76 72 JP12 VCC (3--4) 3 to 8 Decoder FLSH-CS0# FLSH-CS1# I/O I/O I/O I/O I/O SRAM SIZE A[1..7] 2MBYTE 1MBYTE 2MBYTE 1MBYTE I/O I/O I/O I/O I/O I/O I/O 2,4,5,6,7,8,9 - GND IN OUT IN OUT FLASH SIZE (1--2) R767 DAQ ELECTRONICS, INC. tssop/48 146 262B OLD NEW BRUNSWICK ROAD PISCATAWAY, NJ 08854-3756 TEL. (732) 981-0050 FAX. (732) 981-0058 Size C Document Number Date: Friday, April 29, 2005 Rev D A24249 Sheet 3 of 10 2,9 D[0..15] D[0..15] 2,3,5,6,7,8,9 A[1..20] A[1..20] U32 3 FLSH-CS0# A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 RD# WR# 26 28 11 47 CE OE WE BYTE 12 15 RESET RY/BY# FLSH-CS0# 3.3V RTC-RST# 5 FLSH0-BSY# A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19/NC D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15/A-1 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 NC NC NC 10 13 14 VCC 37 VSS VSS 27 46 FD0 FD1 FD2 FD3 FD4 FD5 FD6 FD7 FD8 FD9 FD10 FD11 FD12 FD13 FD14 FD15 U18 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 3 3.3V RCS2# 3.3VQ RD# WR# BHE# BLE# 3.3VQ 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 26 12 28 11 14 15 47 AM29DL800 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19/NC CE1 CE2 OE R/W# UB LB BYTE U11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 NC NC 10 13 VDD 37 GND GND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 3.3VQ 3 RCS3# 3.3VQ 46 27 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19/NC RD# WR# BHE# BLE# 26 12 28 11 14 15 47 CE1 CE2 OE R/W# UB LB BYTE 3.3VQ TC55W800FT-55 TSOP/48 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 NC NC 10 13 VDD 37 GND GND 46 27 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 3.3VQ TC55W800FT-55 SRAM 2 Flash D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 SRAM 3 TSOP/48 TSOP/48 3.3V FD0 FD1 FD2 FD3 FD4 FD5 FD6 FD7 FD8 FD9 FD10 FD11 FD12 FD13 FD14 FD15 31 42 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1 24 A1>B1 A2>B2 OE1 OE2 48 25 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 3 RCS1# 3.3VQ 16 bit Bidirectional Buffer 4 10 15 21 28 34 39 45 GND GND GND GND GND GND GND GND WR# VCC VCC VCC VCC 7 18 U17 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 U42 RD# WR# BHE# BLE# 3.3VQ 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 26 12 28 11 14 15 47 74VCX16245 CE1 CE2 OE R/W# UB LB BYTE U10 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 NC NC 10 13 VDD 37 GND GND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 3.3VQ 46 27 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 3 RCS4# 3.3VQ RD# WR# BHE# BLE# 3.3VQ TC55W800FT-55 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 26 12 28 11 14 15 47 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19/NC CE1 CE2 OE R/W# UB LB BYTE NC NC 10 13 VDD 37 GND GND 46 27 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 3.3VQ TC55W800FT-55 SRAM 1 TSSOP/48 2,3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19/NC SRAM 4 TSOP/48 TSOP/48 UCS# U23 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 U24 3 2,3,6,7,8,9 2,3,6,7,8,9 FLSH-CS1# RD# WR# 2,3,5,8,10 5 RTC-RST# FLSH1-BSY# A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19/NC RD# WR# 26 28 11 47 CE OE WE BYTE FLSH-CS1# 3.3V RTC-RST# 12 15 RESET RY/BY# D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15/A-1 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 FD0 FD1 FD2 FD3 FD4 FD5 FD6 FD7 FD8 FD9 FD10 FD11 FD12 FD13 FD14 FD15 3 NC NC NC 10 13 14 VCC 37 2,9 2,3,6,7,8,9 3.3V RCS0# BHE# BLE# 3.3VQ RD# WR# BHE# BLE# 3.3VQ 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 26 12 28 11 14 15 47 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19/NC CE1 CE2 OE R/W# UB LB BYTE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 NC NC 10 13 VDD 37 GND GND 46 27 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 3.3VQ TC55W800FT-55 VSS VSS 27 46 SRAM 0 AM29DL800 TSOP/48 Flash TSOP/48 DAQ ELECTRONICS, INC. 262B OLD NEW BRUNSWICK ROAD PISCATAWAY, NJ 08854-3756 TEL. (732) 981-0050 FAX. (732) 981-0058 147 Size C Document Number Date: Friday, April 29, 2005 Rev D A24249 Sheet 4 of 10 3,5,6,7,8,9,10 IOD[0..7] IOD[0..7] U6 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 A1 A2 A3 A4 A5 A6 A7 A8 G1 G2 1 19 16 15 14 13 12 11 10 9 NODE1 NODE2 NODE4 NODE8 NODE16 NODE32 NODE64 NODE128 2 3 4 5 6 7 8 9 10 1 3.3V 18 17 16 15 14 13 12 11 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 2K A1 A2 A3 A4 A5 A6 A7 A8 2 3 4 5 6 7 8 9 G1 G2 1 19 2 WD-RST 2 PB-RST 4 FLSH0-BSY# 4 FLSH1-BSY# WD-RST PB-RST FLSH0-BSY# FLSH1-BSY# NODE2 NODE8 NODE32 NODE128 GRP2 GRP8 GRP32 GRP128 STATUS0 STATUS2 74LVX541 10K Buffer 74LVX541 RMODE-REG# 3 IOD0 IOD1 IOD2 IOD3 IOD4 IOD5 IOD6 IOD7 R1 1 2 3 4 5 6 7 8 STAT2 STAT8 STAT32 STAT128 CTRL0 CTRL2 CTRL4 CTRL6 CTRL8 CTRL10 ARCARC+ ARCEN R767 SOIC/20 SIP/10 RSTATUS-REG# SOIC/20 U4 IOD0 IOD1 IOD2 IOD3 IOD4 IOD5 IOD6 IOD7 18 17 16 15 14 13 12 11 Buffer 3 RP2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 A1 A2 A3 A4 A5 A6 A7 A8 2 3 4 5 6 7 8 9 G1 G2 1 19 16 15 14 13 12 11 10 9 R2 1 2 3 4 5 6 7 8 GRP1 GRP2 GRP4 GRP8 GRP16 GRP32 GRP64 GRP128 2 3 4 5 6 7 8 9 10 1 P3 +5V 3.3V DB-CTRL-CS1 DB-CTRL-CS2 IOD0 IOD1 IOD2 IOD3 1 3 5 7 9 11 13 2 4 6 8 10 12 14 DB-STATUS-CS1 RTC-RST# IOD7 IOD6 IOD5 IOD4 2K 10K 14 POS Connector 74LVX541 RGROUP-REG# +12V R767 -12V DINRT-32X3 P1 1 A1 3 A2 5 A3 7 A4 9 A5 11 A6 13 A7 15 A8 17 A9 19 A10 21 A11 23 A12 25 A13 27 A14 29 A15 31 A16 33 A17 35 A18 37 A19 39 A20 41 A21 43 A22 45 A23 47 A24 49 A25 51 A26 53 A27 55 A28 57 A29 59 A30 61 A31 63 A32 +5V SIP/10 Buffer 3 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 A1 A2 A3 A4 A5 A6 A7 A8 2 3 4 5 6 7 8 9 G1 G2 1 19 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 STAT1 STAT2 STAT4 STAT8 STAT16 STAT32 STAT64 STAT128 2 3 4 5 6 7 8 9 10 1 3.3V +5V CTRL0 CTRL1 CTRL2 CTRL3 2K 10K 3.3V R767 SIP/10 1 3 5 7 9 11 13 15 17 CTRL7 CTRL6 CTRL5 CTRL4 +5V 2 18 POS Connector VIN 3 2 3 4 5 6 7 8 9 10 C3 47UF 16V SIP/10 3.3V LED1 3 3 3 3 3 3 3 8 LED-HBEAT# LED-RSV1# LED-LANETCFG# LED-SANETCFG# LED-GDMSG4# LED-GDMSG3# LED-GDMSG2# LED-GDMSG1# LED-RSV2# 11 10 LED-RSV1# 12 9 LED-LANETCFG# 13 8 C53 C52 LED-SANETCFG# 14 7 .01UF .1UF LED-GDMSG4# 15 6 C82 C76 LED-GDMSG3# 16 5 .01UF .1UF LED-GDMSG2# 17 4 18 3 LED-RSV2# 19 2 TXEN-LED# 20 3,7 3,7 3,7 TX3 RX3 TX4 RX4 9 9 ENET-LEDB# 10 RX1 12 9 TX2 13 8 RX2 14 7 TX3 15 6 RX3 16 5 TX4 17 4 18 3 ENET-LEDA# 19 2 ENET-LEDB# 20 1 DIP/20 148 +12V +12V -12V -12V C8 C10 C11 .1UF .01UF .1UF C5 C12 C7 .01UF .1UF C0805 C79 .01UF .1UF .01UF .1UF C78 .01UF C0805 C75 .1UF C0805 C74 C0805 C0805 C0805 C0805 .01UF C0805 C49 .1UF C0805 C80 C0805 C0805 C0805 C0805 .01UF C0805 C81 .1UF C0805 C77 .01UF C0805 C47 .1UF C0805 C48 .01UF C0805 C50 .1UF C0805 C51 .01UF C0805 C30 .1UF C0805 C42 .01UF C0805 C54 .1UF C0805 C55 .01UF C0805 C90 .1UF C0805 C91 C72 C73 .01UF .1UF .01UF C0805 C87 .1UF C0805 C86 C45 C46 .01UF .1UF .1UF C0805 C89 C43 R73 .01UF C0805 C88 .1UF C0805 475 .01UF C0805 C104 R0805 11 LED10 C0805 C9 475 TX1 RX4 ENET-LEDA# C1X1P .01UF 1 3,7 TX2 RX2 C0805 C6 2 3 4 5 6 7 8 9 10 3,6 C2 1UF .1UF C0805 C93 SIP/10 RX1 C4 100UF 16V .01UF C0805 C97 3.3V LED2 3,6 5V - 3.3V Switching Regulator Module .1UF C0805 C96 1 DIP/20 3,6 4 C0805 C92 R76 475 TX1 VOUT C41 LED10 3,6,10 VCC PT5500/5 C1X1P R74 TXEN-LED# C1 1UF 3.3V U1 PT5500 3.3V LED-HBEAT# LED-GDMSG1# +12V 3.3V R0805 .01UF C0805 C109 C0805 C108 .01UF C0805 C100 .1UF C0805 C101 3.3VQ 3.3VQ TP1 TEST POINT 1 3 -12V CTRL11 CTRL10 CTRL9 CTRL8 2 4 6 8 10 12 14 16 18 R75 475 SOIC/20 3 8 ARC8 ARC+ 8 ARCEN DINRTF/64 P4 STATUS0 STATUS1 STATUS2 STATUS3 74LVX541 RSTATION-REG# Backplane Connector 1 18 17 16 15 14 13 12 11 STAT1 STAT4 STAT16 STAT64 CTRL1 CTRL3 CTRL5 CTRL7 CTRL9 CTRL11 ARCARC+ ARCEN R3 1 IOD0 IOD1 IOD2 IOD3 IOD4 IOD5 IOD6 IOD7 RP3 NODE1 NODE4 NODE16 NODE64 GRP1 GRP4 GRP16 GRP64 STATUS1 STATUS3 INH U5 SOIC/20 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 5 Buffer 3 RP1 2 3 4 5 6 7 8 9 ADJ 18 17 16 15 14 13 12 11 GND U3 IOD0 IOD1 IOD2 IOD3 IOD4 IOD5 IOD6 IOD7 C44 .01UF C0805 C38 .1UF C0805 C39 .01UF C0805 C36 .1UF C0805 C37 .01UF C0805 .1UF C0805 C0805 C0805 C0805 C0805 .01UF C0805 C84 .1UF .01UF C0805 .1UF C0805 C0805 C0805 DAQ ELECTRONICS, INC. C0805 C0805 262B OLD NEW BRUNSWICK ROAD PISCATAWAY, NJ 08854-3756 TEL. (732) 981-0050 FAX. (732) 981-0058 C83 Size C Document Number Date: Thursday, May 05, 2005 Rev D A24249 Sheet 5 of 10 TZ10 P4SMA15CA 2 2 2 2 TZ9 P4SMA15CA TZ11 P4SMA15CA TZ1 P4SMA7.5CA 2,7,9,10 2,3,4,7,8,9 2,3,4,7,8,9 2 2 RESET RD# 3WR# PORT1-CS# 3 PORT2-CS# 36 19 15 10 11 RST IOR# IOW# CSA# CSB# 30 29 INTA INTB 43 31 TXRDYA# RXRDYA# RD# WR# PORT1-CS# PORT2-CS# PORT1-INT PORT2-INT R31 4.75K R29 4.75K 6 18 R26 3.3V R0805 R0805 2K 8 4 21 16 35 20 22 23 OPA# OPB# 32 9 NC NC NC NC 12 24 25 37 TXRDYB# RXRDYB# 14 XTAL2 13 XTAL1 3.3V TXB RXB RIB# CDB# DTRB# DSRB# RTSB# CTSB# DCD1-UART DCD1-UART 3 RTS1# 3,5,10 TX2 RX2 RX2 C56 .1UF C0805 10 3 3,5 3 3,5 TX1 RTS1# TX1 C0805 RX1-232 DCD1-232 RX1-232 DCD1-232 C2+ 6 C2- 11 12 T1IN T2IN 10 13 1 V- 7 .1UF C57 8 15 TXD1 RTS1 R1OUT R2OUT R1IN R2IN 9 14 RXD1 DCD1 EN# VCC 17 SD# GND 18 16 3.3V VCC 17 +12V 3 Q5 MMBT2222LT1 4.75k JP5 2 HEADER 3 U36 3.3V GND RJ45/8 DO-214AC 3.3V WOIC/18 U21C 42 P4SMA15CA C0805 1 RX1-485 1 P4SMA7.5CA DO-214AC R46 4.75k R0805 3 TZ12 C0805 ADM3222 RS232 Transceiver R100 RJ45 TZ2 .1UF T1OUT T2OUT RX1-485 5 PTD1 6 74LVX04 1 2 RO RE 3 4 DE DI ST16C2550CQ48 A B VCC RS485-1A 6 SOT-23 RS485-1B 7 8 R0805 3.3V GND 5 HEADER3X1 ADM3485E TZ13 P4SMA15CA RS485 Transceiver UART R27 3 1 5 C65 V+ 2 D0 D1 D2 D3 D4 D5 D6 D7 TX1-UART RX1 C1- R0805 TZ14 P4SMA15CA 2 IOD[0..7] 44 45 46 47 48 1 2 3 7 5 41 40 34 39 33 38 C1+ 4 2 3,5,7,8,9,10 IOD0 IOD1 IOD2 IOD3 IOD4 IOD5 IOD6 IOD7 TXA RXA RIA# CDA# DTRA# DSRA# RTSA# CTSA# 2 PORT 1 1 2 3 A[1..2] A0 A1 A2 3 3,5 2 2,3,4,5,7,8,9 28 27 26 TX1-UART RX1 1 2 3 4 5 6 7 8 RS485-1A RTS1 PTT1 2 BLE# BLE# A1 A2 DCD1 DO-214AC RXD1 TXD1 RS485-1B DO-214AC 1 U26 U20 2,3,4,7,8,9 DO-214AC 2 C64 .1UF 1 1 1 J2 DO-214AC TZ15 P4SMA15CA TZ3 P4SMA7.5CA SOIC/14 4.75K J3 DO-214AC DO-214AC DCD2 DO-214AC RXD2 TXD2 RS485-2B 1 1 1 1 SOIC/8 TQFP/48 DO-214AC Y4 OUT 3 GND UART-CLK C66 .1UF 2,7 U27 2 C1+ 4 C1- 14.7456MHZ Oscillator C58 .1UF C0805 5 C2+ 6 C2- 11 12 T1IN T2IN 10 13 SG-615 TX2 RTS2# 3 C0805 RX2-232 DCD2# RX2-232 +12V 1 RS485-2A RTS2 PTT2 C67 V+ 3 V- 7 .1UF C59 8 15 TXD2 RTS2 R1OUT R2OUT R1IN R2IN 9 14 RXD2 DCD2 EN# VCC 17 SD# GND 18 16 PORT 2 RJ45 TZ4 .1UF T1OUT T2OUT 1 2 3 4 5 6 7 8 1 4 TZ16 P4SMA7.5CA P4SMA15CA RJ45/8 C0805 2 VCC R0805 1 2 OE 2 1 DO-214AC DO-214AC C0805 3.3V P2 PTT1 RS485-1A 10 10MODEM-2WB MODEM-4WB RTS2 PTT2 9 9ENET-5 9ENET-6 9ENET-7 ENET-8 7 RTS3 7 PTT3 7 7 RS485-3A 7 RTS4 7 PTT4 RS485-4A RS485-2A ENET-5 ENET-6 ENET-7 ENET-8 RTS3 PTT3 RS485-3A RTS4 PTT4 RS485-4A 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 DINRT-32X3 Backplane Connector C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 3.3V DCD1 RXD1 TXD1 ADM3222 R101 RS485-1B 10 MODEM-2WA 10 MODEM-4WA 3 3 R48 Q2 MMBT2222LT1 1 4.75k RX2-485 WOIC/18 DCD2 RXD2 TXD2 JP6 2 HEADER 3 U21D U37 RX2-485 9 RS485-2B ENET-1 ENET-2 ENET-3 ENET-4 DCD3 RXD3 TXD3 +12V RS232 Transceiver 4.75k R0805 1 2 3 RTS1 9 ENET-19 ENET-29 ENET-39 ENET-4 DCD3 7 RXD3 7 TXD37 8 74LVX04 PTD2 1 2 RO RE 3 4 DE DI A B VCC RS485-2A 6 SOT-23 RS485-2B 7 8 R0805 3.3V GND 5 ADM3485E RS485 Transceiver +5V HEADER3X1 R47 2K SOIC/14 R42 SOIC/8 RS485-3B DCD4 RXD4 TXD4 RS485-3B DCD4 7 RXD4 7 TXD4 7 R52 120 2K R0805 R53 JP9 R0805 RS485-4B RS485-4B R41 120 7 7 R0805 2K R0805 R54 1 3 5 7 2 4 6 8 RS485-1A RS485-1B RS485-2A RS485-2B HEADER 4X2 2K R0805 HEADER4X2 DINRTF/64 R0805 DAQ ELECTRONICS, INC. 262B OLD NEW BRUNSWICK ROAD PISCATAWAY, NJ 08854-3756 TEL. (732) 981-0050 FAX. (732) 981-0058 149 Size C Document Number Date: Friday, April 29, 2005 Rev D A24249 Sheet 6 of 10 TZ18 P4SMA15CA 6 DCD3 6 RXD3 6 TXD3 RS485-3B 2 2 2 2 TZ17 P4SMA15CA TZ19 P4SMA15CA TZ6 P4SMA7.5CA 6 RST IOR# IOW# CSA# CSB# 30 29 INTA INTB 43 31 TXRDYA# RXRDYA# R28 3.3V R0805 R0805 2K NC NC NC NC 12 24 25 37 TXRDYB# RXRDYB# 14 XTAL2 13 XTAL1 RX3-232 3,5 6 C2- 11 12 10 13 1 17 T1OUT T2OUT 8 15 TXD3 RTS3 R1OUT R2OUT R1IN R2IN 9 14 RXD3 DCD3 EN# VCC 17 SD# GND 18 16 UART-CLK 1 RJ45 TZ5 TZ20 P4SMA7.5CA P4SMA15CA RJ45/8 RS485-3A RTS3 6 PTT3 6 6 C0805 DO-214AC DO-214AC C0805 3.3V ADM3222 3 +12V 3 R50 Q3 MMBT2222LT1 1 4.75k RX3-485 JP7 2 WOIC/18 HEADER 3 U38 1 RX3-485 PTD3 2 74LVX04 1 2 RO RE 3 4 DE DI ST16C2550CQ48 6,2 .1UF RS233 Transceiver 4.75k R0805 3.3V VCC 7 .1UF C61 T1IN T2IN U21A GND V- 3.3V R102 42 3 1 C2+ V+ A B VCC RS485-3A 6 SOT-23 RS485-3B 7 8 R0805 3.3V GND 5 HEADER3X1 ADM3485E TZ21 P4SMA15CA RS485 Transceiver UART R0805 TZ22 P4SMA15CA TZ23 P4SMA15CA 6 DCD4 6 RXD4 TXD4 RS485-4B TZ7 P4SMA7.5CA 6 SOIC/14 J5 SOIC/8 1 TQFP/48 DO-214AC C62 .1UF C0805 TX4 RTS4# 3 C0805 RX4-232 DCD4# RX4-232 2 C1+ 4 C1- 5 C2+ 6 C2- 11 12 T1IN T2IN 10 13 1 V+ 3 V- 7 .1UF C63 .1UF T1OUT T2OUT 8 15 TXD4 RTS4 R1OUT R2OUT R1IN R2IN 9 14 RXD4 DCD4 EN# VCC 17 SD# GND 18 16 1 2 3 4 5 6 7 8 RS485-4A RTS4 PTT4 C71 1 U29 DCD4 DO-214AC RXD4 TXD4 RS485-4B DO-214AC PORT 4 RJ45 TZ8 TZ24 P4SMA7.5CA P4SMA15CA RS485-4A RTS4 RJ45/8 PTT4 6 6 C0805 2 C70 .1UF DO-214AC 1 6 18 RX4 C0805 RX3-232 DCD3# C1- 5 1 R32 4.75K 32 9 RX4 3 C1+ 4 6 2 R30 4.75K OPA# OPB# TX3 RTS3# 3,5 TX4 2 1 PORT3-INT PORT4-INT C60 .1UF C0805 2 36 19 15 10 11 8 4 21 16 35 20 22 23 RX3 3,5 1 RESET RD# 3WR# PORT3-CS# 3 PORT4-CS# TXB RXB RIB# CDB# DTRB# DSRB# RTSB# CTSB# RX3 2 RESET RD# WR# PORT3-CS# PORT4-CS# IOD[0..7] 7 5 41 40 34 39 33 38 2 D0 D1 D2 D3 D4 D5 D6 D7 TXA RXA RIA# CDA# DTRA# DSRA# RTSA# CTSA# PORT 3 1 2 3 44 45 46 47 48 1 2 3 A0 A1 A2 2 IOD0 IOD1 IOD2 IOD3 IOD4 IOD5 IOD6 IOD7 A[1..2] 3,4,5,6,8,9,10 2 2 28 27 26 1 2 3 4 5 6 7 8 RS485-3A RTS3 PTT3 C68 2 2,3,4,5,6,8,9 2,6,9,10 2,3,4,6,8,9 2,3,4,6,8,9 BLE# A1 A2 BLE# DCD3 DO-214AC RXD3 TXD3 RS485-3B DO-214AC 1 3,5 TX3 U22 2,3,4,6,8,9 U28 DO-214AC 2 C69 .1UF 1 1 1 J4 DO-214AC DO-214AC DO-214AC C0805 3.3V 3.3V R103 3 ADM3222 +12V RS233 Transceiver Q4 MMBT2222LT1 1 4.75k RX4-485 3 R49 WOIC/18 JP8 1 2 3 4.75k R0805 2 HEADER 3 U21B U39 RX4-485 3 4 74LVX04 PTD4 1 2 RO RE 3 4 DE DI A B VCC RS485-4A 6 SOT-23 RS485-4B 7 8 R0805 3.3V GND 5 ADM3485E RS485 Transceiver +5V HEADER3X1 R43 2K SOIC/14 R44 SOIC/8 R55 120 R45 120 2K R0805 R56 JP10 R0805 R0805 2K R0805 R57 1 3 5 7 RS485-3A RS485-3B RS485-4A RS485-4B 2 4 6 8 HEADER 4X2 2K R0805 HEADER4X2 R0805 DAQ ELECTRONICS, INC. 262B OLD NEW BRUNSWICK ROAD PISCATAWAY, NJ 08854-3756 TEL. (732) 981-0050 FAX. (732) 981-0058 150 Size C Document Number Date: Thursday, May 05, 2005 Rev D A24249 Sheet 7 of 10 3.3V VDD VDD VDD VDD VDD VDD 8 20 32 35 38 43 U14 COM20020I3V-HD 2,3,4,6,7,8,9 2,3,4,5,6,7,8,9 BLE# A[1..2] 3,5,6,7,8,9,10 BLE# A1 A2 44 45 46 A0/NMUX A1 A2/ALE IOD0 IOD1 IOD2 IOD3 IOD4 IOD5 IOD6 IOD7 1 2 4 7 9 10 12 13 AD0 AD1 AD2 D3 D4 D5 D6 D7 47 48 3 5 14 15 16 17 19 NC NC NC NC NC NC NC NC NC 26 BUSTMG 39 37 36 RD WR CS IOD[0..7] 3.3V RD# 2WR# ANET-CS# RD# WR# ANET-CS# 21 XTAL2 22 NC NC NC NC 33 27 40 42 RXIN 28 Y2 20MHZ C33 33PF C34 33PF CSM-7 U15 C0805 TXEN 29 PULSE1 PULSE2 24 25 1 2 C0805 3 4 RO RE DE DI A B VCC 6 7 8 GND 5 ARC+ ARC- 5 5 3.3V ADM3485E RS485 Transceiver SOIC/8 RST 31 INT 34 +5V VSS VSS VSS VSS VSS VSS 2,3,4,6,7,8,9 2,3,4,6,7,8,9 XTAL1 U9 6 11 18 23 30 41 R25 1K Arcnet Controller TQFP/48 3 U21E 11 10 1 R0805 Q1 2N7002 1 RO 2 3 RE DE 4 D V+ 8 B 7 A 6 V- ARCEN 5 5 MAX485 2 74LVX04 SOIC/14 SOT-23 3 2 1 SOIC/8 JUMPER JP17 (1--2) ARCEN ACTIVE LOW (2--3) ARCEN ACTIVE HIGH HEADER3X1 JP4 HEADER 3 U21F 12 13 3.3V 74LVX04 RTC-RST# R23 1K 8 SOIC/14 2,3,4,5,8,10 U16 2 R0805 1 CLK 6 7 R PR 4 RTC-RST# D VCC ANET-INT Q 5 Q 3 TXEN-LED# 5 GND 2 NC7SZ74 DAQ ELECTRONICS, INC. 262B OLD NEW BRUNSWICK ROAD PISCATAWAY, NJ 08854-3756 TEL. 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(732) 981-0058 151 Size C Document Number Date: Friday, April 29, 2005 Rev D A24249 Sheet 8 of 10 B 3.3VA 3.3VA C85 .01UF 3.3VA 6 ENET-16 ENET-26 ENET-36 ENET-4 3.3VA 6 ENET-56 ENET-66 ENET-76 ENET-8 3.3V R35 C0805 24.9 ENET-CS# ADS# W/R# RD# WR# IOD[0..15] IOD0 IOD1 IOD2 IOD3 IOD4 IOD5 IOD6 IOD7 IOD8 IOD9 IOD10 IOD11 IOD12 IOD13 IOD14 IOD15 1 3.3V 2 3 4 5 6 7 8 9 10 R33 10K 2,3,4,6,7,8,9 2,3,4,9 2,6,7,9,10 2 BLE# BHE# RESET ENET-INT SIP/10 BLE# BHE# RESET ENET-INT 41 37 36 31 32 107 106 105 104 102 101 100 99 76 75 74 73 71 70 69 68 66 65 64 63 61 60 59 58 56 55 54 53 51 50 49 48 R37 49.0 R36 49.0 TPO+ 14 TPO- 15 U41 R0805 R0805 R0805 16 1 * 15 * * J6 2 14 1 2 3 4 5 6 7 8 3 * R38 TPI+ 17 TPI- 18 RBIAS 12 11 24.9 R39 10 9 6 * * * * * * 7 * * 8 R34 LEDA LEDB 22 23 LNK LBK CRTL 20 21 28 RXD0 RXD1 RXD2 RXD3 124 123 122 121 TXD0 TXD1 TXD2 TXD3 116 115 114 113 TXEN100 CRS100 COL100 RXDV RXER 111 119 112 125 126 AEN ADS W/R# RD WR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 MDI MDO MCK 25 26 27 RX25 TX25 118 109 EECS EESK EEDO EEDI 10 9 7 8 ENEEP IOS2 IOS1 IOS0 6 5 4 3 CSOUT 2 30 35 40 42 38 43 46 29 45 34 RESET CYCLE VLBUS LCLK ARDY SRDY RDYRTN INTR0 LDEV DATACS X25OUT 47 24 39 52 57 67 72 93 103 108 117 RJ45 AGND ENET-LEDA# ENET-LEDB# ENET-LEDA# ENET-LEDB# 5 5 R61 75.0 TFORM/16 R0805 R60 75.0 R59 49.0 R58 49.0 R69 49.0 R68 49.0 XTAL1 127 RJ45/8 R0805 R0805 R0805 R0805 R0805 R0805 R0805 R70 49.0 R71 49.0 R0805 R0805 C107 1000PF 2KV C112 1000PF 2KV AGND AGND C1210 C1210 3.3V U46 3 DI 1 CS 6 ORG 2 SK VCC 8 DO 4 DC 7 GND 5 C113 .1UF C0805 AT93C46 3.3V XTAL2 128 ETHERNET 10/100 BASE-T CONNECTOR Transformer R0805 3.3V BE0 BE1 BE2 BE3 TG110-S050N2 24.9 11.0K 94 95 96 97 Ethernet Controller R0805 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 3.3VA L4 AVSS AVSS 2,3,4,6,7,8 2,3,4,6,7,8 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 2 ENET-CS# 2,3 2 ADS# W/R# RD# WR# 3,5,6,7,8,9,10 11 16 VDD VDD VDD VDD VDD VDD VDD VDD A[1..15] 13 19 2,3,4,5,6,7,8,9 AVDD AVDD 1 33 44 62 77 98 110 120 R40 24.9 U30 600 OHM C102 10UF LAN91C111 C103 10UF C98 .01UF C99 .01UF C94 .1UF TANTC C0805 C0805 C0805 C95 .1UF L0805 L5 TANTC 600 OHM C0805 TQFP/128 AGND 25 MHZ CPU CLOCK AGND L0805 2,3 CLKOUT DAQ ELECTRONICS, INC. 262B OLD NEW BRUNSWICK ROAD PISCATAWAY, NJ 08854-3756 TEL. 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(732) 981-0058 152 Size C Document Number Date: Friday, April 29, 2005 Rev D A24249 Sheet 9 of 10 3.3V +5F R5 4.75K R4 4.75K R6 4.75K +5F -5F C15 .01UF C17 .01UF R21 22.1K 6.81K +5F R0805 R0805 MODEM1-CS# 2,6,7,9 11 1 RESET Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 C OC VCC GND 20 10 MC0 MC1 MC2 MC3 MC4 AMDTR BTD 28 BRD 15 BCTS 14 BCD 27 CD 16 DRT 17 18 19 20 21 3 MC0 MC1 MC2 MC3 MC4 RESET +5V 74HCT574 SOIC/20 SOCKET U48 Modem C114 .1UF C0805 Register CAP1 6 CAP2 7 XTAL1 24 XTAL2 23 Op Amp R0805 TANTB D6 MMBD914LT1 2 POT3224X R0805 R0805 T1 * + * 3 4 LA-07754 C0805 R0805 R10 10.00K 22UF 3 3 R9 1.00K C22 620 1 SOT-23 V- 4.75K C21 R0805 1000PF R24 1 +5F -5F SOT-23 6 MODEM-2WA 6 MODEM-2WB TFORM/4 SOIC/8 C20 1000PF Y1 2.4576MHZ C27 10PF 6 MODEM-4WA 6 MODEM-4WB C0805 C28 C0805 10PF SDIP/28 R13 20.0K C29 10PF JP3 R18 R17 20.0K 20.0K 1 3 HC49U C0805 2,3,4,5,8 8 2 V+ CTS AGND D1 D2 D3 D4 D5 D6 D7 D8 19 18 17 16 15 14 13 12 U8A AD8092AR - 1UF RD DGND 3 2 3 4 5 6 7 8 9 2 D5 MMBD914LT1 R0805 C31 R22 11 13 25 R0805 R20 4.75K 5 26 U13 IOD0 IOD1 IOD2 IOD3 IOD4 IOD5 IOD6 IOD7 RC BRTS R15 50K 3224X-1-503 3 1 TD 1 4 RTS 10 U2 AM7911 C0805 8 TC 9 IOD[0..7] IOD[0..7] 4 2 12 DCD1-MODEM VBB RING VCC 1 RX1-MODEM RX1-MODEM DCD1-MODEM 3,4,6,7,8,9 C0805 TX1 TX1 22 3 3 RTS1# RTS1# 3,5,6 3 +5F 6 1 R0805 R19 C0805 C0805 U8B AD8092AR RTC-RST# 7 V+ R0805 - 2 4 T2 1 * R0805 R11 620 JUMPER JP16 1--2 AND 3--4 FOR 4 WIRE 1--3 AND 2--4 FOR 2 WIRE 6 3 HEADER 2X2 2 * 4 LA-07754 HEADER2X2 R0805 R0805 V- TFORM/4 5 R14 10K 3224X-1-103 C19 2 Op Amp 1 +5V 3 3 + +5F D3 MMBD914LT1 D4 MMBD914LT1 1UF SOIC/8 1 R7 100K 600 OHM 3 1 L1 POT3224X SOT-23 D2PAK/3 C14 .01UF C13 .1UF C0805 C0805 L0805 R0805 -5V Linear Regulator U7 79L05 SOT-23 C0805 -5F C25 1UF 1 C23 10UF IN GND L2 2 -12V OUT 3 C24 10UF 600 OHM C26 1UF C18 .01UF C16 .1UF C0805 C0805 L0805 TANTC TANTC TANTC TANTC DAQ ELECTRONICS, INC. 262B OLD NEW BRUNSWICK ROAD PISCATAWAY, NJ 08854-3756 TEL. (732) 981-0050 FAX. (732) 981-0058 153 Size C Document Number Date: Friday, April 29, 2005 Rev D A24249 Sheet 10 of 10 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 HP1 4.825" 4.375" 4.200" 3.750" 3.575" 3.125" 2.950" 2.500" 2.325" 1.875" 1.700" 1.250" 1.075" 0.625" 0.450" DATUM H7 HP2 H5 H8 H3 H1 H4 H2 H6 0.275" 8 1 1.750" 0.725" P.N.5473- S.N. 1 P2 P1 1 DAQ ELECTRONICS TBI1 DATUM 0.850" P.T.NO ACB-05473 ELECTRONICS PISCATAWAY N.J. NAME DRWN R.O. DATE SCHEM. APPD FILE P.L. 17009 9/93 DRILL CKD 17013 ASSY 17011 17012 TITLE 188 TBI1 ECN TBI1 STATUS TERMINAL BLOCK INTERFACE ASSEMBLY DIAGRAM SH. 1 OF DWG.NO. 17011 17012 1 REV P2 P1 1HP1 2HP1 16 HP2 L9017 N/C L9017 15 HP2 L9017 14 HP2 L9017 N/C 13 HP2 L9017 12 HP2 L9017 N/C 1 11 HP2 L9017 2 10 HP2 L9017 N/C 3 9HP2 L9017 4 8HP2 L9017 N/C 5 7HP2 L9017 6 6HP2 L9017 N/C 7 5HP2 L9017 8 4HP2 L9017 N/C 3HP2 L9017 2HP2 L9017 N/C 1HP2 L9017 L9017 N/C 3HP1 L9017 4HP1 L9017 N/C 5HP1 L9017 6HP1 L9017 N/C 7HP1 L9017 8HP1 L9017 N/C 9HP1 L9017 10 HP1 L9017 N/C 11 HP1 L9017 12 HP1 L9017 N/C 13 HP1 L9017 14 HP1 L9017 N/C 15 HP1 L9017 16 HP1 L9017 N/C PT.NO 5473-ACB ELECTRONICS NAME DRWN R.O. CKD APPD DATE P.L.# SCM# 17013 10/93 ASSY# 17009 FILE SHEET1 DRILL# 17012 17011 TITLE SH. 1OF 189 TBI1 STATUS TERMINAL BLOCK SCHEMATIC DIAGRAM DWG. NO. 17009 1 REV 190 191 192 4.925" P2 P3 U3 U2 U4 U5 U6 U7 2.375" DC1 DC2 DC3 DC4 P1 DC6 P.N. 06950-ACB DC5 R2 R1 U1 DC7 DC8 L1 L2 B01 06949 NOTES: 1. CONNECTORS P1, P2 AND P3 ARE MOUNTED ON THE UNDERSIDE OF THE PCB. PT.NO. ACB-06950 FILE ELECTRONICS NAME DRWN CHKD APPD TITLE DATE M.M.R 10/99 P.L.# PMEM SCM # A20469 ASSY # A20473 ECN. RAGEN # A20472 POLARIS MEMORY EXPANSION A21122 SH 1OF 1 DAUGHTER P.C.B. 193 DWG.NO. REV. ASSEMBLY DIAGRAM A20472 A A0-A19 VCC VCC VCC VCC NC 30 32 A0 12 A1 11 A2 10 A3 9 A4 8 A5 7 A6 6 A7 5 A8 27 A9 26 A10 23 A11 25 A12 4 A13 28 A14 29 A15 3 A16 2 A0 VCC A1 GND 1 A0 VPP A1 11 A2 10 A3 9 A4 8 A5 7 A6 6 17 AD3 A7 5 18 AD4 A8 27 U2 A2 A3 D0 27C512 (27C010) A4 D1 A5 EPROM D2 A6 A7 D3 A8 D4 A9 D5 A10 A11 D6 A12 D7 13 AD0 14 AD1 15 AD2 19 AD5 20 AD6 21 AD7 A9 26 A10 23 A11 25 A12 4 A13 28 A13 A14 A14 3 A15 31 A15 A16 A16 /PGM 31 12 'CE 22 2 VCC A0 GND A1 U3 A2 VCC A3 628128 D0 A5 SRAM A6 D1 MID RAM A7 A8 D3 A10 D4 A11 D5 A12 D6 A13 D7 A14 A0 16 A1 32 30 13 AD0 14 AD1 15 AD2 17 AD3 18 AD4 19 AD5 20 AD6 21 AD7 A16 'WE 'OE 24 10 A2 9 A3 A4 8 A4 A5 7 A5 A6 6 A6 A7 5 A7 A8 27 A8 U4 29F010 D0 FLASH D2 3RD D3 D4 26 A9 D5 A10 23 A10 D6 A11 25 A11 D7 A1 A2 A2 11 A1 10 A2 9 A3 8 A4 A3 9 A3 A2 10 A0 13 AD0 A4 14 AD1 A5 15 AD2 A6 17 AD3 A7 18 AD4 A8 5 A7 27 A8 19 AD5 A9 26 20 AD6 A10 23 21 AD7 A11 25 A12 A12 A13 28 A13 A13 U5 D2 A9 D5 A10 D6 A11 D7 4 A12 28 A13 29 A14 A14 3 A15 A15 A16 2 A16 A16 2 A16 A17 22 GND 22 GND U6 29F002/ 29F040 FLASH A4 8 A4 A5 7 A5 A6 6 A6 A7 5 A7 18 AD4 19 AD5 A8 27 A8 A9 26 A9 20 AD6 21 AD7 D5 A10 23 A10 D6 A11 25 A11 D7 16 D0 D1 D2 1ST D3 D4 13 AD0 14 AD1 15 AD2 17 AD3 18 AD4 19 AD5 20 AD6 21 AD7 A0 12 A1 11 A2 10 A3 9 A4 8 A5 7 A6 6 A7 5 A8 27 A9 26 A10 23 A11 25 A12 4 A12 A12 A13 28 A13 A13 28 A14 29 A14 A15 3 A15 A16 2 A16 A14 4 3 A15 31 A16 2 30 A17 1 A18 A17 'CE GND GND 13 AD0 14 AD1 GND 'WE 16 VCC A0 15 AD2 17 AD3 30 A17 'OE 24 31 'CS1' D3 D4 A15 'WE 'CE D1 2ND A14 22 D0 29F002 FLASH 7 A5 6 A6 29 A14 3 A15 'CE 32 VCC A1 A1 11 4 RES 12 12 A12 31 'RD' D1 32 A0 A0 A3 A9 24 'CS' 1 30 32 12 A0 11 A1 A3 A2 A15 'WR' 'WR' D2 A9 29 'OE CS2 A4 NC 1 A18 'OE 31 24 A1 U7 A2 'CS3' 'RD' 22 32 VCC A3 628128 CS2 A4 SRAM A6 14 AD1 D1 UPPER RAM A7 A8 15 AD2 D2 17 AD3 D3 A9 A10 18 AD4 D4 A11 19 AD5 D5 A12 20 AD6 D6 A13 21 AD7 D7 A14 30 13 AD0 D0 A5 A15 A16 'WE 'OE 24 'CE 22 'OE 24 'WR' 'WR' 16 GND 29 'WE 'CE 'WR' 'CS2' 'RD' 'RD' VCC A0 'RD' 'CS5' 'WR' 'CS4' 'RD' VCC A0-A19 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 2 A16 3 A15 4 A12 5 A7 6 A6 7 A5 8 A4 9 A3 10 A2 11 A1 12 A0 13 AD0 14 AD1 15 AD2 16 17 P3 18 19 P3 20 P3 21 P3 22 P3 23 P3 24 P3 25 P3 26 P3 27 P3 28 P3 29 P3 30 P3 31 GND P3 32 P3 P3 P1 20 1 AD3 2 AD4 3 AD5 1 2 2 4 AD6 1 L2 2 3 5 6 R1 10K AD7 P1 GND 'CS' 7 8 A10 P1 P1 P1 'RD' 9 P1 L1 11 ALE 4 6 A19/S6 5 7 A18/S5 6 8 A17/S4 7 9 A16/S3 8 9 A11 10 A9 11 A8 12 A13 13 R2 10K 10 P1 12 A16 11 D9 I3 I4 I5 10 VCC 1 CLK/IO I2 D8 U1 PAL 22V10 D7 D6 I6 D5 I7 D4 I8 D3 I9 D2 I10 13 P1 VCC 24 I1 D1 I11 D0 23 22 DC6 21 DC7 DC8 A17 19 A16 18 'CS5' 17 GND 'CS4' 16 'CS3' 15 'CS2' 14 'CS1' 12 GND A14 GND GND 14 15 DC[1-5] A18 20 PT.NO VCC ACB-06950 ELECTRONICS 'WR' 16 DRWN CKD APPD NAME DATE M.M.R. 10/99 P.L.# SCM# A20473 A20469 ASSY# RAGEN # A20472 FILE PMEM A21122 TITLE 194 Polaris Memory Expansion Daughter Board Schematic Diagram 1 SH. OF DWG. NO. A20473 1 REV A 195 196 197 198 199 200 201 202