Transcript
5
4
3
2
1
SD 600eval MAJOR REVISION HISTORY : PCB REV.
SCH. REV.
I2C ADDRESS TABLE : REFERENCE DESIGNATOR
DATE
DESCRIPTION
D
1.0
1.0
Released for fabrication
19-Nov-2015
2.0
2.0
Released for fabrication
27-March-2016
D
U45
PAGE DESCRIPTION
C
B
PAGE01 : COVER PAGE PAGE02 : BLOCK DIAGRAM PAGE03 : POWER SCHEME PAGE04 : APQ & PMIC GPIO TABLE PAGE05 : APQ_GSBI TABLE PAGE06 : APQ_CNT/AUDIO/GSBI PAGE07 : APQ_CSI/DSI/SDC/HDMI PAGE08 : APQ_WiFi/PCIE/SATA/USB PAGE09 : APQ8064 PWR/GND PAGE10 : APQ8064 DECAPS PAGE11 : eMMC/SD CARD INTERFACE PAGE12 : ETHERNET PHY PAGE13 : WiFi/BLUETOOTH PAGE14 : WiFi/BT PWR & GND PAGE15 : GPS/WIFI INTERFACE PAGE16 : AUDIO CODEC PAGE17 : PCIE & SATA REF CLOCK PAGE18 : USB HUB CONTROLLER PAGE19 : HDMI & USB CONNECTORS PAGE20 : HS / LS EXPANSION CONN PAGE21 : SWITCHES/LED PAGE22 : BATTERY CKT & JTAG PAGE23 : BOOT_CONFIG_SW PAGE24 : INPUT SUPPLY PAGE25 : PMIC INPUT SUPPLY SEC PAGE26 : PMIC CONTROL SECTION PAGE27 : PMIC GPIOs, MMPs & GND PAGE28 : PMM8920 SMPS/LDO PAGE29 : REVISION HISTORY PAGE30 : REVISION HISTORY PAGE31 : REVISION HISTORY
7 BIT SLAVE ADDRESS
DESCRIPTION
Acc & Gyro(LSM6DS3H)
0x6B (1101011b)
U46
Magnetometer(LIS3MDLTR)
0x1E (0011110b)
U22
EEPROM(AT24C128C)
0x25 (0100101b)
PCB LAYER STACK-UP DETAILS :
C
B
PCB MECHANICAL DETAILS : 1. PCB SIZE: 85 mm X 100 mm 2. PCB MATERIAL: FR4 3. NUMBER OF LAYERS: TBD 4. IMPEDANCE CONTROL: YES
NOTES, UNLESS OTHERWISE SPECIFIED : A
Project
1. RESISTANCE VALUES ARE IN OHM. 2. PARTS NOT INSTALLED ARE INDICATED WITH 'DNP'.
Designed eInfochips
A
SD 600eval
Title COVER PAGE
THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
Rev
Size
eInfochips#: 16_00295_02
C
Date: Friday, May 27, 2016 2
2.0
Sheet 1
1
of
31
5
4
3
2
1
BLOCK DIAGRAM D
D
C
C
B
B
Project
Designed eInfochips
A
A
SD 600eval
Title BLOCK DIAGRAM THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved.
Rev
Size
eInfochips#:
C
Date:Friday, May 27, 2016 5
4
3
2
16_00295_02
2.0
Sheet 1
2
of
31
5
4
3
2
1
POWER SCHEME D
D
C
C
B
B
Project
Designed eInfochips
A
A
SD 600eval
Title POWER SCHEME THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved.
Rev
Size
eInfochips#: 16_00295_02
C
Date:Friday, May 27, 2016 5
4
3
2
2.0
Sheet 1
3
of
31
5
4
3
2
1
APQ & PMIC GPIO TABLE APQ8064 GPIOs TABLE
D
PROCESSOR PIN# AP4
SIGNAL NAME
FUNCTION
LS_EXP_GPIO_G
DSI VSYNC SIGNAL
PMM8920 GPIOs TABLE PMIC PIN#
SIGNAL NAME
FUNCTION
R9
EXT_BUCK_VSEL
O/P VOLTAGE SEL SIGNAL FOR EXT BUCK
D38
CPU_GPIO_3
USER LED
A17
PCIE_WAKE#
E23
CPU_GPIO_7
USER LED
D12
AUDIO_PORT1_DET#
B26
CPU_GPIO_10
USER LED
F11
D26
CPU_GPIO_11
USER LED
F12
B30
SD_CARD_DET#
SD CARD DETECTION SIGNAL
G11
BB34
CPU_GPIO_27
AR8151-B RESET SIGNAL
BD30
CPU_GPIO_28
BC31
LS_EXP_GPIO_E
GYRO ACCL INT SIGNAL
BF38
LS_EXP_GPIO_J
CSI0 PWDN SIGNAL
BA33
CPU_GPIO_31
BD32
CPU_GPIO_32
BF32
LS_EXP_GPIO_B
AG5
D
AR8151-B WAKE UP SIGNAL AUDIO PORT DETECTION SIGNAL
PM_GPIO_18
USER SWITCH
EXT_BUCK_4V5_EN EXT_BUCK_EN
ENABLE SIGNAL FOR EXT BUCK ENABLE SIGNAL FOR EXT BUCK
K4
LS_EXP_GPIO_F
DSI BLCTRL SIGNAL
K5
LS_EXP_GPIO_I
CSI0 RST SIGNAL
J6
LS_EXP_GPIO_L
CSI1 PWDN SIGNAL
C
B
C
LSM9DS1TR INTERRUPT (INT2_A/G) SIGNAL
L11
FORCE_USB_BOOT
FORCE USB BOOT SIGNAL
LSM9DS1TR INTERRUPT (INT_M) SIGNAL
M12
PMIC_PM_GPIO_40
WCD9310 RESET SIGNAL
LSM9DS1TR INTERRUPT (INT1_A/G) SIGNAL
L12
PMIC_PM_GPIO_42
EXT AMPLIFIER ENABLE SIGNAL
TS RST SIGNAL
H1
LS_EXP_GPIO_H
DSI RST SIGNAL
LS_EXP_GPIO_K
CSI1 RST SIGNAL
F2
PMIC_MPP_8821_2
EXT AMPLIFIER ENABLE SIGNAL
AF2
LS_EXP_GPIO_A
APQ INT SIGNAL
M13
WiFi_LED
WiFi NOTIFICATION SIGNAL
AF6
CPU_GPIO_36
L14
BT_LED
BT NOTIFICATION SIGNAL
BE31
CPU_GPIO_42
BA29
CPU_GPIO_48
BF30
CPU_GPIO_49
USB HUB RESET SIGNAL
AY2
LS_EXP_GPIO_C
TS INT SIGNAL
AY4
LS_EXP_GPIO_D
MAG INT SIGNAL
AR8151-B CLOCK REQUEST SIGNAL WCD9310 INTERRUPT SIGNAL
B
LSM9DS1TR INTERRUPT (DRDY_M) SIGNAL
Project
Designed eInfochips
A
A
SD 600eval
Title APQ & PMIC GPIO TABLE THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved.
Rev
Size
eInfochips#: 16_00295_02
C
Date:Friday, May 27, 2016 5
4
3
2
2.0
Sheet 1
4
of
31
5
4
3
2
1
APQ_GSBI TABLE PROCESSOR PIN#
GSBI PORT
SIGNAL NAME
FUNCTION
C33
GSBI1_0
LS_EXP_UART_1_RFR
REQUEST TO SEND CONTROL SIGNAL
D32
GSBI1_1
LS_EXP_UART_1_CTS
CLEAR TO SEND CONTROL SIGNAL
E31
GSBI1_2
LS_EXP_UART_1_RX
RECEIVE SERIAL DATA
D30
GSBI1_3
LS_EXP_UART_1_TX
TRANSMIT SERIAL DATA
F34
GSBI2_0
I2C_2_SCL
I2C SERIAL CLOCK FOR SENSOR
D34
GSBI2_1
I2C_2_SDA
I2C SERIAL DATA FOR SENSOR
E33
GSBI2_2
-
-
B32
GSBI2_3
-
-
E25
GSBI3_0
I2C_3_SCL
I2C SERIAL CLOCK
C25
GSBI3_1
I2C_3_SDA
I2C SERIAL DATA
E23
GSBI3_2
CPU_GPIO_7
D24
GSBI3_3
C29
GSBI4_0
HS_EXP_CAM_I2C3_SCL
I2C SERIAL CLOCK FOR CAMERA
B28
GSBI4_1
HS_EXP_CAM_I2C3_SDA
I2C SERIAL DATA FOR CAMERA
D26
GSBI4_2
CPU_GPIO_11
USER LED
B26
GSBI4_3
CPU_GPIO_10
USER LED
BF26
GSBI5_0
LS_EXP_SPI_CLK
SPI SERIAL CLOCK
BE27
GSBI5_1
LS_EXP_SPI_CS_N
SPI CHIP SELECT SIGNAL
BD28
GSBI5_2
LS_EXP_SPI_MISO
SPI DATA INPUT
BF28
GSBI5_3
LS_EXP_SPI_MOSI
AL5
GSBI6_0
BT_DATA
AM4
GSBI6_1
BT_CTL
BLUETOOTH CONTROL SIGNAL
AN5
GSBI6_2
FM_SSBI
FM SSBI SIGNAL
AM2
GSBI6_3
FM_SDI
D22
GSBI7_0
HS_EXP_CAM_I2C2_SCL
I2C SERIAL CLOCK FOR CAMERA
C21
GSBI7_1
HS_EXP_CAM_I2C2_SDA
I2C SERIAL DATA FOR CAMERA
B22
GSBI7_2
LS_DEBUG_UART_RX
RECEIVE SERIAL DATA
D20
GSBI7_3
LS_DEBUG_UART_TX
TRANSMIT SERIAL DATA
D
D
C
B
USER LED
-
C
-
SPI DATA OUTPUT
B
BTLUTOOTH DATA SIGNAL
FM SDI SIGNAL
Project
Designed eInfochips
A
A
SD 600eval
Title APQ_GSBI TABLE THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved.
Rev
Size
eInfochips#: 16_00295_02
C
Date:Friday, May 27, 2016 5
4
3
2
2.0
Sheet 1
5
of
31
5
4
3
2
1
APQ_CNT/AUDIO/GSBI/GPIOs APQ8064 CONTROL / JTAG
APQ8064 AUDIO / GPIOs
CPU_PXO_IN
AB38
R178
5.1K
CPU_JTAG_TRST#
10K
PS_HOLD
PMIC1_SEC_INT_N/GPIO_73 PMIC1_USR_INT_N/GPIO_74 PMIC2_USR_INT_N/GPIO_77 PMIC2_SEC_INT_N/GPIO_76 PMIC1_MDM_INT_N/GPIO_75
G5
SSBI_PMIC1
H2
SSBI_PMIC2/GPIO_79
AB6 PMIC_FCLK
SSBI_PMIC_FCLK
R171
{15} {15} {12} {15}
{22}
{27}
APQ_PMIC_SSBI_8821
{27}
{20} {20} {20} {20}
BF40
0E
BA31
CPU_GPIO_31 CPU_GPIO_32 CPU_GPIO_27 CPU_GPIO_28
BA33 BD32 BB34 BD30
LS_EXP_I2S_DIN LS_EXP_I2S_DOUT LS_EXP_I2S_SCLK LS_EXP_I2S_WS
BF36 BF34 BC35 BD36
(P3) Audio Codec
0E
R212
AUD_SB1_DATA_A/GPIO_41 AUD_SB1_CLK_A/GPIO_40 AUD_SB1_MCLK/GPIO_39
MI2S_SD1/GPIO_31 MI2S_SD0/GPIO_32 MI2S_WS/GPIO_27 MI2S_SCK/GPIO_28 AUDIO_PCM_IN/GPIO_44 AUDIO_PCM_DOUT/GPIO_43 AUDIO_PCM_CLK/GPIO_46 AUDIO_PCM_SYNC/GPIO_45
{26} {23} BOOT_CONFIG_0 {23} BOOT_CONFIG_1 {23} BOOT_CONFIG_6
TP5
Design Note: FWD clock toggles when SSBI clock is in power down mode to communicate with PMIC and processor.
APQ8064
R222
{22}
APQ_PMIC_SSBI_8921
CPU_SSBI_PMIC_FWD_CLK
0E
{16} SLIMBUS1_MCLK
{27}
JTAG_PS_HOLD
PXO_OUT
M2 M4 J5 K2 L3
{27} PM2_APC_SEC_IRQ# {27} PM_MDM_IRQ#
R183
H4
PS_HOLD/GPIO_78
PXO_IN
CPU_PXO_OUT AD38
{27} PM_APC_SEC_IRQ# {27} PM_APC_USR_IRQ#
C9
TRST_N
CXO CXO_EN
{16} CLK_29M_SLIMBUS1
0E
B20 BC29 C37
BOOT_CONFIG_0/GPIO_87 BOOT_CONFIG_1/GPIO_50 BOOT_CONFIG_6/GPIO_4
GPIO (P3)
SLEEP_CLK
AL7 AK6
PMIC (P3)
{26} SLEEP_CLK_32.768KHz {8,26} CLK_19M_USB123_HS_SYSCLK {26} CPU_CXO_EN
CPU_JTAG_RTCK {22} CPU_JTAG_SRST# {22} CPU_JTAG_TCK {22} CPU_JTAG_TDI {22} CPU_JTAG_TDO {22} CPU_JTAG_TMS {22}
BE39
R217
(P3)
B6
(P3)
RESOUT_N
PMIC (P3)
{11} CPU_RESOUT#
F6 B8 C5 D6 D8 E7
RTCK SRST_N TCK/SWD_CLK TDI TDO TMS/SWD_DATA
JTAG (P3)
RESIN_N
B10
{16} SLIMBUS1_DATA
(P3) Bluetooth
MODE_1 MODE_0
B12
{27} CPU_RESIN#
D
U8G
U8L D12 C13
TP2 TP1
(P3) Mode Control
D
GPIO_0 GPIO_1 GPIO_3 GPIO_26 GPIO_29 GPIO_30 GPIO_33 GPIO_34 GPIO_35 GPIO_36 GPIO_37 GPIO_38 GPIO_42 GPIO_47 GPIO_48 GPIO_49 GPIO_55 GPIO_56 GPIO_86
AP4 AP2 D38 B30 BC31 BF38 BF32 AG5 AF2 AF6 AF4 AE5 BE31 BB30 BA29 BF30 AY2 AY4 B24
LS_EXP_GPIO_G
{20}
CPU_GPIO_3 {21} SD_CARD_DET# {11} LS_EXP_GPIO_E {20} LS_EXP_GPIO_J {20} LS_EXP_GPIO_B {20} LS_EXP_GPIO_K {20} LS_EXP_GPIO_A {20} CPU_GPIO_36 {12} CPU_GPIO_42
{16}
CPU_GPIO_48 {15} CPU_GPIO_49 {23} LS_EXP_GPIO_C {20} LS_EXP_GPIO_D {20}
APQ8064 ABM10-27.000MHZ-D30-T X1 CPU_PXO_OUT 1
3
2
4
C
C167 15pF
CPU_PXO_IN C
27MHz_30ppm
C168 15pF
APQ8064 REF VTG (EBI0 / EBI1)
APQ8064 GSBI
V1P8_VREG_S4
V1P2_VREG_L25
R198 10K
BE45
EBI0_CAL_REXT
EBI1_CAL_REXT
EBI0_ZQ_REXT
EBI1_ZQ_REXT
AT40 BF20
{6,15,20} I2C_2_SCL {6,15,20} I2C_2_SDA R218 1% R193 1%
F34 D34 E33 B32
240E 240E {21} CPU_GPIO_7 {6,20,23} I2C_3_SDA {6,20,23} I2C_3_SCL
D24 E23 C25 E25
GSBI1_3/GPIO_18 GSBI1_2/GPIO_19 GSBI1_1/GPIO_20 GSBI1_0/GPIO_21 GSBI2_0/GPIO_25 GSBI2_1/GPIO_24 GSBI2_2/GPIO_23 GSBI2_3/GPIO_22 GSBI3_3/GPIO_6 GSBI3_2/GPIO_7 GSBI3_1/GPIO_8 GSBI3_0/GPIO_9
GSPI5 (P3)
BA35
240E
AY12 L7 AP6 AG3
D30 E31 D32 C33
GSBI5_3/GPIO_51 GSBI5_2/GPIO_52 GSBI5_1/GPIO_53 GSBI5_0/GPIO_54
GSPI7 (P3)
240E
EBI1_VREF_D3 EBI1_VREF_D0_D2 EBI1_VREF_D1 EBI1_VREF_D0_DQ
LS_EXP_UART_1_TX LS_EXP_UART_1_RX LS_EXP_UART_1_CTS LS_EXP_UART_1_RFR
GSBI7_3/GPIO_82 GSBI7_2/GPIO_83 GSBI7_1/GPIO_84 GSBI7_0/GPIO_85
GSPI4 (P3)
R214 1% R225 1%
EBI0_VREF_D3 EBI0_VREF_D2 EBI0_VREF_D1 EBI0_VREF_D0
AU45
(P3) GSPI2
B
EBI1_VREF_CA LPDDR2 REF VTG
E13 N41 E21 F38
C280 0.1uF
EBI0_VREF_CA LPDDR2 REF VTG
R200 100K DNP
{20} {20} {20} {20}
VREF_LPDDR2_R BE35
(P3) GSPI3
U8A VREF_LPDDR2_R
{26} VREF_LPDDR2
(P3) GSPI1
U8C R194 100K DNP
GSBI4_0/GPIO_13 GSBI4_1/GPIO_12 GSBI4_2/GPIO_11 GSBI4_3/GPIO_10
BF28 BD28 BE27 BF26
LS_EXP_SPI_MOSI {20} LS_EXP_SPI_MISO {20} LS_EXP_SPI_CS_N {20} LS_EXP_SPI_CLK {20}
D20 B22 C21 D22
LS_DEBUG_UART_TX {20} LS_DEBUG_UART_RX {20} HS_EXP_CAM_I2C2_SDA {6,20} HS_EXP_CAM_I2C2_SCL {6,20}
C29 B28 D26 B26
HS_EXP_CAM_I2C3_SCL HS_EXP_CAM_I2C3_SDA CPU_GPIO_11 {21} CPU_GPIO_10 {21}
B
{6,20} {6,20}
APQ8064
Note: R194 and R200 need to be mounted in case of PMIC is no able to generate VREF_LPDDR2 supply.
APQ8064
I2C PULL UP RESISTORS V1P8_VREG_S4
R239 2.2K
R237 2.2K
R154 2.2K
R161 2.2K
R240 2.2K
DM1
R238 2.2K
R153 2.2K
LPDDR2 256MX64 EDBA164B2PF-1D-F-R
R152 2.2K
Project
Designed eInfochips
A
I2C_2_SDA {6,15,20} I2C_3_SDA {6,20,23} HS_EXP_CAM_I2C3_SDA HS_EXP_CAM_I2C2_SDA I2C_2_SCL {6,15,20} I2C_3_SCL {6,20,23} HS_EXP_CAM_I2C3_SCL HS_EXP_CAM_I2C2_SCL
Title
{6,20} {6,20}
APQ_CNT/AUDIO/GSBI
{6,20} {6,20}
Rev
Size THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
A
SD 600eval
3
eInfochips#: 16_00295_02
C
Date: Friday, May 27, 2016 2
2.0
Sheet 1
6
of
31
5
4
3
2
1
APQ_CSI/DSI/SDC/HDMI APQ8064 CSI0 / CSI1
APQ8064 DSI0 / DSI1
D
D
U8D
MIPI_CSI0_LN2_P/MIPI_CSI2_CLK_P MIPI_CSI0_LN2_N/MIPI_CSI2_CLK_N
BB44 BC43
{20} MIPI_CSI0_LN1_P {20} MIPI_CSI0_LN1_N
MIPI_CSI0_LN1_P/MIPI_CSI2_LN0_P MIPI_CSI0_LN1_N/MIPI_CSI2_LN0_N
BC41 BB42
{20} MIPI_CSI0_LN0_P {20} MIPI_CSI0_LN0_N
MIPI_CSI0_LN0_P MIPI_CSI0_LN0_N
MIPI_CSI1_LN1_P MIPI_CSI1_LN1_N MIPI_CSI1_LN0_P MIPI_CSI1_LN0_N CAM_MCLK0/GPIO_5 CAM_MCLK2/GPIO_2
BF44 BE43 BF42 BD42 BD44 BD46
MIPI_CSI1_CLK_P MIPI_CSI1_CLK_N MIPI_CSI1_LN1_P MIPI_CSI1_LN1_N
{20} {20}
MIPI_CSI1_LN0_P MIPI_CSI1_LN0_N
{20} {20}
AM46 AN45
{20} MIPI_DSI0_CLK_P {20} MIPI_DSI0_CLK_N
{20} {20}
AP46 AP44
{20} MIPI_DSI0_LN3_P {20} MIPI_DSI0_LN3_N
AN41 AN43
{20} MIPI_DSI0_LN2_P {20} MIPI_DSI0_LN2_N
AL43 AL41
{20} MIPI_DSI0_LN1_P {20} MIPI_DSI0_LN1_N
B38
HS_EXP_CSI0_MCLK
{20}
HS_EXP_CSI1_MCLK
{20}
AK46 AK44
{20} MIPI_DSI0_LN0_P {20} MIPI_DSI0_LN0_N
B36
1 L19
2 2.2uH
AK42 AJ45
C164 2.2uF 10V
APQ8064
MIPI_DSI0_CLK_P MIPI_DSI0_CLK_N
MIPI_DSI1_CLK_P MIPI_DSI1_CLK_N
MIPI_DSI0_LN3_P MIPI_DSI0_LN3_N MIPI_DSI0_LN2_P MIPI_DSI0_LN2_N MIPI_DSI0_LN1_P MIPI_DSI0_LN1_N MIPI_DSI0_LN0_P MIPI_DSI0_LN0_N
4-lane MIPI-DSI1 (MIPI)
BA45 BB46
MIPI_CSI0_LN3_P MIPI_CSI0_LN3_N
MIPI_CSI1_CLK_P MIPI_CSI1_CLK_N
4-lane MIPI-DSI0 (MIPI)
{20} MIPI_CSI0_LN2_P {20} MIPI_CSI0_LN2_N
MIPI_CSI0_CLK_P MIPI_CSI0_CLK_N
4-Lane MIPI_CSI0 (MIPI)
{20} MIPI_CSI0_LN3_P {20} MIPI_CSI0_LN3_N
BA43 BA41
MIPI (P3)
AY44 AY46
{20} MIPI_CSI0_CLK_P {20} MIPI_CSI0_CLK_N
2-Lane MIPI_CSI1 (MIPI)
U8B
MIPI_DSI1_LN3_P MIPI_DSI1_LN3_N MIPI_DSI1_LN2_P MIPI_DSI1_LN2_N MIPI_DSI1_LN1_P MIPI_DSI1_LN1_N MIPI_DSI1_LN0_P MIPI_DSI1_LN0_N
AT44 AT46 AW43 AW41 AV46 AV44 AU41 AU43 AP42 AR43
MIPI_DSI_LDO MIPI_DSI0_CAL
MIPI_DSI1_CAL
AT38
APQ8064
MIPI_LDO_0P4
C
C
APQ8064 SDC1/2/3
APQ8064 HDMI
U8H U8E
U5
{11} SDC1_DATA3
T4
{11} SDC1_DATA2
R3
{11} SDC1_DATA1
R5
{11} SDC1_DATA0
P2
{11} SDC1_CMD R170
{11} SDC1_CLK
33E T2
SDC1_DATA_5
SDC3_CMD
SDC1_DATA_4 SDC1_DATA_3 SDC1_DATA_2
SDC1_CMD
{11}
SDC3_CMD
{11}
SDC3_DAT0 SDC3_DAT1 SDC3_DAT2 SDC3_DAT3
{11} {11} {11} {11}
{19} CLK_165M_HDMI_P {19} CLK_165M_HDMI_N {19} HDMI_TX2_P {19} HDMI_TX2_N {19} HDMI_TX1_P {19} HDMI_TX1_N
SDC1_DATA_1 SDC1_DATA_0
BB4 BC3 BD4 BE3
SDC3_DATA_0 SDC3_DATA_1 SDC3_DATA_2 SDC3_DATA_3
SDC3_CLK
AW3 AT4 AT2 AR3
SDC2_DATA_3/GPIO_58 SDC2_DATA_2/GPIO_60 SDC2_DATA_1/GPIO_61 SDC2_DATA_0/GPIO_62
AW5
SDC2_CMD/GPIO_57
SDC1_CLK
AV2
SDC2_CLK/GPIO_59
SDC2_DAT3_EXP_CONN SDC2_DAT2_EXP_CONN SDC2_DAT1_EXP_CONN SDC2_DAT0_EXP_CONN SDC2_CMD_EXP_CONN SDC2_CLK_EXP_CONN
{20} {20} {20} {20}
{19} HDMI_TX0_P {19} HDMI_TX0_N
CLK_165M_HDMI_P CLK_165M_HDMI_N
N45 P46
HDMI_TX2_P HDMI_TX2_N
U41 U43
HDMI_TX1_P HDMI_TX1_N
T44 T46
HDMI_TX0_P HDMI_TX0_N
R43 R41
HDMI_TCLK_P HDMI_TCLK_M
HDMI_REXT HDMI_CEC/GPIO_69
HDMI_TX2_P HDMI_TX2_M HDMI_TX1_P HDMI_TX1_M
HDMI
{11} SDC1_DATA4
SDC1_DATA_6
33E
P(3)
P6
BB2
HDMI
P4
{11} SDC1_DATA5
BD2 R181
SDC3_CLK SDC3 (P2)
{11} SDC1_DATA6
SDC1_DATA_7
SDC2 (P3)
V2
SDC1 (P3)
W5
{11} SDC1_DATA7
HDMI_TX0_P HDMI_TX0_M
HDMI_DDC_CLK/GPIO70 HDMI_DDC_DATA/GPIO_71 HDMI_HPLUG_DET/GPIO_72
P44
R228
AD4
4.64K HDMI_CEC
AC3
{19}
HDMI_DDC_CLK
AC5
{19}
HDMI_DDC_DATA
AB4
HDMI_HPD#
{19}
{19}
{20} APQ8064
{20}
B
B
CLK_165M_HDMI_P
HDMI_TX2_P
HDMI_TX1_P
HDMI_TX0_P
APQ8064 R230 240E
Design Note: place 10k pull up resistor on SDC2_CMD_EXP_CONN signal receiver side
CLK_165M_HDMI_N
R226 240E
R231 240E HDMI_TX2_N
R232 240E HDMI_TX1_N
HDMI_TX0_N
SDC MODE SUPPORTED BY APQ8064 MODE
FUNCTION
SDC1
eMMC
104 MHz SDR at 1.8 V 152 MHz DDR at 1.8 V
8-bits
SDC2
AT HS CONN
104 MHz SDR at 1.8 V
4-bits
SDC3
SD CARD
208 MHz SDR at 1.8 V 52 MHz DDR at 1.8 V
4-bits
SDC4
WLAN
52 MHz SDR at 1.8 V
4-bits
MAX CLOCK RATE
WIDTH
Project
Designed eInfochips
A
A
SD 600eval
Title APQ_CSI/DSI/SDC/HDMI THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
Rev
Size
eInfochips#: 16_00295_02
C
Date: Friday, May 27, 2016 2
2.0
Sheet 1
7
of
31
5
4
3
2
1
APQ_WiFi/PCIE/SATA/USB/LVDS APQ8064 WiFi / BT / GPS
D
APQ8064 USB
D
U8J U8I
WLAN_REXT
BC27
{13} WLAN_SDC4_SCLK {13} WLAN_SDC4_CMD
BC33 BD34
{13} {13} {13} {13}
BD40 BC39 BA37 BB38
R205
10K
BT_SSBI WLAN_SDC4_D2 WLAN_SDC4_D1 WLAN_SDC4_D0
BA39
{13} WCN_XO
FM_SSBI {13} FM_SDI {13}
{25} CPU_USB1_ID R189
WLAN_CLK/SDC4_CLK/GPIO_68 WLAN_CMD/SDC4_CMD/GPIO_67 SSBI_BT/SDC4_DATA_3/GPIO_63 WLAN_DATA_2/SDC4_DATA_2/GPIO_64 WLAN_DATA_1/SDC4_DATA_1/GPIO_65 WLAN_DATA_0/SDC4_DATA_0/GPIO_66
GNSS_BB_IP GNSS_BB_IM GNSS_BB_QP GNSS_BB_QM
GNSS_BLANKING/GPIO_80 SSBI_EXT_GPS/GSBI1_UART_RX/GPIO_81
BD22 BF22 BC21 BB22 B34 AR5
USB1_HS_ID
BF14
WLAN_VREF WLAN_REXT
USB1_HS_VBUS
BC15
GPS_LNA_EN {15} GPS_SSBI {15}
0E
R182
200E
USB4_HS_VBUS
USB3_HS_DP
BE7
R180
USB4_HS_DM
USB4_HS_ID BF6
{18} CPU_USB3_D_N
GPS_BB_QP {15} GPS_BB_QM {15}
USB1_HS_REXT
200E
{18} CPU_USB3_D_P GPS_BB_IP {15} GPS_BB_IM {15}
USB4_HS_DP
USB1 2.0
AN5 AM2
USB1_HS_DP USB1_HS_DM
BF18
{25} V5_USB1_HS_VBUS
USB4 2.0
BT_DATA {13} BT_CTL {13}
USB3_HS_DM
BD6 BD8 BF4
CLK_19M_USB123_HS_SYSCLK_R
USB4_HS_REXT USB3 2.0
0.1uF 10V
SSBI_FM/GSBI6_3/GPIO_14 FM_SDI/GSBI6_2/GPIO_15
BD16 BF16
{19} CPU_USB1_D_P {19} CPU_USB1_D_N
SB3_HS_VBUS USB3_HS_ID USB3_HS_REXT
BC13
USB1_3_4_HS_SYSCLK
WCN_XO
APQ8064
HSIC USB2
BA27
WLAN_BB_QP WLAN_BB_QM
BT_DATA_STROBE/GSBI6_0/GPIO_17 BT_CTL/GSBI6_1/GPIO_16
AL5 AM4
USB SYS CLK
C318
Bluetooth P(3)
{13} WL_BB_QP {13} WL_BB_QN
WLAN_BB_IP WLAN_BB_IM
GPS P(3)
{26} VREF_WLAN
BD24 BD26
WLAN
{13} WL_BB_IP {13} WL_BB_IN
P(3)
BA25 BC25
USB2_HSIC_STROBE/GPIO_88 USB2_HSIC_DATA/GPIO_89 USB2_HSIC_CAL
BF10 BE11
CPU_USB4_D_P
{20}
CPU_USB4_D_N
{20}
BC11 BD12
R188
0E
BF12
R195
200E
AB2
USB2_HSIC_STROBE
Y4
USB2_HSIC_DATA
{20}
{20}
Y2 R166
1% 240E
APQ8064 0E
CLK_19M_USB123_HS_SYSCLK
R187
{6,26}
C
C
APQ8064 PCIE / SATA
APQ8064 LVDS U8F
U8K
0.1uF C357
0.1uF
CPU_PCIE_HSO_P
B44
CPU_PCIE_HSO_N
D44 E45
{12} CPU_PCIE_RX_P
D46
{12} CPU_PCIE_RX_N B
E43 200E
R224
SATA_CLKM
PCI_E_REFCLK_N SATA_TXP PCI_E_HSO_P PCI_E_HSO_N
SATA_TXM
PCI_E_HSI_P
SATA_RXP
PCI_E_HSI_N
SATA_RXM
PCI_E_REXT SATA_REXT SATA_TPA
K42 L43 K46
CPU_SATA_TX_P
K44
CPU_SATA_TX_M
H46
CPU_SATA_RX_P
J45
CPU_SATA_RX_M
C132 C126 C121
0.01uF 16V 0.01uF 16V 0.01uF 16V 0.01uF 16V
{17}
CLK_100M_CPU_SATA_CLK_N
{17}
CPU_SATA_TX_P_CONN
{17}
CPU_SATA_TX_M_CONN
{17}
CPU_SATA_RX_P_CONN CPU_SATA_RX_M_CONN
AE45 AF46 W43 W41 AA41 AA43
{17}
AA45 AB46
{17}
LVDS_CLK1_P LVDS_CLK1_M
LVDS_TX4_P LVDS_TX4_M
LVDS_CLK0_P LVDS_CLK0_M
LVDS_TX3_P LVDS_TX3_M
LVDS_TX7_P LVDS_TX7_M
LVDS_TX2_P LVDS_TX2_M
LVDS_TX6_P LVDS_TX6_M
LVDS_TX1_P LVDS_TX1_M
LVDS_TX5_P LVDS_TX5_M
LVDS_TX0_P LVDS_TX0_M
AD44 AD46 AC43 AC41 AE41 AE43 AF42 AG43 AH44 AH46 B
H44 CPU_SATA_REXT J43
APQ8064 R223 0E DNP
APQ8064
C129
CLK_100M_CPU_SATA_CLK_P
LVDS (P3)
C373
{12} C_CPU_PCIE_TX_N
PCI_E_REFCLK_P
SATA
{12} C_CPU_PCIE_TX_P
B42
PCIe
CLK_100M_CPU_PCIE_CLK_N
{17} CLK_100M_CPU_PCIE_CLK_N
D42
LVDS (P3)
SATA_CLKP CLK_100M_CPU_PCIE_CLK_P
{17} CLK_100M_CPU_PCIE_CLK_P
Y44 Y46
R229 4.64K
Project
Designed eInfochips
A
A
SD 600eval
Title APQ_WiFi/PCIE/SATA/USB THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
Rev
Size
eInfochips#: 16_00295_02
C
Date: Friday, May 27, 2016 2
2.0
Sheet 1
8
of
31
5
4
3
2
1
APQ8064 PWR/GND V1P05_VREG_S3
C
V1P05_VREG_S3
V1P2_VREG_L25
V1P05_VREG_L24
V2P95_VREG_L7
V1P8_VREG_LVS6
U8P
D
V1P8_VREG_S4
D
U8Q D40 E17 E39 G17 G31 H32 K10 K18 K20 K34 L19 L21 L35 M38 P16 P22 P24 R7 R15 R17 R23 R25 R31 R37 T10 T34 U33 U37 V20 V34 V36 W11 W21 W35 W37 Y22 AA21 AB24 AC17 AC25 AC31 AC37 AD18 AD26 AD34 AE17 AE25 AE33 AF18 AF26
VDD_CORE_1 VDD_CORE_2 VDD_CORE_3 VDD_CORE_4 VDD_CORE_5 VDD_CORE_6 VDD_CORE_7 VDD_CORE_8 VDD_CORE_9 VDD_CORE_10 VDD_CORE_11 VDD_CORE_12 VDD_CORE_13 VDD_CORE_14 VDD_CORE_15 VDD_CORE_16 VDD_CORE_17 VDD_CORE_18 VDD_CORE_19 VDD_CORE_20 VDD_CORE_21 VDD_CORE_22 VDD_CORE_23 VDD_CORE_24 VDD_CORE_25 VDD_CORE_26 VDD_CORE_27 VDD_CORE_28 VDD_CORE_29 VDD_CORE_30 VDD_CORE_31 VDD_CORE_32 VDD_CORE_33 VDD_CORE_34 VDD_CORE_35 VDD_CORE_36 VDD_CORE_37 VDD_CORE_38 VDD_CORE_39 VDD_CORE_40 VDD_CORE_41 VDD_CORE_42 VDD_CORE_43 VDD_CORE_44 VDD_CORE_45 VDD_CORE_46 VDD_CORE_47 VDD_CORE_48 VDD_CORE_49 VDD_CORE_50
VDD_CORE_51 VDD_CORE_52 VDD_CORE_53 VDD_CORE_54 VDD_CORE_55 VDD_CORE_56 VDD_CORE_57 VDD_CORE_58 VDD_CORE_59 VDD_CORE_60 VDD_CORE_61 VDD_CORE_62 VDD_CORE_63 VDD_CORE_64 VDD_CORE_65 VDD_CORE_66 VDD_CORE_67 VDD_CORE_68 VDD_CORE_69 VDD_CORE_70 VDD_CORE_71 VDD_CORE_72 VDD_CORE_73 VDD_CORE_74 VDD_CORE_75 VDD_CORE_76 VDD_CORE_77 VDD_CORE_78 VDD_CORE_79 VDD_CORE_80 VDD_CORE_81 VDD_CORE_82 VDD_CORE_83 VDD_CORE_84 VDD_CORE_85 VDD_CORE_86 VDD_CORE_87 VDD_CORE_88 VDD_CORE_89 VDD_CORE_90 VDD_CORE_91 VDD_CORE_92 VDD_CORE_93 VDD_CORE_94 VDD_CORE_95 VDD_CORE_96 VDD_CORE_97 VDD_CORE_98 VDD_CORE_99 VDD_CORE_100 VDD_CORE_101
AF28 AF34 AF36 AG13 AG19 AG27 AG29 AG35 AH8 AH14 AH22 AJ7 AJ13 AJ21 AJ37 AK14 AK16 AK22 AK24 AK30 AK32 AL15 AL23 AL25 AL31 AL33 AL37 AM10 AM34 AN17 AP10 AP18 AP20 AP26 AP28 AR13 AR19 AR21 AR27 AR29 AT14 AT22 AU13 AV14 AV16 AV24 AY36 BA5 BA9 BA15 BA19
F14 F22 G7 G13 G21 G35 G39 G41 H20 K36 L37 M8 M22 N21 N37 P32 R33 T18 U17 U25 V10 Y8 AB22 AB32 AC23 AC33 AF12 AF20 AG11 AG21 AG37 AH30 AH38 AJ29 AL17 AM18 AM26 AN25 AN33 AP12 AP34 AR7 AR11 AR41 AT30 AU21 AU29 AV12 AV22 AV34
APQ8064
VDD_MEM_1 VDD_MEM_2 VDD_MEM_3 VDD_MEM_4 VDD_MEM_5 VDD_MEM_6 VDD_MEM_7 VDD_MEM_8 VDD_MEM_9 VDD_MEM_10 VDD_MEM_11 VDD_MEM_12 VDD_MEM_13 VDD_MEM_14 VDD_MEM_15 VDD_MEM_16 VDD_MEM_17 VDD_MEM_18 VDD_MEM_19 VDD_MEM_20 VDD_MEM_21 VDD_MEM_22 VDD_MEM_23 VDD_MEM_24 VDD_MEM_25 VDD_MEM_26 VDD_MEM_27 VDD_MEM_28 VDD_MEM_29 VDD_MEM_30 VDD_MEM_31 VDD_MEM_32 VDD_MEM_33 VDD_MEM_34 VDD_MEM_35 VDD_MEM_36 VDD_MEM_37 VDD_MEM_38 VDD_MEM_39 VDD_MEM_40 VDD_MEM_41 VDD_MEM_42 VDD_MEM_43 VDD_MEM_44 VDD_MEM_45 VDD_MEM_46 VDD_MEM_47 VDD_MEM_48 VDD_MEM_49 VDD_MEM_50
VDD_P1_1 VDD_P1_2 VDD_P1_3 VDD_P1_4 VDD_P1_5 VDD_P1_6 VDD_P1_7 VDD_P1_8 VDD_P1_9 VDD_P1_10 VDD_P1_11 VDD_P1_12 VDD_P1_13 VDD_P1_14 VDD_P1_15 VDD_P1_16 VDD_P1_17 VDD_P1_18 VDD_P1_19 VDD_P1_20 VDD_P1_21 VDD_P1_22 VDD_P1_23 VDD_P1_24 VDD_P1_25 VDD_P1_26 VDD_P1_27 VDD_P1_28 VDD_P1_29 VDD_P1_30 VDD_P1_31 VDD_P1_32 VDD_P1_33 VDD_P1_34 VDD_P1_35 VDD_P1_36 VDD_P1_37 VDD_P1_38 VDD_P1_39 VDD_P1_40 VDD_P1_41 VDD_P1_42 VDDA_WLAN VDD_SATA_1 VDD_SATA_2 VREF_SDC
A9 A15 A17 A25 A27 A35 A37 B2 C45 E11 E19 E29 E37 G1 H40 J1 J47 L5 L47 U1 W1 W47 AA5 AE47 AG47 AL1 AU1 AU5 AU47 AV42 AW1 AW47 BC1 BC9 BC37 BF2 BF24 BF46 BG11 BG13 BG35 BG37
C264 U8R
1uF
1uF F42 {28} VREG_S5_REMOTE_SENSE
{28} VREG_S6_REMOTE_SENSE
G27 H24 K26 L27 L29 M30 N29 P30
V1P05_VREG_S6
{28} VREG_S1B_REMOTE_SENSE
E9 V12 W13 Y14 AA13 AB14 AB16 AC15
V1P05_VREG_S1B
{28} VREG_S2B_REMOTE_SENSE
G11 H12 K12 L11 L13 M14 N13 P14
V1P05_VREG_S2B
V1P3_VREG_S2
L41 M44
G25 T26 V26 V28 W27 W29 Y30 AA29
V1P05_VREG_S5
BA23
VDD_A2
VDD_P2
AY8
VDD_KR0_SNS VDD_KR0_1 VDD_KR0_2 VDD_KR0_3 VDD_KR0_4 VDD_KR0_5 VDD_KR0_6 VDD_KR0_7
VDD_P3_1 VDD_P3_2 VDD_P3_3 VDD_P3_4 VDD_P3_5 VDD_P3_6 VDD_P3_7 VDD_P3_8 VDD_P3_9 VDD_P3_10 VDD_P3_11 VDD_P3_12 VDD_P3_13 VDD_P3_14 VDD_P3_15 VDD_P3_16 VDD_P3_17 VDD_P3_18 VDD_P3_19 VDD_P3_20 VDD_P3_21 VDD_P3_22 VDD_P3_23 VDD_P3_24
VDD_KR1_SNS VDD_KR1_1 VDD_KR1_2 VDD_KR1_3 VDD_KR1_4 VDD_KR1_5 VDD_KR1_6 VDD_KR1_7 VDD_KR2_SNS VDD_KR2_1 VDD_KR2_2 VDD_KR2_3 VDD_KR2_4 VDD_KR2_5 VDD_KR2_6 VDD_KR2_7
D4 E27 E35 G15 G19 G23 G33 G37 K6 N7 T40 U7 AA7 AE7 AE37 AJ5 AN7 AU7 AY16 AY20 AY24 AY28 AY32 AY40
V1P2_VREG_L25
C252 1uF
VDD_P4
VDD_KR3_SNS VDD_USBPHY1_1P8 VDD_USBPHY3_1P8 VDD_USBPHY4_1P8
VDD_KR3_1 VDD_KR3_2 VDD_KR3_3 VDD_KR3_4 VDD_KR3_5 VDD_KR3_6 VDD_KR3_7
VDD_USBPHY1_3P3 VDD_USBPHY3_3P3 VDD_USBPHY4_3P3
W3 V1P8_VREG_L4 BB18 BB10 BB14
R168 R199
V1P8_VREG_L23
C
DNP 0E 0E DNP 0E 0E
R169 R206
BA17 BA7 BA13
V3P075_VREG_L3
V1P8_VREG_LVS7
C305
C250
C289
C304
C315
1uF
1uF
1uF
1uF
1uF
APQ8064 BC5
VREF_PADS_SDC C249 1uF 10V
APQ8064
U8M
C358
C307
C361
C364
1uF
1uF
1uF
{26}
U8N U8O
B
A
A1 A3 A7 A11 A13 A19 A21 A23 A29 A31 A33 A39 A43 A45 A47 B14 B16 B18 B46 C1 C3 C17 C41 C47 D10 D14 D16 D18 D28 D36 E1 E5 E15 E41 F2 F4 F10 F18 F26 F30 G3 G9 G29 G47 H16 H28 H36 J7 J41 K4
GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50
APQ8064
GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96 GND_97 GND_98 GND_99 GND_100
K14 K16 K22 K24 K30 K32 K38 L1 L15 L17 L23 L25 L31 L33 M10 M18 M26 M34 M40 M46 N1 N5 N17 N25 N33 N43 N47 P10 P12 P18 P20 P26 P28 P34 P36 P38 R1 R11 R13 R19 R21 R27 R29 R35 R47 T8 T14 T22 T30 U13
U21 U29 U45 U47 V4 V6 V14 V16 V22 V24 V30 V32 V38 V42 V44 V46 W7 W15 W17 W23 W25 W31 W33 Y10 Y18 Y26 Y34 Y38 Y40 AA1 AA17 AA25 AA33 AB12 AB18 AB20 AB26 AB28 AB36 AB42 AB44 AC11 AC13 AC19 AC21 AC27 AC29 AC35 AC47 AD8
GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150
GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192 GND_193 GND_194 GND_195 GND_196 GND_197 GND_198 GND_199 GND_200
AD10 AD14 AD22 AD30 AE1 AE13 AE21 AE29 AF14 AF16 AF22 AF24 AF30 AF32 AF44 AG7 AG15 AG17 AG23 AG25 AG31 AG33 AH4 AH10 AH18 AH26 AH34 AJ1 AJ17 AJ25 AJ33 AJ41 AJ43 AJ47 AK10 AK12 AK18 AK20 AK26 AK28 AK34 AK36 AL11 AL13 AL19 AL21 AL27 AL29 AL35 AL47
AM8 AM14 AM22 AM30 AM40 AM44 AN1 AN13 AN21 AN29 AN37 AP14 AP16 AP22 AP24 AP30 AP32 AR1 AR15 AR17 AR23 AR25 AR31 AR33 AR47 AT8 AT10 AT18 AT26 AU17 AU25 AU33 AU37 AV4 AV6 AV10 AV18 AV20 AV26 AV28
GND_201 GND_202 GND_203 GND_204 GND_205 GND_206 GND_207 GND_208 GND_209 GND_210 GND_211 GND_212 GND_213 GND_214 GND_215 GND_216 GND_217 GND_218 GND_219 GND_220 GND_221 GND_222 GND_223 GND_224 GND_225 GND_226 GND_227 GND_228 GND_229 GND_230 GND_231 GND_232 GND_233 GND_234 GND_235 GND_236 GND_237 GND_238 GND_239 GND_240
GND_241 GND_242 GND_243 GND_244 GND_245 GND_246 GND_247 GND_248 GND_249 GND_250 GND_251 GND_252 GND_253 GND_254 GND_255 GND_256 GND_257 GND_258 GND_259 GND_260 GND_261 GND_262 GND_263 GND_264 GND_265 GND_266 GND_267 GND_268 GND_269 GND_270 GND_271 GND_272 GND_273 GND_274 GND_275 GND_276 GND_277 DNC_1 DNC_2 DNC_3 DNC_4
V1P2_VREG_L25
AV30 AV36 BA1 BA11 BA21 BA47 BB6 BB26 BC7 BC17 BC23 BD10 BD14 BD18 BD20 BD38 BE1 BE15 BE19 BE23 BE47 BF8 BG1 BG3 BG5 BG9 BG15 BG17 BG21 BG25 BG29 BG31 BG33 BG39 BG41 BG45 BG47 AH2 AK2 AK4 AL3
V1P8_VREG_S4
V1P8_VREG_LVS7
V1P2_VREG_L2
U8S B4 B40 D2 E47 AD2 BC47 BG23
V1P8_VREG_LVS7
A5 A41 F46 AA47 AC1 AG1 AN47 BG7 BG19 BG27 BG43
VDD_DDR_C1_1 VDD_DDR_C1_2 VDD_DDR_C1_3 VDD_DDR_C1_4 VDD_DDR_C1_5 VDD_DDR_C1_6 VDD_DDR_C1_7
VDD_LVDS_1 VDD_LVDS_2 VDD_LVDS_PLL VDD_PLL1_1 VDD_PLL1_2 VDD_PLL1_3
VDD_DDR_C2_1 VDD_DDR_C2_2 VDD_DDR_C2_3 VDD_DDR_C2_4 VDD_DDR_C2_5 VDD_DDR_C2_6 VDD_DDR_C2_7 VDD_DDR_C2_8 VDD_DDR_C2_9 VDD_DDR_C2_10 VDD_DDR_C2_11
VDD_PLL2_1 VDD_PLL2_2 VDD_PLL2_3 VDD_PLL2_4 VDD_PLL2_5 VDD_PLL2_6 VDD_PLL2_7 VDD_PXO VDD_QFUSE_PRG
P42 T38 V1P2_VREG_L2
AH40 AK38 AM38 AP38 AV38
VDD_HDMI_1 VDD_HDMI_2
VDD_QDSP6_APP_1 VDD_QDSP6_APP_2 VDD_QDSP6_APP_3 VDD_QDSP6_APP_4
VDD_MIPI_1 VDD_MIPI_2 VDD_MIPI_3 VDD_MIPI_4 VDD_MIPI_5
VDDA_GPS VDDA_PCIE_1 VDDA_PCIE_2
AD40 AF38 VREG_L24_SR_PLL
AG41 V18 AB34 AF10
VREG_L24_SR_PLL
H8 K28 W19 AB10 AB30 AC7 AV32
VREG_LVS7_HF_PLL
R197
V1P05_VREG_L24
R191
0E
V1P8_VREG_LVS7
VREG_LVS7_SR2_PLL VREG_LVS7_SR2_PLL
R210
0E
AA37
V1P1_VREG_L1
AW7 AP36 AR35 AR37 AT34
V1P8_VREG_LVS3 V1P05_VREG_L26
BC19
R190 R184 DNP
F44 G43
APQ8064
B
0E
VREG_LVS7_HF_PLL
C248
C352
1uF
1uF
0E
V1P35_VREG_L18
0E
V1P3_VREG_S2 V1P05_VREG_S3
C290
C322
C273
1uF
1uF
1uF
APQ8064
Project
Designed eInfochips
A
SD 600eval
Title
APQ8064
APQ8064 PWR/GND THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
Rev
Size
eInfochips#: 16_00295_02
C
Date: 2
Friday, May 27, 2016
2.0
Sheet 1
9
of
31
5
4
3
2
1
APQ8064 DECAPS Core De-caps D
P3 De-caps (EBI1)
V1P05_VREG_S3
Krait0 De-caps
V1P8_VREG_S4
D
V1P05_VREG_S5
805 C314
C354
C353
C298
C285
C284
C328
C329
C351
C283
C350
C303
C302
C146
C145
C59
C60
C61
C85
C75
C149
C148
C147
C48
C98
C327
C310
C311
C313
C325
C326
C370
C377
C291
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
2.2uF
2.2uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
2.2uF
2.2uF
1uF
1uF
1uF
1uF
1uF
1uF
2.2uF
2.2uF
47uF
CPU Internal Memory De-caps
VDD_DDR_C1 De-caps
Krait1 De-caps
V1P8_VREG_S4
V1P05_VREG_L24
DNP 10V
V1P05_VREG_S6
C49
C139
C138
C137
C136
C153
C152
C151
C150
C50
C51
C52
C53
C46
C47
C96
C93
C89
C87
C95
C92
C88
C324
C337
C349
C323
C336
C348
C317
C319
C334
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
2.2uF
2.2uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
2.2uF
2.2uF
47uF
805 DNP 10V
C
C
P1 De-caps (EBI0)
VDD_QDSP6
V1P2_VREG_L25
Krait2 De-caps
V1P05_VREG_L26
V1P05_VREG_S1B
C122
C116
C113
C141
C108
C140
C110
C127
C102
C105
C114
C120
C103
C99
C338
C344
C333
C339
C345
C332
C295
C269
C270
C286
C294
C271
C281
C308
C260
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
2.2uF
2.2uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
2.2uF
2.2uF
47uF
PLL2 De-caps
VDD_DDR_C2 De-caps
805 DNP 10V
Krait3 De-caps
B
B
VREG_LVS7_HF_PLL
VREG_LVS7_SR2_PLL
V1P05_VREG_S2B
C266
C261
C306
C293
C330
C255
C57
C143
C144
C142
C58
C56
C55
C54
C268
C276
C263
C262
C275
C267
C256
C257
C247
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
2.2uF
2.2uF
47uF
HDMI De-caps V1P8_VREG_LVS7
V1P2_VREG_L25
LVDS De-caps V1P8_VREG_LVS7
MIPI De-caps V1P2_VREG_L2
805 DNP 10V
PLL1 De-caps VREG_L24_SR_PLL
C362
C372
C360
C371
C359
C367
C366
C368
C369
C277
C292
C301
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
Project
Designed eInfochips
A
A
SD 600eval
Title APQ8064 DECAPS THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
Rev
Size
eInfochips#:
C
Date: Friday, May 27, 2016 2
16_00295_02
2.0
Sheet 1
10
of
31
5
4
3
2
1
eMMC/SD CARD INTERFACE eMMC 16GB V2P95_VREG_L5 D
CAD note: Place these pull up resistors on respective signal trace to avoid stubs in layout
D
V1P8_VREG_S4
C253 0.1uF 10V
C274 1uF 10V
C259 1uF 10V
C245 2.2uF 10V
R172 10K
R173 51K DNP
R174 51K DNP
R175 51K DNP
R162 51K DNP
R176 51K DNP
R165 51K DNP
R164 51K DNP
R163 51K DNP V1P8_VREG_S4
U26 {7} {7} {7} {7} {7} {7} {7} {7}
SDC1_DATA0 SDC1_DATA1 SDC1_DATA2 SDC1_DATA3 SDC1_DATA4 SDC1_DATA5 SDC1_DATA6 SDC1_DATA7
SDC1_DATA0 SDC1_DATA1 SDC1_DATA2 SDC1_DATA3 SDC1_DATA4 SDC1_DATA5 SDC1_DATA6 SDC1_DATA7
H3 H4 H5 J2 J3 J4 J5 J6
SDC1_CLK SDC1_CMD
{7} SDC1_CLK {7} SDC1_CMD
W6 W5 A4 A6 A9 A11 B2 B13 D1 D14 H1 H2 H6 H7 H8 H9 H10 H11 H12 H13 H14 J1 J7 J8 J9 J10 J11 J12 J13 J14 K1 K3 K5 K7 K8 K9 K10 K11 K12 K13 K14 L1 L2 L3 L4 L12 L13 L14 M1 M2 M3 M5 M8 M9 M10 M12 M13 M14 N1 N2 N3 N10 N12 N13 N14 P1 P2 P3 P10 P12 P13 P14 K4 Y2 Y5 AA4 AA6
CAD NOTE: ROUTE SDC TRACE AS 50OHM IMPEDANCE
C
SD CARD CONNECTOR CAD note: Place these pull up resistors on respective signal trace to avoid stubs in layout
DM7
CAD NOTE: PLACE THESE CAPACITORS CLOSE TO VDD PIN
V2P95_VREG_L6 64GB SD CARD
V1P8_VREG_S4 C426 22uF 10V R289 100K
R279 51K DNP
R280 51K DNP
R281 51K DNP
R282 51K DNP
R283 51K DNP
C420 1uF 10V
R48 10K J10 4
B
{7} {7} {7} {7}
SDC3_DAT3 SDC3_DAT2 SDC3_DAT1 SDC3_DAT0
{7} SDC3_CMD
SDC3_DAT3 SDC3_DAT2 SDC3_DAT1 SDC3_DAT0
2 1 8 7
SDC3_CMD
3
SDC3_CLK
5
{7} SDC3_CLK {6} SD_CARD_DET#
R290
SDCARD_DET#
0E
9
VDD CD/DAT3 DAT2 DAT1 GND1 DAT0 GND2 GND3 CMD GND4 GND5 CLK GND6 GND7 CD_SWA VSS
10 11 12 13 14 15 16 6
U41 1 2 3 6 7 8
IO1 IO2 IO3 IO4 IO5 IO6
VCC NC_1 NC_2 GND
1
2
ESD5 2201778-1
10 4 9 5
CAD NOTE: PLACE THIS ESD CLOSE TO CD_SWA PIN NOTE: SEPARATE ESD IS REQUIRED FOR SD_CARD_DET_N.
ESD7C5.0DT5G
3
TPD6E001RSER
DAT0 DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7 CLK CMD
VCC_1 VCC_2 VCC_3 VCC_4 VCCQ_1 VCCQ_2 VCCQ_3 VCCQ_4 VCCQ_5
NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 RFU1 RFU2 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 NC25 NC26 NC27 NC28 RFU3 NC29 NC30 NC31 NC32 NC33 NC34 NC35 NC36 NC37 NC38 NC39 NC40 NC41 NC42 NC43 NC44 NC45 NC46 RFU4 RFU5 RFU6 RFU7 NC47 NC48 NC49 NC50 NC51 NC52 RFU8 NC53 NC54 NC55 NC56 NC57 RFU9 RFU10 NC58 NC59 NC60 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5
VDDI RST_n NC61 NC62 NC63 RFU11 NC64 NC65 NC66 NC67 NC68 NC69 RFU12 NC70 NC71 NC72 NC73 NC74 NC75 RFU13 RFU14 RFU15 NC76 NC77 NC78 NC79 NC80 NC81 NC82 NC83 NC84 NC85 NC86 NC87 NC88 NC89 NC90 NC91 NC92 NC93 NC94 NC95 NC96 NC97 NC98 NC99 NC100 NC101 NC102 NC103 NC104 NC105 NC106 NC107 NC108 RFU16 NC109 NC110 RFU17 NC111 NC112 NC113 NC114 NC115 NC116 NC117 NC118 NC119 NC120 NC121 NC122 VSS1 VSS2 VSS3 VSS4
M6 N5 U9 T10 R201 100K DNP
K6 W4 Y4 AA3 AA5 K2 U5 R1 R2 R3 R5 R12 R13 R14 T1 T2 T3 T5 T12 T13 T14 U1 U2 U3 U6 U7 U10 U12 U13 U14 V1 V2 V3 V12 V13 V14 W1 W2 W3 W7 W8 W9 W10 W11 W12 W13 W14 Y1 Y3 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 AA1 AA2 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AE1 AE14 AG2 AG13 AH4 AH6 AH9 AH11
R196
C363 0.1uF 10V
0E
C331 1uF 10V
CPU_RESOUT#
C265 1uF 10V
C347 2.2uF 10V
{6}
C279 1uF 10V
C
B
M7 P5 R10 U8
eMMC_1 MTFC16GAKAECN-2M WT
Project
Designed eInfochips
A
A
SD 600eval
Title eMMC/SD CARD INTERFACE THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
Rev
Size
eInfochips#: 16_00295_02
C
Date: Friday, May 27, 2016 2
2.0
Sheet 1
11
of
31
5
4
3
2
1
ETHERNET PHY V1P7_ETH_VDDCT
L2 1
D
C211 10uF
C10 0.1uF
V1P7_ETH_VDDCT
ETH_LX
2 2.2uH,600mA
D
C40 0.1uF
C197 10uF
C198 0.1uF
C5 0.1uF
C4 0.1uF
C3 0.1uF
U2
VCC_3V3_PCIE0 1 ETH_DVDDL_1P1
37 24 33 32
{17} CLK_100M_ETH_CLK_P {17} CLK_100M_ETH_CLK_N
35 36
{8} C_CPU_PCIE_TX_P {8} C_CPU_PCIE_TX_N C30 C25
{8} CPU_PCIE_RX_P {8} CPU_PCIE_RX_N
0.1uF 0.1uF
30 29
CLKREQ
4
ETH_PCIE_WAKE#
3
ETH_RST#
2
C
25
{23} I2C2_PCI_CLK
26
{23} I2C2_PCI_DATA
C41 470pF
DNP R64
TRXP0 TRXN0
REFCLK_P REFCLK_N
TRXP1 TRXN1
RX_P RX_N
TRXP2 TRXN2
TX_P TX_N
TRXP3 TRXN3
CLKREQ#
11 12
ETH_TRX0_P ETH_TRX0_N
P1 P2
14 15
ETH_TRX1_P ETH_TRX1_N
P3 P4
17 18
ETH_TRX2_P ETH_TRX2_N
P7 P8
20 21
ETH_TRX3_P ETH_TRX3_N
P9 P10
LEDYC TRDCT_1/2 TRDCT_3/4 LEDYA TRD1+ TRD1-
TRD3+ TRD3TRD4+ TRD4-
PERST# R2 49.9E
SMDATA XTL1
TESTMODE EPAD
10
ETH_BIAS
28
R10 2.37K
R3 49.9E
R4 49.9E
R5 49.9E
R6 49.9E
R7 49.9E
R8 49.9E
C7 0.1uF 10V
C8 0.1uF 10V
C9 0.1uF 10V
4 3
R63
P11
R62
49.9E
ETH_LED2_1Gbps#
LEDGC LEDGA
P14
R66
0E
P13
R65
49.9E
ETH_LED0_ACT#
S
VCC_3V3_PCIE0
ARJ11E-MCSA-A-B-EM2 C
2A
1
27 41
2 120E,2A
XTL0
ETH_GND_EARTH
Layout: 100 ohm differential pairs Place these caps as close as possible to AR8151 ETH_AVDDL_1P1
25MHz_20ppm C13 18pF 50V
0E
Q5 STR1P2UH7
2KV 1000pF FB6
Y1 2
ETH_LED1_LINK#
R9 49.9E C178
C6 0.1uF 10V
P12
J1 J2 J3 J4 J5 J6 J7 J8
TRD2+ TRD2-
WAKE#
SMCLK
0E
J3 P5 P6
DVDDL_REG DVDDL
G
R103 5.1K
D
C42 470pF
VDD33
AR8151-B
1
VCC_3V3_PCIE0
ETH_LED2_1Gbps# ETH_LED0_ACT# ETH_LED1_LINK# ETH_LED2_1Gbps#
C20 470pF
NC
7
38 39 23
AVDDH_REG AVDDH_1 AVDDH_2
RBIAS 8
40
1
LED0 LED1 LED2
2
LX
AVDDL_REG AVDDL_1 AVDDL_2 AVDDL_3 AVDDL_4
3
9 16 22
VDDCT
GND GND
ETH_AVDDH_2P7
6 13 19 31 34
G1 G2
5 ETH_AVDDL_1P1
Place these caps as close as possible to CRYSTAL
C26 18pF 50V
ETH_AVDDH_2P7 C36 1uF
C38 0.1uF
C205 0.1uF
C37 0.1uF
C217 0.1uF
C203 0.1uF
ETH_DVDDL_1P1 C202 1uF
C212 0.1uF
C206 0.1uF
C204 0.1uF
C39 1uF
C23 0.1uF
B
B
V1P8_VREG_S4 FB2
VCC_3V3_PCIE0
1 30E C27 0.1uF 10V
C32 10uF 10V
V1P8_VREG_S4
VCC_3V3_PCIE0
VCC_3V3_PCIE0
VCC3V3 2 1A
R100 10K DNP
R99 10K
C11 1uF 10V {27} PCIE_WAKE#
ETH_PCIE_WAKE#
R101 10K DNP
R14 10K DNP ETH_RST#
{6} CPU_GPIO_27
Project
CLKREQ
{6} CPU_GPIO_36
Designed eInfochips
A
A
SD 600eval
Title ETHERNET PHY
Rev
Size THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
eInfochips#: 16_00295_02
C
Date: Friday, May 27, 2016 2
2.0
Sheet 1
12
of
31
5
4
3
2
1
WiFi/BLUETOOTH CONTROL D
D
WCN3680B_CONTROL
WIFI+BT CHIP ANTENNA1
CAD NOTE: Use 0 ohm if CLK_OUT is a short length, or 33 ohm if CLK_OUTis >3cm. If used, place R207 very close to U10 ball number 36 location. U10A
WL_PDET_IN FM_SSBI FM_DATA FM_HS_RX
BT_DATA BT_CTL BT_SSBI
31 ABM12-48.000MHZ-B2X-T3 Y4 1 3
WL_RFIO_5G
XO_IN
43
XO_OUT
28 36
R207
0E
WCN_XO {8}
47 5
WL_BT_RFIO_2P4G
72
WL_RFIO_5G
16
WL_PDET_IN
ANTENNA1 FB
2
1
R53
WLAN_BT_ANT1_FILTER
0E
MP
FR05-S1-NO-1-004 48 41 61
C160
ANT_OUT
5.6pF 1
WL_CMD_DATA0 WL_CMD_DATA1 WL_CMD_DATA2 WL_CMD_SET WL_CMD_CLK
29 19 24
{8} BT_DATA {8} BT_CTL {8} BT_SSBI
WL_RF_DA_OUT WL_BT_RFIO_2P4G
71 70 77 63 33
WLAN_SDC4_D0 WLAN_SDC4_D1 WLAN_SDC4_D2 WLAN_SDC4_CMD WLAN_SDC4_SCLK
NC CLK_OUT
L18 3.3nH
L17 2.2nH
FM_SSBI {8} FM_SDI {8} FM_RX_ANT {16}
2
WL_BB_IP WL_BB_IN WL_BB_QP WL_BB_QN
1
{8} {8} {8} {8} {8}
58 64 51 57
WL_BB_IP WL_BB_IN WL_BB_QP WL_BB_QN
2
{8} {8} {8} {8}
WL-EXTPA_CTRL0 WL-EXTPA_CTRL1 WL_EXTPA_CTRL2 WL_EXTPA_CTRL3 WL_EXTPA_CTRL4
52 34 49 68 56
CAD NOTE: Place pi filter as close as possible to antenna
C
C
2
4 WCN3680B
C124 12pF
WIFI+BT PATCH ANTENNA
C109 12pF
DM4
0479500001
B
B
CAD NOTE: Put tripad for R52 and R54 J8 1 3 2
R52 DNP
0E
1909763-1 U13 WL_BT_RFIO_2P4G 1
C169
L16 1.0nH
U12
L20
2
1 18pF
IN
OUT GND
3
1
2
2
4
6
DEA202450BT-2114F1 C170 .75pF
WL_RFIO_5G
LBAND
1.1nH C171 .2pF
HBAND
U11 COMM GND1 GND2 GND3
2
4
1 3 5
C131
1
IN CPLD
OUT 50_OHM
3
R54
0E
ANT_OUT
2
10pF TFSC06054125-2113A1
DPX165950DT-8126A1
R51 49.9E DNP
R50 49.9E
C135
R49
WL_PDET_IN
0E
.75pF DNP C130 .5pF
Note: R51 may be installed with a 1pF cap to reduce the feedback power if the ADC is being saturated.
DNP C155 .5pF
Project
Designed eInfochips
A
A
SD 600eval
Title WiFi/BLUETOOTH
Rev
Size THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
eInfochips#:
C
16_00295_02
Date: Friday, May 27, 2016 2
2.0
Sheet 1
13
of
31
5
4
3
2
1
WiFi/BLUETOOTH PWR & GND WCN3680B DECAPS
WCN3680B PWR & GND
V1P3_VREG_S2 D
R242
0E
D
VDD_WL_LNA_1P3
C394 22uF
C386 100pF
U10B VDD_WL_BB_5GLNA_1P3
26
VDD_XO_1P8 C376 100pF
35
VDD_IO_1P8
30
VDD_MODEM_1P2 VDD_FM_1P3_CHIP
74 54 69 75
VDD_BT_TXRF_3P3
4
VDD_WL_PA1_UPC_1P3 C159 0.01uF
C156 100pF
3
VDD_BT_RF_1P3 VDD_WL_5GPA_1P3 C385 4.7uF
C384 100pF
7
VDD_BT_RFLO_1P3
2
VDD_BT_FM_DIG_1P3
25
VDD_WL_LO_1P3
50
VDD_WL_LO_1P3
6 40
VDD_WL_PA1_UPC_1P3
240E,100MHz
C
17
VDD_BT_RFLO_1P3
L14 1
14
VDD_BT_FM_DIG_1P3
C101 22uF
C107 0.01uF
C111 100pF
45 78
VDD_WL_BB_5GLNA_1P3 VDD_WL_LNA_1P3
9
VDD_WL_5GPA_1P3
59
VDD_BT_RF_1P3 C133 10uF
C154 0.01uF
11
VDD_WL_2GPA_3P3
73
VDD_WL_5GPA_3P3
32
VDD_WL_LO_1P3 VDD_BT_RFLO_1P3 C375 0.01uF
VDD_XO_1P8 VDD_IO_1P8 VDD_DIG_1P2 VDD_FM_RXFE_1P3 VDD_FM_RXBB_1P3 VDD_FM_PLL_1P3 VDD_FM_VCO_1P3 VDD_BT_TXRF_3P3
GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13
VDD_BT_RXRF_1P3 VDD_BT_BB_1P3 VDD_BT_PLL_1P3 VDD_BT_VCO_1P3 VDD_D_FM_DIG_1P3 VDD_WL_PLL_1P3 VDD_WL_2GPA_1P3 VDD_WL_UPC_1P3
GND_16 GND_17 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28
1 2 8 10 12 13 15 18 20 21 22 23 27 39 42 46 53 55 60 62 65 66 67 76 79
C
VDD_WL_BB_1P3 VDD_WL_5GLNA_1P3 VDD_WL_2GLNA_1P3
GND_14
VDD_WL_5GPA_1P3
GND_15
VDD_WL_2GPA_3P3
GND_18
37 38 44
VDD_WL_5GPA_3P3 VDD_WL_LO_1P3
WCN3680B
VDD_FM_1P3_CHIP C356 0.01uF
C346 0.01uF
VDD_BT_FM_DIG_1P3 C128 0.01uF
Note: The star routing of 1.3V supply trace as well as maintaining proper trace width is highly critical. B
B
VDD_WL_5GPA_3P3 C112 10uF
C115 0.01uF
V1P8_VREG_L4
C117 100pF DNP
R234
0E
VDD_XO_1P8 C382
C379
4.7uF
.47uF
DNP
VDD_WL_2GPA_3P3
V1P8_VREG_L4
C388 100pF DNP
V2P9_VREG_L10
R46
0E
VDD_IO_1P8
C104
C119
4.7uF
.47uF
DNP R59
0E
VDD_BT_TXRF_3P3 V1P2_VREG_LVS2
C106 10uF
C157 0.01uF DNP
R45 DNP
Note: If 2.4 GHz WLAN spurs are observed around 2.6 to 2.7 GHz,replace R59 with ~20 nH inductor.
0E
VDD_MODEM_1P2 C118 4.7uF
C125 0.01uF DNP
Project
Designed eInfochips
A
Design Note: If VDD_MODEM_1P2 not generated internally then mount the R45.
A
SD 600eval
Title WiFi/BT PWR & GND
Rev
Size THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
eInfochips#: 16_00295_02
C
Date: Friday, May 27, 2016 2
2.0
Sheet 1
14
of
31
5
4
3
2
1
GPS INTERFACE L35 1 22nH
2
C606
1.2pF
DNP
DNP
ACA-104-T GPS CHIP ANTENNA L3 1.0nH
1 L32
L34 22nH DNP
C71 3pF DNP
R302 0E
DNP
2 10nH
3
RF_IN GND GND1
DNP
6
R303 0E DNP
GPS FLTR
1
RF_OUT
1
DNP
VCC EN
V1P3_VREG_S2
L40 1.1nH
1 2
R34 0E DNP
L36 1.1nH DNP
BGU7007,115
2
1 1.0nH L39
1
FEED GND3
4 5
0E
1GPS_ANT_FILTER 4
V1P35_VREG_L18
V1P8_VREG_S4 U47
L38 1.1nH
L37 1.1nH
2
2
DNP
GND2 GND1
D
L33 100nH
2
1
3 2
C605 1nF 2
DNP R300
{8} GPS_LNA_EN ANT1 DNP
GPS_WGR7640 DNP
DNP
1
R301 0E
DNP
2 DNP
C607 0.1uF
1
DNP
D
1
V1P8_VREG_S4
2 C83 1uF 10V
C63 0.1uF 10V
1
1 L41 1.0nH
Place pi filter as close as possible to antenna
C62 0.1uF 10V
C608 U6
100pF
C609 5 13 16
100pF
100pF
VDD_RF_1P3_1 VDD_RF_1P3_2 VDD_RF_1P3_3
17
2 GPS UFL
1
GPS FLTR
2
1
R35
0E
B_PORT1 UNB_PORT B_PORT2
1909763-1
VDD_DIG_1P8
GND1 GND
4
2
RF_P
10nH
C66 1.2pF
SSBI 4
3
RF_M
L11
2 5
V1P8_VREG_TCXO
1
15
C74
1nF
C73
1nF
Y2 4 DNP
DM5
C94 1uF 10V
R39
1
0E
VCC
OUTPUT
AFC/GND
GND
GND1 GND2 GND3 GND4 GND5
2 10nH
{26} CLK_19M_GPS_XO
GPS PATCH ANTENNA
BB_Q_P BB_Q_M
2
TCXO
SF14-1575M5UBA2
C
BB_I_P BB_I_M
L8 U7
1 3
C64 0.1uF 10V
L12 100nH
CAD NOTE: Put tripad for R34,R35 and R303 J7
C610
2
2
CAD NOTE: Put tripad for R302 and L32 V1P8_VREG_S4
3
CLK_19M_GPS_XO_C
9
GPS_BB_IP
6
GPS_BB_IM
14
GPS_BB_QP
11
GPS_BB_QM
8
GPS_BB_IP {8} GPS_BB_IM {8} GPS_BB_QP {8} GPS_BB_QM {8} GPS_SSBI
1 3 7 10 12
GPS_SSBI {8}
R33 0E
R36 0E
C80
C79
C82
C81
10pF DNP
10pF DNP
10pF DNP
10pF DNP
C
WGR7640 C67 120pF DNP
2 DNP
DNP 19.2MHz 7L-19.200MDV-T
DNP
AP.17F.07.0064A
Design Note: Optional crystal in case GPS_XO is not able to generate from PMIC
Accelerometer & Gyroscope V1P8_VREG_S4
C397 0.1uF 10V
V1P8_VREG_S4
SHIELD
VCC3V3
C400 0.1uF 10V
R243 10K
SH11 1 2 3
U45 5 12 R245 10K
B
13
{6,15,20} I2C_2_SCL
14
{6,15,20} I2C_2_SDA
1 10 11
R246 10K DNP
VDDIO CS
8
VDD
4
INT1 SCL
SDO/SA0 CS_AUX NC
CPU_GPIO_32
{6}
CPU_GPIO_28
{6}
1 2 3 S0991-46R
SH2
SH3
1 2 3 S0991-46R
1 2 3 S0991-46R
SH8
SH16
1 2 3 S0991-46R
1 2 3 S0991-46R
S0991-46R B
9
INT2 SDA
SH6
2 3
SDX SCX
6 7
GND1 GND2
SH10
SH7
1 2 3
LSM6DS3H
1 2 3 S0991-46R
SH5
SH4
1 2 3 S0991-46R
1 2 3 S0991-46R
SH1
SH17
1 2 3 S0991-46R
1 2 3 S0991-46R
S0991-46R
Magnetometer V1P8_VREG_S4
SH12
VCC3V3
SH13
1 2 3 C399 0.1uF 10V
V1P8_VREG_S4
C396 0.1uF 10V
R248 10K 6
{6,15,20} I2C_2_SCL {6,15,20} I2C_2_SDA
1 11 9
A
S0991-46R
SH14
SH15
1 2 3 S0991-46R
1 2 3 S0991-46R
SH9 1 2 3
S0991-46R
S0991-46R
U46 10
R235 10K
1 2 3
VDD_IO
VDD
CS
INT DRDY
SCL C1 REV2 REV1 GND
SDA SA1
5 7 8 4 12 2 3
CPU_GPIO_31 CPU_GPIO_48
{6} {6}
C402 0.1uF 10V
Project
LIS3MDLTR
Designed eInfochips
A
SD 600eval
R233 10K DNP
Title GPS/WIFI INTERFACE
Rev
Size THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
eInfochips#:
C
Date: Friday, May 27, 2016 2
16_00295_02
2.0
Sheet 1
15
of
31
5
4
3
2
1
AUDIO CODEC V1P3_VREG_S2
V1P2_VREG_L25
40 PIN AUDIO EXPANSION CONN
VPH U3 VDD_CP_V1P8 VDD_DIG_V1P2 C29 0.1uF VDD_IO_V1P8 10V R15 0E VDDA_RX_V1P8 VDDA_TX_V1P8 R20 0E R19 0E DNP
D
C34 0.1uF 10V
C35 0.1uF 10V
MIC_IN1_P MIC_IN1_N
3 26 33 63 30 64 41
66 55
MIC_IN2_P MIC_IN2_N
58 54
MIC_IN3_P MIC_IN3_N
52 48
MIC_IN4_P MIC_IN4_N
59 53
MIC_IN5_P MIC_IN5_N
61 50
MIC_IN6_P MIC_IN6_N
56 45
CDC_MODE0 CDC_MODE1
14 19 25
{27} PMIC_PM_GPIO_40 CDC_DMIC_D0 CDC_DMIC_D1
21 20
VDD_CP VDD_DIG VDD_IO VDD_VBAT VDDA_RX VDDA_TX VDD_TXADC/LDOL_CAP
EARO_N EARO_P
HPH_LP HPH_RM
CDC_MBHC_IN {6} SLIMBUS1_MCLK
62 42 10 4 11 5
{6} CLK_29M_SLIMBUS1 {6} SLIMBUS1_DATA GND_CCOM
MODE0
MODE1
MODE
0
0
INVALID
0
1
SLIMBUS
35 69 49 44 36 32 24 13 2
CDC_EARO_N CDC_EARO_P
12 17
CDC_HPH_LP CDC_HPH_RM
46 39 40 34 29
CDC_LINE_OUT1 CDC_LINE_OUT2 CDC_LINE_OUT3 CDC_LINE_OUT4 CDC_LINE_OUT5
LINE_OUT1 LINE_OUT2 LINE_OUT3 LINE_OUT4 LINE_OUT5
MIC_IN2_P MIC_IN2_N MIC_IN3_P MIC_IN3_N
CP_VPOS CP_VNEG
8 6
CDC_CP_VPOS CDC_CP_VNEG
MIC_IN4_P MIC_IN4_N
71 70 67 68
CDC_MIC_BIAS1 CDC_MIC_BIAS2 CDC_MIC_BIAS3 CDC_MIC_BIAS4
MIC_BIAS1 MIC_BIAS2 MIC_BIAS3 MIC_BIAS4
MIC_IN5_P MIC_IN5_N MIC_IN6_P MIC_IN6_N
MICB_CFILT1 MICB_CFILT2 MICB_CFILT3
60 65 57
CDC_MICB_CFILT1 CDC_MICB_CFILT2 CDC_MICB_CFILT3
MODE0 MODE1 RESET_N
LDOH_CAP
DMIC_D0 DMIC_D1
CCOMP
MBHC_IN/MIC_IN7 MCLK
DMIC_CK0 DMIC_CK1
RX_I2S_SCK RX_I2S_WS
I2C_SDA I2C_SCL
SB_CK/RX_I2S_SD1 SB_DATA/RX_I2S_SD2 GND_CCOM
TX_I2S_SCK TX_I2S_WS TX_I2S_SD1/DMIC_D2 TX_I2S_SD2/DMIC_CK2
GND8 GND7 GND6 GND5 GND4 GND3 GND2 GND1
HPH_REF CP_C1_P CP_C1_N
47
C214 10V
0
1
1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
CDC_LINE_OUT5 CDC_EARO_N CDC_EARO_P CDC_MIC_BIAS4 CDC_DMIC_CK0 CDC_DMIC_D0
C215 2.2uF 10V
1uF
C28 0.1uF 10V
DNP
MIC_IN1_P MIC_IN1_N
C213 1uF 10V
MIC_IN6_P MIC_IN6_N
VPH
DNP C16 0.1uF 10V
C19 0.1uF 10V
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
CDC_LINE_OUT2 CDC_LINE_OUT4
PMIC_MPP_8821_2
{27}
CDC_MBHC_IN CDC_MIC_BIAS2 CDC_MIC_BIAS1 CDC_DMIC_CK1 CDC_DMIC_D1 MIC_IN4_P MIC_IN4_N MIC_IN5_P MIC_IN5_N
V1P8_VREG_S4
5177983-1
51 43
R96
0E
CPU_GPIO_42
{6}
CDC_DMIC_CK0 CDC_DMIC_CK1
27 15 31 9
C
C220 1uF 10V
22 16
GND_CCOM
37 38
16 PIN AUDIO EXPANSION CONN
CDC_HPH_REF
18 1 7
C24 2.2uF 10V
J6 CDC_LINE_OUT3 VPH
WCD9310
1
D
J4 {27} PMIC_PM_GPIO_42
MIC_IN1_P MIC_IN1_N
INTR_OUT C
28 23
CDC_MIC3_P CDC_HPH_REF
INVALID {27} AUDIO_PORT1_DET#
I2S
{13} FM_RX_ANT
1 3 5 7 9 11 13 15
CDC_LINE_OUT1
2 4 6 8 10 12 14 16
CDC_MIC2_P CDC_HPH_RM CDC_HPH_LP CDC_MIC_BIAS3
55510-116LF
CAD Note: Place this caps close to the respective pin
V1P8_VREG_S4
VDDA_RX_V1P8
V1P8_VREG_S4
B
R13
VDDA_TX_V1P8
0E C22 2.2uF 10V
R21 10K R17 10K DNP
V1P8_VREG_S4 R12
VDD_IO_V1P8
0E
B
C15 0.1uF 10V
C18 2.2uF 10V
CDC_MODE1 CDC_MODE0
MIC_IN3_P
V1P2_VREG_L25 V1P8_VREG_S4 R97
R16 0E
0E
VDD_CP_V1P8
C21 2.2uF 10V
R11
0E
R142
0E
R135
0E
CDC_MIC3_P
MIC_IN2_P
R146
0E
R136
0E
CDC_MIC2_P
VDD_DIG_V1P2 MIC_IN3_N R134 C14 0.1uF 10V
0E
MIC_IN2_N R138
R144 2.2K DNP
0E
R143 2.2K
R145 2.2K
R137 2.2K DNP
DNP CDC_MIC_BIAS3
CDC_MIC_BIAS2
Project
Designed eInfochips
A
A
SD 600eval
Title AUDIO CODEC
Rev
Size THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
eInfochips#: 16_00295_02
C
Date: Friday, May 27, 2016 2
2.0
Sheet 1
16
of
31
5
4
3
2
1
PCIE & SATA REF CLOCK CLOCK GENERATOR D
D
VCC3V3 VCC3V3 C224 10uF 10V
Spread Spectrum Selection Table SSON
Spread%
Spread Type
R106 10K DNP
R132 10K DNP
R110 10K
R108 10K
Output Frequency
1
-0.5
Down
100
0
OFF
NA
100
C227 1uF 10V
C230 0.1uF 10V
U20 21 1 6 12 17
R104 10K DIFF_OE_1
DIFF_OE_1
2
DIFF_OE_0
DIFF_OE_0
7
DIFF_OE_2
DIFF_OE_2
5
DIFF_OE_3
DIFF_OE_3
18
DIFF_SSON
DIFF_SSON
3 23
R111 10K
R123 10K
R105 10K DNP
R107 10K DNP
R109 10K DNP
X2
22
1
3
2
4
VDD_CORE VDD_DIFF_0 VDD_DIFF_1 VDD_DIFF_2 VDD_DIFF_3
DIFF0_P DIFF0_N
OE1
DIFF2_P DIFF2_N
DIFF1_P DIFF1_N
OE0 DIFF3_P DIFF3_N
OE2 OE3
SCLK SDATA
8 9
R112 R113
33E 33E
10 11
R114 R121
33E 33E
14 13
R131 R130
33E 33E
CLK_100M_CPU_SATA_CLK_P CLK_100M_CPU_SATA_CLK_N CLK_100M_ETH_CLK_P CLK_100M_ETH_CLK_N
{8} {8}
{12} {12}
CLK_100M_CPU_PCIE_CLK_P CLK_100M_CPU_PCIE_CLK_N
{8} {8}
16 15 19 20
SSON XIN/CLKIN
VSS_CORE VSS GND
XOUT
24 4 25
Si52144 25MHz_20ppm
C
C
C231
C232
18pF
18pF ABM8-25.000MHZ-B2-T
SATA CONNECTOR J1 CPU_SATA_TX_P_CONN CPU_SATA_TX_M_CONN
{8} CPU_SATA_TX_P_CONN {8} CPU_SATA_TX_M_CONN
CPU_SATA_RX_M_CONN CPU_SATA_RX_P_CONN
{8} CPU_SATA_RX_M_CONN {8} CPU_SATA_RX_P_CONN U1 1 2
B
3 4 5
D1 D2 D3 D4 D5 D6 D7
GND_1 A+ AGND_2 BB+ GND_3
VCC_5V0
LINEIN_1 LINEIN_2 GND1 LINEIN_3 LINEIN_4
LINEOUT_1 LINEOUT_2 GND LINEOUT_3 LINEOUT_4
10 9 8
MH_1
Slimline to standard sata conn MH_2
FB1 1
120E 2 3A C2 22UF 25V
7 6
C1 0.1UF
S1 S2 S3 S4 S5 S6
DP 5V0_1 5V0_2 MD GND_5 GND_6
DM10
M1
SATA_DATA
M2 B
SATA_PWR
MH_3
M3
HSP051-4M10 1735471-3
Project
Designed eInfochips
A
A
SD 600eval
Title PCIE & SATA REF CLOCK
Rev
Size THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
eInfochips#: 16_00295_02
C
Date: Friday, May 27, 2016 2
2.0
Sheet 1
17
of
31
5
4
3
2
1
USB HUB CONTROLLER USB HUB
D
D
VCC_3V3_USB VCC_3V3_USB
VCC_3V3_USB
VCC3V3
VCC_3V3_USB FB13
120E,2A
2A R269 100K
R264 10K DNP
R260 10K DNP
C405 0.1uF 10V
R263 10K DNP
TP7
{23} I2C2_HUB_CLK {23} I2C2_HUB_DATA R261 100K
R262 100K
R258
25 24 22 28
HS_IND / CFG_SEL[1] SCL / SMBCLK / CFG_SEL[0] SDA / SMBDATA / NON_REM[1] SUSP_IND / LOCAL_PWR / NON_REM[0]
8 9 20 21
Internal Defaults USB_HUB_RESET_N
{23} USB_HUB_RESET#
VDD33_1 VDD33_2 VDDA33_1 VDDA33_2 VDDA33_3 VDDA33_4
NC1 NC2 NC3 NC4
VBUS_DET
26 11
C406 0.1uF 10V
OCS_n1 OCS_n2
OCS_N[1] OCS_N[2] OCS_N[3]
30 31
{8} CPU_USB3_D_N {8} CPU_USB3_D_P
PRTPWR[1] / BC_EN[1] PRTPWR[2] / BC_EN[2] PRTPWR[3] / BC_EN[3]
TEST
13 17 19
C
USBDM_DN[1] / PRT_DIS_M[1] USBDP_DN[1] / PRT_DIS_P[1] USBDM_DN[2] / PRT_DIS_M[2] USBDP_DN[2] / PRT_DIS_P[2] USBDM_DN[3] / PRT_DIS_M[3] USBDP_DN[3] / PRT_DIS_P[3]
USBDM_UP USBDP_UP
Layout: 90 Ohm Differential Pairs R297
12K 1%
R278
1M
USB_HUB_RBIAS
HUB_XTALOUT HUB_XTALIN
15 23 5 10 29 36
27
R268 10K
4 3
C424 0.1uF
C408 4.7uF
35
PRTPWR_1 PRTPWR_2
1 2 3 4 6 7
USBDN_DN1 USBDN_DP1 USBDN_DN2 USBDN_DP2
C
{19} {19} {19} {19}
RBIAS
32 33
XTALOUT XTALIN / CLKIN
CRFILT PLLFILT GNDPAD
14 34 37
CRFILT PLLFILT
USB2513BI-AEZG
C421 0.1uF
CAD NOTE: PLACE THESE CAPACITORS AS CLOSER TO RESPECTIVE IC'S PIN
C422 18pF
24.00 MHz
C427 0.1uF
Layout: 90 Ohm Differential Pairs
C419 0.1uF
C409 18pF
C425 0.1uF
HUB_VBUS_DET
12 16 18
Y5 2
C410 0.1uF
C407 1uF
RESET_N
0E
1
C417 0.1uF
U40 CFG_SEL1 CFG_SEL0 NON_REM1 R267 10K
R259 100K
C413 0.1uF
CAD NOTE: PLACE THESE CAPACITORS AS CLOSER TO THE CRYSTAL
B
CFG_SEL[1]
CFG_SEL[0]
USB LOAD SWITCH
Discription
0
0
Internal Defaults (Self Powered)
0
1
SMBUS External Download
1
0
Internal Default (Bus Power)
1
1
2 Wire I2C EEPROM
VCC_5V0_USB_1
VCC_5V0
B
VCC_5V0_USB_2
VCC3V3
VCC_5V0_USB
FB14
30E
1A C412 0.1uF 10V
C411 0.1uF 10V
R277 10K ±1%
U39 7 PRTPWR_1 PRTPWR_2
1 4 6
C423 0.1uF 10V
IN
OUTA
ENA
OUTB
ENB
FLAGA_N
GND
FLAGB_N
R284 10K ±1%
8 5 2
OCS_n1
3
OCS_n2
LM3526-H
Project
Designed eInfochips
A
A
SD 600eval
Title USB HUB CONTROLLER THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
Rev
Size
eInfochips#: 16_00295_02
C
Date: Friday, May 27, 2016 2
2.0
Sheet 1
18
of
31
5
4
3
2
1
HDMI & USB CONNECTORS HDMI ESD
HDMI TYPE 'A' CONNECTOR
D
D
V1P8_VREG_LVS7
V5P0_VREG_HDMI J13 5-1903015-1
C418 0.1uF 10V
C414 0.1uF 10V
U42 TPD12S016PWR 11 24
R286 10K
1
{7} HDMI_CEC
2 3
{7} HDMI_DDC_CLK {7} HDMI_DDC_DATA
4
{7} HDMI_HPD# V1P8_VREG_LVS7
R291
0E
HDMI_CON_HPDB#
HDMI_LEVEL_CNTRL
5
HDMI_HOTPLUG_CTRL
12
VCC5V VCCA
5V_OUT CEC_B
CEC_A
HDMI_CON_5V
7
HDMI_CON_CEC_B HDMI_CON_CLK HDMI_CON_DATA HDMI_CON_HPDB#
8 9 10
SCL_B SDA_B HPD_B#
SCL_A SDA_A
13
HDMI_CON_5V C175 0.1uF 10V V5P0_VREG_HDMI R276
4.7K
HPD_A LS_OE
D2_P D2_N D1_P D1_N
CT_HPD
D0_P D0_N
HDMI_TX2_P HDMI_TX2_N
21 20
HDMI_TX1_P HDMI_TX1_N
18 17
HDMI_TX0_P HDMI_TX0_N
16 15
CLK_165M_HDMI_P CLK_165M_HDMI_N
GND1 GND2 GND3
CLK_P CLK_N
23 22
HDMI_TX1_P {7} HDMI_TX1_N {7} HDMI_TX0_P {7} HDMI_TX0_N {7}
18 HDMI_CON_DATA
16
HDMI_CON_CLK
15
HDMI_CON_CEC_B
13
CLK_165M_HDMI_N
12
CLK_165M_HDMI_P
10
HDMI_TX0_N
9
HDMI_TX0_P
7
HDMI_TX1_N
6
HDMI_TX1_P
4
HDMI_TX2_N CLK_165M_HDMI_P CLK_165M_HDMI_N
{7} {7}
3
HDMI_TX2_P
1
DM9 G4
SHELL4 HOT_PLUG_DET
G3
SHELL3 +5V
G2
SHELL2 I2C_DATA
G1
SHELL1
HDMI cable
I2C_CLK CEC
HDMI_GND
17
GND
CK-
11
CK_SHIELD CK+ D0-
8
D0_SHIELD
D0+
R60 0E
5
D1_SHIELD D1D1+
2
D2_SHIELD
D2-
14
HEC
R61
100E
C176
0.1uF
D2+
HDMI Type-A Layout: HDMI 100 ohm differential pairs
6 14 19
C
HDMI_TX2_P {7} HDMI_TX2_N {7}
19
10V C
HDMI_CHASSIS
USB OTG
USB2.0 TYPE 'A' CONNECTOR
C416 C404
1000pF
1000pF 2KV V5_OTG
2KV VCC_5V0_USB_2
J14 1981584-1
VCC_USB_HOST2 J11 292303-5 D+
G
5V
FB4
3
{18} USBDN_DP2
1
USB_DM_HOST2
4
USB_DP_HOST2
ESD4 1 2 3
1 2 3
6 5 4
USB_DM_HOST2_CONN
6 5 4
USB_DP_HOST2_CONN
1 2 3 4
FB11
CAD NOTE: PLACE THIS ESD CLOSE TO CONNECTOR J11
1
{8} CPU_USB1_D_N
HSP061-2M6
Layout: 90 Ohm Differential Pairs
ID
G
10 8 9
470E
500mA
USB_VBUS_OTG B
0E
2
{18} USBDN_DN2
L31
D+
CAD NOTE: 90 Ohm Differential Pairs
C177 4.7uF 10V
2USB_DM 3USB_DP
4
{8} CPU_USB1_D_P
500mA 470E
L22
90E
C415 0.1uF 16V
ESD3 3 2 1
3 2 1
4 5 6
4 5 6
USB_DM_CONN USB_DP_CONN R274
90E
B
D-
6 1
5
D-
5
V
11 6 7
C174 4.7uF 10V
4
500mA
3
470E
C398 100uF 6.3V
2
FB10 C395 22uF 10V
HSP061-2M6
470E FB5
500mA
USB1_ID {25}
CAD NOTE: PLACE THIS ESD CLOSE TO J14 (OTG) CONNECTOR. C403
1000pF
VCC_5V0_USB_1 2KV FB3 C172 22uF 10V
470E
500mA
VCC_USB_HOST1
C173 100uF 6.3V
J12 292303-5 5
CAD NOTE: PLACE THIS ESD CLOSE TO CONNECTOR J12 L21 90E {18} USBDN_DN1 A
{18} USBDN_DP1
1
2
USB_DM_HOST1
4
3
USB_DP_HOST1
Layout: 90 Ohm Differential Pairs
ESD2 3 2 1
3 2 1
4 5 6
USB_DM_HOST1_CONN
4 5 6
USB_DP_HOST1_CONN
V
D-
D+
G
6
1 2 3 4
Project
HSP061-2M6 FB12
Designed eInfochips
A
SD 600eval 500mA
Title
470E
HDMI & USB CONNECTORS
Rev
Size THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
eInfochips#: 16_00295_02
C
Date: Friday, May 27, 2016 2
2.0
Sheet 1
19
of
31
5
4
3
2
1
HS / LS EXPANSION CONNECTOR CSI0 / CSI1 EMI FILTERS
HIGH SPEED EXPANSION CONNECTOR
D
D
J9 U29 CSI0_D2CSI0_D2+
1 2
CSI0_D1CSI0_D1+
4 5 3
In_1_P In_1_N
Out_1_P Out_1_N
In_2_P In_2_N
Out_2_P Out_2_N
GND1
{7} {7} {7} {7} {7} {7}
U28
GND2
10 9 7 6
MIPI_CSI0_LN2_N MIPI_CSI0_LN2_P
{7} {7}
MIPI_CSI0_LN1_N MIPI_CSI0_LN1_P
{7} {7}
CSI1_CCSI1_C+
1 2
CSI1_D1CSI1_D1+
4 5
8
3
In_1_P In_1_N
Out_1_P Out_1_N
In_2_P In_2_N
Out_2_P Out_2_N
GND1
GND2
10 9 7 6
MIPI_CSI1_CLK_N MIPI_CSI1_CLK_P
{7} {7}
MIPI_CSI1_LN1_N MIPI_CSI1_LN1_P
{7} {7}
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
SDC2_DAT0_EXP_CONN SDC2_DAT1_EXP_CONN SDC2_DAT2_EXP_CONN SDC2_DAT3_EXP_CONN SDC2_CLK_EXP_CONN SDC2_CMD_EXP_CONN
{7} HS_EXP_CSI0_MCLK {7} HS_EXP_CSI1_MCLK
8
DSI0_C+ DSI0_CECMF04-4HSWM10
ECMF04-4HSWM10
DSI0_D0+ DSI0_D0-
U31 CSI1_D0CSI1_D0+ CSI0_D3CSI0_D3+
1 2 4 5 3
In_1_P In_1_N In_2_P In_2_N GND1
Out_1_P Out_1_N Out_2_P Out_2_N GND2
U30
10 9
MIPI_CSI1_LN0_N MIPI_CSI1_LN0_P
7 6
MIPI_CSI0_LN3_N MIPI_CSI0_LN3_P
{7} {7}
CSI0_D0CSI0_D0+
{7} {7}
1 2
CSI0_CCSI0_C+
4 5
8 3
In_1_P In_1_N
Out_1_P Out_1_N
In_2_P In_2_N
Out_2_P Out_2_N
GND1
GND2
DSI0_D1+ DSI0_D1-
10 9 7 6
MIPI_CSI0_LN0_N MIPI_CSI0_LN0_P
{7} {7}
MIPI_CSI0_CLK_N MIPI_CSI0_CLK_P
{7} {7}
DSI0_D2+ DSI0_D2DSI0_D3+ DSI0_D3-
8 {8} CPU_USB4_D_P {8} CPU_USB4_D_N
ECMF04-4HSWM10 ECMF04-4HSWM10
{8} USB2_HSIC_STROBE {8} USB2_HSIC_DATA
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
CSI0_C+ CSI0_CCSI0_D0+ CSI0_D0CSI0_D1+ CSI0_D1CSI0_D2+ CSI0_D2CSI0_D3+ CSI0_D3R255 R254 R253 R252
0E 0E 0E 0E
HS_EXP_CAM_I2C2_SCL HS_EXP_CAM_I2C2_SDA HS_EXP_CAM_I2C3_SCL HS_EXP_CAM_I2C3_SDA
{6} {6} {6} {6}
CSI1_D0+ CSI1_D0CSI1_D1+ CSI1_D1CSI1_C+ CSI1_C-
R256
V1P8_VREG_S4
100K
1-5177983-2
C
DSI0 EMI FILTERS
C
LOW SPEED EXPANSION CONNECTOR J5 1
U33 DSI0_D1DSI0_D1+
1 2
DSI0_D0DSI0_D0+
4 5 3
In_1_P In_1_N In_2_P In_2_N GND1
U34 Out_1_P Out_1_N Out_2_P Out_2_N GND2
10 9 7 6
MIPI_DSI0_LN1_N MIPI_DSI0_LN1_P MIPI_DSI0_LN0_N MIPI_DSI0_LN0_P
{7} {7}
DSI0_CDSI0_C+
1 2 4 5
{7} {7}
8
3
ECMF04-4HSWM10
In_1_P In_1_N In_2_P In_2_N GND1
Out_1_P Out_1_N Out_2_P Out_2_N GND2
10 9
MIPI_DSI0_CLK_N MIPI_DSI0_CLK_P
7 6
LS_EXP_I2C0_SCL LS_EXP_I2C0_SDA LS_EXP_I2C1_SCL LS_EXP_I2C1_SDA
8
{6} {6} {6} {6} {27} {6}
U32 1 2
DSI0_D2+ DSI0_D2-
4 5 3
In_1_P In_1_N
Out_1_P Out_1_N
In_2_P In_2_N
Out_2_P Out_2_N
GND1
15 17 19 21
ECMF04-4HSWM10
B
DSI0_D3+ DSI0_D3-
3 5 7 9 11 13
{6} LS_EXP_UART_1_CTS {6} LS_EXP_UART_1_TX {6} LS_EXP_UART_1_RX {6} LS_EXP_UART_1_RFR {6} LS_DEBUG_UART_TX {6} LS_DEBUG_UART_RX
{7} {7}
GND2
10 9 7 6
MIPI_DSI0_LN3_P MIPI_DSI0_LN3_N
{7} {7}
MIPI_DSI0_LN2_P MIPI_DSI0_LN2_N
{7} {7}
V1P8_VREG_L15
R128
0E
V1P8_VREG_S4
R129 DNP
0E
8
23 25 27 29 31 33
(APQ_INT) (TS_INT_N) (GYRO_ACCL_INT_N) (DSI_VSYNC) (CSI0_RST) (CSI1_RST)
LS_EXP_GPIO_A LS_EXP_GPIO_C LS_EXP_GPIO_E LS_EXP_GPIO_G LS_EXP_GPIO_I LS_EXP_GPIO_K
35 37
VCC_5V0
39
1
2
3 5 7 9 11 13
4 6
15 17 19 21 23 25 27 29 31 33
8 10 12 14 16 18 20 22 24 26 28 30 32 34
35 37
36 38
39
40
2 4 6
PWRBTN# {21,27} RSTBTN# {21,22,27}
8 10 12 14
LS_EXP_SPI_CLK {6} LS_EXP_SPI_MISO {6} LS_EXP_SPI_CS_N {6} LS_EXP_SPI_MOSI {6}
16 18 20 22 24 26 28 30 32 34
LS_EXP_I2S_WS {6} LS_EXP_I2S_SCLK {6} LS_EXP_I2S_DOUT {6} LS_EXP_I2S_DIN {6} B
(TS_RST_N) (MAG_INT) (DSI_BLCTRL) (DSI_RST) (CSI0_PWDN) (CSI1_PWDN)
36 38
LS_EXP_GPIO_B {6} LS_EXP_GPIO_D {6} LS_EXP_GPIO_F {26} LS_EXP_GPIO_H {27} LS_EXP_GPIO_J {6} LS_EXP_GPIO_L {27} SYS_12V_DCIN
40
ECMF04-4HSWM10 9-1734516-0
{6,15} I2C_2_SCL
{6,15} I2C_2_SDA
R127
0E
LS_EXP_I2C0_SCL
R126
0E
LS_EXP_I2C0_SDA
{6,23} I2C_3_SCL
{6,23} I2C_3_SDA
Project
R125
0E
LS_EXP_I2C1_SCL
R124
0E
LS_EXP_I2C1_SDA
Designed eInfochips
A
A
SD 600eval
Title HS / LS EXPANSION CONN
Rev
Size THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
eInfochips#: 16_00295_02
C
Date: Friday, May 27, 2016 2
2.0
Sheet 1
20
of
31
5
4
3
2
1
SWITCHES/LEDs USER LEDs
D
POWER BUTTON
D
SW2 1
2
R93
0E
VPH
U44
PWRBTN# {20,27}
LED2 OUT
1
SWTACT_1_EVQ9P
1
C208 1uF 10V
{6} CPU_GPIO_3
D4 ESDAVLC8-1BU2
R292
2
1
R296
120E
1
R295
120E
1
R294
120E
1
R293
120E
1
R288
27E
R1
1
0E
3
IN
GRN R2
2
2
GND DDTC143ZUA
2
R98 0E DNP
VPH
U43
LED3 OUT
{6} CPU_GPIO_7
R285
2
R1
1
0E
3
IN
GRN R2
RESET BUTTON
GND
2
DDTC143ZUA
VOL/ZOOMSW3 1
2
R102
0E
VPH
U38
RSTBTN# {20,22,27}
C
LED4
C225 1uF 10V
1
SWTACT_1_EVQ9P
1
OUT {6} CPU_GPIO_10
D5 ESDAVLC8-1BU2
R275
2
C
R1
1
0E
3
IN
GRN R2
2
2
GND 2
DDTC143ZUA
VPH
U35
LED5 OUT
{6} CPU_GPIO_11
R270
2
R1
1
0E
3
IN
GRN R2
GND
2
DDTC143ZUA
GENERAL PURPOSE BUTTONs VOL/ZOOM+ 1
BT LED VPH
U37
SW1
KYPD_ZOOM_VOL_+
2
R85
0E
PMIC_PM_GPIO_18
LED6
{27} OUT
B
{27} BT_LED
1
SWTACT_1_EVQ9P
D3 ESDAVLC8-1BU2
R272
B
R1
1
0E
2
IN
BLUE
C193
R2
GND
0.1uF 10V DNP
2
DDTC143ZUA
2
2
1
R91 0E
3
WiFi LED VPH
U36
LED7 OUT
{27} WiFi_LED
R271
1
0E
3
2
1
R287
120E
R1
IN
YELLOW R2
GND
2
DDTC143ZUA
Project
Designed eInfochips
A
A
SD 600eval
Title SWITCHES/LED THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
Rev
Size
eInfochips#: 16_00295_02
C
Date: 2
Friday, May 27, 2016
2.0
Sheet 1
21
of
31
5
4
3
2
1
BATTERY CKT & JTAG BATTERY CIRCUIT
D
RTC BATTERY
D
VBATT LOAD SWITCH VBATT R299 C180 1uF 10V
R71 300K DNP
DM12
R298 DNP
C2
0E
1
VBATT
3 VREF_BATT
VIN1 VIN2
VOUT1 VOUT2
ON
GND
DM2
P1 N1
2
P2
ML1220
A1 B1 R89 100K
C1
FPF1039BUCX DNP
2
BAT_TH
1
U15 A2 B2
{20,21,27} RSTBTN#
BAT1 BK-890
V3_COIN C179 1uF 10V
NOTE: Battery pack required with inbuilt thermistor and its current capacity should be less then 3500mAh J16
0.01E
R72
16K
PMIC_BAT_THERM
{25}
3 1
GND 87233-3
D12 ESDAVLC8-1BU2
1
BATTERY CABLE ASSEMBLY R80
0E
PMIC_BMS_CSP
C604 R56 68.1K DNP
{25} 2
DM3 R81 0.01E
100pF C
2
C
ROUTE DIFFERENTIALLY WITH 3x CLEARENCE AREA
3.7V@3000mAh R84
0E
PMIC_BMS_CSN
{25}
JTAG CONNECTOR B
B
V1P8_VREG_S4
U5
Note: Supply 5V or 3.3V required on 2nd pin for non luterbach trace32 debugger tools. R24 51K
Q2 V1P8_VREG_S4 3
S D G
R28 100K
C45 1uF 10V
3
S D G
4 5
GND1
GND
LINEIN_3 LINEIN_4
LINEOUT_3 LINEOUT_4
10 9
CPU_JTAG_TRST# CPU_JTAG_TDI
8 7 6
CPU_JTAG_TMS CPU_JTAG_SRST#
R22 0E DNP
R23 0E DNP
J17 {6} CPU_JTAG_TRST# {6} CPU_JTAG_TDI {6} CPU_JTAG_TMS {6} CPU_JTAG_TCK {6} CPU_JTAG_TDO {6} CPU_JTAG_RTCK {6} CPU_JTAG_SRST#
D2 2
1
JTAG_CONN_DET_N
100E STR1P2UH7
CPU_JTAG_TMS CPU_JTAG_SRST#
VCC3V3
LINEOUT_1 LINEOUT_2
1
STR1P2UH7
2 1
3
LINEIN_1 LINEIN_2
HSP051-4M10
JTAG_CONN_VREF
{6} JTAG_PS_HOLD
VCC_5V0
1 2
2
Q3 R27
C43 1uF 10V
CPU_JTAG_TRST# CPU_JTAG_TDI
BAT54KFILM
R26
33E
C44 0.1uF TP3 TP4
1 3 5 7 9 11 13 15 17 19 21
1 3 5 7 9 11 13 15 17 19 21
2 4 6 8 10 12 14 16 18 20 22
2 4 6 8 10 12 14 16 18 20 22
U4 CPU_JTAG_TDO CPU_JTAG_RTCK
1 2 3
CPU_JTAG_TCK JTAG_CONN_DET_N
4 5
LINEIN_1 LINEIN_2
LINEOUT_1 LINEOUT_2
GND1
GND
LINEIN_3 LINEIN_4
LINEOUT_3 LINEOUT_4
10 9
CPU_JTAG_TDO CPU_JTAG_RTCK
8 7 6
CPU_JTAG_TCK
HSP051-4M10
5-104655-3 R25 10K
Project
Designed eInfochips
A
A
SD 600eval
Title BATTERY CKT & JTAG THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
Rev
Size
eInfochips#:
C
Date: Friday, May 27, 2016 2
16_00295_02
2.0
Sheet 1
22
of
31
5
4
3
2
1
BOOT_CONFIG_SW BOOT MODE CONFIG SWITCH
D
D
V1P8_VREG_S4
R273 10K
R266 10K
R265 10K
R257 10K SW5_SPST1
{6} {6} {6} {27}
BOOT_CONFIG_0 BOOT_CONFIG_1 BOOT_CONFIG_6 FORCE_USB_BOOT 1 1 2
ESDAVLC8-1BU2
2
D7
CONFIG_1, CONFIG_0
2
1 1
D8
2
1 1 2 2
D9 ESDAVLC8-1BU2
ESDAVLC8-1BU2
1 2 2
ESDAVLC8-1BU2
1
1571983-4 D10
CONFIG_6
00
EMERGENCY BOOT (SDC3 FOLLOWED BY USB HS)
01
SDC3 FOLLOWED BY SDC1 (eMMC)
10
SDC3 FOLLOWED BY SDC2
11 0
SDC1 (eMMC) DEFAULT
1
FAST BOOT
SECURITY BOOT
C
C
I2C LEVEL TRANSLATOR
EEPROM
VCC3V3
V1P8_VREG_S4
V1P8_VREG_S4
C235 0.1uF 10V
C236
0.1uF 10V
U21 2
VREF1
VREF2 EN
3
{6,20,23} I2C_3_SCL
4
{6,20,23} I2C_3_SDA
SCL1
SCL2
SDA1
SDA2 GND
C233 0.1uF 10V
V1P8_VREG_S4 R117 2.2K
R133 2.2K
7 8 6 5
R141
200K
R139
I2C2_CLK_LEVEL
R122
I2C2_DATA_LEVEL
R116
1
R115
0E DNP DNP
0E 0E 0E
I2C2_PCI_CLK
I2C2_HUB_DATA I2C2_PCI_DATA
R155 100K DNP
{12}
I2C2_HUB_CLK
R158 100K
R159 100K DNP
R119 100K DNP
{18} {18} {12}
PCA9306DCUR
U22 8 BOARD_ID_EEPROM_A0 BOARD_ID_EEPROM_A1 BOARD_ID_EEPROM_A2
1 2 3
BOARD_ID_EEPROM_WP
7 6
{6,20,23} I2C_3_SCL R156 100K
Direction is from 1 to 2
R157 100K DNP
R160 100K
R118 100K
VCC SDA
5 R120
0E
I2C_3_SDA
{6,20,23}
A0 A1 A2 WP SCL
GND
4
AT24C128C
B
B
V1P8_VREG_S4
C240 1uF 10V
C241 0.1uF 10V
VCC3V3
R148 10K 3
{6} CPU_GPIO_49
C237 0.1uF 10V
U24
6 5 4
VCCA OE A1 A2
VCCB B1 B2 GND
7 8 1
USB_HUB_RESET#
{18}
2
TXS0102
Project
Designed eInfochips
A
A
SD 600eval
Title BOOT_CONFIG_SW THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
Rev
Size
eInfochips#: 16_00295_02
C
Date: Friday, May 27, 2016 2
2.0
Sheet 1
23
of
31
5
4
3
2
1
INPUT SUPPLY FROM ADAPTOR DM8 DC_VCC_12V F1
SYS_12V_DCIN
Reverse Voltage Protection
1
2
0.01E
12V,5A DC power adapter
1
SM6T30CA
3 2
3 2 1
D
Over Current Protection
C17 0.1UF 25V
4
2
C33 22UF 25V
3
C31 0.1UF 25V
700E/4A
ESD1
2 D1
3
PJ-041H
L1
1 C12 22UF 25V
1
Fast Blow at 5A blows in 1s J2
External Supply Input VIN: 12V (Vmin: 8V, Vmax: 18V)
R18
STPS8L30DEE-TR
Fuse 4.5A,32V D
12V TO 5V @5.5A DC/DC CONVERTER SYS_12V_DCIN
C195 22UF 25V
C
C196 0.1UF 25V
10K
VIN1 VIN2 VCC
6
R87
R82
C187 1uF 10V
C200 25V
9 10 11
SW1 SW2 SW3
1
0.1UF
FB9 1
2 22E,6A
R94 C181 10pF
25V DNP C209 0.1UF
R73 124K 1%
C218 47uF 10V
C222 22UF 25V
C
C228 0.1uF 10V
R1
1
VFB SS PGND1 PGND2
2 3.3uh L24
330E DNP
PG
3 7 8
C185 3300PF 25V
12
VBST
VREG
5
100K
16
VO
EN
2
VCC_5V0
DESIGN NOTE:RC Snubber Circuit for tunning
U17 13 14 15
4 17
GND TPAD
R76 22.1K 1%
TPS54526RSAT
Vout = (0.765)*(R1+R2)/R2 = (0.765)*(124k+22.1k)/22.1k = 5.05V
R2
CAD NOTE:Take trace to vout pin from VCC_5V after decoupling capacitors
12V TO 4.5V @5.5A DC/DC CONVERTER FOR PMIC VPH POWER
SYS_12V_DCIN
C191 22UF 25V
C194 0.1UF 25V
VIN1 VIN2 VCC
6
VBATT
SYS_12V_DCIN
R83
100K
VO VBST
EN
2
SW1 SW2 SW3
VREG
5
R88 10K
C188 1uF 10V
Q1 1
G D
2
VFB
3 7 8
C186 3300PF 25V
3
SS PGND1 PGND2
GND TPAD
VPH D6
12
C201 25V
9 10 11
1
0.1UF
2 3.3uh
FB8 1
2
C184 10pF C210 DNP
1
2
1
4.2V
22E,6A
L25 R95 330E DNP 25V 0.1UF
R78 110K 1%
C219 47uF 10V
C223 22UF 25V
330mV @ 4A MBRS410LT3G
C229 0.1uF 10V
ARM ENERGY PROBE
R1 DC_VCC_12V
4 17
SYS_12V_DCIN
VPH_PWR
VPH
B
J15 R77 22.1K 1%
TPS54526RSAT
R2
S FDN335N
Vout = (0.765)*(R1+R2)/R2 = (0.765)*(110k+22.1k)/22.1k = 4.57V
+ -
CAD NOTE:Take trace to vout pin from VCC_5V0(4.5V) after decoupling capacitors
{27} EXT_BUCK_4V5_EN Battery (VBAT)
SUPP_VPH_5V0
16
PG
B
R1 0E
NOTE: VPH SUPPLY SUPPLEMENTARY DIODE
DESIGN NOTE:RC Snubber Circuit for tunning
U18 13 14 15
NC
1
SNS_P
R67
0E
DCIN_SNS_P
2
SNS_N
R69
0E
DCIN_SNS_N
R68
0EDNP
VPH_PWR_SNS_P
R70
0EDNP
VPH_PWR_SNS_N
3
87233-3
Regualtor (U18)Status
Connected
OFF (EN=0)
Not connected
ON (EN=1)
12V TO 3.3V @2A DC/DC CONVERTER
DM11
CAD NOTE : Use tripad in layout for R67 with R68 & R69 with R70 ground and star route their traces in layout.
SYS_12V_DCIN
U16 C190 22UF 25V
13 14 15
C192 0.1UF 25V
10K
R90
6 2
R86
C189 1uF 10V
A
C183 3300PF 25V
100K
5 3 7 8
VIN1 VIN2 VCC
VO VBST
EN VREG
SW1 SW2 SW3
12 9 10 11
VFB GND TPAD
1
ARM Energy Assembly
FB7
16
PG SS PGND1 PGND2
VCC3V3
DESIGN NOTE:RC Snubber Circuit for tunning C199 25V
0.1UF
1
2 3.3uh
1
L23 R92 330E DNP
120E,2A C182 10pF
C207 DNP
25V 0.1UF
2
R75 73.2K 1%
C216 47uF 10V
C221 22UF 25V
C226 0.1uF 10V
2A
R1
Project
4 17 R74 22.1K 1%
TPS54226RGTR
Vout = (0.763+0.0017*Vout)*(R1+R2)/R2 = (0.763+0.0017*5)*(73.2k+22.1k)/22.1k = 3.31V
R2
CAD NOTE:Take trace to vout pin from VCC3V3 after decoupling capacitors
THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
Designed eInfochips
A
SD 600eval
Title INPUT SUPPLY
Rev
Size
eInfochips#: 16_00295_02
C
Date: Friday, May 27, 2016 2
2.0
Sheet 1
24
of
31
5
4
3
2
1
PMIC INPUT SUPPLY SECTION D
D
Q6 V5P0_VREG_OTG
1
2
S1
D1_1 D1_2
G1
G2
6 7
5 V5_OTG R185 20.5K
3 8
D2_1 D2_2
4
S2
R202 20.5K R192
FDMA1032CZ
R186 0E
47K
C297
1uF 10V
C
V5_USB_OUT_DCIN C
U9A
VCC_5V0 U25A FDMB3800N
USB Charger & OTG Switch
U25B FDMB3800N
D15 E17 V5_USB_OUT_DCIN
S
6
USB_N1 USB_IN2
USB_OUT1 USB_OUT2
USB_ID
PHYVBUS
4.7uF 10V
E15 F17 F16
PMIC_PHY_VBUS
E16
PMM8920_OVP_CTL
R204
0E
V5_USB1_HS_VBUS
{8}
Wall charger
H14 J14
4
2 C244 4.7uF 10V
E6
5 G
G
C242 22uF 10V 603
USB1_ID
D
3 S
D
1
C321
D17
PMM8920_OVP_CTL
DC_IN1 DC_IN2
OVP_CTL
VPH_PWR
OPV_SNS/DC_IN
VPH
SMBC Circuit
C340 22uF 10V 603
VPH
C335 0.1uF 10V C162
0.1uF
PMIC_VDRV_N
J17 F3 G17 J15 K15
VDD_CDRV VPH_PWR_8821 VPH_PWR_8921
VSW_CHG1 VSW_CHG2
VDRV_P VDRV_N
VPRE_CAP
PMIC_VSW_CHG
L17 M17
1 L15
2 1uH,3.8A
0.01E R251
H16
C355
0.1uF 10V
BMS Circuit
R40 47K
G16 K16 F13 N17
10V C97 1uF 10V
{22} PMIC_BMS_CSN {22} PMIC_BMS_CSP
NOTE: Please Refer Page 22 for BMS circuit
{22} PMIC_BAT_THERM L16 C374 4.7uF 10V
CAD NOTE: Place C97 close to pin U9.D17
BMS_CSM BMS_CSP BAT_ID BAT_THERM
VBAT VREF_BAT ATC_LED_SRC BET_FET_N
J16 P10 B17 H17
Q4 VREF_BATT PMIC_ATC_LED_SRC
{26}
CPU_BAT_FET_N
3
G
Coin cell/keep Alive battery
V3_COIN
R55 0E
C134 10uF 10V
VCOIN PMM8920
S1 D1 D2 D3 D4
C158 0.1uF 10V
C166 10uF 10V
4 1 2 5 6
STT7P2UH7
VBATT B
B
V3P075_VREG_L3
G
1
R215 100K DNP
3
2
S
D
Q7 RUM002N05
R209
{8} CPU_USB1_ID
0E
USB1_ID {19}
DNP
Project
Designed eInfochips
A
A
SD 600eval
Title PMIC INPUT SUPPLY SEC THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
Rev
Size
eInfochips#: 16_00295_02
C
Date: 2
Friday, May 27, 2016
2.0
Sheet 1
25
of
31
5
4
3
2
1
PMIC CONTROL SECTION V1P8_VREG_TCXO
D
D
CAD NOTE: Place series resistor close to Oscillator
C100 1uF 10V Y3
R47
CAD NOTE: Place close to 19.2MHz Oscillator
V1P8_VREG_L4
0E
19.2_XTAL_OUTPUT
3
U9D
RT1
PMIC_XO_THERM
100K_NTC PMIC_AMUX_IN
F7 F14 D16
XO_THERM PA_THERM AMUX_IN
GND
VCC
AFC/GND
4 1
19.2_XTAL_AFC_GND
VREF_XO VREF_LPDDR2
F4 K17 R221
0E
VREF_LPDDR2
R44
0E DNP
19.2MHz 7L-19.200MDV-T ±0.5ppm
Analog MUX &HK/XO ADC Circuits
R41 100K DNP
OUTPUT
2
CAD NOTE: Provide separation between the 32 kHz and 19.2 MHz crystals
{6}
19.2 MHz XO circuits
XTAL_19M_IN XTAL_19M_OUT
R203 100K {6} CPU_CXO_EN
C246
D1
XO_OUT_A0 XO_OUT_A1 XO_OUT_A2
XO_OUT_D0_EN
XO_OUT_D0 XO_OUT_D1
XTAL_32K_IN
20pF DNP
XTAL_32K_IN XTAL_32K_OUT
X3 32.768KHz C258
20pF DNP
XTAL_32K_OUT_R
R177
F8 F9 J7 K7 F5
PMIC_XTAL_19M_IN
PMIC_GPS_XO_CLK
PMIC_XO_OUT_D0
R211
0E
R213
0E
CLK_19M_GPS_XO
{15}
CLK_19M_USB123_HS_SYSCLK
{6,8}
32.768 kHz XTAL, sleep clock, and MP3 clock circuits
ABS07-32.768KHZ-T
C
J5 J4
0E
SLEEP_CLK0 SLEEP_CLK1/MP3_CLK1/GPIO_43 SLEEP_CLK2/MP3_CLK2/GPIO_44
XTAL_32K_OUT
SSBI_ALT_CLK/GPIO_39
B6 B5 P4 M10 K14
XTAL_32K_IN XTAL_32K_OUT PMIC_SLEEP_CLK0
C
R236
0E
K13
SLEEP_CLK_32.768KHz
{6}
CPU_SSBI_PMIC_FWD_CLK
{6}
VREF output
VREF_DAC/MPP_8921_06 VREF_PADS/MPP_8921_05
CAD NOTE: Provide separation between the 32 kHz and 19.2 MHz crystals
E14 E12
Current drivers
LED_DRV0_N LPG_DRV3/GPIO_26
C17 K4
VREF_WLAN {8} VREF_PADS_SDC
{9}
PMIC_LED_DRV0_N LS_EXP_GPIO_F
{20}
Current drivers
VIB_DRV_N
G14
PMM8920
B
B
VPH
{25} PMIC_ATC_LED_SRC
R58 120E
1
DNP R57 120E
2
LED1 GRN
PMIC_LED_DRV0_N
Project
Designed eInfochips
A
A
SD 600eval
Title PMIC CONTROL SECTION THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
Rev
Size
eInfochips#: 16_00295_02
C
Date: Friday, May 27, 2016 2
2.0
Sheet 1
26
of
31
5
4
3
2
1
PMIC GPIOs, MMPs & GND EXTERNAL BUCK REGULATOR D
D
TP6 U9E VPH {20,21} PWRBTN# R247
{6} PS_HOLD {20,21,22} RSTBTN#
0E
C16 F15 D11 B16 P13 D6
VPH
CBL_PWR0_N CBL_PWR1_N KYPD_PWR_N OPT3_8921 PS_HOLD RESIN_N
Poweron circuits
PON_RST_N_8821 PON_RST_N_8921 EXT_REG_EN2/GPIO_41 EXT_REG_EN1/GPIO_40
PMIC_PON_RST_N_8821 B4 B12 L13 M12
R179
DNP 0E CPU_RESIN#
{6}
PMIC_PM_GPIO_40
{16}
C239 1uF 10V DNP
R140 DNP
C238 10uF 10V DNP
U23 D1 D2 E1 E2
Primary PM/modem IC interface signals
SSBI_8821 SSBI_8921 INT_N_8821 INT_MDM_N_8921 INT_SEC_N_8921 INT_USR_N UIM interfaces L4
UIM1_M_CLK/GPIO_29 UIM1_CLK/GPIO_30 UIM1_DATA/MPP_8921_02 UIM1_M_DATA/MPP_8921_01 UIM1_RMV_DET_N/GPIO_36/UART_M_TX
M4 J6
{20} LS_EXP_GPIO_L
K5
{20} LS_EXP_GPIO_I
UIM1_RST/GPIO_27 UIM2_M_CLK/GPIO_31 UIM2_CLK/GPIO_32 UIM2_DATA/MPP_8921_04 UIM2_M_DATA/MPP_8921_03 UIM2_RMV_DET_N/GPIO_37/UART_M_RX UIM2_RST/GPIO_28
E2 M16 L2 P5 P12 P6
EXT_BUCK_OUT
V1P05_VREG_S3
APQ_PMIC_SSBI_8821 {6} APQ_PMIC_SSBI_8921 {6} PM2_APC_SEC_IRQ# {6} PM_MDM_IRQ# {6} PM_APC_SEC_IRQ# {6} PM_APC_USR_IRQ# {6}
VIN_1 VIN_2 VIN_3 VIN_4
VOUT
B4 B2 B3 C1 C2 C3 C4
L7 E11 D14 K11
VSEL EN SCL SDA
AGND GND_1 GND_2 GND_3 GND_4 GND_5 GND_6
0E 0E
0E
EXT_BUCK_VSEL EXT_BUCK_EN
PM_GPIO_5 PM_GPIO_20
EXT_BUCK_OUT
A4 L26
SW_1 SW_2 SW_3 SW_4
FAN53555UC08X K6 D13 E13 M11
DNP R150 R147 DNP
A1 A2 A3 B1
D3 D4 E3 E4
1
2
DNP .47uH,2.5A
DNP C234 22uF 10V
R149 200K DNP
R151 200K DNP
DNP
REGULATOR STATUS TABLE
UART multiplexing
G13 L10 K12 C
UART_RX1/GPIO_33 UART_RX2/GPIO_34 UART_RX3/GPIO_35
UART_M_RX/GPIO_38 UART_TX2/GPIO_22 UART_TX3/GPIO_23
L11 G12 K10
FORCE_USB_BOOT
SIGNAL NAME
{23}
NOTE: Optional regulator required for VDD_Core_supply according to 80-N7752-6 APQ8064 HARDWARE MIGRATION Document
PMM8920
STATUS
LOW
DISABLE
HIGH
ENABLE
LOW
1.02V
HIGH
1.15V
C
EXT_BUCK_EN
EXT_BUCK_VSEL
PMIC GPIOS/MPPS
LOGIC
PMIC GND
U9F U9G E3 F1 G1 G8 G9 G10 H10 H11 H12 H13 J2 J9 J10 J11 J12 J13 L1 N12
MPPs
M13 L14 M14 P14 P16 N16
{21} WiFi_LED {21} BT_LED
MPP_8921_07 MPP_8921_08 MPP_8921_09 MPP_8921_10 MPP_8921_11 MPP_8921_12
MPP_8821_01 MPP_8821_02 MPP_8821_03
H1 F2 E1
GPIO's
EXT_BUCK_VSEL
B
{12} PCIE_WAKE# {16} AUDIO_PORT1_DET# {21} PMIC_PM_GPIO_18
R9 A17 D12 F11
GPIO_05 GPIO_06 GPIO_07 GPIO_18
LS_EXP_GPIO_H PMIC_MPP_8821_2
DNP R29 GPIO_19 GPIO_20 GPIO_42
F12 G11 L12
0E
{20} {16}
EXT_BUCK_4V5_EN
{24}
PMIC_PM_GPIO_42
{16}
EXT_BUCK_EN
No Connect
A1 B1 B2 B3 C1 C2 G2 H2
NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8
NC9 NC10 NC11 NC12 NC13 NC14 NC15
K1 M1 M2 N2 P2 P3 R1
K9 L15 M15 P17 R17
GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18
GND_8921_DRV GND_8921_REF GND_8821_REF
B
GND_CHG GND_CHG_HP_1 GND_CHG_HP_2 GND_CHG_HP_3 GND_CHG_HP_4
G15 D7 J1
GND_8921_XO_1 GND_8921_XO_2 GND_8921_XOADC GND_8921_XOBUF
A6 E7 M6 H9
PMM8920
PMM8920
Project
Designed eInfochips
A
A
SD 600eval
Title PMIC GPIOs, MMPs & GND THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
Rev
Size
eInfochips#:
C
16_00295_02
Date: Friday, May 27, 2016 2
2.0
Sheet 1
27
of
31
5
4
3
2
1
PMM8920 SMPS
PMM8920 SMPS IP BULK CAP VPH
VPH
C381
U9B Pwr_mgmt-SMPS
R4 R5
10V V1P05_VREG_S1B {9} VREG_S1B_REMOTE_SENSE C91
DNP 0E
R216
0E
K2 A4 A5
10uF V1P05_VREG_S2B
10V
{9} VREG_S2B_REMOTE_SENSE
R42
0E
R43
D2
DNP
B9
0E
V1P225_VREG_S1 C76
D8 A11
4.7uF 10V
C78
B13
V1P3_VREG_S2
C10
4.7uF 10V
C77
B11
V1P05_VREG_S3
R11
4.7uF 10V
C296
P11
V1P8_VREG_S4
VDD_8821_S2_1 VDD_8821_S2_2 VREG_8821_S2
A13 A14
10V 10uF
VREG_8921_S1 VDD_8921_S2
{9} VREG_S5_REMOTE_SENSE
C165
R37
0E
R38
0E
GND_8921_S1 VREG_8921_S3 VDD_8921_S4 VREG_8921_S4
B15
10V
R220
{9} VREG_S6_REMOTE_SENSE 10uF
C387
0E
DNP
VDD_8921_S5_1 VDD_8921_S5_2
VREG_8921_S5
VSW_8921_S4_1 VSW_8921_S4_2
P15
VDD_8921_S6_1 VDD_8921_S6_2
P7
VSW_8921_S6_1 VSW_8921_S6_2 VSW_8921_S6_3
VREG_8921_S6
GND_8921_S6_1 GND_8921_S6_2
VDD_8921_S7
VSW_8921_S7_2 VSW_8921_S7_1
0E P9
VSW_8921_S5_1 VSW_8921_S5_2 VSW_8921_S5_3 GND_8921_S5_1 GND_8921_S5_2
10V V1P2_VREG_S7
GND_8921_S2 VSW_8921_S3_1 VSW_8921_S3_2 GND_8921_S3_1 GND_8921_S3_2
C
R227
VSW_8921_S2_1 VSW_8921_S2_2
GND_8921_S4
R13 R14
V1P05_VREG_S6
GND_8821_S2_1 GND_8821_S2_2 VSW_8921_S1_1 VSW_8921_S1_2
VDD_8921_S3
DNP
10uF
VSW_8821_S2_1 VSW_8821_S2_2 VSW_8821_S2_3
VREG_8921_S2
10V V1P05_VREG_S5
GND_8821_S1_1 GND_8821_S1_2
VDD_8921_S1
4.7uF
C84
VSW_8821_S1_1 VSW_8821_S1_2 VSW_8821_S1_3
VREG_8821_S1
VREG_8921_S7
GND_8921_S7
N3 N4 N5
V1P05_VREG_S1B
2A
1 L27
2 1uH,3.8A
C380
R2 R3 C3 C4 C5
1 L13
2 1uH,3.8A
1 L6
2 1uH,2.1A
C90
A2 A3 V1P225_VREG_S1 C9 D9
1.5A
1 L5
2 2.2uH,1.85A
C69
A12
2A
1 L4
2 0.5uH,2.3A
C68
A10 B10
1.5A
1 L30
2 2.2uH,1.85A
Pwr_mgmt-LDO
C392
R12
VPH
VDD_8921_L1_2_12_18 VDD_8921_L3_15_17 VDD_8921_L4_14 VDD_8921_L5_8_16 VDD_8921_L6_7
B
H6 A7 R208
H3
0E
VDD_8921_L9_11 VDD_8921_L10_22 VDD_8921_L21_23_29
V1P225_VREG_S1 E9 C7 M3 L9 N8
V1P2_VREG_S7
47uF 805 10V
C13 C14 C15
V1P05_VREG_S5
2A
1 L7
A15 A16
2 1uH,3.8A
C86
47uF 805 10V
N13 N14 N15
V1P05_VREG_S6
2A
C
1 L28
R15 R16 N9 M9
2 1uH,3.8A
C383
V1P2_VREG_S7
1.5A
1 L29
R10
2 1uH,2.1A
47uF 805 10V
C393
22uF 10V 603
VDD_8921_L24 VDD_8921_L25 VDD_8921_L26 VDD_8921_L27 VDD_8921_L28
VREG_8921_L5 VREG_8921_L4 VREG_8921_L3 VREG_8921_L2 VREG_8921_L1 VREG_8921_L6 VREG_8921_L7 VREG_8921_L8 VREG_8921_L9 VREG_8921_L10 VREG_8921_L11 VREG_8921_L12 VREG_8921_L14 VREG_8921_L15 VREG_8921_L16 VREG_8921_L17 VREG_8921_L18 VREG_8921_L22 VREG_8921_L23 VREG_8921_L24 VREG_8921_L25 VREG_8921_L26 VREG_8921_L27 VREG_8921_L28 VREG_XO
G5 J8 E5 D3 C6 L3 N1 G6 H4 B7 H5 D4 H15 K3 H8 G3 B14 B8 L5 F10 C8 L8 M8 R8 F6
300mA 50mA 150mA 150mA 150mA 600mA 150mA
V2P95_VREG_L5 V1P8_VREG_L4 V3P075_VREG_L3 V1P2_VREG_L2 V1P1_VREG_L1 V2P95_VREG_L6 V2P95_VREG_L7
600mA
V2P9_VREG_L10
150mA
V1P8_VREG_L15
V1P1_VREG_L1 V1P2_VREG_L2 V3P075_VREG_L3 V1P8_VREG_L4 V2P95_VREG_L5 V2P95_VREG_L6 V2P95_VREG_L7
C272
2.2uF 10V
C287
1uF
10V
C320
1uF
10V
C391
1uF
10V
V2P9_VREG_L10
C299
1uF
10V
V1P8_VREG_L15
C389
1uF
10V
V1P8_VREG_L23 V1P05_VREG_L24 V1P2_VREG_L25
C123
1uF
150mA 1.2A 1.2A 1.2A 1.2A
V1P35_VREG_L18
10V
C254
4.7uF 10V
V1P8_VREG_L23 V1P05_VREG_L24 V1P2_VREG_L25 V1P05_VREG_L26 V1P2_VREG_L27
V1P8_VREG_TCXO
C288
1uF
1uF
10V
C390
1uF
10V
CAD NOTE: Place these caps close to PMM8920
C282
4.7uF 10V
C316
4.7uF 10V
MH1 2.5mm
MH2 2.5mm
MH3 2.5mm
MH4 2.5mm
MH5 2.5mm
MH6 2.5mm
10V 1 C343
V1P8_VREG_LVS3 V1P8_VREG_TCXO
2.2uF 10V
C341
B
V1P35_VREG_L18 150mA
C300
V1P8_VREG_LVS6
C163
1uF
10V
V1P2_VREG_LVS2
C342
1uF
10V
V1P8_VREG_LVS7
C161
1uF
10V
V5P0_VREG_HDMI
C312
1uF
10V
V1P05_VREG_L26
C365
4.7uF 10V
V1P2_VREG_L27
C378
4.7uF 10V
1uF
1
1
1
1
1
10V 1
J3 G7 G4 P1
47uF 805 10V
V1P8_VREG_S4 N10 N11
CAD NOTE:All SMPS GNDs should be routed individually to the main GND plane.
47uF 805 10V
V1P05_VREG_S3 D10 E10
D
22uF 10V 603
V1P3_VREG_S2
1.5A
805 10V
C72
A9 C11 C12
47uF
PMM8920 LDO
U9C
E8
CAD NOTE: Place these caps close to 8920, Then input cap and inductor
V1P05_VREG_S2B
1.5A
PMM8920
V1P8_VREG_S4
47uF 805 10V
1
D
R219
VDD_8821_S1_1 VDD_8821_S1_2
1
C65 22uF 10V 603
1
C243 22uF 10V 603
1
C278 22uF 10V 603
1
C251 22uF 10V 603
10uF
Pwr_mgmt-LVS
R6
V1P8_VREG_S4
H7
V1P225_VREG_S1
R7 E4
V1P8_VREG_S4 V5_USB_OUT_DCIN C309 0.1uF 10V
VIN_8921_LVS1_3_6 VIN_8921_LVS2 VIN_8921_LVS4_5_7 VIN_5VS
VOUT_8921_LVS1 VOUT_8921_LVS3 VOUT_8921_LVS6 VOUT_8921_LVS2 VOUT_8921_LVS4 VOUT_8921_LVS5 VOUT_8921_LVS7 VOUT_5VS_OTG VOUT_5VS_HDM
N7 L6 N6 K8 M5 M7 P8 A8 D5
100mA 300mA 300mA
100mA 500mA 500mA
V1P8_VREG_LVS3 V1P8_VREG_LVS6 V1P2_VREG_LVS2 V1P8_VREG_LVS7 V5P0_VREG_OTG V5P0_VREG_HDMI
PMM8920
V1P2_VREG_L27
V1P05_VREG_S3
Project
Designed eInfochips
A
R167
0E
A
SD 600eval
Title PMM8920 SMPS/LDO THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
Rev
Size
eInfochips#: 16_00295_02
C
Date: 2
Friday, May 27, 2016
2.0
Sheet 1
28
of
31
5
4
3
2
1
REVISION HISTORY PCB REV D
SCH REV
CHANGE DESCRIPTION
AUTHOR
DATE
0.1
Intial draft schematic released for Arrow review
10/08/2015
eINFOCHIPS
0.2
Implemented following Suggestion and comments given by Lawrence on 11 AUG 2015 1. Removed Ferrite beads on all processor power supplies added sense resistor only on SYS_DC_IN and VPH power as per NT276 schematic 2. Removed FB3 and added capacitor on FB1(VCC3V3 power rail) in Ethernet section 3. changed 100nf capacitors(C253,C254) in GPS Anteena section as DNP(do not populate) instead mounting 3. changed 100nf capacitors(C253,C254) in GPS Anteena section as DNP(do not populate) instead 4. Added a CAD note for R106 and R109 in GPS section to remove the stubs in the layout 5. Changed the WCD9311 audio codec part to WCD9310 to save board space 6. Changed the Audio expansion connector to two separate connectors in order to match 410C mezanine expansion boards 7. Added Codec mic_in6, line_out5, dmic_d1 and dmic_clk1 ,MBHC signal ,codec earo_n and earo_p signals on expansion header 8. Added Separate buck regullator for VPH power supply to avoid high current loads when processor running in peak core frequencies 9. Added thermistor on battery connector and implemented a circuit to monitor battery capacity by BMS 10. Change the D5 revece protection diode part to 10 Amps instead of 3Amps to protect the fuse on input power supply 11.Removed one set of resistors on USB hub I2C line 12.changed nets OSC_n1 and OSC_n2,to OCS_n1 and OCS_n2.
17/08/2015
eINFOCHIPS
D
1.0
C
0.3
B
0.4
0.5
C
1. Micro SD Connector Part number is changed to 101-00660-68-6 2. Magnetics and ethernet jack replaced with magnetic jack (ARJ11E-MCSA-A-B-EM2) 3. GPS Antenna Part number is chnged to ACA-104-T 4. Crystal X1 part number is changed to ABM10-27.000MHZ-12-R60-4-N50-T 5. Added Sheild for RF and Digital Section 6. Removed SATA 22 Pin Connector 7. Added SATA Data connector (0470804005) 8. Added SATA Power connector (770997-1) 9. Crystal X3 part number is changed to ABS07-32.768kHz-T 10. Coaxial connector J19 part number is changed to MM8430-2610RA1
07/09/2015
1. 30 pin audio connector part number is changed to DF17(2.0)-30DP-0.5V(57) 2. 16 pin audio connector part number is changed to 55510-116LF 3. 3 pin battery connector part number is changed to 0781710003 4. Removed debug section & added debug UART signals to low speed expansion connector 5. 20 pin JTAG connector part number is changed to DF12C(3.0)-20DS-0.5V(81) 6. Removed SW4 section 7. Added EEPROM section 1. Added MOSFET Q7 to control buck regulator U42
14/09/2015
eINFOCHIPS
16/09/2015
eINFOCHIPS
eINFOCHIPS
B
Project
Designed eInfochips
A
A
SD 600eval
Title REVISION HISTORY
Rev
Size THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
eInfochips#: 16_00295_02
C
Date: 2
Friday, May 27, 2016
2.0
Sheet 1
29
of
31
5
4
3
2
1
REVISION HISTORY PCB REV
SCH REV
D
1.0
0.6
C
0.7
0.8
1.0 2.0
B
1.1
CHANGE DESCRIPTION
AUTHOR
DATE
1. PCIE clock generator part no. is changed to Si52144 2. Micro SD card part no. is changed to 2201778-1 3. HDMI connector part no. is changed to 1903015-1 4. USB type A connector part no. is changed to 292303-5 5. USB micro AB connector part no is changed to 1981584-1 6. 60 pin high speed expansion connector part no is changed to 5177983-2 7. 40 pin low speed connector part no is change to 9-1734516-0 8. 4 posistion dip switch part no. is changed to 1571983-4 9. SATA connector part no. is changed to 1735418-1 10. 3 pin battery connector part no. is changed to 87233-3 11. UFL connector part no. is changed to 1757254-1 12. JTAG connector part no. is changed to 5-104655-3 13. 30 pin Audio expansion connector part no. is changed to 5177983-1
24/09/2015
1. Added alternate part no.for resistors,capacitors and inductors 2. Removed Battery protection circuitry 3. ST Microelectronics part added as per costomer feedback
07/10/2015
eINFOCHIPS
1. ST Microelectronics part added as per costomer feedback for sensors 2. Slimline SATA connector part no. is changed to 1735471-3 3. Alternate part number ( ABM10-27.000MHZ-D30-T) is added for 27MHz crystal
26/10/2015
eINFOCHIPS
19/11/2015
eINFOCHIPS
07/03/2016
eINFOCHIPS
eINFOCHIPS
D
C
Released For Fabrication and Baselined
1. SATA RX and TX lines are swapped 2. Connector J7 and J8 part no. is changed to U.FL-R-SMT-1(01) 3. R71 changed to 300K and mounting status changed to DNP 4. R298 is added and U15 mounting status is changed to DNP 5. R299 is added to bypass the load switch 6. R78 value changed to 124K and D6 part no. is changed to ES3AB-13-F 7. Connector J7 and J8 part no. is changed to 1909763-1instaed of U.FL-R-SMT-1(01) 8. LNA circuitry added in GPS section 9. Connector J5 footprint name is changed to MOLEX_0791091014 10. R302,R303 are added in GPS section 11. C70 replaced with 22 nH inductor ,12. L10 replaced with 1.2pF Capacitor and L9 replaced with 0 ohm resistor 12. In GPS and WiFi tuning circuit components parts changed with RF grade parts
Project
B
Designed eInfochips
A
A
SD 600eval
Title REVISION HISTORY
Rev
Size THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
eInfochips#: 16_00295_02
C
Date: 2
Friday, May 27, 2016
2.0
Sheet 1
30
of
31
5
4
3
2
1
REVISION HISTORY PCB REV
SCH REV
CHANGE DESCRIPTION
AUTHOR
DATE 16/03/2016
D
2.0
2.0
1.1
2.0
13. R30, R31 and R32 replaced with 1.1nH (L36,L37 and L38) inductor respectively 14. C282 value changed to 4.7uF 15. Added C608, C609 and C610 in GPS power section 16. V1P35_VREG_L18 power rail is connected to GPS 1.3V supply and V1P3_VREG_S2 is used as optional power supply for it 17. R190 mounting status changed to polulated and R184 mounting status changed to DNP 18. R304 replaced with 1.0nH (L39) inductor 19. Added L41 in GPS section 20. GPS LNA Section and Internal Antenna Section marked as DNP. External Antenna Section updated as Mounting.
eINFOCHIPS
D
25/03/2016 27/03/2016
1. Released For Fabrication and Baselined
eINFOCHIPS
C
C
B
B
Project
Designed eInfochips
A
A
SD 600eval
Title REVISION HISTORY
Rev
Size THE CONTENTS OF THIS DOCUMENT ARE PROPRIETARY TO EINFOCHIPS. ANY CONTENTS OF THIS DOCUMENT SHALL NOT BE DISCLOSED, DISSEMINATED, COPIED OR USED EXCEPT FOR PURPOSES EXPRESSLY AUTHORIZED IN WRITING BY EINFOCHIPS. Copyrights 2015 eInfochips Ltd. All Rights Reserved. 5
4
3
eInfochips#: 16_00295_02
C
Date: 2
Friday, May 27, 2016
2.0
Sheet 1
31
of
31
