Transcript
88SE9480/88SE9485 R3.3 Eight-Lane PCI-Express 2.0 to Eight-Port SAS/SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
Doc No. MV-S105606-00 Rev. J April 23, 2015
Document Classification: Proprietary Marvell. Moving Forward Faster
88SE9480/88SE9485 R3.3 Eight-Lane PCI-Express 2.0 to Eight-Port SAS/SATA 6 Gbps RAID I/O Controller
For more information, visit our website at: www.marvell.com
No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use Marvell products in these types of equipment or applications. With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees: 1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control Regulations ("EAR"), to a national of EAR Country Groups D:1 or E:2; 2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are controlled for national security reasons by the EAR; and, 3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant, not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons by the EAR, or is subject to controls under the U.S. Munitions List ("USML"). At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information. Copyright © 1999–2015. Marvell International Ltd. All rights reserved. Alaska, ARMADA, Avanta, Avastar, CarrierSpan, Kinoma, Link Street, LinkCrypt, Marvell logo, Marvell, Moving Forward Faster, Marvell Smart, PISC, Prestera, Qdeo, QDEO logo, QuietVideo, Virtual Cable Tester, The World as YOU See It, Vmeta, Xelerated, and Yukon are registered trademarks of Marvell or its affiliates. G.now, HyperDuo, Kirkwood, and Wirespeed by Design are trademarks of Marvell or its affiliates. Patent(s) Pending—Products identified in this document may be covered by one or more Marvell patents and/or patent applications.
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Ordering Information
ORDERING INFORMATION Ordering Part Numbers and Package Markings The following figure shows the ordering part numbering scheme for the 88SE9480/88SE9485 part. For complete ordering information, contact your Marvell FAE or sales representative. Sample Ordering Part Number
88XXXXX - XX - XXX - C000 - XXXX Part Number
Custom Code (optional )
Extended Part Number
Custom Code
Product Revision Temperature Code C = Commercial I = Industrial
Custom Code Package Code
Environmental Code
3-character alphabetic code such as BCC, TEH
+ = RoHS 0/6 – = RoHS 5/6 1 = RoHS 6/6 2 = Green)
The standard ordering part numbers for the respective solutions are indicated in the following table. Ordering Part Numbers Part Number
Description
88SE9480C3-BJA2C000 88SE9485C3-BJA2C000
484-Ball HSBGA 23 × 23 mm 484-Ball HSBGA 23 × 23 mm This product does not support Marvell RAID stack.
The next figure shows a typical Marvell package marking. 88SE9480/88SE9485 Package Marking and Pin 1 Location Marvell Logo Country of origin (contained in the mold ID or marked as the last line on the package)
Pin 1 location
88XXXXX-AAAe Lot Number YYWW xx@ Country of Origin
Part number, package code, environmental code e XXXXX = Part number AAA = Package code e = Environmental code (+ = RoHS 0/6, no code = RoHS 5/6, 1 = RoHS 6/6, 2 = Green) Date code, custom code, assembly plant code YYWW = Date code (YY = year, WW = Work Week) xx = Custom code or die revision @ = Assembly plant code
iii Copyright © 2015 Marvell April 23, 2015
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88SE9480/88SE9485 R3.3 Eight-Lane PCI-Express 2.0 to Eight-Port SAS/SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
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Change History
CHANGE HISTORY The following table identifies the document change history for Rev. J. Document Changes * Location
Type
Description
Date
Page 1-1
Update
Updated the description for chapter 1, Overview:
December 8, 2014
from The 88SE9480/88SE9485 is an eight-port, 6.0 Gbps SAS/SATA controller that provides a one- four-, or eight-lane PCIe 2.0 host interface, and supports advanced RAID topologies. The 88SE9xx5 is similar to the 88SE9xx0, but does not support the Marvell RAID stack. to The 88SE9480/88SE9485 is an eight-port, 6.0 Gbps SAS/SATA controller that provides a one-, two-, four-, or eight-lane PCIe 2.0 host interface, and supports advanced RAID topologies. The 88SE9xx5 is similar to the 88SE9xx0, but does not support the Marvell RAID stack. Page 2-2
Update
Updated the description for section 2.1, General.
December 5, 2014
Page 3-5
Update
Updated Table 3-1, Signal Type Definitions.
December 8, 2014
Page 3-8
Update
Updated the description for PIN_TEST[9:8] in Table 3-2, General Purpose I/O Signals:
January 14, 2015
from PIN_TEST[9:8]–PCIe maximum lane width 0h: 1h: 2h: 3h: to
x8 x1 x4 x8
PIN_TEST[9:8]–PCIe maximum lane width 0h:
x8
Note: Always use 0h.
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88SE9480/88SE9485 R3.3 Eight-Lane PCI-Express 2.0 to Eight-Port SAS/SATA 6 Gbps RAID I/O Controller
Document Changes * (continued) Location
Type
Description
Date
Page 4-3
Update
Updated the following schematics for section 4.1, 88SE9480/88SE9485 Board Schematics:
June 27, 2014
Page 4-4
• Figure 4-1, 88SE9480/88SE9485 PCIe and SAS • Figure 4-2, 88SE9480/88SE9485 Bootstrap, NI, SPI, UART, I2C, LED • Figure 4-3, 88SE9480/88E9485 Power and Ground • Figure 4-4, 88SE9480/88SE9485 Power Regulators
Page 4-5 page 4-6
Page 5-4
Parameter Updated Table 5-3, DC Electrical Characteristics:
December 18, 2014
• Corrected the Maximum value of Input Low Voltage of Digital I/O from 0.8 to 0.3 × VDDOx. • Corrected the Minimum value of Input High Voltage of Digital I/O from 2.0 to 0.7 × VDDOx. • Corrected the Maximum value of Input High Voltage of Digital I/O from 3.6 to VDDOx + 0.4. • Corrected the Typical value of Output High Voltage of Digital I/O from VDDO1/VDDO2 to VDDOx. * The type of change is categorized as: Parameter, Revision, or Update. A Parameter change is a change to a spec value, a Revision change is one that originates from the chip Revision Notice, and an Update change includes all other document updates.
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Contents
CONTENTS 1
OVERVIEW ........................................................................................................................................................ 1-1
2
FEATURES ........................................................................................................................................................ 2.1 GENERAL .................................................................................................................................................. 2.2 PCIE ......................................................................................................................................................... 2.3 SAS (DIRECT ATTACH OR EXPANDER) ....................................................................................................... 2.4 SATA (DIRECT ATTACH) ............................................................................................................................ 2.5 XOR ENGINE ............................................................................................................................................ 2.6 PERIPHERALS ............................................................................................................................................
2-1 2-2 2-3 2-4 2-5 2-6 2-7
3
PACKAGE ......................................................................................................................................................... 3.1 BALL DIAGRAM .......................................................................................................................................... 3.2 MECHANICAL DIMENSIONS ......................................................................................................................... 3.3 SIGNAL DESCRIPTIONS ............................................................................................................................... 3.3.1 Signal Definitions ...................................................................................................................... 3.3.2 Signal Descriptions ...................................................................................................................
3-1 3-2 3-3 3-5 3-5 3-6
4
LAYOUT GUIDELINES ...................................................................................................................................... 4-1 4.1 88SE9480/88SE9485 BOARD SCHEMATICS .............................................................................................. 4-2 4.2 LAYER STACK-UP ...................................................................................................................................... 4-8 4.2.1 Layer 1–Topside, Parts, Low and High-Speed Signal Routes, and Power Routes ................... 4-8 4.2.2 Layer 2–Solid Ground Plane ..................................................................................................... 4-8 4.2.3 Layer 3–Power Plane and Low Speed Signals ......................................................................... 4-8 4.2.4 Layer 4–Power Plane ................................................................................................................ 4-8 4.2.5 Layer 5–Solid Ground Plane ..................................................................................................... 4-8 4.2.6 Layer 6–Bottom Layer, Low and High-Speed Signal Routes, and Power Routes .................... 4-9 4.3 POWER SUPPLY ...................................................................................................................................... 4-10 4.3.1 VDD Power (1.0V) ................................................................................................................... 4-10 4.3.2 PCIe Analog Power Supply (1.8V) .......................................................................................... 4-10 4.3.3 SAS/SATA Analog Power Supply (2.5V) ................................................................................ 4-10 4.3.4 General I/O Power (3.3V) ........................................................................................................ 4-10 4.3.5 Bias Current Resistor (RSET) ................................................................................................. 4-11 4.4 PCB TRACE ROUTING ............................................................................................................................. 4-12 4.5 RECOMMENDED LAYOUT .......................................................................................................................... 4-13
5
ELECTRICAL SPECIFICATIONS ...................................................................................................................... 5.1 ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 5.2 RECOMMENDED OPERATING CONDITIONS ................................................................................................... 5.3 DC ELECTRICAL CHARACTERISTICS ........................................................................................................... 5.4 THERMAL DATA ......................................................................................................................................... 5.5 AC TIMING ................................................................................................................................................ 5.5.1 SATA ......................................................................................................................................... 5.5.2 PCIe .......................................................................................................................................... 5.5.3 Parallel Flash and NVSRAM .....................................................................................................
5-1 5-2 5-3 5-4 5-5 5-6 5-6 5-6 5-6
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88SE9480/88SE9485 R3.3 Eight-Lane PCI-Express 2.0 to Eight-Port SAS/SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
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Part 1: Chip Overview Overview
1
OVERVIEW The 88SE9480/88SE9485 is an eight-port, 6.0 Gbps SAS/SATA controller that provides a one-, two-, four-, or eight-lane PCIe 2.0 host interface, and supports advanced RAID topologies. The 88SE9xx5 is similar to the 88SE9xx0, but does not support the Marvell RAID stack. The 88SE9480/88SE9485 controller brings a high-performance, low-cost 6.0 Gbps per port combined SAS and SATA solution to HBA, workstation, and server designs utilizing a one-, four-, or eight-lane PCIe 2.0 interface. The 88SE9480/88SE9485 integrates eight high-performance SAS/SATA PHYs and a self-configuring eight-lane PCIe core. Each of the eight PHYs is capable of 1.5 Gbps, 3.0 Gbps, and 6.0 Gbps SAS and SATA link rates. The 88SE9480/88SE9485 supports ANSI Serial Attached SCSI - 2.0 (SAS-2.0). The controller also supports the SATA protocol defined in the Serial ATA, Revision 3.0 Specification. Figure 1-1 shows the system block diagram. Figure 1-1 88SE9480/88SE9485 (8-port) Block
Config, Interrupts , and Timers GPPs, UART, and TWSI
AHB Bus
XOR x2
PBSRAM
MXI Bus
FLASH NVSRAM PCIExpress x8
SAS / SATA x4
SAS / SATA x4
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Part 1: Chip Overview Features
2
FEATURES The chapter contains the following sections:
General
PCIe
SAS (Direct Attach or Expander)
SATA (Direct Attach)
XOR Engine
Peripherals
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88SE9480/88SE9485 R3.3 Eight-Lane PCI-Express 2.0 to Eight-Port SAS/SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
2.1
General
Eight 6 Gbps SAS/SATA ports.
Choice of x1, x2, x4, or x8 lane PCIe 2.0 host interface.
Supports three Serial Device Bus (I2C) controllers for communicating with hardware monitoring ICs.
Supports two industry standard 57600 UARTs.
Supports two SFF-8485 compliant SGPIO ports.
Supports autodetection of SAS or native SATA device.
Up to 4096 concurrent I/O operations (2048 per 4 ports).
Up to 128 concurrent SATA Devices (64 per 4 ports).
No hardware limit on the number of SAS devices supported.
55 nm CMOS process, 1.0V digital core, 2.5V analog power supply, and 3.3V I/O supply.
Estimated power (8-port): 6W.1
Up to 34 LED/GPIO ports.
Supports hardware RAID 5 and RAID 6 acceleration.
Supports Data Path Parity Protection (DPP).
1.
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2.2
PCIe
Supports x1, x2, x4, or x8 lane PCIe 2.0 Interface (5.0 Gbps).
Supports four fully independent PCIe functions.
Supports independent interrupt mechanisms for each PCIe function.
Supports Message Signal Interrupts (MSI).
All registers memory mapped.
Supports PCIe Power Management: D0, D1, D3COLD, D3HOT.
PCIe Copyright © 2015 Marvell April 23, 2015
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2.3
SAS (Direct Attach or Expander)
Serial Attached SCSI (SAS-2.0) compliant.
Supports 6 Gbps, 3 Gbps, and 1.5 Gbps devices.
Supports SAS Multiplexing. Up to 16 logical ports when multiplexing is enabled on all PHYs.
Supports SSC, with independent control for each PHY using SSC_EN (R060h [17]).
Supports wide SAS ports. Up to four wide when multiplexing is disabled, and up to eight wide when multiplexing is enabled.
Supports Serial SCSI Protocol (SSP), initiator and target mode.
Supports SAS Management Protocol (SMP), initiator mode.
Supports Serial ATA Tunneling Protocol (STP), initiator mode.
Non-zero offset and non-sequential data delivery.
ATA and ATAPI commands.
Native Command Queuing (NCQ).
Supports T10 Protection Information Model. DIF fields can be inserted, checked, replaced, and/or removed.
Supports Transport Layer Retries.
Supports hardware assisted Scatter-Gather.
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Part 1: Chip Overview Features
2.4
SATA (Direct Attach)
Serial ATA Revision 3.0 (6 Gbps) compliant, with speed negotiation to 3.0 Gbps and 1.5 Gbps.
Supports programmable SATA signaling levels, including Gen1x, Gen2i, and Gen2x.
Supports ATA and ATAPI commands.
Supports Native Command Queuing (NCQ).
Non-zero offset and non-sequential data delivery.
32 outstanding commands per device.
Supports Port Multiplier.
FIS based Switching on NCQ and legacy commands.
Supports Host mode and Device mode of operation.
Supports hardware assisted Scatter-Gather.
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2.5
XOR Engine
Supports Advanced RAID features including:
Dual XOR RAID 6.
P + Q + Copy, or Q + Q + Q RAID 6.
Memory Block Fill.
Zero Result Check.
Generates up to 3 checksums concurrently, including any combination of P and Q.
Independent GF Multiply coefficient for each of 3 concurrent Q checksum calculations.
Supports rebuilding three failed drives simultaneously with a single read of remaining good drives.
Supports chained XOR Descriptor Tables, with up to 32 operations in each table.
Supports Scatter-Gather transfers using a common PRD format.
Supports CRC32 checksum generation and checking.
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Part 1: Chip Overview Features
2.6
Peripherals
Supports up to 4 MB of external NVSRAM memory (x8/x16).
Supports up to 4 MB of external PBSRAM memory (x32).
Supports up to 8 MB of external Parallel Flash memory (x8/x16).
Supports up to 16 MB of external SPI Flash memory.
Peripherals Copyright © 2015 Marvell April 23, 2015
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Part 1: Chip Overview Package
3
PACKAGE This chapter contains the following sections:
Ball Diagram
Mechanical Dimensions
Signal Descriptions
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88SE9480/88SE9485 R3.3 Eight-Lane PCI-Express 2.0 to Eight-Port SAS/SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
3.1
Ball Diagram The 484-pin HSBGA ball diagram is illustrated in Figure 3-1. Figure 3-1 Ball Diagram
A B C D E F G H J K L M N P R T U V W Y AA AB
1
2
3
4
5
6
7
8
9
S VS
S VS
S VS
[ 7] XN PR
S VS
[ 6] XN PR
S VS
[ 5] XN PR
S VS
10 XP PT
[4]
11 S VS
12
F RE
13
14
KN S CL VS
XP PR
[ 3]
15
16
S VS
XP PR
[ 2]
17
18
S VS
XP PR
[ 1]
19 S VS
20
X PT
] N[0
21
22
S VS
S VS
P [ 3] [ 2] [ 1] [ 6] [4 ] [0] [ 7] [ 5] LK S S S S S S S S S S S S XN XP XN XN XN FC VS VS PRXP VS PRXP VS PRXP VS VS VS VS VS VS VS VS PT PT PR PR PR RE ] N 7 ] _ ] 1 N 4 T [ _ [ 11 [1 4] TA SE _WE [ 0] [7] [6] [2 ] [5] [3] [1 ] ST S S S S S S S S S ST N[ RE DA XP XP XP XP XN XN VS VS VS VS VS VS VS VS PRXP VS RX _TE IN_TE _N F_ P_ PT PT PT PT PT PT _ P N IN _ I P P PI N PIN 2 0] P 3 4] 2] [8 ] _N A[ A[ T[ 1 [ 0] [ 4] [7 ] [6 ] [2] [1] [5 ] [3 ] ST AT AT CE S S S S S S S S S XN XN XN XN XP XP ES XN _D _D F_ VS VS VS VS PRXP VS VS VS VS VS T T T T T T T _ _T E R _ P P P P P P P P _ _ P IN IN IN N N P P I P I ] P P 2 3] ] ] [ [1 9 DY [4 ] T [ 13 ST [9 E_N S ] -2 TA TA EA ST S S S S S P S S S S S ST I SE VSS _C D[8 E DA DA _R VS VS VS VS VS VS PT VS VS VS VS VS _T E _N IN_ _TE IN_T P_ P_ VD _F N N _ _ P I I IN A N I P P P PI N PI N 2 7] P 2 2] P 1 6] ] N ] ] [ [ [ [0 ] _N _0 E_ [ 15 -2 -1 -1 -1 -2 -1 [ 10 ST [5 2 TA TA TA ST 25 [8] OE YT ST [8] [8] [8] [8] [8] S S S S S ST [ 8] DA DA DA _B VS VS VS VS VS TE DD DD DD DD DD DD DD _T E N_T E TE _F_ DD _ F _ P_ P_ P_ V V V V V V V _ V N _ _ N _ I I I IN IN A A A A A A A A N I N N P P P N I I I P P ] ] ] P P P 28 P 26 1 [6 ] _N _N [3 ] A[ A[ A[2 [8] ] -2 ] -1 ] -2 ] -2 ] -2 ] -1 ] -1 ] -1 5 _1 ST ST OE AT AT LT S S S S S WE AT D[8 D[8 D[8 D[8 D[8 D[8 D[8 D[8 D2 TE _D _D T E IN _F N_ _D VS VS VS VS VS F_ VD VD VD VD VD VD VD VD VD N_ N_ N_ _P _P N_ _P I I I I A A A A A A A A A P N N P P P P N ] ] PI PI 3 1] PI 2 9] ] ] [2 5 [1 8 2 [ [ [7] [4] T [1 T [7 1 TA TA TA TA D D S S D D D D D D D LT LT DO _T ES _T ES DO VDD DA DA DA DA VS VS _F _F VD VD VD VD VD VD VD VD VD N P_ P_ I P_ P_ VD VD _ _ N _ _ N P PIN PI PI ] PI N PI N [3 ] PI N 3 5] PI N 3 0] 4 ] R A[ A[2 A[ [6] [2] T [2 1 2 AT AT AT S S S S S S S S S S S DD D LT LT DO _T ES DO VDD _D _D _A _D VS VS VS VS VS VS VS VS VS VS VS _F _F VD VD VD _P _P _P _P IN PIN PIN N N N I N P I I I P P [1 ] P [2 ] P [4 ] [5 ] [1] [0] [3] [5] 1 2 DR DR DR DR LT LT S S S S S S S S D S S LT LT AD AD AD AD DO DO VDD VS VS VS VS VS VS VS VS VS VS _F _F _F _F VD P_ P_ P_ P_ VD VD _ _ _ _ PIN PIN PIN PIN PI N PI N 7] PI N 8] PI N 9] ] ] ] ] ] R[0 R[ 1 R[ 1 R[ 1 1 2 T[ 6 T[ 7 T[ 5 T[ 8 DD S S S S S S S S D S S DD DD DD DO DO VDD _A _AC N_AC N_AC N_AC VS VS VS VS VS VS VS VS VS VS _A _A _A VD VD VD IN I I _P I _P _P _P P P P P N N N I N I I I ] P P 10] P 11] P 12] ] ] ] [ [ [ [ 14 1 T[ 1 T[ 3 T[ 4 DR DR DR DR DO2 S S S S S S S S S D D S S DO AC AD AD AD AD AC AC VS VS VS VS VS VS VS VS VS VS VS VD VD N_ N_ VD VD P_ P_ N_ P_ P_ I I I _ _ _ _ P P P PIN PIN 13] PIN 15] PIN 3 2] ] [ 4] ] A[ R[ R[ [ 0] [ 2] TA 1 2 T[ 2 T[ 0 CL CL S S S S S S S S S S D DD DD _DAT _DA DO DO VDD _S _S VS VS VS VS VS VS VS VS VS VS _AC N_AC _A _A VD P P P P VD VD _ _ _ _ PI N PI N PI N PI N N N I N I I I ] ] P P P 16 P [ 0] 0 [ 3] ] ] [ ] A A[1 [ 1] TA 1 2 I[ 1 A[ 1 A[ 2 DR DAT AT S S S S S S S S S S CL D DA UA DO DO VDD AD SD _D VS VS VS VS VS VS VS VS VS VS _SD N_S VD P_ _P_ I N_ PI N_ VD VD _P_ _P I IN P _ N P P N N I I N P 1] P 5] PI 8] PI 5] N [ [ [ N ] ] S_ A[1 TA TA TA W_ I[ 0 A[ 0 AT O1 D D S S S D D D D D D D D I_C DA DA DA _G UA _D VS VS VS _SD SP DD VD VD VD VD VD VD VD VD VD VD P_ P_ P_ _P N_ _ P I _ V _ _ N _ I P N I PI N ] PI N PI N 2] PI N 7] PI N 3] P N P ] 0 I [ [ ] O R[7 C_ LK A A[1 R[ 2 TA TA I _D O [1 -3] -7] -7] -7] -3] -3] -3] -7] I _D DD ADD DS AT AN FC S S S DA DA A[ 0 A[ 0 A[ 0 A[ 4 A[ 4 A[ 4 A[ 4 A[ 0 _A _A _D SP A_ VS VS VS RE _SP N_UA _ _P_ _P_ I _P _P IN IN_ VA VA VA VA VA VA VA VA _P IN _ VA _P P P N N N N I I I I N P P N I I ] ] P 9] P 3] P 6] P P 6] P ] [ [ [ ] [ 21 K [1 1 N[ TA G [1 DR DDR DR O [0 TA E_ CL S S S S S S S S S S T S S DA AD N F _UA A M_ DA P_AD P_W VS VS VS VS VS VS VS VS VS VS VS VS I SE P_ _C _P_ P_ N_ N P_ _ _ _ I I N _ I _ N N N N P P P PI PI N [ 9] PI 1 4] PI N PI N PIN _ _ LK [0] A[ TA DV S1 FG TP AT S S S S S S S S S S S S S S S I_C DA _A _P_C N_ _D VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS SP CN P I P_ P _ P _ _ IN _ I N_ IN IN N P P P P I ] PI N ] P 12 [8 ] ] A ] ] ] ] ] ] [ _N N[1 2] AT DR TA P[ 0 P[ 3 P[ 5 P[ 7 P[ 1 P[ 4 P[ 6 ET E_ N[ S S S S S S S S S _D DA P_AD P_W ES RX TX TX TX RX TX TX TX VS VS VS VS VS VS VS VS VS _M P_ _R N_ N_ N_ N_ N_ N_ N_ N_ _ _ I I I I I I I I _ N I N I N N P P P P P P P P P P PI 3] PI LK PI N N [2 ] ] [3 5] 3] 6] 7] T_ 4] _C [ 1] [ 0] _N TA P[ 2 N[ N[ N[ N[ N[ SE S S S S S S S S U T _WE XN VSS XN VSS DA RE _TX _TX VS VS VS VS VS VS VS VS _TX _TX _TX _TX _O _R _R P P P P_ N N N N N N N N _ I I I I I I I _ _ I _ P P P P P P P P PI N 0 ] PI N PI N PIN ] ] ] ] ] ] N[ 1] _N 0] P[ 2 N[ 4 N[ 3 N[ 6 N[ 7 N[ 5 E_ N[ N[ OE S S SS SS SS SS SS SS SS SS SS SS TX TX RX RX RX RX RX RX _W P_ VS V V V V V V V V V V VS _ _ _ _ _ _ _ _ P _ _ PI N PI N PI N PIN PIN PIN PIN PIN PI N PI N N ] ] ] ] ] ] ] ] [4 [5 [7 [3 [6 [2 W_ P[ 0 P[ 1 XP XP XP S S S S S S S S S S S S XP XP XN VSS _B _R _R _R _TX _R _TX VS VS VS VS VS VS VS VS VS VS VS VS _R _R _P PI N PI N PIN PI N PI N PI N PI N PI N PIN S VS
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Part 1: Chip Overview Package
3.2
Mechanical Dimensions The package mechanical drawing is shown in Figure 3-2 and the mechanical dimensions are shown in Figure 3-3. Figure 3-2 Package Mechanical Drawing (BJA)
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Figure 3-3 Package Mechanical Dimensions (BJA)
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Part 1: Chip Overview Package
3.3
Signal Descriptions This section includes information on signal definitions and descriptions:
3.3.1
Signal Definitions
Signal Descriptions
Signal Definitions Signal type definitions are shown in Table 3-1. Table 3-1 Signal Type Definitions Signal Type Definition I/O
Input and output
I
Input only
O
Output only
OC
Open Collector
OD
Open-Drain pad
Ground
Ground
Power
Power
NC
No Connect*
DNC
Do Not Connect†
N/A
Not Applicable
* Pin is floating and is not connected internally to any active circuitry nor has any electrical continuity to any other pin † Device pin to which there may or may not be an internal connection, but to which no external connections are allowed.
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3.3.2
Signal Descriptions This section outlines the 88SE9480/88SE9485 signal descriptions. Signals ending with the letter “N” are active-low signals. Table 3-2 General Purpose I/O Signals Signal Name
Signal Number
Type
Description
PIN_ACT[8]
L22
I/O, OC
Activity LED.
PIN_ACT[7]
L19
Active low.
PIN_ACT[6]
L20
PIN_ACT[5]
L21
PIN_ACT is active when SAS/SATA PHY is transmitting or receiving.
PIN_ACT[4]
M22
These pins can be used as GPIO.
PIN_ACT[3]
M20
PIN_ACT[7:0]–SAS/SATA PHY[7:0] activity.
PIN_ACT[2]
N22
PIN_ACT[1]
M19
PIN_ACT[0]
N21
PIN_ACT[8]–Global Activity. Enabled when any
SAS/SATA PHY is active.
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Table 3-2 General Purpose I/O Signals (continued) Signal Name
Signal Number
Type
Description
PIN_FLT[8]
G22
I/O, OC
Fault LED.
PIN_FLT[7]
H21
Active low signals.
PIN_FLT[6]
J20
PIN_FLT[5]
K19
PIN_FLT[4]
H22
PIN_FLT is active when PHY is not ready or when PHY is ready and there is any PHY related error or connection error.
PIN_FLT[3]
K20
PIN_FLT[2]
J22
These pins can be used as GPIO, SGPIO, I2C, or FLT_LED. See GPIO_FLT_CFG (R10080h [7:0]) and I2C_SGPIO_FLT_PAD_SEL (R10104h [9:8]).
PIN_FLT[1]
K21
Pins used as Fault LED:
PIN_FLT[0]
K22
• PIN_FLT[8]: Global Fault indication. The indicator is on when any SAS/SATA_PHY has a fault. • PIN_FLT[7:0] corresponds to SAS/SATA_PHY7 through PHY0. Note: When PHY is not ready, PIN_FLT[7:0] is always on. After the PHY is ready, a fault occurs.
Pins used as SGPIO: • PIN_FLT[8]: Same as FLT mode. • PIN_FLT[7:4]: SGPIO1 SCLK, SLOAD, SDOUT, SDIN • PIN_FLT[3:0]: SGPIO0 SCLK,SLOAD,SDOUT,SDIN Used as I2C: • • • • •
PIN_FLT[8]: Same as FLT Mode PIN_FLT[7:6]: I2C2 CLK, DATA PIN_FLT[5:4]: Not used PIN_FLT[3:2]: I2C1 CLK, DATA PIN_FLT[1:0]: Not used
Signal Descriptions Copyright © 2015 Marvell April 23, 2015
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Table 3-2 General Purpose I/O Signals (continued) Signal Name
Signal Number
Type
Description
PIN_TEST[15]
F19
I/O
Configuration and test pins.
PIN_TEST[14]
C21
These pins can be used as GPIO.
PIN_TEST[13]
E20
PIN_TEST[15]-PCIe power-up disable
PIN_TEST[12]
D21
PIN_TEST[11]
C22
PIN_TEST[10]
F20
PIN_TEST[9]
E21
0h: Enable PCIe after power-up 1h: Disable PCIe after power-up Not applicable to this chip. This signal needs pull-down.
PIN_TEST[8]
D22
PIN_TEST[7]
H19
PIN_TEST[6]
G20
PIN_TEST[5]
F21
0h: 1h: 2h: 3h:
PIN_TEST[4]
E22
PIN_TEST[12:11]–Reserved
PIN_TEST[3]
G21
PIN_TEST[10]–PCIe ROM location
PIN_TEST[2]
J19
PIN_TEST[1]
H20
0h: 1h:
PIN_TEST[0]
F22
PIN_TEST[14:13]–Chip reference clock selection
20 MHz 50 MHz 100 MHz 75 MHz
Parallel Flash Serial Flash PIN_TEST[9:8]–PCIe maximum lane width
0h:
x8
Always use 0h.PIN_TEST[7:6]–Reserved PIN_TEST[5]—PCIe configuration access enable. 0h: 1h:
PCIe responds to configuration access. PCIe returns a retry configuration access.
Not applicable to this chip. This signal needs pull-down. PIN_TEST[4]–Parallel Flash x8/x16
0h: 1h:
Byte mode Word mode PIN_TEST[3:2]–Reserved PIN_TEST[1]–UART baudrate
0h: 1h:
57600 Reserved PIN_TEST[0]–UART mode
0h: 1h:
Reserved Terminal mode
Table 3-3 Clock and Reset Signals Signal Name
Signal Number
Type
Description
PIN_REFCLK
T19
I
Reference clock input. 2.5V, ± 350 ppm.
PIN_RESET_N
W22
I
Power-on reset.
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Table 3-3 Clock and Reset Signals (continued) Signal Name
Signal Number
Type
Description
PIN_PRESET_N Y22
I
PCIe Reset
PIN_TP
O
SAS/SATA analog test port.
Description
V20
Table 3-4 I2C Signals Signal Name
Signal Number
Type
PIN_SCL[2]
N20
I/O, OC I2C clock.
PIN_SCL[1]
P22
PIN_SCL[0]
N19
PIN_SDA[2]
P21
PIN_SDA[1]
P20
PIN_SDA[0]
R22
I/O, OC I2C data.
Table 3-5 UART Signals Signal Name
Signal Number
Type
Description
PIN_UAI[1]
P19
I
UART input.
PIN_UAI[0]
R20
PIN_UAO[1]
T22
O
UART output.
PIN_UAO[0]
U22
. Table 3-6 Parallel Flash Signals Signal Name
Signal Number
Type
Description
PIN_F_BYTE_N
F5
O
Parallel flash Byte mode.
PIN_F_CE_N
D3
O
Parallel flash chip select.
PIN_F_OE_N
F4
O
Parallel flash output enable.
PIN_F_READY
E3
I
Parallel flash ready signal. Requires external pull-up resistor.
PIN_F_RESET_N C2
O
Parallel flash reset.
PIN_F_WE_N
O
Parallel flash write enable.
G5
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Table 3-6 Parallel Flash Signals (continued) Signal Name
Signal Number
Type
Description
O
PIN_P_ADDR[20] T6
Shared address bus for parallel flash, NVSRAM and PBSRAM.
PIN_P_ADDR[19] L3
For Parallel Flash, signals are word addresses.
PIN_P_ADDR[18] L2
For NVSRAM, signals are WORD addresses.
PIN_P_ADDR[17] L1
For PBSRAM, signals are Dword addresses.
PIN_P_ADDR[21] U6
PIN_P_ADDR[16] P1 PIN_P_ADDR[15] N2 PIN_P_ADDR[14] M4 PIN_P_ADDR[13] N1 PIN_P_ADDR[12] M3 PIN_P_ADDR[11] M2 PIN_P_ADDR[10] M1 PIN_P_ADDR[9]
U3
PIN_P_ADDR[8]
W2
PIN_P_ADDR[7]
T5
PIN_P_ADDR[6]
U5
PIN_P_ADDR[5]
K4
PIN_P_ADDR[4]
K3
PIN_P_ADDR[3]
J1
PIN_P_ADDR[2]
K2
PIN_P_ADDR[1]] K1 PIN_P_ADDR[0]
L4
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Table 3-6 Parallel Flash Signals (continued) Signal Name
Signal Number
PIN_P_DATA[35] J2
Type
Description
I/O
Shared Data Bus for Parallel Flash/NVSRAM/PBSRAM.
PIN_P_DATA[34] D2
For Parallel Flash, DATA[15:0] are used.
PIN_P_DATA[33] Y1 PIN_P_DATA[32] N3
In Byte mode, DATA[15] is address bit 0. DATA[7:0] are data.
PIN_P_DATA[31] H1
In Word mode, DATA[15:0] are data.
PIN_P_DATA[30] J3
For NVSRAM, DATA[15:0] are used.
PIN_P_DATA[29] H2
For PBSRAM, DATA[35:0] are used.
PIN_P_DATA[28] G1
DATA[35] is parity for Byte 3.
PIN_P_DATA[27] F1
DATA[34] is parity for Byte 2.
PIN_P_DATA[26] G2
DATA[33] is parity for Byte 1.
PIN_P_DATA[25] H3
DATA[32] is parity for Byte 0.
PIN_P_DATA[24] J4 PIN_P_DATA[23] E1 PIN_P_DATA[22] F2 PIN_P_DATA[21] G3 PIN_P_DATA[20] D1 PIN_P_DATA[19] E2 PIN_P_DATA[18] H4 PIN_P_DATA[17] C1 PIN_P_DATA[16] F3 PIN_P_DATA[15] R4 PIN_P_DATA[14] V2 PIN_P_DATA[13] T3 PIN_P_DATA[12] W1 PIN_P_DATA[11] U2 PIN_P_DATA[10] P4 PIN_P_DATA[9]
V1
PIN_P_DATA[8]
R3
PIN_P_DATA[7]
T2
PIN_P_DATA[6]
U1
PIN_P_DATA[5]
R2
PIN_P_DATA[4]
N4
PIN_P_DATA[3]
P3
PIN_P_DATA[2]
T1
PIN_P_DATA[1]]
R1
PIN_P_DATA[0]
P2
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Table 3-7 NVSRAM Signals Signal Name
Signal Number
Type
Description
PIN_N_CE_N
E4
O
nvSRAM chip select.
PIN_N_OE_N
G4
O
nvSRAM output enable.
PIN_N_WE_N
C3
O
nvSRAM write enable.
Table 3-8 PBSRAM Signals Signal Name
Signal Number
Type
Description
PIN_P_ADSC_N
T4
O
PBSRAM ASDC mode.
PIN_P_ADV_N
V3
O
PBSRAM address advance.
PIN_P_BW_N
AB2
O
PBSRAM BW.
PIN_P_CS1_N
V4
O
PBSRAM chip select.
PIN_P_GW_N
R5
O
PBSRAM global write enable.
PIN_P_OE_N
AA1
O
PBSRAM output enable.
PIN_P_OUT_CLK Y2
O
PBSRAM clock.
PIN_P_WE_N[3]
U4
O
PBSRAM write enable.
PIN_P_WE_N[2]
Y3
PIN_P_WE_N[1]
W3
PIN_P_WE_N[0]
AA2
Table 3-9 System Interface Signals Signal Name
Signal Number
Type
PIN_CNFG[1]
U21
I
PIN_CNFG[0]
V21
REFCLKP
B12
Description Configuration. 00: Normal Functional mode. Others:Test Mode.
I
PCIe reference clock input. 100MHz ± 300ppm.No internal clock termination.
REFCLKN
A12
I
PCIe reference clock input. 100MHz ± 300ppm.No internal clock termination.
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Table 3-10 SPI Interface Signals Signal Name
Signal Number
Type
Description
PIN_SPI_DI
T21
I
SPI data input.
PIN_SPI_CLK
V22
O
SPI clock.
PIN_SPI_CS_N
R19
O
SPI chip select.
PIN_SPI_DO
T20
O
SPI data output.
Table 3-11 PCIe Interface Signals Signal Name
Signal Number
Type
Description
ISET
U18
I/O
Reference Current for PCI-Express PHY. This pin must be connected to an external 6.04 kΩ, 1% resistor to ground.
PIN_ISET
E12
I
Chip reference resistor 5 kΩ.
PTP
E14
O
Analog test port for PCIe.
PIN_M_CLK
U20
I
PCIe debugging MDIO interface, clock.
PIN_M_DATA
W21
I/O
PCIe debugging MDIO interface, data.
Table 3-12 SAS/SATA Transmitter and Receiver Interface Signals Signal Name
Signal Number
PIN_RXP[7]
AB18
–
PIN_RXP[6]
AB16
–
PIN_RXP[5]
AB14
–
PIN_RXP[4]
AB12
–
PIN_RXP[3]
AB10
PIN_RXP[2]
AA8
PIN_RXP[1]
W7
PIN_RXP[0]
W5
PIN_RXN[7]
AA18
–
PIN_RXN[6]
AA16
–
PIN_RXN[5]
AA14
–
PIN_RXN[4]
AA12
–
PIN_RXN[3]
AA10
PIN_RXN[2]
AB8
PIN_RXN[1]
Y7
PIN_RXN[0]
Y5
Type
Description
I
PIN_RXP[7:0]–SAS/SATA PHY 7–0 Receiver Differential Signal.
I
PIN_RXN[7:0]–SAS/SATA PHY 7–0 Receiver Differential Signals.
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Table 3-12 SAS/SATA Transmitter and Receiver Interface Signals (continued) Signal Name
Signal Number
PIN_TXP[7]
W19
–
PIN_TXP[6]
W17
–
PIN_TXP[5]
W15
–
PIN_TXP[4]
W13
–
PIN_TXP[3]
W11
PIN_TXP[2]
Y9
PIN_TXP[1]
AB6
PIN_TXP[0]
AB4
PIN_TXN[7]
Y19
PIN_TXN[6]
Y17
PIN_TXN[5]
Y15
PIN_TXN[4]
Y13
PIN_TXN[3]
Y11
PIN_TXN[2]
W9
PIN_TXN[1]
AA6
PIN_TXN[0]
AA4
Type
Description
O
PIN_TXP[7:0]–SAS/SATA PHY 7–0 Transmitter Differential Signals.
O
PIN_TXN[7:0]–SAS/SATA PHY 7–0 Transmitter Differential Signals.
Table 3-13 PCIe Transmitter and Receiver Interface Signals Signal Name
Signal Number
PRXP[7]
B4
–
PRXP[6]
B6
–
PRXP[5]
B8
–
PRXP[4]
D11
–
PRXP[3]
A14
PRXP[2]
A16
PRXP[1]
A18
PRXP[0]
C19
PRXN[7]
A4
–
PRXN[6]
A6
–
PRXN[5]
A8
–
PRXN[4]
C11
–
PRXN[3]
B14
PRXN[2]
B16
PRXN[1]
B18
PRXN[0]
D19
Type
Description
I
PRXP[7:0]–PCI-Express Lane 7–0 Receiver Differential Signal (PCIe Rx +/-).
I
PRXN[7:0]–PCI-Express Lane 7–0 Receiver Differential Signals (PCIe Rx +/-).
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Table 3-13 PCIe Transmitter and Receiver Interface Signals (continued) Signal Name
Signal Number
PTXP[7]
C5
–
PTXP[6]
C7
–
PTXP[5]
C9
–
PTXP[4]
A10
–
PTXP[3]
C13
PTXP[2]
D15
PTXP[1]
D17
PTXP[0]
B20
PTXN[7]
D5
–
PTXN[6]
D7
–
PTXN[5]
D9
–
PTXN[4]
B10
–
PTXN[3]
D13
PTXN[2]
C15
PTXN[1]
C17
PTXN[0]
A20
Type
Description
O
PTXP[7:0]–PCI-Express Lane 7–0 Transmitter Differential Signals (PCIe Tx -/+).
O
PTXN[7:0]–PCI-Express Lane 7–0 Transmitter Differential Signals (PCIe Tx -/+).
Table 3-14 Power Interface Signals Signal Name
Signal Number
Type
Description
AVDD25_0
F6
Power, I
I/O Pad Power 2.5V.
AVDD25_1
G18
Power, I
I/O Pad Power 2.5V.
AVDD[8]-1
F13, F14, F15, F16, G13, G14, G15, G16
Power, I
1.8V analog power for PCI-Express PHY.
F8, F9. E10, F10, G7, G8, G9, G10
Power, I
VAA[0-3]
T7, T8, T9, T10
Power, I
2.5V analog power for SAS/SATA PHY.
VAA[4-7]
T13, T14, T15, T16
Power, I
2.5V analog power for SAS/SATA PHY.
VAA_ANA
T18
Power, I
2.5V analog power for PLL.
AVDD[8]-2
AVDD[8] is for PLL and the current source.
1.8V analog power for PCI-Express PHY. AVDD[8] is for PLL and the current source.
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Table 3-14 Power Interface Signals (continued) Signal Name
Signal Number
Type
Description 1.0V digital core power.
VDD
H6, H7, H8, H9, H10, H13, H14, H15, H16, H17, J6, J17, K6, K17, L6, L17, M6, M17, N6, N17, P6, P17, R6, R7, R8, R9, R10, R13, R14, R15, R16, R17
Power, I
VDDO1
H18, J18, K18, L18, M18, N18, P18, R18
Power, I
VDDO2
Digital Power. 3.3V I/O Power to supply digital and I/Os.
H5, J5, K5, L5, M5, N5, P5
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Table 3-14 Power Interface Signals (continued) Signal Name VSS
Signal Number A1, A2, A3, A5, A7, A9, A11, A13, A15, A17, A19, A21, A22, AA3, AA5, AA7, AA9, AA11, AA13, AA15, AA17, AA19–AA 22, AB1, AB3, AB5, AB7, AB9, AB11, AB13, AB15, AB17, AB19–AB 22, B1, B2, B3, B5, B7, B9, B11, B13, B15, B17, B19, B21, B22, C4, C6, C8, C10, C12, C14, C16, C18, C20, D4, D6, D8, D10, D12, D14, D16, D18, D20, E5, E6, E7, E8, E9, E11, E13, E15, E16, E17, E18, E19, F7, F11, F12, F17, F18, G6, G11, G12, G17, G19, H11, H12
Type
Description
Ground
Ground.
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Table 3-14 Power Interface Signals (continued) Signal Name VSS
Signal Number J7–J16, J21, K7–K16, L7–L16, M7–M16, M21, N7–N16, P7–P16, R11, R12, R21, T11, T12, T17, U7–U17, U19, V5–V19, W4, W6, W8, W10, W12, W14, W16, W18, W20, Y4, Y6, Y8, Y10, Y12, Y14, Y16, Y18, Y20, Y21
Type
Description
Ground
Ground.
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Part 1: Chip Overview Layout Guidelines
4
LAYOUT GUIDELINES This chapter describes the system recommendations from the Marvell Semiconductor design and application engineers who work with the 88SE9480/88SE9485. It is written for those who are designing schematics and printed circuit boards for an 88SE9480/88SE9485-based system. Whenever possible, the PCB designer should try to follow the suggestions provided in this chapter. The information in this chapter is preliminary. Please consult with Marvell Semiconductor design and application engineers before starting your PCB design. This chapter contains the following sections:
88SE9480/88SE9485 Board Schematics
Layer Stack-Up
Power Supply
PCB Trace Routing
Recommended Layout
Refer to Chapter 3, Package, for package information.
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4.1
88SE9480/88SE9485 Board Schematics This section contains board schematics for the 88SE9480/88SE9485. It contains the following figures:
Figure 4-1, 88SE9480/88SE9485 PCIe and SAS
Figure 4-2, 88SE9480/88SE9485 Bootstrap, NI, SPI, UART, I2C, LED
Figure 4-3, 88SE9480/88E9485 Power and Ground
4-2 Copyright © 2015 Marvell April 23, 2015
88SE9480/88SE9485 Board Schematics Doc No. MV-S105606-00 Rev. J Document Classification: Proprietary
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
PTXN7
PTXP7
PTXN6
PTXP6
PTXN5
PTXP5
PTXN4
PTXP4
PTXN3
PTXP3
PTXN2
PTXP2
PTXN1
PTXP1
PTXN0
PTXP0
C32
C31
C28
C27
C24
C22
C21
C20
C16
C14
C13
C12
C11
C23
C7
C5
12V0
PCLKN PCLKP
HSIN0 HSIP0
HSIN1 HSIP1
HSIN2 HSIP2
HSIN3 HSIP3
HSIN4 HSIP4
HSIN5 HSIP5
HSIN6 HSIP6
HSIN7 HSIP7
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
A49 A48 A47 A46 A45 A44 A43 A42 A41 A40 A39 A38 A37 A36 A35 A34 A33 A32 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
3V3_PCIE
P1
WAKE# 3.3VAux TRST# 3V3_3 GND_20 SMDAT SMCLK GND_19 RSVD_4 +12V_4 +12V_3
PCIE x8
PWRGD 3V3_2 3V3_1 TMS TDO TDI TCK GND_1 +12V_2 +12V_1 PRSNT#1
GND_18 GND_37 HSIn(7) PRSNT#2C HSIp(7) GND_36 GND_17 HSOn(7) GND_16 HSOp(7) HSIn(6) GND_35 HSIp(6) GND_34 GND_15 HSOn(6) GND_14 HSOp(6) HSIn(5) GND_33 HSIp(5) GND_32 GND_13 HSOn(5) GND_12 HSOp(5) HSIn(4) GND_31 HSIp(4) GND_30 GND_11 HSOn(4) RSVD_3 HSOp(4) RSVD_2 GND_29 GND_10 PRSNT#2B HSIn(3) RSVD_6 HSIp(3) GND_28 GND_9 HSOn(3) GND_8 HSOp(3) HSIn(2) GND_27 HSIp(2) GND_26 GND_7 HSOn(2) GND_6 HSOp(2) HSIn(1) GND_25 HSIp(1) GND_24 GND_5 HSOn(1) RSVD_1 HSOp(1) GND_4 GND_23 HSIn(0) PRSNT#2A HSIp(0) GND_22 GND_3 HSOn(0) REFCLKHSOp(0) REFCLK+ GND_21 GND_2 RSVD_5
TOP
PCIEx8_Gold_Finger BOT
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
B49 B48 B47 B46 B45 B44 B43 B42 B41 B40 B39 B38 B37 B36 B35 B34 B33 B32 B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 R1
C56 0.1U
12V0
0R
3V3
88SE9480/88SE9485 Board Schematics
Document Classification: Proprietary PCLKP
PCLKN
PCIE_RESET
0.1U
C51
1
6.04K
TP39
R22
R21 100R_X
A20 B20
PTXN0 PTXP0
U18
E14
B12
A12
Y22
C17 D17
C15 D15
D13 C13
B10 A10
PTXN1 PTXP1
PTXN2 PTXP2
PTXN3 PTXP3
PTXN4 PTXP4
D9 C9
D7 C7
PTXN6 PTXP6 PTXN5 PTXP5
D5 C5
D19 C19
B18 A18
B16 A16
B14 A14
C11 D11
A8 B8
A6 B6
A4 B4
PTXN7 PTXP7
PRXN0 PRXP0
PRXN1 PRXP1
PRXN2 PRXP2
PRXN3 PRXP3
PRXN4 PRXP4
PRXN5 PRXP5
PRXN6 PRXP6
PRXN7 PRXP7
PEX
REFCLKP
REFCLKN
PIN_PRESET_N
88SE9480/88SE9485
ISET
PTP
PIN_RXN[7] PIN_RXP[7]
PIN_TXP[7] PIN_TXN[7]
PIN_RXN[6] PIN_RXP[6]
PIN_TXP[6] PIN_TXN[6]
PIN_RXN[5] PIN_RXP[5]
PIN_TXP[5] PIN_TXN[5]
PIN_RXN[4] PIN_RXP[4]
PIN_TXP[4] PIN_TXN[4]
PIN_RXN[3] PIN_RXP[3]
PIN_TXP[3] PIN_TXN[3]
PIN_RXN[2] PIN_RXP[2]
PIN_TXP[2] PIN_TXN[2]
PIN_RXN[1] PIN_RXP[1]
PIN_TXP[1] PIN_TXN[1]
PIN_RXN[0] PIN_RXP[0]
PIN_TXP[0] PIN_TXN[0]
SAS/SATA
OE
GND
Vcc
OUT
Y1
T19
V20
E12
W22
V21 U21
AA18 AB18
W19 Y19
AA16 AB16
W17 Y17
AA14 AB14
W15 Y15
AA12 AB12
W13 Y13
AA10 AB10
W11 Y11
AB8 AA8
Y9 W9
Y7 W7
AB6 AA6
Y5 W5
AB4 AA4
50MHZ_8W50000002
1
2
PIN_REFCLK
PIN_TP
PIN_ISET
PIN_RESET_N
PIN_CNFG[0] PIN_CNFG[1]
CLOCK & RESET
PTXN[0] PTXP[0]
PTXN[1] PTXP[1]
PTXN[2] PTXP[2]
PTXN[3] PTXP[3]
PTXN[4] PTXP[4]
PTXN[5] PTXP[5]
PTXN[6] PTXP[6]
PTXN[7] PTXP[7]
PRXN[0] PRXP[0]
PRXN[1] PRXP[1]
PRXN[2] PRXP[2]
PRXN[3] PRXP[3]
PRXN[4] PRXP[4]
PRXN[5] PRXP[5]
PRXN[6] PRXP[6]
PRXN[7] PRXP[7]
U1A
4
3
1
C49 0.1U
4.99K
R20
TP1
S_RXN7 S_RXP7
S_TXP7 S_TXN7
S_RXN6 S_RXP6
S_TXP6 S_TXN6
S_RXN5 S_RXP5
S_TXP5 S_TXN5
S_RXN4 S_RXP4
S_TXP4 S_TXN4
S_RXN3 S_RXP3
S_TXP3 S_TXN3
S_RXN2 S_RXP2
S_TXP2 S_TXN2
S_RXN1 S_RXP1
S_TXP1 S_TXN1
S_RXN0 S_RXP0
S_TXP0 S_TXN0
C50 1U
1
2
4.7U
C117
FB_1A
FB1
C59 1U
2V5
PCIE_RESET
CNFG1
CNFG0
3
CFG1_1 CFG1_0
CFG0_1 CFG0_0
10K_X 1K
10K_X 1K
S_RXP7
0.01U
0.01U
0.01U S_RXN7
0.01U S_TXN7
0.01U
S_RXP6
S_TXP7
0.01U
0.01U
S_TXN6 S_RXN6
0.01U
0.01U
0.01U
0.01U
0.01U
0.01U
S_TXP6
S_RXP5
S_RXN5
S_TXN5
S_TXP5
S_RXP4
0.01U
0.01U
S_RXN4
0.01U
S_TXP4
0.01U
S_TXN4
0.01U
S_RXP3
0.01U
0.01U
0.01U
0.01U
0.01U
0.01U
0.01U
0.01U
0.01U
S_RXN3
S_TXN3
S_TXP3
S_RXP2
S_RXN2
S_TXN2
S_TXP2
S_RXP1
S_RXN1
S_TXN1
0.01U
0.01U
S_RXP0
S_TXP1
0.01U
S_RXN0
3V3
C48
C47
C46
C45
C44
C43
C42
C41
C40
C39
C38
C37
C36
C35
C34
C33
C30
C29
C26
C25
C19
C18
C17
C15
C10
C9
C8
C6
C4
C3
C2
C1
3 3
3 3
3 3
3 3
S_DOUT1 S_DIN1
S_CLK1 S_LOAD1
S_DOUT0 S_DIN0
S_CLK0 S_LOAD0
CNFG[1:0] *00: Normal 01: 10: 11:
(INTERNAL TEST MODE SELECTION)
SRXP7
SRXN7
STXN7
STXP7
SRXP6
SRXN6
STXN6
STXP6
SRXP5
SRXN5
STXN5
STXP5
SRXP4
SRXN4
STXN4
STXP4
SRXP3
SRXN3
STXN3
STXP3
SRXP2
SRXN2
STXN2
STXP2
SRXP1
SRXN1
STXN1
STXP1
SRXP0
SRXN0
STXN0
STXP0
S_DOUT0 S_DIN0
S_CLK0 S_LOAD0
C175 S_DOUT1 S_DIN1
S_CLK1 S_LOAD1
1000pF_X
STXP3 STXN3
STXP2 STXN2
STXP1 STXN1
STXP0 STXN0
SRXP3 SRXN3
SRXP2 SRXN2
SRXP1 SRXN1
SRXP0 SRXN0
STXP7 STXN7
STXP6 STXN6
STXP5 STXN5
STXP4 STXN4
SRXP7 SRXN7
SRXP6 SRXN6
SRXP5 SRXN5
SRXP4 SRXN4
C171
0.01U
C178 1000pF_X
0.01U
C176 1000pF_X C172
S_TXN0
C177 1000pF_X C173
1000pF_X C174 1000pF_X
Copyright © 2015 Marvell April 23, 2015 1000pF_X
B8 B9 B10 A9 A10 A11 B11 A8
B16 B17
B13 B14
B5 B6
B2 B3
A16 A17
A13 A14
A5 A6
A2 A3
B8 B9 B10 A9 A10 A11 B11 A8
B16 B17
B13 B14
B5 B6
B2 B3
A16 A17
A13 A14
A5 A6
A2 A3
J1
GND7 GND8 GND9 GND10 GND11 GND12
GND1 GND2 GND3 GND4 GND5 GND6
PEG2
PEG1
MTH1 MTH2 MTH3 MTH4 MTH5 MTH6
B1 B4 B7 B12 B15 B18
A1 A4 A7 A12 A15 A18
H2
H1
H3 H4 H5 H6 H7 H8
J2
GND7 GND8 GND9 GND10 GND11 GND12
GND1 GND2 GND3 GND4 GND5 GND6
PEG2
PEG1
MTH1 MTH2 MTH3 MTH4 MTH5 MTH6
B1 B4 B7 B12 B15 B18
A1 A4 A7 A12 A15 A18
H2
H1
H3 H4 H5 H6 H7 H8
iPASS_0.8mm_36 conn32_minisas_smd_36_01_paste
SB0-SCLK SB1-SLOD SB2-GND SB3 SB4_SDO SB5_SDI SB6 SB7
TX+3 TX-3
TX+2 TX-2
TX+1 TX-1
TX+0 TX-0
RX+3 RX-3
RX+2 RX-2
RX+1 RX-1
RX+0 RX-0
iPASS_0.8mm_36 conn32_minisas_smd_36_01_paste
SB0-SCLK SB1-SLOD SB2-GND SB3 SB4_SDO SB5_SDI SB6 SB7
TX+3 TX-3
TX+2 TX-2
TX+1 TX-1
TX+0 TX-0
RX+3 RX-3
RX+2 RX-2
RX+1 RX-1
RX+0 RX-0
1000pF_X
S_TXP0
Part 1: Chip Overview Layout Guidelines
Figure 4-4, 88SE9480/88SE9485 Power Regulators
Figure 4-1 88SE9480/88SE9485 PCIe and SAS
4-3
Doc No. MV-S105606-00 Rev. J
Document Classification: Proprietary
A
B
C
D
S_DIN1 S_DOUT1 S_LOAD1 S_CLK1
2 2 2 2
TEST[15]
1 1
1
TP42 TP43
TP32
1K 1K
100R
L4 K1 K2 J1 K3 K4 U5 T5 W2 U3 M1 M2 M3 N1 M4 N2 P1 L1 L2 L3 T6 U6
C3 E4 G4
P_ADDR0 P_ADDR1 P_ADDR2 P_ADDR3 P_ADDR4 P_ADDR5 P_ADDR6 P_ADDR7 P_ADDR8 P_ADDR9 P_ADDR10 P_ADDR11 P_ADDR12 P_ADDR13 P_ADDR14 P_ADDR15 P_ADDR16 1 TP13 1 TP14 1 TP15 1 TP16 1 TP17
N_WE_N N_CE_N N_OE_N
ACT0 ACT1 ACT2 ACT3 ACT4 ACT5 ACT6 ACT7 ACT8
N21 M19 N22 M20 M22 L21 L20 L19 L22
F22 H20 J19 G21 E22 F21 TEST[6]_FLT4 G20 TEST[7]_FLT5 H19 D22 E21 F20 TEST[10] TEST[11]_FLT6 C22 TEST[12]_FLT7 D21 E20 TEST[13] C21 TEST[14] F19
TEST[0] TEST[1] TEST[2] TEST[3]_FLT2 TEST[4]_FLT3
SMCLK N19 I2C_SCL P22 1 N20 TP23
SMDAT R22 I2C_SDA P20 1 P21
AA2 W3 Y3 U4
1 1 1 1
TP9 TP10 TP11 TP12
TP20
AA1 V4
1 1
TP7 TP8
PIN_F_RESET_N PIN_F_CE_N PIN_F_READY PIN_F_WE_N PIN_F_OE_N PIN_F_BYTE_N
PIN_UAO[0] PIN_UAO[1] PIN_UAI[0] PIN_UAI[1]
PIN_SPI_DI PIN_SPI_DO PIN_SPI_CLK PIN_SPI_CS_N
LED
88SE9480/88SE9485
PIN_ACT[0] PIN_ACT[1] PIN_ACT[2] PIN_ACT[3] PIN_ACT[4] PIN_ACT[5] PIN_ACT[6] PIN_ACT[7] PIN_ACT[8]
PIN_TEST[0] PIN_TEST[1] PIN_TEST[2] PIN_TEST[3] PIN_TEST[4] PIN_TEST[5] PIN_TEST[6] PIN_TEST[7] PIN_TEST[8] PIN_TEST[9] PIN_TEST[10] PIN_TEST[11] PIN_TEST[12] PIN_TEST[13] PIN_TEST[14] PIN_TEST[15]
PIN_FLT[0] PIN_FLT[1] PIN_FLT[2] PIN_FLT[3] PIN_FLT[4] PIN_FLT[5] PIN_FLT[6] PIN_FLT[7] PIN_FLT[8]
PIN_M_CLK PIN_M_DATA
CONFIG/TEST/RSVD
PIN_SCL[0] PIN_SCL[1] PIN_SCL[2]
PIN_SDA[0] PIN_SDA[1] PIN_SDA[2]
SERIAL INTERFACE
PIN_N_WE_N PIN_N_CE_N PIN_N_OE_N
NVSRAM/FLASH
PIN_P_ADDR[0] PIN_P_ADDR[1] PIN_P_ADDR[2] PIN_P_ADDR[3] PIN_P_ADDR[4] PIN_P_ADDR[5] PIN_P_ADDR[6] PIN_P_ADDR[7] PIN_P_ADDR[8] PIN_P_ADDR[9] PIN_P_ADDR[10] PIN_P_ADDR[11] PIN_P_ADDR[12] PIN_P_ADDR[13] PIN_P_ADDR[14] PIN_P_ADDR[15] PIN_P_ADDR[16] PIN_P_ADDR[17] PIN_P_ADDR[18] PIN_P_ADDR[19] PIN_P_ADDR[20] PIN_P_ADDR[21]
PIN_P_WE_N[0] PIN_P_WE_N[1] PIN_P_WE_N[2] PIN_P_WE_N[3]
PIN_P_OE_N PIN_P_CS1_N
PIN_P_GW_N PIN_P_ADSC_N PIN_P_ADV_N
K22 K21 J22 K20 H22 K19 J20 H21 G22
U20 W21
U22 T22 R20 P19
T21 T20 V22 R19
C2 D3 E3 G5 F4 F5
1
1
1 1 TP45 TP44
SPI_DI SPI_DO SPI_CLK SPI_CS_N
3V3
TP116
TP115
56R 56R 56R 56R
TP109 TP110 TP111 TP112 TP113 TP114
TP24 TP82 TP83 TP84 TP85 TP86 TP87 TP88 TP89 TP90 TP91 TP92 TP93 TP94 TP95 TP96 TP97 TP98 TP99 TP100 TP101 TP102 TP103 TP104 TP105 TP106 TP107 TP108
S_DIN0 S_DOUT0 S_LOAD0 S_CLK0 S_DIN1 S_DOUT1 S_LOAD1 S_CLK1 FLT8
M_CLK M_DATA
UAI_0
UAO_0
R95 R96 R97 R98
1 1 1 1 1 1
P_DATA0 P_DATA1 P_DATA2 P_DATA3 P_DATA4 P_DATA5 P_DATA6 P_DATA7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R47
100R
H2
H1
J9 1 2 3 4
1 2 3 4 UAO_0 UAI_0
10K
10K
10K
R78
3V3
1K
3V3
TEST[10]
LED3 GREEN/YELLOW led_bi_smd4
H2
H1 H1 1 2 H2 3
J3
5
4
3
1 I2C_SDA 2 I2C_SCL 3
3V3
4.7K
4.7K
5 6
SPI_DO SPI_CLK GND
VCC HOLD WP
W25X40AVSNIG
CS
SCK
SI
SO
4
8 7 3
3V3
3V3
10K
R58
4.7K
R93
TEST[13] TEST[14]
R56
0R
R102
1K
0R
1
R101
J4 2x1 header100_smd2-1h
R111 R112 R113 R114 R115 R116 R117 R118
R103 R104 R105 R106 R107 R108 R109 R110
100R 100R 100R 100R 100R 100R 100R 100R
100R 100R 100R 100R 100R 100R 100R 100R
2
100uF/16V
+ C52
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
U5 VCC2 A15 HSB# WE# A13 A8 A9 NC14 A11 NC13 NC12 NC11 VSS2 NC10 NC9 DQ6 OE# A10 CE# DQ7 DQ5 DQ4 DQ3 VCC1
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
CY14B256LA-SP25XIT
Vcap A16 A14 A12 A7 A6 A5 NC1 A4 NC2 NC3 NC4 VSS1 NC5 NC6 DQ0 A3 A2 A1 A0 DQ1 DQ2 NC7 NC8
3V3
10K
R51
2
P_DATA6 N_OE_N P_ADDR10 N_CE_N P_DATA7 P_DATA5 P_DATA4 P_DATA3
P_ADDR11
N_WE_N P_ADDR13 P_ADDR8 P_ADDR9
P_ADDR15 R26
Amber Amber Amber Amber Amber Amber Amber Amber
FLT0 FLT1 FLT2 FLT3 FLT4 FLT5 FLT6 FLT7
(DRIVE FAULT LED)
GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN
ACT0 ACT1 ACT2 ACT3 ACT4 ACT5 ACT6 ACT7
3V3
J17 2 4 6 8 10 12 14 16 18
LED_Header
1 3 5 7 9 11 13 15 17
C55 0.1U
3V3
ACT0 ACT1 ACT2 ACT3 ACT4 ACT5 ACT6 ACT7
C53 0.1U
1
Drive Fault/ Activity LED headers
FLT0 FLT1 TEST[3]_FLT2 TEST[4]_FLT3 TEST[6]_FLT4 TEST[7]_FLT5 TEST[11]_FLT6 TEST[12]_FLT7
3V3
10K
1
3V3
NVRAM 128KB pin 2: A16, pin47: A15
NVRAM 32KB pin 2: NC, pin47: NC
(ACTIVITY LED)
P_DATA0 P_ADDR3 P_ADDR2 P_ADDR1 P_ADDR0 P_DATA1 P_DATA2
P_ADDR4
P_ADDR16 P_ADDR14 P_ADDR12 P_ADDR7 P_ADDR6 P_ADDR5
Install R49, 10K and R54, 1K for debug purposes (UART)
FLT0 FLT1 TEST[3]_FLT2 TEST[4]_FLT3 TEST[6]_FLT4 TEST[7]_FLT5 TEST[11]_FLT6 TEST[12]_FLT7
ACT0 ACT1 ACT2 ACT3 ACT4 ACT5 ACT6 ACT7
U2 Buzzer buzzer_pb-12n24m-12q Q4 NPN sot23 600mA
12V0
SPI FLASH, 4MBit
SPI_CS_N 1
2
SPI_DI
U6
C54 0.1U
R92
R91
I2C connector
4510-E03C-03R_SMT
BUZZER ON
BUZZER
R99
3V3
R28
R27
3V3
Top - Activity (Green) Bottom - Fault (Yellow)
TEST[2]
UART
4510-E04C-03R_SMT
H2
H1
3V3
3
3V3 PIN_TEST[15:0] Configuration and Test pins, GPIO. 0 R49 PIN_TEST[15] => Must tie low PIN_TEST[14:13] => Chip reference clock selection 00: 20MHz, 01: 50MHz(default),10: 100MHz, 11: 75MHz 10K TEST[0] PIN_TEST[12:11] => RSVD 0: Parallel Flash, 1: Serial Flash PIN_TEST[10] => PCIE ROM Location TEST[1] 00 or 11 PIN_TEST[9:8] => RSVD 000 PIN_TEST[7:5] => Must tie low R54 1K 0: Byte Mode, 1: Word Mode PIN_TEST[4] => Parallel Flash x8/x16 => PIN_TEST[3:2] => RSVD PIN_TEST[1] => UART Baud Rate => 0: 57600, 1: RSVD PIN_TEST[0] => UART Mode => 0: RSVD, 1: Terminal Mode
R48
(ACTIVITY LED)
TEST[5] R100 R127 TEST[8] TEST[9]
1
TP27
(DRIVE FAULT LED)
S_DIN0 S_DOUT0 S_LOAD0 S_CLK0
2 2 2 2
R5 T4 V3
1 1 1
TP4 TP5 TP6
P2 R1 T1 P3 N4 R2 U1 T2 R3 V1 P4 U2 W1 T3 V2 R4 F3 C1 H4 E2 D1 G3 F2 E1 J4 H3 G2 F1 G1 H2 J3 H1 N3 Y1 D2 J2
2.0K R119
PIN_P_DATA[0] PIN_P_DATA[1] PIN_P_DATA[2] PIN_P_DATA[3] PIN_P_DATA[4] PIN_P_DATA[5] PIN_P_DATA[6] PIN_P_DATA[7] PIN_P_DATA[8] PIN_P_DATA[9] PIN_P_DATA[10] PIN_P_DATA[11] PIN_P_DATA[12] PIN_P_DATA[13] PIN_P_DATA[14] PIN_P_DATA[15] PIN_P_DATA[16] PIN_P_DATA[17] PIN_P_DATA[18] PIN_P_DATA[19] PIN_P_DATA[20] PIN_P_DATA[21] PIN_P_DATA[22] PIN_P_DATA[23] PIN_P_DATA[24] PIN_P_DATA[25] PIN_P_DATA[26] PIN_P_DATA[27] PIN_P_DATA[28] PIN_P_DATA[29] PIN_P_DATA[30] PIN_P_DATA[31] PIN_P_DATA[32] PIN_P_DATA[33] PIN_P_DATA[34] PIN_P_DATA[35]
2.0K R120
PBSRAM
2.0K R121
U1B
2.0K R122
PIN_P_BW_N PIN_P_OUT_CLK
2.0K R123
AB2 Y2
2.0K R124
1 1
2.0K R125
3 2
TP2 TP3
2.0K R126
4
A2 C2 A1 C1
TP124 TP123 TP122 TP121 TP120 TP119 TP118 TP117 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Copyright © 2015 Marvell April 23, 2015 4 3 2 1
4-4 TP132 TP131 TP130 TP129 TP128 TP127 TP126 TP125
5
A
B
C
D
88SE9480/88SE9485 R3.3 Eight-Lane PCI-Express 2.0 to Eight-Port SAS/SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
Note: This diagram is for reference only. Contact your Marvell field applications engineer for the latest schematics.
Figure 4-2 88SE9480/88SE9485 Bootstrap, NI, SPI, UART, I2C, LED
88SE9480/88SE9485 Board Schematics
Doc No. MV-S105606-00 Rev. J
Copyright © 2015 Marvell April 23, 2015
Document Classification: Proprietary
1V0_core
3_3V
VAA
AVDD_25
AVDD[8]_0 AVDD[8]_1 AVDD[8]_2 AVDD[8]_3 AVDD[8]_4 AVDD[8]_5 AVDD[8]_6 AVDD[8]_7
V11 V12 V13 V14 V15 V16 V17 V18 V19 W4 W6 W8 W10 W12 W14 W16 W18 W20 Y4 Y6 Y8 Y10 Y12 Y14 Y16 Y18 Y20 Y21 AA3 AA5 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA20 AA21 AA22 AB1 AB3 AB5 AB7 AB9 AB11 AB13 AB15 AB17 AB19 AB20 AB21 AB22
H6 H7 H8 H9 H10 H13 H14 H15 H16 H17 J6 J17 K6 K17 L6 L17 M6 M17 N6 N17 P6 P17 R6 R7 R8 R9 R10 R13 R14 R15 R16 R17
H5 J5 K5 L5 M5 N5 P5
H18 J18 K18 L18 M18 N18 P18 R18
VAA_ANA T18 T7 T8 T9 T10 T13 T14 T15 T16
VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206
VDD0 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28 VDD29 VDD30 VDD31
VDDO2_0 VDDO2_1 VDDO2_2 VDDO2_3 VDDO2_4 VDDO2_5 VDDO2_6
VDDO1_0 VDDO1_1 VDDO1_2 VDDO1_3 VDDO1_4 VDDO1_5 VDDO1_6 VDDO1_7
VAA_ANA VAA[0_3]_0 VAA[0_3]_1 VAA[0_3]_2 VAA[0_3]_3 VAA[4_7]_0 VAA[4_7]_1 VAA[4_7]_2 VAA[4_7]_3
F6 G18 AVDD25_0 AVDD25_1
G7 G8 G9 G10 G13 G14 G15 G16
AVDD[4] AVDD[5] AVDD[6] AVDD[7] AVDD[0] AVDD[1] AVDD[2] AVDD[3]
88SE9480/88SE9485
POWER/GND VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134
A1 A2 A3 A5 A7 A9 A11 A13 A15 A17 A19 A21 A22 B1 B2 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B22 C4 C6 C8 C10 C12 C14 C16 C18 C20 D4 D6 D8 D10 D12 D14 D16 D18 D20 E5 E6 E7 E8 E9 E11 E13 E15 E16 E17 E18 E19 F7 F11 F12 F17 F18 G6 G11 G12 G17 G19 H11 H12 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J21 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M21 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R11 R12 R21 T11 T12 TP33 TP34
2V5
1
F10 E10 F9 F8 F16 F15 F14 F13
VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153
88SE9480/88SE9485 Board Schematics T17 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U19 V5 V6 V7 V8 V9 V10
10U_10V
C76
1
AVDD_18
3V3
1 FB_1A
FB13 2 C78 0.1U
FB_1A
FB15
FB_1A
FB3
FB_1A
C77
1
1
1
FB2
10U_10V 0.1U
C80
2V5
2V5
2V5
2
2
2
0.1U
C79 0.01U
0.01U
C82
0.01U
C81
C116
0.1U
0.01U
C74
0.01U
C66
VAA_ANA
0.01U
C83 0.01U
C84
AVDD_25
0.1U
C118
C73
2.2U
0.1U
C72
C65
2.2U
0.01U
0.1U
C64
C58
C57
0.01U
C85
1000P
C75
VAA
1000P
C67
VAA
3_3V
1V8
1
FB14
FB_2A
2
1V0
1 FB_4A
FB11 2
2.2U
0.1U
C130
0.1U
C131
C121
2.2U
0.1U
C127
2.2U
C69
0.1U
2.2U
C68
C61
C60
AVDD_18
0.1U
C97 0.1U
C96 10U_10V 0.1U
C95
C87
C86
1000P
C129
AVDD_18
1000P
C115
AVDD_18
1000P
C71
AVDD_18
1000P
C63
10U_10V 0.1U
C90
0.01U
C128
0.01U
C114
0.01U
C70
0.01U
C62
0.1U
C98
0.1U
C88
0.01U
C99
0.01U
C89
0.01U
C100
0.01U
C91
0.01U
C101
0.01U
C92
0.01U
C102
0.01U
C93
0.01U
C103
0.01U
C94
1V0_core
1V0_core
Part 1: Chip Overview Layout Guidelines
Note: This diagram is for reference only. Contact your Marvell field applications engineer for the latest schematics.
Figure 4-3 88SE9480/88E9485 Power and Ground
4-5
Doc No. MV-S105606-00 Rev. J
R68
11K
R67
0R
0.1U
C108
R74 100K
60.4K
R69
3
VSET
8
7
6
5
4
2
PSET
PWM/SDI
GND
SFB
ILIM
PG
VSW
CSH
VIN
PGND
BG
VCC
VBS
TG
88PH8101
VSET
PSET
EN
U8
4-6
Document Classification: Proprietary Hole
Hole
1 Hole
MTH4
1
MTH3
1
R70
R66
Hole MTH2
1
MTH1
9
10
11
12
13
14
15
16
4.7U
C111
2.2R
0R
C104 1U_16V
4
0.22U
C109
4
0.1U
C107 22U_16V
C136
C105 22U_16V
Q1 FDMS8692
5 6 7 8
1
4 Q2 FDMS8672S
1
1
1
1.5uH
L2
1.5uH
L21
1.2uH
L1
TP35
C112 470UF_6.3V
+
330uF_16V
+ C106
1
12V0
Q3 FDMS8692_X
2
2
2
1 2
VIN2
1 2
2.2R
C169 470UF_6.3V
+
1 2
1 2 3 5 6 7 8 1 2 3
5 6 7 8 1 2 3
C113 470UF_6.3V
+
1
2
2
C170
2
H1
470UF_6.3V
+ 0.1U
C133
TP36
1
1
1V0
1V8
2V5
0.1U
C134
TP40
0.1U
C135
TP37
1
R65
1
22U
22U
22U
C123
C126
C120
1
2.0uH
22U
C124
3V3
1
2
22U
22U
2
C125
L5
2.0uH
C122
3V3
L4
8
10
7 9
5
19
17
20 18
2
88PG8237
PGND1
PVIN1
SW1_1 SW1_0
SFB1
PGND2
PVIN2
SW2_1 SW2_0
SFB2
U10
VSET1
PSET1
VSET2
PSET2
POR1
POR2
SDI
SGND
SVIN
EN
3V3
10K
R79
10R
R73
97.6K
VSET1
13 VSET1
12 PSET1
14 VSET2
15 PSET2
11
16
6 SDI
4
3
1
R81 100K
0R
PSET1
165K
3V3
0R
PSET2
100K
R80
TP38
VSET2
0.1U
C110
1
Copyright © 2015 Marvell April 23, 2015 1
VIN1
88SE9480/88SE9485 R3.3 Eight-Lane PCI-Express 2.0 to Eight-Port SAS/SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
Note: This diagram is for reference only. Contact your Marvell field applications engineer for the latest schematics.
Figure 4-4 88SE9480/88SE9485 Power Regulators
88SE9480/88SE9485 Board Schematics
Doc No. MV-S105606-00 Rev. J
Part 1: Chip Overview Layout Guidelines
Note: This diagram is for reference only. Contact your Marvell field applications engineer for the latest schematics.
88SE9480/88SE9485 Board Schematics Copyright © 2015 Marvell April 23, 2015
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88SE9480/88SE9485 R3.3 Eight-Lane PCI-Express 2.0 to Eight-Port SAS/SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
4.2
Layer Stack-Up The following layer stack up is recommended:
Layer 1–Topside, Parts, Low and High-Speed Signal Routes, and Power Routes
Layer 2–Solid Ground Plane
Layer 3–Power Plane and Low Speed Signals
Layer 4–Power Plane
Layer 5–Solid Ground Plane
Layer 6–Bottom Layer, Low and High-Speed Signal Routes, and Power Routes
Note: 5 mil traces and 5 mil spacing are the recommended minimum requirements.
4.2.1
Layer 1–Topside, Parts, Low and High-Speed Signal Routes, and Power Routes All active parts are to be placed on the topside. Some of the differential pairs for SAS/SATA and PCIe are routed on the top layer, differential 100 ohm impedance needs to be maintained for those high-speed signals.
4.2.2
Layer 2–Solid Ground Plane A solid ground plane should be located directly below the top layer of the PCB. This layer should be a minimum distance below the top layer in order to reduce the amount of crosstalk and EMI. There should be no cutouts in the ground plane. Use of 1 ounce copper is recommended.
4.2.3
Layer 3–Power Plane and Low Speed Signals Use solid planes on layer 3 to supply power to the ICs on the PCB. Avoid narrow traces and necks on this plane.
4.2.4
Layer 4–Power Plane Use solid planes on layer 4 to supply power to the ICs on the PCB. Avoid narrow traces and necks on this plane.
4.2.5
Layer 5–Solid Ground Plane A solid ground plane should be located directly below the top layer of the PCB. This layer should be a minimum distance below the top layer in order to reduce the amount of crosstalk and EMI. There should be no cutouts in the ground plane. Use of 1 ounce copper is recommended.
4-8 Copyright © 2015 Marvell April 23, 2015
Layer Stack-Up Doc No. MV-S105606-00 Rev. J Document Classification: Proprietary
Part 1: Chip Overview Layout Guidelines
4.2.6
Layer 6–Bottom Layer, Low and High-Speed Signal Routes, and Power Routes Some of the differential pairs for SAS/SATA and PCIe are routed on the top layer, differential 100Ω impedance needs to be maintained for those high speed signals.
Layer Stack-Up Copyright © 2015 Marvell April 23, 2015
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88SE9480/88SE9485 R3.3 Eight-Lane PCI-Express 2.0 to Eight-Port SAS/SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
4.3
Power Supply The 88SE9480/88SE9485 operates using the following power supplies:
4.3.1
VDD Power (1.0V) for the digital core
PCIe Analog Power Supply (1.8V)
SAS/SATA Analog Power Supply (2.5V)
General I/O Power (3.3V)
Bias Current Resistor (RSET)
VDD Power (1.0V) All digital power pins (VDD pins) must be connected directly to a VDD plane in the power layer with short and wide traces to minimize digital power-trace inductances. Use vias close to the VDD pins to connect to this plane and avoid using the traces on the top layer. Marvell recommends placing capacitors around the three sides of the PCB near VDD pins with the following dimensions:
0.001 µF (1 capacitor)
0.1 µF (2 capacitors)
2.2 µF (1 ceramic capacitor)
The combinations of small capacitors are used to suppress switching noise at various frequency ranges. The 2.2 µF ceramic decoupling capacitor is required to filter the lower frequency power-supply noise. To reduce system noise, place high-frequency surface-mount monolithic ceramic bypass capacitors as close as possible to the channel VDD pins. Place at least one decoupling capacitor on each side of the IC package.
4.3.2
PCIe Analog Power Supply (1.8V) The analog supply provides power for the PCIe link’s high speed serial signals. To ensure high speed link operation, use a series of bypass capacitors for the supplies. A typical capacitor value combination is 1 nF, 0.1µF, and 2.2 µF.
4.3.3
SAS/SATA Analog Power Supply (2.5V) The analog supply provides power for the SAS/SATA link’s high speed serial signals. To ensure high speed link operation, use a series of bypass capacitors for the supplies. A typical capacitor value combination is 1 nF, 0.1µF, and 2.2 µF.
4.3.4
General I/O Power (3.3V) A general I/O power supply provides power to the GPIO, flash and I2C blocks. A stable and clean power source is desired. Use proper bypass capacitors to provide a clean power source with good stability. A typical capacitor value combination is 0.1µF, and 2.2 µF.
4-10 Copyright © 2015 Marvell April 23, 2015
Power Supply Doc No. MV-S105606-00 Rev. J Document Classification: Proprietary
Part 1: Chip Overview Layout Guidelines
4.3.5
Bias Current Resistor (RSET) Connect a 6.04KΩ (1%) resistor between the ISET pin and the adjacent top ground plane. This resistor should lie as close as possible to the ISET pin. Avoid routing noisy signals close to the ISET pin.
Power Supply Copyright © 2015 Marvell April 23, 2015
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88SE9480/88SE9485 R3.3 Eight-Lane PCI-Express 2.0 to Eight-Port SAS/SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
4.4
PCB Trace Routing The stack-up parameters for the reference board are shown in Table 4-1. Table 4-1 PCB Board Stack-up Parameters Layer
Layer Description
Copper Weight (oz)
Target Impedance (±10%)
1
Signal
0.5
50
2
GND
1
N/A
3
Power and Signal
1
50
4
Power
1
N/A
5
GND
1
N/A
6
Signal
0.5
50
\
4-12 Copyright © 2015 Marvell April 23, 2015
PCB Trace Routing Doc No. MV-S105606-00 Rev. J Document Classification: Proprietary
Part 1: Chip Overview Layout Guidelines
4.5
Recommended Layout High-speed designs must consist of a good board stack-up and careful consideration of the power planes. For the 88SE9480/88SE9485, the following power planes are required:
VDDIO_C, VDDIO_D, and VDDIO_P power plane (3.3V power source for the digital I/O pins)
VDD (1.0V power source for the core and digital circuitry)
VAA (2.5V power source for SAS/SATA analog)
AVDD (1.8V power source for PCIe analog)
Solid ground planes are recommended. However, special care should be taken when routing VAA, AVDD, and VSS pins. The following general tips describe what should be considered when determining your stack-up and board routing. These tips are not meant to substitute for consulting with a signal-integrity expert or doing your own simulations. Note: Specific numbers or rules-of-thumb are not used here because they might not be applicable in every situation.
Do not split ground planes. Keep good spacing between possible sensitive analog circuitry on your board and the digital signals to sufficiently isolate noise. A solid ground plane is necessary to provide a good return path for routing layers. Try to provide at least one ground plane adjacent to all routing layers (see Figure 4-5).
Keep trace layers as close as possible to the adjacent ground or power planes. This helps minimize crosstalk and improve noise control on the planes.
Figure 4-5 Trace Has At Least One Solid Plane For Return Path
GND V2
V1
When routing adjacent to only a power plane, do not cross splits. Route traces only over the power plane that supplies both the driver and the load. Otherwise, provide a decoupling capacitor near the trace at the end that is not supplied by the adjacent power plane.
Critical signals should avoid running parallel and close to or directly over a gap. This would change the impedance of the trace.
Separate analog powers onto opposing planes. This helps minimize the coupling area that an analog plane has with an adjacent digital plane.
Recommended Layout Copyright © 2015 Marvell April 23, 2015
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88SE9480/88SE9485 R3.3 Eight-Lane PCI-Express 2.0 to Eight-Port SAS/SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
For dual strip-line routing, traces should only cross at 90 degrees. Avoid more than two routing layers in a row to minimize tandem crosstalk and to better control impedance.
Planes should be evenly distributed in order to minimize warping.
Calculating or modeling impedance should be made prior to routing. This helps ensure that a reasonable trace thickness is used and that the desired board thickness is available. Consult with your board fabricator for accurate impedance.
Allow good separation between fast signals to avoid crosstalk. Crosstalk increases as the parallel traces get longer.
When packages become smaller, route traces over a split power plane Smaller packages force vias to become smaller, thereby reducing board thickness and layer counts, which might create the need to route traces over a split power plane. Some alternatives to provide return path for these signals are listed below. Caution must be used when applying these techniques. Digital traces should not cross over analog planes, and vice-versa. All of these rules must be followed closely to prevent noise contamination problems that might arise due to routing over the wrong plane. By tightly controlling the return path, control noise on the power and ground planes can be controlled.
Place a ground layer close enough to the split power plane in order to couple enough to provide buried capacitance, such as SIG-PWR-GND (see Figure 4-6). Return signals that encounter splits in this situation simply jumps to the ground plane, over the split, and back to the other power plane. Buried capacitance provides the benefit of adding low inductance decoupling to your board. Your fabricator may charge for a special license fee and special materials. To determine the amount of capacitance your planes provide, use the following equation: C = 1.249 • 10
– 13
• Er • L • W ⁄ H
Where ER is the dielectric coefficient, L • W represents the area of copper, and H is the separation between planes.
Provide return-path capacitors that connect to both power planes and jumps the split. Place them close to the traces so that there is one capacitor for every four or five traces. The capacitors would then provide the return path (see Figure 4-7).
Allow only static or slow signals on layers where they are adjacent to split planes.
Figure 4-6 shows the ground layer close to the split power plane. Figure 4-6 Close Power and Ground Planes Provide Coupling For Good Return Path
V2 PLANE
H V1 PLANE GND PLANE
4-14 Copyright © 2015 Marvell April 23, 2015
Recommended Layout Doc No. MV-S105606-00 Rev. J Document Classification: Proprietary
Part 1: Chip Overview Layout Guidelines
Figure 4-7 shows the thermal ground plane in relation to the return-path capacitor. Figure 4-7 Suggested Thermal Ground Plane On Opposite Side of Chip V2
V1
Recommended Layout Copyright © 2015 Marvell April 23, 2015
4-15 Doc No. MV-S105606-00 Rev. J Document Classification: Proprietary
88SE9480/88SE9485 R3.3Eight-Lane PCI-Express 2.0 to Eight-Port SAS/SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
THIS PAGE LEFT INTENTIONALLY BLANK
4-16 Copyright © 2015 Marvell April 23, 2015
Recommended Layout Doc No. MV-S105606-00 Rev. J Document Classification: Proprietary
Part 1: Chip Overview Electrical Specifications
5
ELECTRICAL SPECIFICATIONS This chapter contains the following sections:
Absolute Maximum Ratings
Recommended Operating Conditions
DC Electrical Characteristics
Thermal Data
AC Timing
5-1 Copyright © 2015 Marvell April 23, 2015
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88SE9480/88SE9485 R3.3 Eight-Lane PCI-Express 2.0 to Eight-Port SAS/SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
5.1
Absolute Maximum Ratings Table 5-1 Absolute Maximum Ratings Parameter
Symbol
Minimum
Typical
Maximum
Units
Absolute Analog Power for PCIe PHY
AVDD[8:0]
1.62
1.8
1.98
V
Absolute Analog Power for SAS/SATA PHY, Chip PLL
VAA[7:0], VAA_ANA
2.25
2.5
2.75
V
Absolute Power for Digital Core
VDD
0.9
1.0
1.1
V
Absolute Digital I/O Power
VDDO1/VDDO2 3
3.3
3.6
V
CAUTION: Exposure to conditions at or beyond the maximum rating may damage the device. Operation beyond the recommended operating conditions (Table 5-2) is neither recommended nor guaranteed. Note: Before designing a system, it is recommended that you read application note AN-63: Thermal Management for Marvell Technology Products. This application note presents basic concepts of thermal management for integrated circuits (ICs) and includes guidelines to ensure optimal operating conditions for Marvell Technology's products.
5-2 Copyright © 2015 Marvell April 23, 2015
Absolute Maximum Ratings Doc No. MV-S105606-00 Rev. J Document Classification: Proprietary
Part 1: Chip Overview Electrical Specifications
5.2
Recommended Operating Conditions Table 5-2 Recommended Operating Conditions Parameter
Symbol
Minimum
Typical
Maximum
Units
Analog Power for PCIe PHY
AVDD[8:0]
1.71
1.8
1.89
V
Analog Power for SAS/SATA PHY, Chip PLL
VAA[7:0], VAA_ANA
2.38
2.5
2.63
V
Digital Core Power
VDD
0.95
1.0
1.05
V
Digital I/O Power
VDDO1/VDDO2 3.14
3.3
3.47
V
Internal Bias Reference
ISET, PIN_ISET 5.74
6.04
6.34
KΩ
Ambient Operating Temperature
TA
0
N/A
70
°C
Junction Operating Temperature
TJ
0
N/A
125
°C
CAUTION: Operation beyond the recommended operating conditions is neither recommended nor guaranteed.
Recommended Operating Conditions Copyright © 2015 Marvell April 23, 2015
5-3 Doc No. MV-S105606-00 Rev. J Document Classification: Proprietary
88SE9480/88SE9485 R3.3 Eight-Lane PCI-Express 2.0 to Eight-Port SAS/SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
5.3
DC Electrical Characteristics Table 5-3 DC Electrical Characteristics Parameter
Symbol Minimum
Typical
Maximum
Units
Analog Power for PCIe PHY 1.8V
IAVDD
N/A
0.78
N/A
A
Analog Power for SAS/SATA PHY 2.5V, IVAA Chip PLL
N/A
0.78
N/A
A
Digital Core Power
IVDD
N/A
2.0
N/A
A mA
Digital I/O Power
IVDDO
N/A
50
N/A
Input Low Voltage of Digital I/O
VIL
-0.4
N/A
0.3 × VDDOx V
Input High Voltage of Digital I/O
VIH
0.7 × VDDOx N/A
VDDOx + 0.4 V
Output Low Voltage of Digital I/O
VOL
N/A
0.13
N/A
V
Output High Voltage of Digital I/O
VOH
2.0
VDDOx*
N/A
V
* VDDOx: VDDO1/VDDO2.
CAUTION: Operation beyond the recommended operating conditions is neither recommended nor guaranteed.
Table 5-4 shows the internal pull-up and pull-down strength. Table 5-4 Internal Pull-Up and Pull-Down Strength Specifications
Condition
Minimum
Nominal
Maximum Unit
Pull-Up Strength
V(PAD) = 0.5 × VDDO
10
N/A
50
µA
V(PAD) = 0
10
N/A
65
µA
V(PAD) = 0.5 × VDDO
10
N/A
50
µA
Pull-Down Strength
5-4 Copyright © 2015 Marvell April 23, 2015
DC Electrical Characteristics Doc No. MV-S105606-00 Rev. J Document Classification: Proprietary
Part 1: Chip Overview Electrical Specifications
5.4
Thermal Data It is recommended to read application note AN-63 Thermal Management for Selected Marvell® Products (Document Number MV-S300281-00) and the ThetaJC, ThetaJA, and Temperature Calculations White Paper, available from Marvell, before designing a system. These documents describe the basic understanding of thermal management of integrated circuits (ICs) and guidelines to ensure optimal operating conditions for Marvell products. Table 5-5 provides the thermal data for the 88SE9480/88SE9485. The simulation was performed according to JEDEC standards. The heat sink is 25.4 mm × 25.4 mm × 25 mm. Table 5-5 shows the values for the package thermal parameters for the484-ball HSBGA mounted on a 4-layer PCB. Table 5-5 Package Thermal Data, 4-Layer PCB* Airflow Value Parameter
Definition 0 m/s
1 m/s
2 m/s
3 m/s
θJA
Thermal resistance: junction to ambient (no heat sink)
16.2 C/W
13.9 C/W
13.0 C/W
12.6 C/W
θJA
Thermal resistance: junction to ambient (with heat sink)
11.7 C/W
8.4 C/W
7.8 C/W
7.6 C/W
θJC
Thermal resistance: junction to case
5.30 C/W
N/A
N/A
N/A
* All data is based on parts mounted on a 4” x 4.5” JEDEC 4L PCB.
Thermal Data Copyright © 2015 Marvell April 23, 2015
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88SE9480/88SE9485 R3.3 Eight-Lane PCI-Express 2.0 to Eight-Port SAS/SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
5.5
AC Timing This section discusses the following topics:
5.5.1
SATA
PCIe
Parallel Flash and NVSRAM
SATA This product conforms to AC timing requirements as specified in the Serial ATA Revision 3.0 Specification (www.sata-io.org).
5.5.2
PCIe This product conforms to AC timing requirements as specified in the PCIe® Base 2.0 specification (www.pcisig.com/).
5.5.3
Parallel Flash and NVSRAM This section describes the timing for Parallel Flash and NVSRAM.
5-6 Copyright © 2015 Marvell April 23, 2015
AC Timing Doc No. MV-S105606-00 Rev. J Document Classification: Proprietary
Part 1: Chip Overview Electrical Specifications
Figure 5-1 illustrates the Parallel Flash and NVSRAM Read timing, and Table 5-6 provides parameter information for the timing diagram. Figure 5-1 Parallel Flash / NVSRAM Read Timing tRC P_ADDR
Address Valid tRCEH
CE_N tRCEL tOEH OE_N tOEL
P_DATA
Input Data Valid tACC
Table 5-6 Timing Parameters for Figure 5-1, Parallel Flash / NVSRAM Read Timing Parameter
Description
tRC
Read Cycle Time
tRCEL
Read CE Assert Time
NVSRAM
Parallel Flash
Unit ns
(NV_RD_CYCLE_TM
(FLSH_RD_CYCLE_TM
(R0C968h [7:0]) + 2) × Tclk
(R0C978h [7:0]) + 2) × Tclk
(NV_RD_CE_ASSRT_TM
(FLSH_RD_CE_ASSRT_TM
ns
(R0C96Ch [23:16]) + 1) × (R0C97Ch [23:16]) + 1) × Tclk Tclk tRCEH
Read CE Deassert Time
(NV_RD_CE_DEASSRT_T (FLSH_RD_CE_DEASSRT_TM ns M (R0C96Ch [31:24]) + 2) (R0C97Ch [31:24]) + 2) × Tclk
× Tclk tOEL
Read OE Assert Time
(NV_RD_OE_ASSRT_TM
(FLSH_RD_OE_ASSRT_TM
(R0C96Ch [7:0]) + 1) × Tclk
(R0C97Ch [7:0]) + 1) × Tclk
ns
tOEH
Read OE Deassert Time (NV_RD_OE_DEASSRT_T (FLSH_RD_OE_DEASSRT_TM ns M (R0C96Ch [15:8]) + 2) × (R0C97Ch [15:8]) + 2) × Tclk Tclk
tACC
Read Data Latch Time
(NV_RD_DATA_LTCH_TM (FLSH_RD_DATA_LTCH_TM
(R0C968h [15:8]) + 1) × Tclk - 20
ns
(R0C978h [15:8]) + 1) × Tclk 20
Note: Tclk—Internal system clock cycle, default value is 3.33ns.
AC Timing Copyright © 2015 Marvell April 23, 2015
5-7 Doc No. MV-S105606-00 Rev. J Document Classification: Proprietary
88SE9480/88SE9485 R3.3 Eight-Lane PCI-Express 2.0 to Eight-Port SAS/SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
Figure 5-2 illustrates the Parallel Flash and NVSRAM Write timing, and Table 5-7 provides parameter information for the timing diagram. Figure 5-2 Parallel Flash / NVSRAM Write Timing
tWC P_ADDR
Address Valid tWCEH
CE_N tWCEL tWEH WE_N tWEL
P_DATA
Output Data Valid tDL tDH
Table 5-7 Timing Parameters for Figure 5-1, Parallel Flash / NVSRAM Read Timing Parameter
Description
tWC
Write Cycle Time
tWCEL
tWCEH
NVSRAM
Write CE Assert Time
Write CE Deassert Time
Parallel Flash
Unit ns
(NV_WRT_CYCLE_TM
(FLSH_WRT_CYCLE_TM
(R0C960h [7:0]) + 2) × Tclk
(R0C970h [7:0]) + 2) × Tclk ns
(NV_CE_ASSRT_TM
(FLSH_CE_ASSRT_TM
(R0C960h [15:8]) + 1) × Tclk
(R0C970h [15:8]) + 1) × Tclk
(NV_CE_DEASSRT_TM
(FLSH_CE_DEASSRT_TM
ns
(R0C960h [23:16]) + 2) × (R0C970h [23:16]) + 2) × Tclk Tclk ns
tWEL
Write WE Assert Time
tWEH
Read WE Deassert Time (NV_WRT_WE_DEASSRT (FLSH_WRT_WE_DEASSRT_T ns _TM (R0C964h [15:8]) + M (R0C974h [15:8]) + 2) × Tclk 2) × Tclk
tDL
Write Data IO Enable Time
(NV_WRT_WE_ASSRT_T (FLSH_WRT_WE_ASSRT_TM M (R0C964h [7:0]) + 1) × (R0C974h [7:0]) + 1) × Tclk
Tclk
(NV_WRT_DATA_IO_EN_ (FLSH_WRT_DATA_IO_EN_TM ns TM (R0C964h [23:16]) + (R0C974h [23:16]) + 1) × Tclk
1) × Tclk tDH
Write Data IO Disable Time
(NV_WRT_DATA_IO_DSB (FLSH_WRT_DATA_IO_DSBL_ ns L_TM (R0C964h [31:24]) TM (R0C974h [31:24]) + 2) ×
+ 2) × Tclk
5-8 Copyright © 2015 Marvell April 23, 2015
Tclk
AC Timing Doc No. MV-S105606-00 Rev. J Document Classification: Proprietary
Marvell Technology Group www.marvell.com
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