Transcript
Semiconductor Memory Markets, Standards and Test Equipment Backgrounder March 28, 2011
1. Introduction 2. Memory Usage and Applications 3. Memory Market Segments 4. JEDEC 5. Agilent's Industry Leadership 6. Agilent's Digital Applications and Standards Program 7. Related Information Introduction
Memory data rates continue to increase while operating voltages decrease. System and memory designers implementing DDR3 2133 at 1.35 and 1.25 volts and early DDR4 (Double Data-Rate Synchronous DRAM) prototypes are striving for innovations in performance, density and power efficiency in their systems. Reliable measurements and deep analysis that enable market-changing innovations are in critical demand. Probing to obtain functional and signal integrity validation has become critical for reliable performance. Validating signal integrity on all channels of a DDR system with an oscilloscope can be time consuming. Access to the signals for signal integrity characterization is beyond challenging. Sensitive DRAM parts are designed to operate in an environment defined by JEDEC. When designers push beyond JEDEC specifications to achieve higher performance, system reliability can suffer. Innovations in monitoring and triggering on DDR3 protocol violations allow rapid capture of protocol flow around violations, insight into the root cause of violations, and visibility into effects on system performance. Memory Snapshot Memory can be found in an ever-widening variety of products from computers to cameras, telephones and greeting cards. According to industry experts, the memory bus is often the most challenging part of a design. A typical memory bus connects memory devices to a memory controller, and thus the processor, over dozens to hundreds of wires -- many operating at multi-gigabit speeds -- that are crowded close together. A memory interface is a high-speed interface that uses a large proportion of a computer's power, so manufacturers face pressure to design buses that use power more efficiently and thereby reduce costs. The need for even higher-speed interconnects continues to accelerate and is driving the architecture of next-generation memories. However, there are physical limits to how much memory can be handled at next-generation speeds. As a result, memory devices and memory architectures are changing to satisfy the demand for higher performance. These changes drive the need for new standards. As memory technologies become more complex and operate at faster speeds, it becomes more critical for standards bodies to take test and measurement requirements into account while they are writing new specifications. Otherwise, engineers may be unable to characterize the performance of their devices or prove compliance with the spec. Measurements are central to the diagnosis of problems and to proving the correct fix has been applied. "We are focused on working with organizations and companies that rely on these new technologies for their business and strategic success," said Perry Keller, memory program manager at Agilent Technologies. "Our goal is to enable them to successfully develop new
memory technologies and deploy them in their products. Assuring 'design for test' is a key way Agilent contributes to the standards groups, and it provides tremendous benefit to engineers and consumers throughout the world." Memory Usage and Applications
Memory is segmented into various application areas, which continue to evolve as market demands change. Computer and chip manufacturers seek high performance and reliable operation at low costs while maintaining compatibility between products and technologies. They face a number of challenges: they need to take advantage of the higher speeds to nextgeneration flash memory, the down deployment of desktop technology into embedded applications and the launch of GDDR5 (fifth-generation graphics double data rate memory) graphics-based cards. At the same time, they must meet the market demands of the desktop and server sectors for higher speed and lower power.. Working with organizations such as the Joint Electron Devices Engineering Council (JEDEC) to establish standards is key to their success.
Figure 1: Memory Market Segments and Industry Structure Memory Market Segments
Computer memory for desktops, laptops, non-handheld gaming products and servers consists of dynamic random access memory (DRAM). DRAM stores each bit of data in a separate capacitor with a single transistor used to detect the charge on the capacitor. This provides structural simplicity, high density and low cost. This is the largest market segment. DDR memory is the most common form of memory in computer systems. DDR is the acronym for double data-rate synchronous DRAM (SDRAM). Introduced in 2000, DDR continues to evolve to meet the demands of computer and mobile computing markets. DDR provides the ability to fetch data on both the rising and falling edge of a clock cycle, doubling the data rate for a given clock frequency. For example, a DDR3 2133 device transfers data at 2133 Mb/s, using a bus clock frequency of 1066 MHz. DDR memory accesses are burst oriented: An access starts at a selected location and continues for the burst length (bursts of 4 or 8 reads or writes are typical). In DDR memory systems, data and data strobe (DQ/DQS) signals are bidirectional, which adds complexity to functional and signal integrity testing. This complexity increases as data rates increase.
JEDEC approved increasing DDR3 data rates up to 2133 Mb/s per pin and allowing an operating voltage of 1.35 or 1.25 volts from the original DDR3 standard of 1600 Mb/s and 1.5 volts. DDR3's built-in power conservation features, are desirable for mobile applications. For example, the partial refresh feature eliminates the need to use battery power to refresh a portion of the DRAM not in active use. DDR3 also has a specification for an optional thermal sensor that allows engineers designing mobile products to save power by providing minimum refresh cycles. DDR3 memory modules use "fly-by" routing where the address and control lines lie on a single path chaining from one DRAM to another. This routing produces a natural time delay from one DRAM on the chain to the next. The memory controller must use special modes and commands in the JEDEC standard to calculate and remember these delays to assure reliable data transfer. Characterizing and debugging DDR buses often requires triggering on timing and protocol violations. Some of the timing specifications are asynchronous and specified in terms of pure time (such as ns or ps). Most, however, are specified in terms of the number of clock cycles that must occur between specific signal edges. Examples include read or write latency or the minimum time between issuing certain types of command sequences. Because they run at double the DRAM clock rate (DDR), signal integrity measurements are a very important requirement for the DQ data lines. Agilent is working to support all of the interface standards and is helping define and drive the development of the DDR4 specification, which is being reviewed by JEDEC and is expected to be completed in late 2011 Graphics memory is generally one or two generations faster than computer DRAM chips, and it is meant for higher-speed devices. This market segment is growing because of the rise of next-generation technology for gaming systems and high-end, special-purpose computers. A number of industry players are moving toward graphics double data rate, version 5 (GDDR5)., The GDDR standards are specified by JEDEC. Embedded memory is used in electronic devices such as MP3 players, cell phones and car stereos. It is based on computer DRAM technology but has been modified to better fit the needs of battery-operated devices that are designed to operate at reduced power at the expense of speed. The demand to create handheld devices with the power of today’s laptop and desktop computers is fueling tremendous growth in the embedded memory market. Today’s mainstream embedded technology, LPDDR (400 MT/s), is rapidly being replaced by LPDDR2 (up to 1067 MT/s), which will itself be supplanted by LPDDR3 and a radical chipstacking memory technology known as Wide-IO over the next few years. Because of the low power, unterminated architecture of LPDDR buses, signal integrity problems have proliferated and are forcing the entire industry to upgrade or replace the relatively simple test equipment they have used for many years. Traditional DDR memory usually finds its way into embedded designs 2-3 years after its first use in computers. The spiraling demand for HD and 3D multimedia has accelerated the deployment of high-speed DDR3 memory almost as fast as the next faster DDR3 memory becomes available. As a result, this market has one of the fastest growth rates. Flash memory is exploding as GPS systems, mobile devices, digital cameras and personal digital assistants (PDAs) gain momentum. A non-volatile memory retains its contents even when the power is turned off, and it can be electronically erased and reprogrammed. Flash offers fast read access times, durability and the ability to handle extreme temperatures. According to a Wikipedia posting, as of 2006, the flash memory industry stood at $20 billion and comprises more than 34 percent of the semiconductor memory market. Currently, industry leaders such as Intel and Samsung have developed flash memory interfaces that aren't compatible, leading to more competition (and confusion) in the market. Currently the next generation of flash memory chips, called Future NAND, is being developed in JEDEC in collaboration with the Open NAND Flash Initiative (ONFI). Future NAND does not eliminate the differences between the two standards but does provide for increased pinout compatibility. This standard will be published by JEDEC in 2011.
Agilent supports all of the interface standards. Most consumers’ experience with flash memory is in the form of flash modules such as compact flash or secure digital modules memory sticks or multimedia cards. To take advantage of the higher speeds of Future NAND and support the ultra-high throughput required by HD multimedia content, a new generation of flash module standards is in development. JEDEC is driving the development of the universal flash storage (UFS) standard (V1.0 was released in early 2011), while the Secure Digital Association is developing an ultra-high speed II (UHS-II) standard. These standards are incompatible, and it's impossible to say if one of them will become dominant. However, Agilent is active in aiding the development of both standards. Agilent is responsible for drafting the official compliance test specification for UHS-II and is a member of the UFS Association Board of Directors, with responsibility for designing the compliance and technology enablement ecosystem for UFS. Agilent's exclusive involvement in these key activities enables us to support the earliest developers of products using these technologies. Solid state drive (SSD) memory is an emerging sector that is poised for significant growth in the next several years. This type of memory, which has been adopted by the industrial, automotive, computer and military sectors, offers high performance, high reliability and low power consumption in packages smaller than traditional rotating disk drives. SSD is priced higher than rotating disk drives, but the cost is decreasing rapidly, which is driving rapid market growth. JEDEC (www.jedec.org)
JEDEC was formed in 1958 as part of an alliance with the Electronic Industries Association (EIA) to develop standards for the emerging semiconductor industry. In 1999, JEDEC was incorporated as an independent association, and the organization adopted the name JEDEC Solid State Technology Association. Today, JEDEC's core mission is to facilitate the creation of voluntary standards that are open, accessible and developed quickly to meet industry demands. With more than 3,000 volunteers representing nearly 300 companies, JEDEC committees provide industry leadership in developing standards for a broad range of technologies. As the leading developer of standards for the microelectronics industry, JEDEC standards include virtually every key standard for semiconductor memory technology on the market today. One of JEDEC's core values is the ability to develop standards for all aspects of a memory system -- including components, packages, testing and quality and reliability -- to address the needs of all memory applications. Agilent�s Industry Leadership
Agilent Technologies has built a strong position by helping the memory industry focus on customer needs, including keeping up with higher signaling speeds, aiming for lowering development costs and addressing the growth of multimedia applications. Agilent's memoryspecific offerings are the broadest and deepest in the industry. Agilent's involvement with organizations such as JEDEC makes it possible to support key customers even as standards are still in development and devices are prototyped with correspondingly advanced support as memory technology segments continue to evolve. Presently, Agilent supports all of the memory technology areas and is contributing measurement expertise to help define the specifications required by each standard. Agilent’s support spans the complete development lifecycle from pre-silicon design (thru the industry leading Advanced Design System EDA toolset), silicon prototype evaluation and testing, and advanced probing and measurement of signal integrity and protocol traffic in complete systems. In the last several years, memory innovation -- serial and low-power memory speeds, mobile and desktop applications, and non-volatile flash memory -- has exploded. The entire industry relies on Agilent to help enable these advances through its understanding of both digital and microwave design and test. Agilent will continue to pay close attention to these innovations as the rise in consumer demand for greater bandwidth and the convergence of computing and communications drive the need for faster, larger and lower-power memory. Agilent's portfolio of test instruments addressing the various memory test challenges includes: The U4154A logic analysis module with 4.0-Gb/s state speed and 2.5-GHz trigger
sequence speed enables full capability to reliably trigger and capture DDR3 2133 signals. When used with new DDR3 probing solutions and analysis software tools, this module provides full test capability for system integration in the memory industry. 9000 Series Infiniium Oscilloscopes -- 1-GHz to 4-GHz digital storage and mixed signal oscilloscopes with 10 Mpts of standard memory are engineered for the broadest measurement capability. They combine the powerful features of Infiniium scopes, the ability to see critical data values and timing relationships and the first scope-based protocol viewer. 90000A Series Infiniium Oscilloscopes -- 2.5-GHz to 13-GHz high-performance real-time lab scopes offer 1 Gpts deep memory, the industry's only hardware-software triggering combination, upgradeable bandwidth, and the industry's lowest noise floor. The 16962A logic analysis module with 2.0-Gb/s state speed and 2-GHz trigger sequence speed enables full capability to reliably trigger and capture DDR3 1600 signals. When used with the new DDR3 probing solution and analysis software tool, this module provides full test capability for system integration in the memory industry. J-BERT N4903A/B high-performance serial BERT -- Up to 12.5 Gb/s-pattern generator and error detector with built-in jitter injection offers the most complete jitter tolerance testing of receivers using embedded and forwarded clock architectures. Using the J-BERT with the Agilent N4916A de-emphasis signal converter, R&D engineers can evaluate their receiver's tolerance under real and worst-case channel and de-emphasis conditions. Agilent Technologies and its partners provide an extensive range of quality tools that offer non-intrusive, full-speed, real-time analysis of buses, FPGAs, protocols and processors. Engineers can save time working with their unique designs by using application-specific analysis probes, protocol solutions, inverse assemblers and bus cycle decode software. Probing Solutions
The W2630A Series DDR2 BGA probe adapters enable viewing of data traffic on industry-standard DDR2 DRAMs with the Agilent 16900 Series logic analysis system and Infiniium 90000 Series oscilloscopes.
The W3630A Series DDR3 BGA probe adapters provide signal access to the clock, strobe, data, address and command signals to the DDR3 BGA package for making electrical and timing measurements with an Infiniium oscilloscope and for functional testing with a logic analyzer. The DDR3 JEDEC specification (JESD79-3C) is defined at the DRAM ballout; the BGA probe adapter provides direct signal access to the BGA package for true compliance testing.
The W2637A, W2678A and W2639A low-power double data rate (LPDDR) probing solution provides signal access points for LPDDR and mobile-DDR synchronous dynamic random access memory (SDRAM) for electrical, timing and protocol characterization. It is an ideal probing solution at the LPDDR and mobileDDR BGA package ballout, as defined in the JESD209A LPDDR SDRAM standard.
FuturePlus FS2352 and Nexus Technology NT-DDR3DIHS interposers provide quick and easy access to the industry's standard DDR3 DIMM for full 1867 Mb/s DDR3 speed debug and validation.
Custom probing solutions are offered by Agilent's application engineering team. The same advanced technology used to develop Agilent's BGA probes can be applied to the development of custom probes for standard or non-standard devices. Agilent's field applications engineers work with customers to define the requirements, evaluate possible solutions (including providing simulation models to assure proper operation in the customer's design), and supervise the design and fabrication of custom probes.
Analysis software
The B4622A DDR protocol compliance and analysis software offers automated protocol compliance testing per JEDEC specifications and provides performance analysis capability through bus statistics information and a histogram view of address access count.
The B4623A LPDDR/LPDDR2 protocol compliance and analysis software offers automated protocol compliance testing per JEDEC specifications and provides performance analysis capability through bus statistics information and a histogram view of address access count.
The U7233A DDR1 compliance test application software with LPDDR and mobile-DDR support offers automated testing, debugging and characterizing of DDR1 designs and provides an informative HTML report comparing the results with JEDEC specification test limits.
The N5413A DDR2 compliance test application software performs a combination of clock jitter measurements and electrical tests to help engineers thoroughly evaluate DDR2 devices in accordance with the JEDEC specification. It provides a fast, easy way to test, debug and characterize DDR2 devices operating as fast as 1066 MT/s.
The U7231A DDR3 compliance test application software offers a user-friendly setup wizard and comprehensive report to provide a fast and easy way for engineers to test, debug and characterize DDR3 designs based on the JEDEC DDR3 SDRAM Specification. Advanced debug mode covers crucial measurements such as eyediagram, mask testing, ringing and other tests critical for characterizing the higher bandwidth and smaller-chip footprints of DDR3 devices.
Agilent's Digital Test Standards Program
Agilent's measurement solutions and services development for digital applications is driven and supported by the work done by Agilent's experts in various international standards committees. The Agilent Digital Applications and Standards Program comprises DDR, flash and embedded memory, PCI Express®, DisplayPort, Universal Serial Bus (USB), Serial ATA (SATA), High-Definition Multimedia Interface (HDMI), standards developed by the MIPI Alliance (DigRF, D-Phy, M-Phy, Unipro, CSI, QPI, etc.) and optical transceiver test. Our experts are on the board of directors of the Joint Electronic Devices Engineering Council (JEDEC), PCI-SIG® and Video Electronics Standards Association (VESA). Agilent is a contributing member of the Serial ATA International Organization (SATA-IO), USBImplementers Forum (USB-IF) and Mobile Industry Processor Interface (MIPI) Alliance. Agilent's involvement in these standards gives Agilent and its customers two main advantages:
First, it enables us to bring the right products to the market when our customers need them. We aim to be first to market with our solutions so our customers can be first to market with their standards-compliant products.
Second, with Agilent's involvement in plug-fests, workshops and seminars, we are in the unique position to develop solutions that evolve with the standards, giving our customers the ability to design the best products with the highest confidence.
PCI Express and PCI-SIG are registered trademarks of the PCI-SIG. RELATED INFORMATION
Press Release:
Agilent Technologies Introduces Industry’s Fastest Logic Analyzer (2011-March-28)
Agilent Technologies, Nexus Technology Deliver DDR3 Memory Bus Debug Solutions (2009-November-9)
Agilent Technologies Introduces Industry-First, Most Comprehensive DDR3 Test Suite with Industry's Fastest Full Channel Logic Analysis Tool (2009-February-3) Contacts:
Janet Smith, Americas +1 970 679 5397
[email protected] Sarah Calnan, Europe +44 (118) 927 5101
[email protected] Iris Ng, Asia +852 31977979
[email protected]
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