Transcript
CDX-C5750/C5850 SERVICE MANUAL
US Model CDX-C5750/C5850
Canadian Model CDX-C5750
Photo: CDX-C5750
SPECIFICATIONS
Model Name Using Similar Mechanism
AUDIO POWER SPECIFICATIONS (US Model) POWER OUTPUT AND TOTAL HARMONIC DISTORTION 17 watts per channel minimum continuous average power into 4 ohms, 4 channels driven from 20 Hz to 20 kHz with no more than 1% total harmonic distortion.
CD Drive Mechanism Type
MG-363T-121
Optical Pick-up Name
KSS-521A
Other Specifications CD player section
Power amplifier section
System
Outputs
Compact disc digital audio system 90 dB 10 – 20,000 Hz Below measurable limit
Signal-to-noise ratio Frequency response Wow and flutter Laser Diode Properties Material GaAlAs Wavelength 780 nm Emission Duration Continuous Laser output power Less than 44.6 µW* * This output is the value measured at a distance of 200 mm from the objective lens surface on the Optical Pick-up Block.
Speaker outputs (sure seal connectors) Speaker impedance 4 – 8 ohms Maximum power output 40 W × 4 (at 4 ohms)
General Outputs
Tone controls
Tuner section FM
Tuning range Antenna terminal Intermediate frequency Usable sensitivity Selectivity Signal-to-noise ratio
87.5 – 107.9 MHz External antenna connector 10.7 MHz 12 dBf 75 dB at 400 kHz 65 dB (stereo), 68 dB (mono) Harmonic distortion at 1 kHz 0.7% (stereo), 0.5% (mono) Separation 35 dB at 1 kHz Frequency response 30 – 15,000 Hz AM
CDX-C480/C580
Power requirements Dimensions
Mounting dimensions
Mass Supplied accessories
Line outputs (2) Power antenna relay control lead Power amplifier control lead Telephone ATT control lead Bass ±8 dB at 100 Hz Treble ±8 dB at 10 kHz 12 V DC car battery (negative ground) Approx. 178 × 50 × 185 mm (7 1/8 × 2 × 7 3/8 in.) (w/h/d) Approx. 182 × 53 × 162 mm (7 1/4 × 2 1/8 × 6 1/2 in.) (w/h/d) Approx. 1.2 kg (2 lb. 10 oz.) Parts for installation and connections (1 set) Front panel case (1)
Design and specifications are subject to change without notice.
Tuning range 530 – 1,710 kHz Antenna terminal External antenna connector Intermediate frequency 10.7 MHz/450 kHz Sensitivity 30 µV
FM/AM COMPACT DISC PLAYER MICROFILM
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CDX-C5750/C5850
(Page 33)
4-5. SCHEMATIC DIAGRAM — CD MECHANISM SECTION — • Refer to page 41 for IC Block Diagrams. • Refer to page 24 for Waveforms.
note: • Voltage and waveforms are dc with respect to ground under no-signal conditions. no mark : CD PLAY : Impossible to measure ∗
– 27 –
– 28 –
CDX-C5750/C5850
(Page 28)
4-7. SCHEMATIC DIAGRAM — MAIN SECTION (1/2) — • Refer to page 41 for IC Block Diagrams.
(Page 35)
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note: • Voltage is dc with respect to ground under no-signal (detuned) condition. no mark : FM ( ) : AM < > : CD PLAY
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CDX-C5750/C5850
4-8. SCHEMATIC DIAGRAM — MAIN SECTION (2/2) — • Refer to page 43 for IC Block Diagrams.
(Page 34)
(Page 39)
MB90574PFV-G-193-BND
note: • Voltage is dc with respect to ground under no-signal (detuned) condition. no mark : FM ( ) : AM < > : CD PLAY
– 35 –
– 36 –
CDX-C5750/C5850
4-10. SCHEMATIC DIAGRAM — DISPLAY SECTION —
(Page 36)
note: • Voltage is dc with respect to ground under no-signal (detuned) condition. no mark : FM
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– 40 –
• IC Block Diagrams
LD
RF M
RF O
RF I
CP
CB
CC1
36
35
34
33
32
31
30
29
28
27 26 25
FOK
CC2
PHD
64 63 62 61 60 59 58 57 56 55 54 53 52
PHD 1
SEIN CLOK XLAT
VDD XLTO DATO CNIN
XLON SPOD SPOC SPOB SPOA CLKO
IC2 CXA1782BQ PHD 2
IC402, 403 TDA8574 (CDX-C5850 only)
IC1 CXD2507AQ
VCCL 1 INL 2
FILO
7
FILI PCO VSS AVSS CLTV AVDD
8 9 10 11 12 13
SUB CODE PROCESSOR
CPU INTERFACE
14
EFM DEMODULATOR
DIGITAL PLL
REFERENCE
VCCL SIGNAL AMP
INML 4
ERROR CORRECTOR
6
3
15 CL–
14 LGND
12 OUTR
39 DOUT
MIRR
11 RGND RF IV AMP1
REFERENCE 38 37 36 35 34
WDCK 19
LEVEL S
APC
VCCR
SIGNAL AMP
DIGITAL OUT
16 CL+
13 OUTL
INMR 5
D/A INTERFACE
16K RAM
LIFT AMP
BUFFER
ASYMMETRY CORRECTOR
14 15 16 17 18
VCCL
SVRL 3
3
5
C4M FSTT XTSL XTAO XTAI
SVRR 6
33 MNTO
INR 7
BUFFER
24
SENS
TTL
23
C.OUT
22
XRST
21
DATA
20
XLT
19
CLK
18
VCC
17
ISET
16
SL O
15
SL M
14
SL P
13
TA O
10 CR– 9
BUFFER
CR+
TTL RF IV AMP2
TTL
FE BIAS 37
IIL DATA REGISTER
INPUT SHIFT REGISTER
VCCR 8
ADDRESS DECODER
GTOP XUGF XPCK VDD GFS RFCK C2PO XROF MNT3 MNT1
FE AMP
20 21 22 23 24 25 26 27 28 29 30 31 32 LRCK PCMD BCLK
IIL DFCT
VCCR LIFT AMP
F
IIL IIL
OUTPUT DECODER
38 TOG1-3 BAL1-3
F IV AMP E
39
EI
40
FS1-4
TG1-2
TM1-7
PS1-4
FZC COMP
IC3 BA6796FP-T1
VREF
CH3
CH3-IN
CH2
CH2-IN
VCC
CH1
CH1-IN
CH1 +
CH1 –
CH2 +
CH2 –
27
26
25
24
23
22
21
20
19
18
17
16
15
BAL 3
OP IN +
28
TE AMP BAL2
OP IN –
E IV AMP
BAL1
HPF COMP
DRIVE BUFFER
VCC LEVEL SHIFT
DRIVE BUFFER
DRIVE BUFFER
DRIVE BUFFER
VEE
TRACKING PHASE COMPENSATION
LPF COMP
ISET
41 TM6
TED 42 TOG3
LEVEL SHIFT
TG1 TOG2
LEVEL SHIFT
TOG1
TM5 TM4
THERMAL SHUT DOWN
TEI
TZC
TM3
44
ATSC 45
LEVEL SHIFT
46
FCS PHASE COMPENSATION
TZC COMP
LPFI 43
TM2
DFCT
WINDOW COMP
FS1
TM1
TM7 FS2
ATSC
TDFCT 47
TRAY
GND
13
14
– 41 –
1
2
3
TG2 4
5
6
7
8 9
10
11
12 TA M
REV
12
FSET
FWD
11
TG2
CTL2
10
SRCH
9
FE O
8
FE M
7
FS4
48
FLB
6
VC
FGD
5
DRIVE BUFFER
FDFCT
4
DRIVE BUFFER
FEI
3
DRIVE BUFFER
CH3 –
2
DRIVE BUFFER
CH3 +
1
CTL1
REV
CH4
FWD
CH4-IN
CTL2
OPOUT
CTL1
DRIVE BUFFER
CH4 +
V/I
COM
LOGIC
CH5 –
DFCT
FEO
RF BIAS ASYI ASYO ASYE
DIGITAL CLV
4
BUFFER
F SET
2 3 4 5 6
5
DATA XRST SENS MUTE SQCK SQSO EXCK SBSO SCOR VSS WFCK EMPH
– 42 –
TGU
MON MDP MDS LOCK TEST
51 50 49 48 47 46 45 44 43 42 41 40
FOK
SERVO AUTO SEQUENCER
1
CLOCK GENERATOR
FOK
IC401 TDA7462D
28 27 26 25 24 23
INPUT GAIN & AUTO ZERO
LOUDNESS CONTROL CIRCUIT
VOLUME CONTROL CIRCUIT
SOFT MUTE
TREBLE/ BASS CONTROL CIRCUIT
VOICE BANDPASS HP
FRONT FADER
22 OUT FL
FRONT FADER
21 OUT FR
REAR FADER
20 OUT RL
REAR FADER
19 OUT RR
LP
COMPANDER
REAR SIDE SELECTOR
1 2 3 4 5 6 7 8 9 10 11 12 13
INPUT MULTIPLEXER & MIXING STAGE
SE1L SE1R MD+ MD– CDL+ CDL– CDR– CDR+ PDR PDGND PDL SE2L SE2R
FRONT SIDE SELECTOR
PAUSE DETECT
SE3L SE3R MUTE SDA SCL PAUSE
LOUDNESS CONTROL CIRCUIT
INPUT GAIN
SUBWOOFER LP
BEEP
FADER 18 SUBOUT+
SUBWOOFER OUT
17 SUBOUT– SDA
IIC BUS
DIGITAL CONTROL CIRCUIT
SCL 16 VDD
POWER SUPPLY
CREF 14
IC901 BA4903
IC702 PCM1717E-S
DGND
1 2
VDD
3
XTI
LRCIN 4 DIN
5
BCKIN
6
ZERO
7
5.7V
20 XTO 19 CLKO
CLK CONTROL
ON
18 ML/MUTE
INPUT INTERFACE
MODE CONT ROL
DIGITAL FILTER
ON –
17 MC/DM1
+
+
16 MD/DM0 THERMAL SHUT DOWN
15 RSTB 14 MODE
NOISE SHAPER 5LEVE DAC LOWPASS FILTER
D/C R
8
VOUTR 9 AGND 10
CMOS AMP
15 GND
5LEVEL DAC
CIRCUIT ON
LOWPASS FILTER CMOS AMP
1 AMP ON
13 D/C L 12 VOUTL 11 VCC
– 43 –
2 AMP OUT
3 GND
–
REGULATOR VREF
OVER VOLTAGE PROTECT
4 VCC
5 VDD OUT
IC601 TDA7427AD1
28 LPOUT VDD1 LP FM
1
LP HC
2
LP AM
3
V REF
4
LCL/DX
5
SEEK
6
NIL
7
MONO
8
SWITCH LP1/LP2
CHARGE PUMP
PHASE COMP
SWITCH SWM/DIR INLOCK DETECTOR
PORT EXTENSION
27 VDD2
11 BIT PROG COUNTER
6 BIT PROG COUNTER
26 GND AM
SWITCH SWM/DIR PRE COUNTER :32/33
25 AM IN
SWITCH AM/FM
24 FM IN
TEST LOGIC
23 NC
OSCIN 9 OSCOUT 10
REF OSCILLATOR
SUPPLY & POWER ON RESET
16 BIT PROG COUNTER
22 GND D 21 VDD1
NC 11 SCL 12 SDA 13
20 ADDR 19 HFREF
I2C
BUS INTERFACE
18 AMOSC
14 BIT PROG COUNTER
IF AM 14
SWITCH AM/FM
TIMER
SWITCH OUT
CONTROL
17 DOUT/INLOCK
11-21 BIT PROG COUNTER
16 SSTOP 15 IF FM
IC703 LC89170M-T
IC803 BA8270F-E2
VDD EXCK 1
CPU INTERFACE
32 WORD X 8 BIT DUAL PORT RAM
CRC CHECKER
WFCK 4
MCK 5
XMODE 6
BUS ON SWITCH
RST 2
RESET SWITCH
BATT 3
BATTERY SWITCH
12 SRDT
11 SCLK
TIMING & SYNCHRONIZATION SIGNAL PROTECTION
14 VCC
14 VDD
13 DQSY
SBSO 2
SCOR 3
BUS ON 1
10 SW2
CLK 4 VREF 5 DATA 6 GND 7
9 SW1
GND 7 8 TEST
– 44 –
13 12 11 10
RST BUS ON CLK IN BU IN
9 DATA IN 8 DATA OUT
4-11. IC PIN DESCRIPTION • IC801 MB90574PFV-G-193-BND (SYSTEM CONTROL) Pin No. Pin Name I/O 1 LD ON O Laser ON/OFF control output
Pin Description
2 3
FOK XLAT25
I O
Focus OK signal detection input CD signal processing latch output
4 5
DATA25 XRST
O O
CD signal serial data output Reset output to CD signal processor IC.
6 7
GFS NIL
I —
GFS signal detection input Not used. (Connect to ground in this set.)
8 9 – 11
VCC NIL
— —
Power supply pin (+5 V) Not used. (Open)
12 13
FLS SI/NOSE1 LCD SO/FLS SO
I O
Front panel attachment detection input LCD serial data output
14 15
LCD CKO BEEP
O O
LCD serial clock output BEEP output
16 17
NIL SQ SI
— I
Not used. (Open) Sub Q data input
18 19
NIL SQ CKO
— O
Not used. (Connect to ground in this set.) Sub Q read clock output
20 21
UNI SI UNI SO
I O
BUS system serial interface input BUS system serial interface output
22 23
UNI CK C IN
I/O I
BUS system serial clock input/output Track jump No. count input
24 25 26
SIRCS TXT SI NIL
I I —
Remote commander input CD-TEXT data input Not used. (Connect to ground in this set.)
27 28
TXT CKO CLOK25
O O
CD-TEXT data read clock output CD signal processing serial clock output
29 30
SYSRST DEEMPH
O O
System reset output De-emphasis output
31 32
AMP ATT MD ON
O O
Power amplifier attenuator control output CD mechanism power control output
33 34
VSS C
— —
Ground Power stabilization capacitor pin
35 36
CD ON BUS ON
O O
CD power control output BUS ON control output
37 38
AD ON DVCC
O —
Power control output of A/D conversion. VREF input of D/A converter.
39 40
DVSS NIL
— —
Ground of D/A converter. Not used. (Open)
41 42
ANGLE AVCC
O —
LCD view angle alignment output (Not used in this set.) Analog power supply pin (+5 V)
43 44
AVRH AVRL
— —
VREF + input of A/D converter. VREF – input of A/D converter.
45 46 – 48
AVSS KEY IN0 – 2
— I
Analog ground Key input 0 – 2
49 50
RC IN0 QUALITY
I I
51 52
NIL MPDH
— I
Not used. (Connect to ground in this set.) Tuner multi path input (Not used in this set.)
53 54
S-METER VCC
I —
S-meter voltage detection input Power supply pin (+5 V)
55
NS MASK
O
Not used in this set.
Rotary commander input 0 Not used in this set.
– 45 –
Pin No. 56
Pin Name AMP ON
I/O O
Pin Description Power amplifier power control output
57 58
TXT ON VOL ATT
O O
Reset output to CD-TEXT decoder IC. Electric volume mute control output
59 60
NIL ATT
— O
Not used. (Open) System attenuate control output
61 62
RC IN1 TU ATT
I O
Rotary commander shift key input 1 Tuner attenuate output (Not used in this set.)
63 64
VSS NIL
— —
Ground Not used. (Open)
65 66
SSTOP TEST
I I
IF counter result signal detection input of PLL. Test mode initial setting detection input
67 68
DAVN FM ON/AM ON
I O
RDS IC data acquisition detection input (Fixed at “L” in this set.) FM ON output
69 70
TU ON SDA
O I/O
71 72
SCL NOSE2
O I
I2C BUS serial clock output Front panel OPEN detection input (Not used in this set.)
73 74
X1A X0A
O I
Sub ceramic oscillator output (32 kHz) Sub ceramic oscillator input (32 kHz)
75 76
SCOR BU IN
I I
SCOR signal detection input Backup power detection input
77 78
DQSY CD SENS
I I
CD-TEXT data setting completion signal detection input CD SENS signal detection input
79 80 81
KEY ACK TEL ATT ST/MONO
I I I/O
82 83
SEEKOUT SD IN
O I
SEEK output Signal detector input
84 85
WIDE NARROW
O O
WIDE/NARROW select output (Not used in this set.) WIDE/NARROW select output (Not used in this set.)
86 87
HSTX MD2
— —
Hardware standby input (Connect to pin (º (RESET).) Operation mode input (Connect to ground in this set.)
88, 89 90
MD1, 0 RESET
— I
Operation mode input (Connect to VCC in this set.) Reset input
91 92
VSS X0
— I
Ground Main ceramic oscillator input (4.19 MHz)
93 94
X1 VCC
O —
Main ceramic oscillator output (4.19 MHz) Power supply pin (+5 V)
95 96
COM8V ON NIL
O —
COM 8V control output Not used. (Open)
97 98
AREA1 AREA2
I I
Destination select input 1 (Fixed at “L” in this set.) Destination select input 2 (Fixed at “L” in this set.)
99 100
AREA3 BAND
I I
Destination select input 3 (Fixed at “L” (CDX-C5750) or “H” (CDX-C5850) in this set.) Not used in this set.
101 102, 103
ACC IN PH3, 2
I I
Accessory power detection input Disc insertion detection photo sensor input (Not used in this set.)
104 105
LCD CE FLS W
O I
LCD chip enable output Flash write input (Fixed at “H” in this set.)
106, 107 108
RE IN0, 1 ILL ON
I O
Rotary encoder input Illumination power control output
109 110
PW ON NIL
O —
System power control output Not used. (Open)
111
ANT REM
O
ANT REMOTE power control output
Tuner power control output I2C BUS serial data input/output
Key input acknowledge Telephone attenuate detection input Tuner stereo signal detection input/forced monaural output
– 46 –
Pin No. 112, 113
Pin Name NIL
I/O —
Pin Description
114 115
CD LD CD EJ
O O
Loading motor control output (Loading direction) Loading motor control output (Eject direction)
116 117
L SW IN SW/(PH1)
I I
Sled limit switch detection input Disc insertion detection input
118 119
D SW VSS
I —
DOWN switch detection input Ground
120
SELF SW/(IN SW)
I
Disc self store detection input
Not used. (Open)
– 47 –
