Transcript
LBT PROJECT 2x8,4m TELESCOPE Doc.No.: 641a021 Issue: B Date: 11 August 2008
LBT PROJECT
ADAPTIVE SECONDARY CONTROL SYSTEM
CONTROL SYSTEM MAINTENANCE MANUAL
Document : Issue : Date :
641a021 B 11 August 2008
Prepared by :
MICROGATE R.Biasi M.Andrighettoni D.Veronese
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Checked by :
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Approved by :
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Released by :
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Microgate Srl – Via Stradivari, 4 – 39100 Bolzano – ITALY ADS International Srl –via Roma, 87- 23868 Valmadrera (Lc) – ITALY
LBT PROJECT 2x8,4m TELESCOPE
Doc.No: 641a021 Issue: B Date: 11 August 2008
CHANGE RECORDS
ISSUE
DATE
Author
A
30.05.2008
Microgate
B
11.08.2008
Microgate
Approved
QA/QC
SECTION / PARAG. AFFECTED All
REASON/INITIATION DOCUMENTS/REMARKS
First Issue
1, 4.1, 5.1.1 Document updated according to review comments by G.Brusa (doc. MG acceptance docs review.doc)
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TABLE OF CONTENTS 1
SCOPE OF WORK .......................................................................................................................6
2
RELATED DOCUMENTS...........................................................................................................7
3
ABBREVIATIONS, ACRONYMS AND SYMBOLS ................................................................8
4
HARDWARE MAINTENANCE..................................................................................................9 4.1
5
Status Led............................................................................................................................................ 9
SOFTWARE MAINTENANCE .................................................................................................11 5.1 DSP FIRMWARE............................................................................................................................. 11 5.1.1 Project Organization .................................................................................................................. 11 5.1.2 Building the AO projects ........................................................................................................... 12 5.2 FIRMWARE UPDATE UTILITY (LBT_FWUpdater).................................................................... 16
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LIST OF FIGURES Figure 1 - Project Options: Main menu .............................................................................................13 Figure 2 - Project Options: Compile General (1)...............................................................................13 Figure 3 - Project Options: Compile General (2)...............................................................................14 Figure 4 - Project Options: Link General...........................................................................................14 Figure 5 - Project Options: Link Elimination ....................................................................................15 Figure 6 - Project Options: Load Processor .......................................................................................15
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LIST OF TABLES Table 1 – BCU board led .....................................................................................................................9 Table 2 – DSP board led ......................................................................................................................9 Table 3 – SIGGEN board led...............................................................................................................9 Table 4 – ACCEL board led ..............................................................................................................10 Table 5 – Ethernet copper board led ..................................................................................................10 Table 6 – Etherenet optical board led ................................................................................................10 Table 7 – FastLink board led .............................................................................................................10 Table 8 - VisualDSP++ project group organization ..........................................................................12
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1 SCOPE OF WORK The Control System Maintenance Manual covers the HW and SW maintenance of the real time control system. It provides an insight into the various project organization of the various AS system Firmware and detailed instructions on how to rebuild the various projects.
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2 RELATED DOCUMENTS [RD1] LBT Project - 2 x 8,4 Optical Telescope - Adaptive Secondary Control System - Design Report – Doc. 641a006, Issue D, May 6th, 2008 [RD2] LBT Project - 2 x 8,4 Optical Telescope – Adaptive Secondary Control System Configuration Control Document, doc. 641a017, Issue A, May 30th, 2008 [RD3] LBT Project - 2 x 8,4 Optical Telescope – Adaptive Secondary Control System Real Time Software User Manual, Doc. 641a022, Issue A, May 30th, 2008
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3 ABBREVIATIONS, ACRONYMS AND SYMBOLS Symbol ACC ADC AS336 ASCU BER CPLD DAC DMA DSP FIFO FPGA LBT MAC MGP MMT MMT336 MTBF P30 P36 PCB PECL PWM RTR RSS SIMD SS336 TBC TBD TCS
Description Accelerometer control board Analog to Digital Converter Aspheric Shell MMT336 thin mirror Adaptive Secondary Control Unit Bit Error Rate Complex Programmable Logic Device Digital to Analog Converter Direct Memory Access Digital Signal Processor First In First Out sequential memory Field Programmable Gate Array Large Binocular Telescope Multiply And Accumulate MicroGate udp Protocol Multiple Mirror Telescope 336 actuators MMT adaptive secondary unit Mean Time Between Failure 30 actuators adaptive secondary prototype 36 actuators reduced size MMT adaptive secondary prototype Printed Circuit Board Positive Emitter Coupled Logic Pulse Width Modulation Real Time Reconstructor Root of Sum of Squares Single Instruction Multiple Data Spherical Shell MMT336 thin mirror To Be Confirmed To Be Defined Telescope Control System
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4 HARDWARE MAINTENANCE 4.1
Status Led
The AO system includes for each boards a set of status led. Most of led can be switched of by the software when they are not used, while some hardware connected led can’t be switched off, to hide them, they has been covered by a black plastic tape. The following table lists all the boards provided with led and the use of it: BCU board LED 1
Switch ON/OFF yes
Red on
Red off
Green on
Green off
NIOS programming from Flash
NIOS programming from Serial Debug System reset non active User config loading successful
FPGA User
FPGA Default
2
yes
System reset active
3
yes
System reset active
Flashing @ 1.8Hz Clock divided 2^25 (552ms) Default config loading Both flash user and successful or JTAG default loading NOT connected successful
Table 1 – BCU board led
DSP board LED 1
Switch ON/OFF yes
Red on
Red off
Green on
2
yes
System reset active
3
yes
System reset active
Green off
Driver disabled
Driver enabled System reset non active User configuration loading successful
FPGA FPGA User Default Flashing @ 3.6Hz Clock divided 2^24 (276ms) Default configuration Both flash user and loading successful or default loading NOT JTAG connected successful
Table 2 – DSP board led
LED 1
Switch ON/OFF yes
Red on
2
yes
System reset active
3
yes
System reset active
SIGGEN board Red off Always System reset non active User configuration loading successful
Green on
Green off
FPGA FPGA User Default Flashing @ 3.6Hz Clock divided 2^24 (276ms) Default configuration Both flash user and loading successful or default loading NOT JTAG connected successful
Table 3 – SIGGEN board led
LED
Switch ON/OFF
Red on
ACCEL board Red off
Green on
Green off
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LBT PROJECT 2x8,4m TELESCOPE Always
1
yes
2
yes
System reset active
3
yes
System reset active
System reset non active User configuration loading successful
Doc.No: 641a021 Issue: B Date: 11 August 2008 FPGA FPGA User Default Flashing @ 3.6Hz Clock divided 2^24 (276ms) Default configuration Both flash user and loading successful or default loading NOT JTAG connected successful
Table 4 – ACCEL board led
LED 1 2
Switch ON/OFF no no
Red on 100 Mbit/s
Ethernet copper board Green on 1000 Mbit/s
Orange on
10 Mbit/s Flashes off when a packet is handled
All off Disconnected Disconnected
Table 5 – Ethernet copper board led
LED 1 2
Switch ON/OFF no no
Red on 100 Mbit/s
Ethernet optical board Blue on 1000 Mbit/s
Orange on
10 Mbit/s Flashes off when a packet is handled
All off Disconnected Disconnected
Table 6 – Etherenet optical board led
LED 1 2
Switch ON/OFF no no
Red on
FastLink board Red off
Orange on
All off
Signal detected Transmitter fault
Table 7 – FastLink board led
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Doc.No: 641a021 Issue: B Date: 11 August 2008
5 SOFTWARE MAINTENANCE 5.1
DSP FIRMWARE
5.1.1 Project Organization In the AO system, all the computation is executed by the DSPs available in the SwitchBCU, CrateBCU, DSP and ACCEL boards. The DSP code has been developed using the VisualDSP++ 4.5. The AO system is structured in 4 different projects: •
SwitchBCU
•
CrateBCU
•
DSPMainProgram
•
AccAcquisition
The SwitchBCU project contains the code developed to manage the reconstructor computation, it realizes the initialization of the various parallel matrix multiplier computations and waits, with a polling mechanism, the end of the computation before going on to the following one. This code runs on the DSP of the SwitchBCU board. The CrateBCU project contains the code developed to organize the real time diagnostic data read from the DSP control boards of the single crate and starts the storing to the local SDRAM memory. This code runs on the DSP of the CrateBCU board. The DSPMainPogram project contains the code developed to realize the reconstructor computation, the various matrix multipliers are executed in parallel to every DSP obtaining a very fast and efficient computation. This code also implements the actuator local control loop, this task is performed in an interrupt routine for the minimum latency of this time critical part. This code runs on the DSP of the DSP control boards. The ACCAcquisition project contains the code developed to acquire the accelerometers data, at this level the acquired data are filtered and prepared to be read by the SwitchBCU board. The code also collects and starts the raw data storing to the local SDRAM memory This code runs on the DSP of the ACC control boards. The VisualDSP++ allows organizing more projects in a project group. For the AO a project group called “lbt.dpg” has been created, it contains the four projects. Finally each project has a release number; the release is organized in two parts Vxx.yy. The first number (xx) indicates the main release and it is increased when a substantial modification of the code is requested. The second number (yy) indicates a minor software update or a bug fix. Each project directory contains a ‘Version.txt’ file describing the modifications introduced at each new release.
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The directories organization of the entire project group is the following: Directory LBTAO-DSP codes SwitchBCU
Debug
Release
CrateBCU
Debug
Release
DSPMainProgram
Debug
Release
AccAcquisition
Debug
Release
ProgramMemoryMap
lbt.dpg
Description This folder is the root of the LBTAO DSP projects This folder contains the SwitchBCU project. The project includes: the project file “SwitchBCU.dpj”, the source and include files (.c, .asm, .h) and the temporary files crated during the compilation. This folder contains the building output files generated by the debug building options. Typically this kind of build is not used because the optimization level is extremely low This folder contains the building output files generated by the release building options. This is the executable file that should be used in the AO system This folder contains the CrateBCU project. The project includes: the project file “CrateBCU.dpj”, the source and include files (.c, .asm, .h) and the temporary files crated during the compilation. This folder contains the building output files generated by the debug building options. Typically this kind of build is not used because the optimization level is extremely low This folder contains the building output files generated by the release building options. This is the executable file that should be used in the MGAOS system This folder contains the DSPMainProgram project. The project includes: the project file “DSPMainProgram.dpj”, the source and include files (.c, .asm, .h) and the temporary files crated during the compilation. This folder contains the building output files generated by the debug building options. Typically this kind of build is not used because the optimization level is extremely low This folder contains the building output files generated by the release building options. This is the executable file that should be used in the MGAOS system This folder contains the AccAcquisition project. The project includes: the project file “AccAcquisition.dpj”, the source and include files (.c, .asm, .h) and the temporary files crated during the compilation. This folder contains the building output files generated by the debug building options. Typically this kind of build is not used because the optimization level is extremely low This folder contains the building output files generated by the release building options. This is the executable file that should be used in the MGAOS system This folder contains the spread sheet excel file called “LBT codes memory map x_yy”. This excel file describe in details the DSP memory addressing and organization and the control variable initialization. x_yy refers to the file release. This file is the project group file generated by the VisualDSP++
Table 8 - VisualDSP++ project group organization
5.1.2 Building the AO projects The building of the AO projects shall be done independently or for each project or for all setting the proper flag in the project option menu.
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The single/all projects building is executed directly in the VisualDSP++ software using the appropriate build command. Before to do this is important to verify and set all the building options as described the following figures and the project configuration should be set to Release:
Figure 1 - Project Options: Main menu
Figure 2 - Project Options: Compile General (1)
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Figure 3 - Project Options: Compile General (2)
Figure 4 - Project Options: Link General
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Figure 5 - Project Options: Link Elimination
Figure 6 - Project Options: Load Processor
All the not included options window should be leave by default. The projects are configured to generate, as output, a loader file instead an executable file. This is the standard raw file used to download the code to the DSP memory at the system startup. Also the Load Processor options should be configured as shown in Figure 6 in order to obtain a compatible file with the download automatic routine. Microgate Srl – Via Stradivari, 4 – 39100 Bolzano – ITALY ADS International Srl –via Roma, 87- 23868 Valmadrera (Lc) – ITALY Page 15 of 16
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Doc.No: 641a021 Issue: B Date: 11 August 2008
FIRMWARE UPDATE UTILITY (LBT_FWUpdater)
The Firmware Update utility allows to reprogram partially or totally all user programmable devices in the LBT672 real time control system. In particular, the following devices can be re-programmed: -
Switch BCU FPGA configuration – user partition
-
Switch BCU Nios code – user partition
-
Crate BCU FPGA configuration – user partition
-
Crate BCU Nios code – user partition
-
DSP Board BCU FPGA configuration – user partition
-
DSP Board Nios code – user partition
-
Signal generator BCU FPGA configuration – user partition
-
Signal generator BCU Nios code – user partition
-
Accelerometer Board BCU FPGA configuration – user partition
-
Accelerometer Board BCU Nios code – user partition
The configuration occurs remotely by means of the diagnostic Ethernet link. … To Be Completed …
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