Transcript
240PIN DDR2 667 Registered DIMM 4096MB With 256Mx4 CL5
TRV4G36CA5-Y5 Description
Placement
The TRV4G36CA5-Y5 is a 512M x 72bits DDR2-667 Registered DIMM. The TRV4G36CA5-Y5 consists of 36 pcs 256Mx4bits DDR2 SDRAMs in 60 ball FBGA package, 2 pcs register in 176 ball TFBGA package, 1 pcs PLL driver IC and a 2048 bits serial EEPROM on a 240-pin printed circuit board. The TRV4G36CA5-Y5 is a Dual In-Line Memory Module and is intended for
B
mounting into 240-pin edge connector sockets.
E
D
F
Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance
A
memory system applications.
C
Features •
RoHS compliant products.
•
JEDEC standard 1.8V ± 0.1V Power supply
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VDDQ=1.8V ± 0.1V
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Max clock Freq: 333MHZ; 667Mb/Sec/Pin.
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Posted /CAS
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Programmable /CAS Latency: 3, 4, 5
•
Programmable Additive Latency :0, 1, 2, 3 and 4
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Write Latency (WL) = Read Latency (RL)-1
•
Burst Length: 4,8(Interleave/nibble sequential)
•
Programmable sequential / Interleave Burst Mode
•
Bi-directional Differential Data-Strobe (Single-ended
I
Off-Chip Driver (OCD) Impedance Adjustment
•
MRS cycle with address key programs.
•
On Die Termination
•
Serial presence detect with EEPROM
M J K L
data-strobe is an optional feature)
•
G
H
1
240PIN DDR2 667 Registered DIMM 4096MB With 256Mx4 CL5
TRV4G36CA5-Y5 Dimensions
Pin Description
Side
Millimeters
Inches
Symbol
A
133.35±0.15
5.250±0.006
A0~A13, BA0~ BA2
Address input, bank address
B
55
2.165
DQ0~DQ63
Data Input / Output.
C
63
2.480000
D
5
0.197
CB0~CB7
Data Check Bits Input/Output
E
2.5
0.0980
DQS0~DQS8
Data strobe
F
1.5±0.10
0.059±0.039
/DQS0~/DQS8
Data strobe , negative line
G
5.175
0.204
CK0, /CK0
Clock Input.
H
2.2
0.867
CKE0, CKE1
Clock Enable Input.
I
4
0.157
ODT0, ODT1
On-die termination control line
J
10
0.394
/CS0, /CS1
Chip Select Input.
K
17.8
0.701
/RAS
Row Address Strobe
L
30±0.15
1.181±0.006
/CAS
Column Address Strobe
M
1.27±0.15
0.050±0.006
/WE
Write Enable
DM0~DM8
Data-in Mask
/DQS9~/DQS17
Data strobes(Read),negative line
VDD
+1.8 Voltage power supply
VDDQ
+1.8 Voltage Power Supply for DQS
VREF
Power Supply for Reference
VDDSPD
Serial Supply
SA0~SA2
Address select for EEPROM
SCL
Serial PD Clock
SDA
Serial PD Add/Data input/output
VSS
Ground
/RESET
Register and PLL control pin
/Err_Out
Parity error found in the bus
Par_In
Parity bit for address and control bus
NC
No Connection
(Refer Placement)
2
Function
EEPROM
Positive
Power
240PIN DDR2 667 Registered DIMM 4096MB With 256Mx4 CL5
TRV4G36CA5-Y5 Pinouts: Pin Pin No Name 01 VREF
Pin Pin No Name 41 VSS
02
VSS
DQ0 DQ1 VSS /DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS /DQS1 DQS1 VSS /RESET NC VSS DQ10
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61
CB1 VSS /DQS8 DQS8 VSS CB2 CB3 VSS VDDQ CKE0 VDD NC, BA2 NC,***Err_Out VDDQ A11 A7 VDD A5 A4
83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101
22
DQ11
62
63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
VDDQ
A2 VDD VSS VSS VDD NC, ***Par_in VDD A10/AP BA0 VDDQ /WE /CAS VDDQ NC, **/CS1 ODT1 VDDQ VSS
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119
40
DQ27
80
DQ32
03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
VSS DQ16 DQ17 VSS /DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS /DQS3 DQS3 VSS DQ26
42
CB0
Pin Pin No Name 81 DQ33
*RFU = Reserved for Future Use
82
VSS
/DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS /DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2
Pin No 121 122
Pin Name VSS DQ4
Pin Pin No Name 161 CB4 162 CB5
202 DM4,DQS13
123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141
DQ5 VSS DM0,DQS9 NC,/DQS9 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1,DQS10 NC,/DQS10 VSS *RFU *RFU VSS DQ14 DQ15
163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181
102 NC
142
VSS
182 A3
222 VSS
120 SCL
160
VSS
200 DQ37
240 SA1
VSS /DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS /DQS7 DQS7 VSS DQ58 DQ59 VSS SDA
143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159
**CKE1, /CS1 are used for 2 rank registered DIMM.
DQ20 DQ21 VSS DM2,DQS11 NC,/DQS11 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3,DQS12 NC,/DQS12 VSS DQ30 DQ31
183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199
VSS DM8,DQS17 NC,/DQS17 VSS CB6 CB7 VSS VDDQ NC, **CKE1 VDD NC NC VDDQ A12 A9 VDD A8 A6 VDDQ
Pin Pin No Name 201 VSS
A1 VDD CK0 /CK0 VDD A0 VDD BA1 VDDQ /RAS /CS0 VDDQ ODT0 A13 VDD VSS DQ36
***NC, /E rr Out and NC, /Par_In are for optional function to check address and command parity.
3
203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239
NC,/DQS13 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5,DQS14 NC,/DQS14 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS *RFU *RFU DM6,DQS15 NC,/DQS15 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7,DQS16 NC,/DQS16 VSS DQ62 DQ63 VSS VDDSPD SA0
