Single And Dual, Ultralow Distortion, Ultralow Noise Op Amps Ad8597/ad8599

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Single and Dual, Ultralow Distortion, Ultralow Noise Op Amps AD8597/AD8599 PIN CONFIGURATIONS Low noise: 1.1 nV/√Hz at 1 kHz Low distortion: −120 dB THD @ 1 kHz Input noise, 0.1 Hz to 10 Hz: <76 nV p-p Slew rate: 14 V/μs Wide bandwidth: 10 MHz Supply current: 4.8 mA/amp typical Low offset voltage: 10 μV typical CMRR: 120 dB Unity-gain stable ±15 V operation NC 1 –IN 2 AD8597 +IN 3 TOP VIEW V– 4 (Not to Scale) 8 NC 7 V+ 6 OUT 5 NC NC = NO CONNECT 06274-060 FEATURES Figure 1. AD8597 8-Lead SOIC (R-8) APPLICATIONS PIN 1 INDICATOR 8 NC –IN 2 AD8597 7 V+ +IN 3 TOP VIEW 6 OUT 5 NC V– 4 Professional audio preamplifiers ATE/precision testers Imaging systems Medical/physiological measurements Precision detectors/instruments Precision data conversion NOTES 1. NC = NO CONNECT. 2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE CONNECTED TO V–. 06274-061 NC 1 OUT A 1 –IN A 2 AD8599 +IN A 3 TOP VIEW –V 4 (Not to Scale) 8 +V 7 OUT B 6 –IN B 5 +IN B 06274-054 Figure 2. AD8597 8-Lead LFCSP (CP-8-2) Figure 3. AD8599 8-Lead SOIC (R-8) GENERAL DESCRIPTION The AD8597/AD8599 are very low noise, low distortion operational amplifiers ideal for use as preamplifiers. The low noise of 1.1 nV/√Hz and low harmonic distortion of −120 dB (or better) at audio bandwidths give the AD8597/AD8599 the wide dynamic range necessary for preamplifiers in audio, medical, and instrumentation applications. The excellent slew rate of 14 V/μs and 10 MHz gain bandwidth make them highly suitable for medical applications. The low distortion and fast settling time make them ideal for buffering of high resolution data converters. The AD8597 is available in 8-lead SOIC and LFCSP packages, while the AD8599 is available in an 8-lead SOIC package. They are both specified over a −40°C to +125°C temperature range. The AD8597 and AD8599 are members of a growing series of low noise op amps offered by Analog Devices, Inc., (see Table 1). Table 1. Low Noise Op Amps Package Single Dual Quad 0.9 nV AD797 1.1 nV AD8597 AD8599 1.8 nV ADA4004-1 ADA4004-2 ADA4004-4 2.8 nV AD8675 AD8676 3.8 nV AD8671 AD8672 AD8674 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved. AD8597/AD8599 TABLE OF CONTENTS Features .............................................................................................. 1  ESD Caution...................................................................................5  Applications ....................................................................................... 1  Typical Performance Characteristics ..............................................6  Pin Configurations ........................................................................... 1  Functional Operation..................................................................... 15  General Description ......................................................................... 1  Input Voltage Range ................................................................... 15  Revision History ............................................................................... 2  Output Phase Reversal ............................................................... 15  Specifications..................................................................................... 3  Noise and Source Impedance Considerations ........................... 15  Absolute Maximum Ratings............................................................ 5  Outline Dimensions ....................................................................... 17  Thermal Resistance ...................................................................... 5  Ordering Guide .......................................................................... 17  Power Sequencing ........................................................................ 5  REVISION HISTORY 12/09—Rev. B to Rev. C Changes to Table 1 ............................................................................ 1 10/08—Rev. A to Rev. B Added AD8597 ................................................................... Universal Added LFCSP_VD ............................................................. Universal Added Table 1.................................................................................... 1 Changes to Specifications Section .................................................. 3 Changes to Absolute Maximum Ratings Section ......................... 5 Changes to Typical Performance Characteristics Section ........... 6 Added Figure 12 and Figure 15....................................................... 7 Added Figure 18 and Figure 19....................................................... 8 Added Figure 30 and Figure 33..................................................... 10 Added Figure 34 to Figure 38........................................................ 11 Added Figure 42 and Figure 45..................................................... 12 Added Figure 52, Figure 55, Figure 57......................................... 14 Added Functional Operation Section .......................................... 15 Added Figure 58.............................................................................. 15 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 17 4/07—Rev. 0 to Rev. A Updated Layout .................................................................................5 Changes to Figure 45 Caption ...................................................... 12 Added Figure 48 ............................................................................. 12 Changes to Figure 51 Caption ...................................................... 13 2/07—Revision 0: Initial Version Rev. C | Page 2 of 20 AD8597/AD8599 SPECIFICATIONS VSY = ±5 V, VCM = 0 V, VO = 0 V, TA = 25°C, unless otherwise specified. Table 2. Parameter INPUT CHARACTERISTICS Offset Voltage Symbol Conditions Min VOS Typ Max Unit 15 120 180 μV μV 0.8 40 2.2 210 340 250 340 +2.0 μV/°C nA nA nA nA V dB dB dB dB −40°C ≤ TA ≤ +125°C Offset Voltage Drift Input Bias Current ΔVOS/ΔT IB Input Offset Current IOS −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +125°C 65 −40°C ≤ TA ≤ +125°C Input Voltage Range Common-Mode Rejection Ratio IVR CMRR Large Signal Voltage Gain AVO Input Capacitance Differential Capacitance Common-Mode Capacitance OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Short-Circuit Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier −2.0 V ≤ VCM ≤ +2.0 V −40°C ≤ TA ≤ +125°C RL ≥ 600 Ω, VO = −11 V to +11 V −40°C ≤ TA ≤ +125°C −2.0 120 105 105 100 CDIFF CCM VOH VOL ISC ZOUT PSRR RL = 600 Ω −40°C ≤ TA ≤ +125°C RL = 2 kΩ −40°C ≤ TA ≤ +125°C RL = 600 Ω −40°C ≤ TA ≤ +125°C RL = 2 kΩ −40°C ≤ TA ≤ +125°C 3.5 3.3 3.7 3.5 ISY 110 15.4 5.5 pF pF 3.7 V V V V V V V V mA Ω 3.8 −3.6 −3.7 120 118 140 4.8 −40°C ≤ TA ≤ +125°C DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Peak-to-Peak Noise Voltage Noise Density SR tS GBP ΦM en p-p en Correlated Current Noise Uncorrelated Current Noise Total Harmonic Distortion + Noise Channel Separation THD + N CS AV = −1, RL = 2 kΩ AV = 1, RL = 2 kΩ To 0.01%, step = 10 V 14 14 2 10 60 0.1 Hz to 10 Hz f = 1 kHz f = 10 Hz f = 1 kHz f = 10 Hz f = 1 kHz f = 10 Hz G = 1, RL ≥ 1 kΩ, f = 1 kHz, VRMS = 1 V f = 10 kHz 76 1.07 Rev. C | Page 3 of 20 −3.4 −3.3 −3.5 −3.4 ±52 5 At 1 MHz, AV = 1 VSY = ±18 V to ±4.5 V −40°C ≤ TA ≤ +125°C 135 2.0 4.2 2.4 5.2 −120 −120 5.5 6.5 dB dB mA mA V/μs V/μs μs MHz Degrees 1.15 1.5 nV p-p nV/√Hz nV/√Hz pA/√Hz pA/√Hz pA/√Hz pA/√Hz dB dB AD8597/AD8599 VS = ±15 V, VCM = 0 V, VO = 0 V, TA = +25°C, unless otherwise specified. Table 3. Parameter INPUT CHARACTERISTICS Offset Voltage Symbol Conditions Min VOS Typ Max Unit 10 120 180 μV μV 0.8 2.2 μV/°C 25 200 300 200 300 +12.5 nA nA nA nA V dB dB dB dB −40°C ≤ TA ≤ +125°C Offset Voltage Drift ΔVOS/ΔT Input Bias Current IB −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +125°C Input Offset Current IOS 50 −40°C ≤ TA ≤ +125°C Input Voltage Range Common-Mode Rejection Ratio IVR CMRR Large Signal Voltage Gain AVO Input Capacitance Differential Capacitance Common-Mode Capacitance OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Short-Circuit Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier −12.5 V ≤ VCM ≤ +12.5 V −40°C ≤ TA ≤ +125°C RL ≥ 600 Ω, VO = −11 V to +11 V −40°C ≤ TA ≤ +125°C −12.5 120 115 110 106 CDIFF CCM VOH VOL ISC ZOUT PSRR RL = 600 Ω −40°C ≤ TA ≤ +125°C RL = 2 kΩ −40°C ≤ TA ≤ +125°C RL = 600 Ω −40°C ≤ TA ≤ +125°C RL = 2 kΩ −40°C ≤ TA ≤ +125°C 13.1 12.8 13.5 13.2 ISY 116 12.1 5.1 pF pF 13.4 V V V V V V V V mA Ω 13.7 −13.2 −13.5 120 118 140 5.0 −40°C ≤ TA ≤ +125°C DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Peak-to-Peak Noise Voltage Noise Density SR ts GBP ΦM en p-p en Correlated Current Noise Uncorrelated Current Noise Total Harmonic Distortion + Noise Channel Separation THD + N CS AV = −1, RL = 2 kΩ AV = 1, RL = 2 kΩ To 0.01%, step = 10 V 16 15 2 10 65 0.1 Hz to 10 Hz f = 1 kHz f = 10 Hz f = 1 kHz f = 10 Hz f = 1 kHz f = 10 Hz G = 1, RL ≥ 1 kΩ, f = 1 kHz, VRMS = 3 V f = 10 kHz 76 1.07 Rev. C | Page 4 of 20 −12.9 −12.8 −13.4 −13.3 ±52 5 At 1 MHz, AV = 1 VSY = ±18 V to ±4.5 V −40°C ≤ TA ≤ +125°C 135 1.9 4.3 2.3 5.3 −120 −120 5.7 6.75 dB dB mA mA V/μs V/μs μs MHz Degrees nV p-p 1.15 1.5 nV/√Hz nV/√Hz pA/√Hz pA/√Hz pA/√Hz pA/√Hz dB dB AD8597/AD8599 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Supply Voltage Input Voltage Differential Input Voltage1 Output Short-Circuit to GND Storage Temperature Range Operating Temperature Range Lead Temperature Range (Soldering 60 sec) Junction Temperature 1 Rating ±18 V −V ≤ VIN ≤ +V ±1 V Indefinite −65°C to +150°C −40°C to +125°C 300°C 150°C If the differential input voltage exceeds 1 V, the current should be limited to 5 mA. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. θJA is specified with the device soldered on a circuit board with its exposed paddle soldered to a pad (if applicable) on a 4-layer JEDEC standard PCB with zero air flow. Table 5. Package Type 8-Lead LFCSP_VD (CP-8-2) 8-Lead SOIC (R-8) (AD8597) 8-Lead SOIC (R-8) (AD8599) θJA 78 140 120 θJC 20 39 36 Unit °C/W °C/W °C/W POWER SEQUENCING The op amp supplies should be applied simultaneously. The op amp supplies should be stable before any input signals are applied. In any case, the input current must be limited to 5 mA. ESD CAUTION Rev. C | Page 5 of 20 AD8597/AD8599 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. 70 50 AD8599 MEAN = 7.91 STDEV = 21.89 MIN = –63.02 MAX = 57.5 VSY = ±15V 60 NUMBER OF AMPLIFIERS 60 40 30 20 50 40 30 20 10 10 0 –75 –65 –55 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 VOS (µV) 06274-001 0 –75 –65 –55 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 VOS (µV) Figure 4. Input Offset Voltage Distribution 60 45 AD8599 MEAN = 0.765 STDEV = 0.234 MIN = 0.338 MAX = 1.709 VSY = ±15V 40 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS Figure 7. Input Offset Voltage Distribution AD8599 MEAN = 0.346 STDEV = 0.218 MIN = 0.010 MAX = 1.155 VSY = ±5V 50 06274-002 NUMBER OF AMPLIFIERS 70 AD8599 MEAN = 8.23 STDEV = 24.47 MIN = –72.62 MAX = 62.09 VSY = ±5V 40 30 20 35 30 25 20 15 10 10 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 TCVOS (µV) 2.2 2.4 0 06274-004 0 60 60 AD8599 MEAN = 0.461 STDEV = 0.245 MIN = 0.026 MAX = 1.26 VSY = ±5V 40 AD8599 MEAN = 0.342 STDEV = 0.221 MIN = 0.013 MAX = 1.239 VSY = ±15V 50 NUMBER OF AMPLIFIERS 50 30 20 40 30 20 10 10 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 TCVOS (µV) 2.2 2.4 0 06274-006 NUMBER OF AMPLIFIERS 2.2 2.4 Figure 8. TCVOS Distribution, −40°C ≤ TA ≤ +125°C Figure 5. TCVOS Distribution, −40°C ≤ TA ≤ +125°C 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 TCVOS (µV) Figure 6. TCVOS Distribution, −40°C ≤ TA ≤ +85°C 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 TCVOS (µV) 2.2 2.4 Figure 9. TCVOS Distribution, −40°C ≤ TA ≤ +85°C Rev. C | Page 6 of 20 06274-005 0 06274-007 5 AD8597/AD8599 75 50 25 25 VOS (µV) 50 0 0 –25 –25 –50 –50 –75 –75 –100 –5.0 –2.5 AD8599 VSY = ±15V 75 0 2.5 5.0 VCM (V) –100 –15 06274-009 –10 Figure 10. Offset Voltage vs. VCM 0 VCM (V) 5 10 15 Figure 13. Offset Voltage vs. VCM 350 350 AD8599 VSY = ±5V VCM = 0V 300 250 250 200 200 150 150 100 100 50 50 0 0 –50 –50 –100 –100 –150 –150 –25 0 25 50 TEMPERATURE (°C) 75 100 125 –200 –50 06274-011 –200 –50 AD8599 VSY = ±15V VCM = 0V 300 IB (nA) IB (nA) –5 Figure 11. Input Bias Current vs. Temperature –25 0 25 50 TEMPERATURE (°C) 75 100 125 06274-012 VOS (µV) 100 AD8599 VSY = ±5V 06274-010 100 Figure 14. Input Bias Current vs. Temperature 50 350 AD8597 300 40 AD8597 VSY = ±15V 250 30 200 20 150 TA = –40°C IB (nA) 10 0 –10 ±15V 50 TA = +25°C 0 TA = +85°C –50 –100 –20 –200 –30 –250 –25 0 25 50 75 100 125 06274-063 –40 –50 –50 TA = +125°C –150 ±5V 06274-062 VOS (µV) 100 –300 –350 –12 –10 150 TEMPERATURE (°C) –8 –6 –4 –2 0 2 4 6 8 VCM (V) Figure 12. Input Offset Voltage vs. Temperature Figure 15. Input Bias Current vs. Temperature Rev. C | Page 7 of 20 10 12 AD8597/AD8599 150 80 AD8597 AD8599 70 100 60 50 IB (nA) IOS (nA) 50 40 IOS @ VSY = ±5V ±15V 0 ±5V 30 –50 20 IOS @ VSY = ±15V 06274-065 –100 10 –25 0 25 50 TEMPERATURE (°C) 75 100 125 –150 –50 06274-013 0 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) Figure 16. Input Offset Current vs. Temperature Figure 19. Input Offset Current vs. Temperature 114 120 AD8599 VSY = ±5V 112 AD8599 VSY = ±15V 118 RL = 2kΩ, VO = ±11V RL = 2kΩ, VO = ±2V 108 AVO (dB) AVO (dB) 110 RL = 600Ω, VO = ±2V 106 116 RL = 600Ω, VO = ±11V 114 104 112 –25 0 25 50 75 TEMPERATURE (°C) 100 125 150 110 –50 06274-015 100 –50 Figure 17. Large Signal Voltage Gain vs. Temperature 8 –25 0 25 50 75 TEMPERATURE (°C) 100 125 150 06274-016 102 Figure 20. Large Signal Voltage Gain vs. Temperature 350 AD8597 300 7 TA = +125°C 6 250 TA = +85°C AD8599 VSY = ±15V TA = –40°C 200 150 TA = +25°C 100 4 IB (nA) TA = –40°C 3 TA = +25°C 50 0 TA = +85°C –50 –100 –150 2 TA = +125°C –200 –250 0 0 2 4 6 –300 –350 –12 –10 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 VSY (V) Figure 18. Supply Current vs. Supply Voltage –8 –6 –4 –2 0 2 VCM (V) 4 6 Figure 21. Input Bias Current vs. VCM Rev. C | Page 8 of 20 8 10 12 06274-014 1 06274-064 ISY (mA) 5 AD8597/AD8599 80 80 AD8599 VSY = ±5V 60 AD8599 VSY = ±15V 60 OUTPUT CURRENT (mA) 20 0 –20 –40 ISOURCE ISINK 40 20 0 –20 –40 ISOURCE –60 –25 0 75 25 50 TEMPERATURE (°C) 100 125 150 –80 –50 06274-017 –80 –50 –25 0 Figure 22. ISC vs. Temperature 125 150 10k OUTPUT SATURATION VOLTAGE (mV) AD8599 VSY = ±5V ISINK 1k ISOURCE 100 0.001 100 Figure 25. ISC vs. Temperature 0.01 0.1 1 10 100 IL (mA) AD8599 VSY = ±15V ISINK 1k ISOURCE 100 0.001 06274-021 OUTPUT SATURATION VOLTAGE (mV) 10k 75 25 50 TEMPERATURE (°C) 06274-018 –60 0.01 0.1 1 10 100 IL (mA) Figure 23. Output Saturation Voltage vs. Current Load 06274-022 OUTPUT CURRENT (mA) ISINK 40 Figure 26. Output Saturation Voltage vs. Current Load 2.5 2.5 AD8599 VSY = ±5V AD8599 VSY = ±15V 2.0 2.0 VCC – VOH (V) 1.5 VCC – VOH @ RL = 600Ω 1.0 VCC – VOH @ RL = 2kΩ 0.5 1.5 VCC – VOH @ RL = 2kΩ 1.0 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 150 0 –50 Figure 24. Output Saturation Voltage vs. Temperature –25 0 75 25 50 TEMPERATURE (°C) 100 125 Figure 27. Output Saturation Voltage vs. Temperature Rev. C | Page 9 of 20 150 06274-029 0.5 06274-027 VCC – VOH (V) VCC – VOH @ RL = 600Ω AD8597/AD8599 0 0 AD8599 VSY = ±5V AD8599 VSY = ±15V –0.5 –1.0 VEE – VOL @ RL = 2kΩ –1.5 VEE – VOL @ RL = 600Ω –2.0 –1.0 VEE – VOL @ RL = 2kΩ –1.5 VEE – VOL @ RL = 600Ω –2.0 –25 75 25 50 TEMPERATURE (°C) 0 100 125 150 –2.5 –50 06274-028 –2.5 –50 Figure 28. Output Saturation Voltage vs. Temperature –25 0 25 50 75 TEMPERATURE (°C) 100 125 150 06274-030 VEE – VOL (V) VEE – VOL (V) –0.5 Figure 31. Output Saturation Voltage vs. Temperature 15.0 –13.0 VOL @ RL = 600Ω AD8599 VSY = ±15V 14.8 14.6 –13.5 14.4 VOL @ RL = 2kΩ VOH (V) VOL (V) 14.2 –14.0 14.0 VOH @ RL = 2kΩ 13.8 13.6 –14.5 13.4 VOH @ RL = 600Ω 100 150 13.0 –50 120 80 100 GAIN (dB) AND PHASE (Degrees) 100 60 40 CL = 20pF 20 0 –20 CL = 200pF –40 –60 –80 –100 10 AD8597 VSY = ±5V RL = 2kΩ 100 1k 10k 50 TEMPERATURE (°C) 100 150 Figure 32. Output Voltage High vs. Temperature 06274-066 GAIN (dB) AND PHASE (Degrees) Figure 29. Output Voltage Low vs. Temperature 0 06274-031 50 TEMPERATURE (°C) 50k 80 60 40 CL = 20pF 20 0 –20 CL = 200pF –40 AD8597 VSY = ±15V RL = 2kΩ –60 –80 1 FREQUENCY (kHz) 06274-067 0 06274-032 –15.0 –50 13.2 AD8599 VSY = ±15V 10 100 1k FREQUENCY (kHz) Figure 30. Gain and Phase vs. Frequency Figure 33. Gain and Phase vs. Frequency Rev. C | Page 10 of 20 10k 50k AD8597/AD8599 50 50 40 40 AV = 100 AV = 100 30 30 20 AV = 10 GAIN (dB) 10 0 AV = 1 –10 AV = 10 10 0 AV = 1 –10 –20 –30 06274-068 AD8597 VSY = ±5V RL = 2kΩ –40 1 10 100 1k 10k AD8597 VSY = ±15V RL = 2kΩ –30 06274-071 –20 –40 50k 1 10 FREQUENCY (kHz) Figure 34. Closed-Loop Gain vs. Frequency 1k 50k 100 AV = –100 AV = –100 10 10 AV = –10 AV = –10 AV = +1 ZOUT (Ω) AV = +1 1 1 AD8597 VSY = ±5V 0.01 10 100 1k 10k 06274-072 0.1 06274-069 0.1 AD8597 VSY = ±15V 0.01 10 100k 100 FREQUENCY (kHz) 1k 10k 100k FREQUENCY (kHz) Figure 35. Closed-Loop Output Impedance vs. Frequency Figure 38. Closed-Loop Output Impedance vs. Frequency 110 120 AD8599 ±5V ≤ VSY ≤ ±15V 100 100 PSRR+ (dB) PSRR– (dB) 90 80 PSRR (dB) 80 70 60 AD8597 VSY = ±5V, ±15V 60 40 50 20 40 06274-070 CMRR (dB) 10k Figure 37. Closed-Loop Gain vs. Frequency 100 ZOUT (Ω) 100 FREQUENCY (kHz) 30 20 1 10 100 1k 0 –20 100 10k FREQUENCY (kHz) Figure 36. Common-Mode Rejection Ratio vs. Frequency 1k 10k 100k FREQUENCY (Hz) 1M Figure 39. Power Supply Rejection Ratio vs. Frequency Rev. C | Page 11 of 20 10M 06274-038 GAIN (dB) 20 AD8597/AD8599 600 90 AD8599 MEAN = 1.30 STDEV = 0.09 MIN = 1.1 MAX = 1.5 ±5V ≤ VSY ≤ ±15V 70 60 AD8599 MEAN = 1.07 STDEV = 0.02 MIN = 1.05 MAX = 1.15 ±5V ≤ VSY ≤ ±15V 500 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 80 50 40 30 400 300 200 20 100 10 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 VOLTAGE NOISE DENSITY (nV/ Hz) 2.0 0 0.95 1.04 1.07 1.10 1.13 1.16 1.19 Figure 43. Voltage Noise Density @ 1 kHz 100 CURRTENT NOISE DENSITY (pA/ Hz) AD8599 ±5V ≤ VSY ≤ ±15V 10 1 10 100 FREQUENCY (Hz) 1k 10 1 0.1 1 10 Figure 44. Current Noise Density vs. Frequency Figure 41. Voltage Noise Density vs. Frequency 1 1 0.1 0.1 THD + N (%) RL = 600Ω 0.01 AD8597 VSY = ±5V AV = +1 0.001 0.01 AD8597 VSY = ±15V AV = +1 RL = 600Ω 0.001 RL = 100kΩ 0.01 0.1 1 06274-073 0.0001 0.001 1k 100 FREQUENCY (Hz) 10 V rms (V) 0.0001 0.001 RL = 100kΩ 0.01 0.1 1 V rms (V) Figure 42. THD + N vs. Amplitude Figure 45. THD + N vs. Amplitude Rev. C | Page 12 of 20 10 06274-074 1 06274-041 0.1 AD8599 ±5V ≤ VSY ≤ ±15V 06274-042 100 VOLTAGE NOISE DENSITY (nV/ Hz) 1.01 VOLTAGE NOISE DENSITY (nV/ Hz) Figure 40. Voltage Noise Density @ 10 Hz THD + N (%) 0.98 06274-040 1.0 06274-039 0 AD8597/AD8599 0.1 0.1 AD8599 VSY = ±15V AD8599 VSY = ±15V VIN = 3V rms VIN = 3V rms VIN = 5V rms VIN = 7V rms THD + N (%) 0.01 THD + N (%) 0.01 0.001 0.001 RL = 600Ω 100 1k FREQUENCY (Hz) 10k 100k 0.0001 10 100 Figure 46. THD + N vs. Frequency 100k 20 AD8599 AD8599 15 10 10 AMPLITUDE (V) 15 0 VSY = ±15V VIN = 20V p-p AV = 1 RF = 1kΩ RL = 2kΩ VERTICAL AXIS = 5V/DIV HORIZONTAL AXIS = 4µs/DIV –5 –10 –15 –20 –8.6 –4.6 –0.6 3.4 7.4 11.4 15.4 TIME (µs) 19.4 5 VSY = ±15V VIN = 20V p-p AV = –1 RF = 2kΩ RS = 2kΩ CL = 0pF VERTICAL AXIS = 5V/DIV HORIZONTAL AXIS = 4µs/DIV 0 –5 –10 –15 23.4 27.4 31.4 –20 –8.6 Figure 47. Large Signal Response –4.6 –0.6 3.4 7.4 11.4 15.4 TIME (µs) 19.4 23.4 27.4 31.4 06274-048 5 06274-047 Figure 50. Large Signal Response 80 45 AD8599 40 40 35 OVERSHOOT (%) 60 20 0 VSY = ±15V, ±5V VIN = 100mV p-p AV = 1 EXTERNAL CL = 100pF EXTERNAL RL = 10kΩ VERTICAL AXIS = 20mV/DIV HORIZONTAL AXIS = 400ns/DIV –40 –60 –80 –800 –400 0 400 800 1200 1600 2000 2400 2800 3200 TIME (ns) 30 25 20 15 10 5 06274-046 –20 AD8599 ±5V ≤ VSY ≤ ±15V AV = 1 RL = 10kΩ Figure 48. Small Signal Response 0 10 100 CAPACITANCE (pF) Figure 51. Overshoot vs. Capacitance Rev. C | Page 13 of 20 1k 06274-049 AMPLITUDE (V) 10k Figure 49. THD + N vs. Frequency 20 AMPLITUDE (mV) 1k FREQUENCY (Hz) 06274-043 0.0001 10 06274-044 RL = 2kΩ AD8597/AD8599 45 45 AD8597 VSY = ±5V 40 AD8597 VSY = ±15V 40 35 35 30 30 OVERSHOOT (%) OVERSHOOT (%) OS– 25 20 OS– 15 25 20 15 OS+ 10 5 0 10 100 OS+ 06247-078 06247-077 10 5 0 10 1k 100 CAPACITANCE (pF) Figure 52. Overshoot vs. Capacitive Load Figure 55. Overshoot vs. Capacitive Load 0 15.0 AD8599 VSY = ±15V AV = 100 RL = 1kΩ –20 –40 AD8599 VIN = 10V p-p VIN = 20V p-p 12.5 –60 ISY (mA) CHANNEL SEPARATION (dB) 1k CAPACITANCE (pF) –80 10.0 VSY = ±15V –100 VSY = ±5V –120 7.5 1k 10k FREQUENCY (Hz) 100k 1M 5.0 –50 06274-050 –160 100 –25 Figure 53. Channel Separation vs. Frequency 6.0 AD8599 ±5V ≤ VSY ≤ ±15V 75 100 125 AD8597 5.5 400 VSY = ±15V ISY (mA) 200 0 5.0 VSY = ±5V –200 06274-075 4.5 –400 –600 –800 0 1 2 3 4 5 6 TIME (Seconds) 7 8 9 10 06274-053 AMPLITUDE (nV) 25 50 TEMPERATURE (°C) Figure 56. Supply Current vs. Temperature 800 600 0 06274-020 –140 Figure 54. Peak-to-Peak Noise 4.0 –40 –25 –10 5 20 35 50 65 80 95 TEMPERATURE (°C) Figure 57. Supply Current vs. Temperature Rev. C | Page 14 of 20 110 125 AD8597/AD8599 FUNCTIONAL OPERATION These diodes are connected between the inputs and each supply rail to protect the input transistors against an electrostatic discharge event and they are normally reverse-biased. However, if the input voltage exceeds the supply voltage, these ESD diodes can become forward-biased. Without current limiting, excessive amounts of current may flow through these diodes, causing permanent damage to the device. If inputs are subject to overvoltage, insert appropriate series resistors to limit the diode current to less than 5 mA maximum. The input stage has two diodes between the input pins to protect the differential pair. Under high slew rate conditions, when the op amp is connected as a voltage follower, the diodes may become forward-biased and the source may try to drive the output. A small resistor should be placed in the feedback loop and in the noninverting input. The noise of a 100 Ω resistor at room temperature is ~1.25 nV/√Hz, which is higher than the AD8597/AD8599. Thus, there is a tradeoff between noise performance and protection. If possible, limiting should be placed earlier in the signal path. For further details, see the Amplifier Input Protection…Friend or Foe article at http://www.analog.com/amplifier_input. Because of the large transistors used to achieve low noise, the input capacitance may seem rather high. To take advantage of the low noise performance, impedance around the op amp should be low, less than 500 Ω. Under these conditions, the pole from the input capacitance should be greater than 50 MHz, which does not affect the signal bandwidth. NOISE AND SOURCE IMPEDANCE CONSIDERATIONS The AD8597/AD8599 ultralow voltage noise of 1.1 nV/√Hz is achieved with special input transistors running at high collector current. Therefore, it is important to consider the total inputreferred noise (eN total), which includes contributions from voltage noise (eN), current noise (iN), and resistor noise (√4 kTRS). eN total = [eN2 + 4 kTRS + (iN × RS)2]1/2 (1) where RS is the total input source resistance. This equation is plotted for the AD8597/AD8599 in Figure 58. Because optimum dc performance is obtained with matched source resistances, this case is considered even though it is clear from Equation 1 that eliminating the balancing source resistance lowers the total noise by reducing the total RS by a factor of 2. At a very low source resistance (RS < 50 Ω), the voltage noise of the amplifier dominates. As source resistance increases, the Johnson noise of RS dominates until a higher resistance of RS > 2 kΩ is achieved; the current noise component is larger than the resistor noise. 100 10 TOTAL NOISE RESISTOR NOISE ONLY 1 06274-076 The AD8597/AD8599 are not rail-to-rail input amplifiers; therefore, care is required to ensure that both inputs do not exceed the input voltage range. Under normal negative feedback operating conditions, the amplifier corrects its output to ensure that the two inputs are at the same voltage. However, if either input exceeds the input voltage range, the loop opens and large currents begin to flow through the ESD protection diodes in the amplifier. The AD8597/AD8599 amplifiers have been carefully designed to prevent any output phase reversal if both inputs are maintained within the specified input voltage range. If one or both inputs exceed the input voltage range but remain within the supply rails, the op amp specifications, such as CMRR, are not guaranteed, but the output remains close to the correct value. TOTAL NOISE (nV/ Hz) INPUT VOLTAGE RANGE OUTPUT PHASE REVERSAL Output phase reversal occurs in some amplifiers when the input common-mode voltage range is exceeded. As the commonmode voltage is moved outside the input voltage range, the outputs of these amplifiers can suddenly jump in the opposite direction to the supply rail. This is the result of the differential input pair shutting down that causes a radical shifting of internal voltages that results in the erratic output behavior. Rev. C | Page 15 of 20 0.1 10 100 1k SOURCE RESISTANCE (Ω) Figure 58. Noise vs. Source Resistance 10k AD8597/AD8599 general noise theory with extensive calculations, see the AN-358 Application Note, Noise and Operational Amplifier Circuits. A good selection table for low noise op amps can be found in AN-940 Application Note, Low Noise Amplifier Selection Guide for Optimal Noise Performance. An interesting note on using one section of a monolithic dual to phase compensate the other section is in the AN-107 Application Note, Active Feedback Improves Amplifier Phase Accuracy. The AD8597/AD8599 are the optimum choice for low noise performance if the source resistance is kept < 1 kΩ. At higher values of source resistance, optimum performance with respect to only noise is obtained with other amplifiers from Analog Devices. Both voltage noise and current noise need to be considered. For more information on avoiding noise from grounding problems and inadequate bypassing, see the AN-345 Application Note, Grounding for Low- and High-Frequency Circuits. For V+ 7 Q36 R18 R19 D1 D31 R31 D2 D34 6 2 INVERTING – INPUT Q18 Q19 D39 D41 D40 D42 C1 VB Q19 OUTPUT R1 Q20 D3 R32 3 NONINVERTING + INPUT Q32 Q27 Q28 4 V– Figure 59. Simplified Schematic Rev. C | Page 16 of 20 06247-079 D2 AD8597/AD8599 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 4.00 (0.1574) 3.80 (0.1497) 1 5 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 012407-A COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 60. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 0.60 MAX 5 TOP VIEW PIN 1 INDICATOR 2.95 2.75 SQ 2.55 8 12° MAX 0.50 0.40 0.30 0.70 MAX 0.65 TYP 0.05 MAX 0.01 NOM 0.30 0.23 0.18 SEATING PLANE 0.20 REF 1.60 1.45 1.30 EXPOSED PAD (BOTTOM VIEW) 4 0.90 MAX 0.85 NOM 0.50 BSC 0.60 MAX 1 1.89 1.74 1.59 PIN 1 INDICATOR FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATIONS SECTION OF THIS DATA SHEET. 101708-B 3.25 3.00 SQ 2.75 Figure 61. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm × 3 mm Body, Very Thin, Dual Lead (CP-8-2) Dimensions shown in millimeters ORDERING GUIDE Model AD8597ACPZ-R2 1 AD8597ACPZ-REEL1 AD8597ACPZ-REEL71 AD8597ARZ1 AD8597ARZ-REEL1 AD8597ARZ-REEL71 AD8599ARZ1 AD8599ARZ-REEL1 AD8599ARZ-REEL71 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] Z = RoHS Complaint Part. Rev. C | Page 17 of 20 Package Option CP-8-2 CP-8-2 CP-8-2 R-8 R-8 R-8 R-8 R-8 R-8 Branding A22 A22 A22 AD8597/AD8599 NOTES Rev. C | Page 18 of 20 AD8597/AD8599 NOTES Rev. C | Page 19 of 20 AD8597/AD8599 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06274-0-12/09(C) Rev. C | Page 20 of 20