Transcript
SiRFstarII GPS Architecture GSP2e/LP Family GPS Engine with Integrated Processor SIRFSTARII/LP ARCHITECTURE HIGHLIGHTS
GSP2e/LP PRODUCT HIGHLIGHTS
Industry Leading GPS performance - Builds on high performance SiRFstarIIe - Architecture supports user task integration - High speed signal acquisition using 1920 time/frequency search channels - WAAS, EGNOS and U.S. Coast Guard Beacon support - Patented multipath-mitigation hardware - Cold-start under 45 seconds Low Power - Under 175mW at full power - TricklePowerTM mode reduces power to under 60mW - Push-To-FixTM reduces power by as much as 98%
Low Power Digital IC - Advanced low power 0.18u CMOS process with embedded SRAM - Integrated ARM7TDMI™ processor up to 50 MHz - Supports 8-, 16-, and 32-bit data bus operations - Separate internal and external buses - On-chip 1 Mb (32KBx32) SRAM for GPS navigation - 8KB of cache memory and 32KB of ROM - Integrated high-precision Real-Time Clock - Extensive GPS peripherals, 2 UARTS, synchronous serial bus, battery-backed SRAM, and > 40 GPIO - 100TQFP, 144LQFP and 144 fpBGA packaging High Quality - 99% effective fault coverage - Memory with Built-In Self-Test (BIST) - Robust development environment and support More Compute Power for User Applications - Microprocessor throughput measured at up to 40MIPS
Maximizes GPS Position Availability - SingleSat updates in reduced visibility - Superior urban canyon performance - FoliageLock for weak signal tracking - Compatible with SiRFlocTM and SiRFDRiveTM
R T C XT AL R S 232 Power B attery
AGC
R E F XT AL
UAR T S erial Data T imemark
GS P2e/L P R es et Controller
(Optional) RF F ilter
2-B it Data
L NA
GPS Antenna Input
GR F 2i/LP
GP S CLK ACQCL K DAT A B US ADDR E S S B US
R OM
S R AM (Optional)
GS P 2eL P-01
Figure 1. Sample Architecture Diagram
GSP2e/LP Family GPS Engine with Integrated Processor SIRFSTARII/LP ARCHITECTURE DESCRIPTION
GSP2E/LP DIGITAL IC DESCRIPTION
SiRFstarIIe/LP architecture sets the standard for high volume GPS performance. The SiRFstarIIe/LP still uses 1920 corrolators and 12 channels to provide fast acquisition and reaquisition times, but peak current is reduced to under 65mA. TricklePower extends battery life even further by reducing current to under 20mA. Now superior performance features like SingleSat, SnapLock, and FoliageLock are available using less power.
The GSP2e/LP is a highly integrated GPS signal processor and microprocessor. The GPS performance is state of the art and the microprocessor is 20 times more powerful than required to support GPS alone. This leaves plenty of power to run user tasks. The GSP2e/LP is designed to be the ’engine’ that can drive an entire product such as an AVL tracking unit, handheld GPS, or chart plotter. The GSP2e/LP is also a low power chip, hence the “LP” designation. The chip can operate at under 30mA. In combination with the GRF2i/LP they can power a receiver using less than 175mW. In TricklePower™ mode power can be reduced to under 60mW. The GSP2e/LP is fully compatible with both the GRF2i/LP and GRF2i. To support the variety of applications, the GSP2e/LP is available in two series and three packages, 100-pin TQFP, 144-pin fpBGA, and 144-pin LQFP (32 bit bus).
The chipset consists of the GSP2e/LP, a tightly integrated digital chip with 40 MIPS of processing power and the GRF2i/LP, a low power version of the GRF2i integrated front end. The GSW2 software completes the package providing flexible system architecture for standalone GPS based products. SiRstarIIe/LP is an easy upgrade from the SiRFstarIIe and the best solution when low power, low cost, and high performance matter.
Table 1. GSP2e/LP Series Comparison Features
7450- 7451 Series 7460 Series
Data Bus
8/16 bit
8/16/32 bit
Address Lines
19 + 1
22 + 2
Address Range / CS
2MB
16MB
Interrupt Pins
1
3
Chip Selects
4
8
GPIO
13 (max.)
46 (max.)
External Bus Ready
No
Yes
Table 2. GSP2e/LP Packaging Options
2
Rev 1.1
Part Name
Pins
7450
100
Package TQFP
7451
144
BGA
7460
144
LQFP
March 2002
GSP2e/LP Family GPS Engine with Integrated Processor
Figure 2. GSP2e/LP Digital IC Internal Block Diagram
March 2002
Rev 1.1
3
GSP2e/LP Family GPS Engine with Integrated Processor FUNCTIONAL DESCRIPTION
Cache
The GSP2e/LP is the second chipset in the SiRFstarII architecture. To support the variety of possible applications, the family is available in two series: the 7450-7451 series has a 16-bit data bus and the 7460 series with a 32-bit data bus and additional peripherals. It has all the necessary on-chip processing and external interfaces to be the engine that drives a GPS-based product. It is a true system-on-a-chip architecture built on a low power 0.18u CMOS process, at 1.8V-core and 3.3V I/O pins. The internal functions are split into two main sections that are defined by the buses that run them. The ARM System Bus (ASB) has all the core CPU components and the SiRF IP bus (SIPB) contains all the GPS and other DSP peripherals.
A two-way 8KB associative instruction/data cache provides fast access to external cache source which gets selected by CS0 only.
ARM7TDMI The ARM7TDMI is an ideal core providing high performance and low power consumption. The ARM7TDMI CPU can run at speeds up to 50 MHz and is supported by a wide variety of development tools. Because the SSTE eliminates the need for the CPU to service high-rate interrupts, it is easier than ever to use the ARM processing power for user tasks. ARM JTAG The ARM7TDMI is an ideal core providing high performance and low power consumption. The ARM7TDMI CPU can run at speeds up to 50 MHz and is supported by a wide variety of development tools. Because the SSTE eliminates the need for the CPU to service high-rate interrupts, it is easier than ever to use the ARM processing power for user tasks.
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Rev 1.1
SRAM The on-chip SRAM size is 1-Mbit (32Kx32) memory that can be used for either instructions or data. In many applications, it completely eliminates the need for external data memory. The SRAM is designed for a combination of low power and high speed, and can support single cycle reads for all bus speeds. Boot ROM The Boot ROM contains a very small code set that can load a set of user code through the DUART into the SRAM and execute it. This allows the GSP2e/LP to be used as a measurement generator with no external memory. Real-Time Clock (RTC) RTC is an ultra-low power implementation of a high precision 32-kHz driven clock. It is separately powered by the VDDRTC to allow maximum battery life by maintaining time for the next power on. The precise time enables both TricklePower operation and SnapStart capability, which significantly reduces power consumption during normal operation.
March 2002
GSP2e/LP Family GPS Engine with Integrated Processor Clock/Power Management
Default Memory Map Configuration
This block manages the four major internal clocks: GPS, ACQ, CPU and RTC. It also controls the various power management modes and allows maximum power savings and system flexibility. Factory Testing The GSP2e/LP uses a memory built in self-test called MEMBIST to provide complete coverage of all the memory during chip testing and qualification. This is combined with the SCAN block using Automatic Test Pattern Generation (ATPG) to provide over 99% test coverage for the entire chip. Bus Interface Unit The Bus Interface Unit (BIU) provides an interface to external 8-, 16- and 32-bit memory and peripherals such as SRAM, ROM or Flash EEPROM with variable cycle timing. A 32-bit external memory can be accessed in byte, half-word and word mode by generating MUL[1:0] and MUB[1:0] signals according to ARM signals BSIZE[1:0] and BA[1:0]. Each chip select has by default the same 16-Mb memory size and an independent start address. The external source for Boot code be it ROM, SRAM, or Flash memory must be selected by CS0. The number of wait states for each bank can be independently set to a maximum of seven. In the 7460 series, a special pin called ERDY is provided for an external ready signal. This allows the chip to interface to very slow memories and external devices such as LCDs that occasionally require additional wait states.
March 2002
Rev 1.1
Address(26:0)
Signal
Description
7FF FFFF … 700 0000
CS7
Available
6FF FFFF … 600 0000
CS6
Available
5FF FFFF … 500 0000
CS5
Available
4FF FFFF … 400 0000
CS4
Available
3FF FFFF … 300 0000
CS3
Available
2FF FFFF … 200 0000
CS2
Available
1FF FFFF … 100 0000
CS1
Available
0FF FFFF … 000 0000
CS0
External BOOT ROM
SiRF Bridge Unit The SiRF Bridge Unit (SBU) is the key to the SiRFstarII architecture flexibility. It is a 16/32-bit bus optimized for minimal power consumption and reduced interface complexity to support the SiRF-developed IP blocks. All the internal peripherals are memory mapped through the SBU, which enables them to communicate directly with each other without interfering with the operation on the ARM system bus.
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GSP2e/LP Family GPS Engine with Integrated Processor Satellite Signal Tracking Engine (SSTE)
Beacon Processor
SSTE is the key portion of the GPS engine and communicates directly with the GPS/WAAS DSP. The SSTE handles all high-rate interrupts and feeds back tracking control to all 12 channels. After initialization from the navigation code, it can handle acquisition, tracking and reacquisition autonomously. The SSTE also contains a built-in data demodulator for GPS and WAAS signal structures.
The GSP2e/LP contains a DSP dedicated to processing USCG-compatible Beacon signals in the 300 kHz band. An external RF section providing amplification, filtering and A/D sampling is all that is required to provide full Beacon capability.
GPS and WAAS DSP The DSP is the heart of all SiRFstarII architecture, and connects directly to the GRF2i/LP and correlates the incoming signals with locally generated codes. Wide parallel search architecture enables simultaneous search of 1,920 time/frequency bins which enables a powerful combination of very fast reacquisition along with the capability to find and track very weak signals.
Synchronous Serial This standard 3-wire bus allows high-speed connections to an off-the-shelf SEEPROM and A/D devices. GPIO Unit Up to 46 GPIO lines are provided in the GSP2e/LP family to support a variety of peripherals. The GPIO unit centralizes management of all GPIO lines and provides a simple software interface for their control. DUART
Battery-Backed SRAM (BB-SRAM) The GSP2e/LP contains a small block of batterybacked SRAM which contains all necessary GPS information for hot starts and a small amount for user configuration variables. Interrupt Controller
The GSP2e/LP contains two full duplex serial ports. One port is normally used for GPS data reports and receiver control and the second serial port is used for the reception of differential corrections (RTCM). The transmit and receive side of each port contains a 16byte deep FIFO with selectable bit rates ranging from 1.2 to 115.2 Kbps.
The Interrupt Controller manages all possible sources of interrupts from within the SIPB. These includes the SSTE, Beacon, DSP, DUART and external user interrupts.
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March 2002
ED[15] ED[7] ED[14] ED[6] ED[13] ED[5] GND ED[12] ED[4] VDD ED[11] ED[3] ED[10] ED[2] ED[9] ED[1] ED[8] ED[0] MOE GND CS0 CS1 CS2 CS3 MWE
GSP2e/LP Family GPS Engine with Integrated Processor
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
GPIO4 AGCDAT GPIO3 GND CLKGPS GND CLKACQ PECLREF MAG VDD SIGN GND JTDI JTDO JTRST VDD JTMS JTCK SRESET RTCRST VDDRTC RIN ROUT TMODE WAKEUP
GSP2e/LP-7450
Index
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
EA[17] EA[16] VDD EA[15] EA[14] EA[13] EA[12] EA[11] EA[10] EA[9] TMBIST VDD EA[19] EA[18] EA[8] EA[7] GND EA[6] VDDK VDD GND VDD GND GND GND
1
GND DBGRQ GPIO1 PWRCTL EIT[0] SK SI SO TIMEMARK VDD RXA TXA RXB TXB MUL GND MUL[1] SCLK ECLK EA[0] EA[1] EA[2] EA[3] EA[4] EA[5]
GSP2eLP-03
Figure 3. GSP2e/LP-7450 Pin Configuration Diagram
Note 1: Please refer to Table 3 for signals which have alternate GPIO functions.
March 2002
Rev 1.1
7
GSP2e/LP Family GPS Engine with Integrated Processor SAMPLE MEMORY INTERCONNECT DIAGRAMS
VCC
VSTANDBY VCC
JTDI JTMS JTCK
CPU Supervisor
VCC
A[1:20]
JTRST SRESET
ED[0:15]
D[0:15] VCC
32.768 kHz 180K ROUT 15pF
15pF
BYTE RESET
A[1:20] EA[0:17]
ECLK
RIN
D7
68K
D15
68K
D8
68K
D0
68K 68K
D1
6 GRF2
CSO
CE
MWE
WE OE
MOE RTCRST TMBIST
MUL[0]
TMODE
MUL[1] CS[3:1]
CS[3:1]
GSP2e/LP-04
Figure 4. 7450-7451 Series VCC
GS P2e/LP7460
10M
15pF
RES ET A[0:21]
F LAS H ME MOR Y 8M X 16
S RE SET
180K R OUT
15pF
C E A[0:21] T R D D V
D D V
JT R S T
CPU S upervis or
32.768 kHz
A[2:23]
) 0 (1
JT DI JT MS JT CK E CLK
VCC
VS T ANDBY
F LAS H ME MOR Y 8M X 16
A[0:21]
A[0:21]
S R AM 8M X 16
S R AM 8M X 16
MWE MOE
WE OE D[15:0] CS
D[15:0] CS
D[15:0] CS UB LB
D[15:0] CS UB LB
E D[31:16] E D[15:0]
RIN 6 GR F 2
RT CR S T T MBIS T T MODE
R E S ET A[0:21]
) 2 (1 D N G
VCC
CS 0 CS 1 MUB1 MUB0 MUL1 MUL0 CS [7:2]
D15 D0 D1 D7 D8
68K 68K 68K 68K 68K
CS [7:2]
GS P2eLP -05
Figure 5. 7460 Series 8
Rev 1.1
March 2002
GSP2e/LP Family GPS Engine with Integrated Processor
1
2
3
A B
GND
C D
EA[3]
4
5
6
7
8
9
10
11
12
GND
VDD
EA[7]
VDD
EA[11]
EA[15]
EA[17]
RES
RES
GND
GND
EA[8]
EA[19]
EA[12]
VDD
EA[16]
WAKEUP
ROUT
EA[14]
TMODE
VDD
VDD
VDD
EA[18]
EA[9]
EA[5]
EA[2]
GND
EA[10]
VDDRTC 1.8V
EA[4]
TMBIST
SRESET
VDD
JTMS
EA[13]
GND
JTDI
GND
VDD
E
EA[1]
VDD-out 1.8V
F
ECLK
EA[0]
MUL[1]
SCLK
G
RXB
GND
VDD
MUL
PWRCTL
TXB
ED[9]
H
TXA
RXA
SI
SO
EIT[0]
GND
VDD
J
TIMEMARK
SK
DBGRQ
CS1
CS2
MOE
ED[11]
ED[12]
GPIO3
K
GPIO1
GND
GND
ED[1]
ED[2]
ED[4]
ED[6]
ED[14]
MWE
CS0
ED[0]
ED[3]
ED[5]
ED[8]
ED[10]
GND
L M
RES
EA[6]
CS3
RIN
RTCRST
JTCK
JTRST
JTDO
SIGN
PECLREF
MAG
CLKACQ
GND
CLKGPS
GND
GPIO4
AGCDAT
ED[7]
RES
RES
RES
ED[13]
ED[15]
RES
RES
Figure 6. GSP2e/LP-7451 144 pin BGA Ball Configuration Diagram (Top View)
Note 1: Unused balls are not tied to any signal. Note 2: Balls marked RES are reserved and should not be connected. Note 3: Please refer to Table 3 for signals which have alternate GPIO functions.
March 2002
Rev 1.1
9
GSP2e/LP Family GPS Engine with Integrated Processor Table 3. GSP2e/LP-7450-1 Series Pin Identification Name
7450 Pin
7451 Ball
Name
7450 Pin
7451 Ball
Name GND
7450 Pin
7451 Ball
Name
7450 Pin
7451 Ball
81
M8
SRESET
94
E8
87
K10
TIMEMARK / GPIO9
42
J1
11
E7
AGCDAT
77
K12
ECLK
32
F1
CLKACQ
82
H12
ED[0]
58
L6
CLKGPS
80
J12
ED[10]
63
M7
CS1 / GPIO13
54
J4
ED[11]
65
J7
GPIO3
78
J9
TMODE
99
C10
CS2 / GPIO14
53
J5
ED[12]
68
J8
GPIO4
76
K11
TXA
39
H1
F9 & G2 TMBIST
CS3 / GPIO15
52
M4
ED[13]
71
M9
JTCK
93
D12
TXB
37
G6
GPIO1
48
K1
ED[14]
73
K9
JTDI
88
F10
VDD
3
A7
DBGRQ / GPIO0
49
J3
ED[15]
75
M10
JTDO
89
E12
EA[0]
31
F2
ED[1]
60
K5
JTMS
92
E10
12
B9 G10
EA[10]
9
D7
ED[2]
62
K6
JTRST
90
E11
20
A5
EA[11]
8
A8
ED[3]
64
L7
MAG
84
G12
22
C6
EA[12]
7
B8
ED[4]
67
K7
MOE
57
J6
41
C2
EA[13]
6
F8
ED[5]
70
L8
MUL[0]
36
G4
66
C3
EA[14]
5
C9
ED[6]
72
K8
MUL[1]
34
F3
85
H7
EA[15]
4
A9
ED[7]
74
L9
MWE
51
L4
91
E9
83
EA[16]
2
B10
ED[8]
59
M6
PECLREF
G11
VDD-out 1.8V
19
E5
EA[17]
1
A10
ED[9]
61
G7
PWRCTL / GPIO8 47
G5
VDDRTC
96
D8
EA[18]
14
C7
EIT[0] / GPIO10
46
H5
RIN
97
C12
WAKEUP
100
EA[19]
13
B7
GND
17
B3
CS0
55
L5
RES
B11 A11
EA[1]
30
E3
21
B5
ROUT
98
B12
A12
EA[2]
29
D3
23
A4
RTCRST
95
D11
L10
EA[3]
28
D1
24
B4
RXA
40
H2
L11
EA[4]
27
E6
25
D6
RXB
38
G1
L12
EA[5]
26
D2
35
G9
SCLK
33
F4
M3
EA[6]
18
F6
50
J11
SI / GPIO5
44
H3
M11
EA[7]
16
A6
56
K3
SIGN
86
F12
M12
EA[8]
15
B6
69
H6
SK / GPIO7
45
J2
EA[9]
10
C8
79
K4
SO / GPIO6
43
H4
10
Rev 1.1
March 2002
GSP2e/LP Family GPS Engine with Integrated Processor
GPIO43 GPIO44 GPIO45 ERDY ED[15] ED[7] VDD ED[14] ED[6] ED[13] ED[5] GND ED[12] ED[4] VDD ED[11] ED[3] ED[10] ED[2] GND ED[9] ED[1] ED[8] ED[0] MOE GND CS0 CS1 CS2 CS3 MWE CS4 GND EIT[1] MUB[0] MUB[1]
.
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
SRESET RTCRST VDDRTC RIN ROUT TMODE WAKEUP GPIO39 GPIO38 GPIO37 GPIO36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
EIT[2] GPIO42 GPIO41 GPIO40 GND BREAKPT GPIO4 AGCDAT GPIO3 GND VDD CLKGPS GND CLKACQ PECLREF MAG VDD SIGN GND JTDI JTDO JTRST VDD JTMS JTCK
GSP2e/LP-7460
Index
2
3
4
5
6
7
8
9
DBGRQ GPIO1 PWRCTL EIT[0] SK SI SO TIMEMARK VDD RXA TXA RXB TXB MUL GND MUL[1] SCLK ECLK EA[0] EA[1] EA[2] EA[3] EA[4] EA[5] ED[18] ED[26] ED[19] VDD ED[27] ED[20] ED[28]
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
CS7 CS6 CS5 EA[21] EA[20] EA[17] EA[16] VDD EA[15] EA[14] EA[13] EA[12] EA[11] EA[10] EA[9] TMBIST VDD EA[19] EA[18] EA[8] EA[7] GND EA[6] VDDK VDD GND VDD GND GND ED[31] GND ED[23] ED[30] ED[22] ED[29] ED[21]
1
ED[16] ED[24] ED[17] GND ED[25]
GSP2eLP-07
Figure 7. GSP2e/LP-7460 Pin Configuration Diagram
Note 1: Please refer to Table 4 for signals which have alternate GPIO functions.
March 2002
Rev 1.1
11
GSP2e/LP Family GPS Engine with Integrated Processor Table 4. GSP2e/LP-7460 Series Pin Identification Name
Pin 7460 Name
Pin 7460 Name
Pin 7460 Name
Pin 7460
AGCDAT
116
85
22
54
ED[0]
GND
MUL[0]
BREAKPT / GPIO2
114
ED[10]
91
26
MUL[1]
52
CLKACQ
122
ED[11]
93
28
MWE
78 123
CLKGPS
120
ED[12]
96
29
PECLREF
CS1 / GPIO13
81
ED[13]
99
31
PWRCTL / GPIO8
65
CS2 / GPIO14
80
ED[14]
101
53
RIN
137
CS3 / GPIO15
79
ED[15]
104
69
CS0
82
CS4 / GPIO16
77
ED[16] / GPIO20
72
76
ROUT
138
CS5 / GPIO17
3
ED[17] / GPIO21
70
83
RTCRST
135
CS6 / GPIO18
2
ED[18] / GPIO22
43
89
RXA
58
CS7 / GPIO19
1
ED[19] / GPIO23
41
97
RXB
56
GPIO1
66
ED[1]
87
113
SCLK
51
DBGRQ / GPIO0
67
ED[20] / GPIO24
38
118
SI / GPIO5
62
EA[0]
49
ED[21] / GPIO25
36
121
SIGN
126
EA[10]
14
ED[22] / GPIO26
34
127
SK / GPIO7
63
EA[11]
13
ED[23] / GPIO27
32
GPIO3
117
SO / GPIO6
61
EA[12]
12
ED[24] / GPIO28
71
GPIO4
115
SRESET
134
EA[13]
11
ED[25] / GPIO29
68
GPIO36
144
TIMEMARK / GPIO9
60
EA[14]
10
ED[26] / GPIO30
42
GPIO37
143
TMBIST
16
EA[15]
9
ED[27] / GPIO31
39
GPIO38
142
TMODE
139
EA[16]
7
ED[28] / GPIO32
37
GPIO39
141
TXA
57
EA[17]
6
ED[29] / GPIO33
35
GPIO40
112
TXB
55
EA[18]
19
ED[2]
90
GPIO41
111
VDD
EA[19]
18
ED[30] / GPIO34
33
GPIO42
110
17
8
EA[1]
48
ED[31] / GPIO35
30
GPIO43
108
131
EA[20]
5
ED[3]
92
GPIO44
107
25
EA[21]
4
ED[4]
95
GPIO45
106
27
EA[2]
47
ED[5]
98
JTCK
133
40
EA[3]
46
ED[6]
100
JTDI
128
59
EA[4]
45
ED[7]
103
JTDO
129
94
EA[5]
44
ED[8]
86
JTMS
132
102
EA[6]
23
ED[9]
88
JTRST
130
119
EA[7]
21
EIT[0] / GPIO10
64
MAG
124
EA[8]
20
EIT[1] / GPIO11
75
MOE
84
VDD-out 1.8V
EA[9]
15
EIT[2] / GPIO12
109
MUB[0]
74
VDDRTC
136
ECLK
50
ERDY
105
MUB[1]
73
WAKEUP
140
12
Rev 1.1
125 24
March 2002
GSP2e/LP Family GPS Engine with Integrated Processor Table 5. GSP2e/LP Signal Description Signals
Type
Table 5. GSP2e/LP Signal Description (Continued)
Descriptions
Signals
Type
Descriptions
Address and Data Pins - CPU Interface
GRF2i/LP Interface - AGC Data and Clock
EA[21:0]
O
System address bus.
AGCDAT
O
Automatic gain control serial data.
ED[15:0]
IO
Lower 16 bits of the bi-directional system data bus. Note: ED[0, 1, 7, 8, 15] are power-up configuration bits and do not have pull-up resistors.
CLKGPS
In_P
Differential GPS clock input to PECLREF. It is PECL (Pseudo ECL) compatible.
CLKACQ
In_P
Differential data acquisition clock to PECLREF. It is PECL compatible.
Higher 16 bits of the bi-directional system data bus.
MAG
In_P
Differential satellite magnitude bit to PECLREF. It is PECL compatible.
SIGN
In_P
Differential satellite data bit to PECLREF. It is PECL compatible
In_P
PECL input reference voltage. It is PECL compatible.
ED[31:16]1, 5
IO
CS[0]1
O
External memory chip select.
CS[3:1]1, 5
IO
External memory chip select.
CS[7:4]1, 5
IO
External memory chip select.
PECLREF
MWE, MOE
O
External memory write enable and output enable.
Peripheral Interface SI, SO, SK2, 5
IO
Synchronous serial interface (in, out and clock).
PWRCTL3, 5, 6
IO
GRF2i/LP Power Control.
2,5
IO
1 PPS timemark output.
In
Reserved.
MUL[1:0]
O
External memory byte select.
MUB[1:0]
O
External memory word select.
ECLK
In
External clock source.
SCLK
SRESET
ERDY
O
In
In
System clock. All the control signals on the system bus synchronize with the system clock.
TIMEMARK
Low level sensitive reset to initialize the system and ARM7TDMI to known states.
TXA, TXB
O
Serial outputs for channel A and B.
RXA, RXB
In
Serial inputs for channel A and B.
External slave to de-assert ERDY to add the additional wait states to the memory cycle. To assert ERDY high to terminate the memory cycle.
EIT[0]1, 5
IO
External interrupt[0].
EIT[2:1]1, 5
IO
External interrupt[2:1].
RTC Interface Pins RTCRST
In
RTC reset.
RIN
In
32 kHz clock input
ROUT
O
WAKEUP
O
Active low wake up from the RTC.
GPIO[4]3
IO
GPIO Lines
March 2002
32 kHz clock output
Rev 1.1
TMODE, TMBIST
Debug Interface Pins JTDI, JTDO, JTCK, JTRST, JTMS
In
JTAG Interface.
DBGRQ2, 5
IO
DBGRQ ICE BREAKER interface.
BREAKPT2
In
Processor Break
13
GSP2e/LP Family GPS Engine with Integrated Processor Table 5. GSP2e/LP Signal Description (Continued) GPIO Lines
Type
Descriptions
GPIO [0, 1, 3, 5, IO 6, 7, 9] 2, 4
GPIO Lines
GPIO [2, 36-45] 2, 4
IO
GPIO Lines
GPIO [4]3, 6
IO
GPIO Lines
GPIO [8]3
IO
GPIO Lines
GPIO [10, 1315] 1, 4
IO
GPIO Lines
GPIO [11, 12, 16-35] 1, 4
IO
GPIO Lines
VDD
Supply
GSP2e/LP Supply
VDDRTC
Supply
RTC Circuit Supply
GND
Ground
GSP2e/LP Ground
VDD-out
O
VDD-out at 1.8V
Supply
Note 1:Internal pull-up resistor Note 2:Internal pull-down resistor Note 3:Default output high at reset Note 4:Default input at reset Note 5:Share function with GPIO Line Note 6:Although both GPIO[4] and PWRCTL are set to output high at reset, only PWRCTL will be set to output high on RTC interrupt
14
Rev 1.1
March 2002
GSP2e/LP Family GPS Engine with Integrated Processor ELECTRICAL SPECIFICATIONS This data sheet contains information about SiRF products in their development and sampling phases. SiRF reserves the right to make changes in its products, specifications and other information at any time without notice. SiRF assumes no liability or responsibility for any claims or damages arising out of the use of this data sheet, or from the use of integrated circuits based on this data sheet, including, but not limited to claims or damages based on infringement of patents, copyrights or other intellectual property rights. SiRF makes no warranties, either express or implied with respect to the information and specifications contained in this data sheet. Performance characteristics listed in this data sheet do not constitute a warranty or guarantee of product performance. All terms and conditions of sale are governed by the SiRF Terms and Conditions of Sale, a copy of which you may obtain from your authorized SiRF sales representative. Table 6. Absolute Maximum Ratings Parameter
Symbol
Min
Max
Units
Power Supply Voltage VDD
-0.3
3.6
V
Input Pin Voltage 1
VIN
-0.3
5
V
Output Pin Voltage
VOUT
-0.3
Output Current
IOUT
Storage Temperature TSTG
-45
VDD+0.3
V
±25
mA
125
°C
Table 7. Operating Conditions Parameter
Min Typ 2.7 1 3.3
Max
Units
Power Supply Voltage VDD
Symbol
3.6
V
Power Supply Voltage VDDRTC
1.65
1.95
V
1.8
Input Pin Voltage
VIN
0
3.6
V
Operating Temperature
TOPR
-40
85
°C
Operating Current
ICC
50 2
mA
Note 1: 2.7V operation limits CPU speed to max 25MHz. Note 2: At 3.3V and CPU speed at 12MHz.
Table 8. Battery Conditions Parameter
Symbol
RTC Power
VDDRTC
Supply Current
IDDRTC
Power Supply
VDD
Note 1:
Min 1.65
1
Typ
Max
1.8
1.95
10 0
0
Units V µA
0
V
Guaranteed by design.
Note 1: Does not apply to RIN/ROUT Warning – Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability.
March 2002
Rev 1.1
15
GSP2e/LP Family GPS Engine with Integrated Processor DC CHARACTERISTICS Table 9. DC Characteristics Parameter
Symbol
Min
Input High Level
Vih
2.0
-----
Input Low Level
Vil
-----
0.8
PECL Input High Level Vihp
Max
Conditions
Units V V
PECLREF+0.1
PECL Input Low Level
Vilp
PECL Input peak-topeak Voltage
Vpp
200
Output High Level
Voh
2.4 @ 3.0V 2.2 @ 2.7V
Output Low Level
Vol
Input Leakage Current
Ii
V PECLREF-0.1
mV
0.4
2
V
Ioh=2mA for CS, TXB, TXA, TIMEMARK, SO, SI, SK, EIT[0,1,2], PWRCTL, DBGRQ, GPIO, BREAKPT, AGCDAT, JTDO, WAKEUP Ioh=4mA for EA, ED, MUL[0,1], MUB[0,1], MWE, MOE Ioh=6mA for SCLK
V
Iol=2mA for CS, TXB, TXA, TIMEMARK, SO, SI, SK, EIT[0,1,2], PWRCTL, DBGRQ, GPIO, BREAKPT, AGCDAT, JTDO, WAKEUP Iol=4mA for EA, ED, MUL[0,1], MUB[0,1], MWE, MOE Iol=6mA for SCLK
V
2
µA
Input Capacitance 1
3
pF
Output Capacitance 1
3
pF
Bi-directional Buffer Capacitance 1
3
pF
PECL Input Capacitance 1
7
pF
Input High Level1
Vih
1.27
-----
SRESET_N, RTCRST, WAKEUP_N, TMODE are 1.8V input and 3.3V tolerant.
V
Input Low Level1
Vil
-----
0.57
SRESET_N, RTCRST, WAKEUP_N, TMODE are 1.8V input and 3.3V tolerant.
V
Note 1: Guaranteed by design.
16
Rev 1.1
March 2002
GSP2e/LP Family GPS Engine with Integrated Processor AC CHARACTERISTICS All measurements in Tables 10 and 11 are characterized except as noted with (*) which are guaranteed by design. Table 10. AC Characteristics for Write Access Parameter List
Timing
Max
Unit
SCLK -> EA
T1
Min
10
ns
SCLK -> CS
T2
12
ns
SCLK -> MWE
T3
3.5
ns
SCLK -> MUL, MUB*
T4
7
ns
SCLK -> ED*
T5
7
ns
MWE Pulse Width*
T8
SCLK -> MUL, MUB*
T9
20 10
ns ns
SCLK -> MWE
T10
3.5
ns
SCLK -> EA
T11
10
ns
SCLK -> CS
T12
10
ns
SCLK -> ED*
T13
0
ns
SCLK T1
T11
EA CS
T8 T2
T12
T3 T10
MWE T4
T9
MUL, MUB ED
T13
T5
Figure 8. Write Access Timing Diagram
March 2002
Rev 1.1
17
GSP2e/LP Family GPS Engine with Integrated Processor
Table 11. AC Characteristics for Read Access Parameter List
Timing
Min
Max
Unit
SCLK -> EA
T1
10
ns
SCLK -> CS
T2
10
ns
SCLK -> MUL, MUB*
T4
7
ns
SCLK -> MOE
T6
3.5
ns
SCLK -> MOE
T7
MOE Pulse Width*
T8
3.5
ns
SCLK -> MUL, MUB*
T9
10
ns
SCLK -> EA
T11
10
ns
10
ns
20
ns
SCLK -> CS
T12
SCLK -> ED HOLD*
T13
10
ns
SCLK -> ED SET UP
T14
25
ns
SCLK T1
T11
EA CS
T2
T8
T6
T12
T3 T7
MOE T4
T9
MUL, MUB ED T14
T13
Figure 9. Read Access Timing Diagram
18
Rev 1.1
March 2002
GSP2e/LP Family GPS Engine with Integrated Processor
Table 12. AC Characteristics for Ready Access All measurements in this table are guaranteed by design. Parameter List
Timing
Min
Unit
CSN -> ERDY
T15
15
ns
CSN -> ERDY
T16
10
ns
SCLK T15
T16
ERDY
EA CS MWE MUL, MUB ED
Figure 10. Read/Write Timing with Wait State Insertion Timing Diagram
March 2002
Rev 1.1
19
GSP2e/LP Family GPS Engine with Integrated Processor
Table 13. SCLK and Reset Timing All measurements in this table are guaranteed by design. Parameter
Symbol
Rise/fall time
T17
Min
Max
Units
5
ns
Clock pulse width
T18
5
ns
Clock period
T19
20
ns
Reset duration
T20
200
µs
T19
T17
T18
SCLK
T17 T18 T20
SRESET
Figure 11. SCLK and Reset Timing Diagram
Table 14. Maximum Output Loading
20
Name
AC
Unit
EA
50
pF
SCLK
50
pF
MWE
50
pF
CS
20
pF
MOE
50
pF
ED
50
pF
MUL
50
pF
MUB
50
pF
Rev 1.1
March 2002
GSP2e/LP Family GPS Engine with Integrated Processor MECHANICAL SPECIFICATIONS
Top View
Side View
_ 0.2 16.0 + _ 0.1 14.0 + 75
51
1.0 MAX
0.05-0.15 1.2 MAX
_ 0.2 16.0 +
50
_ 0.1 14.0 +
76
INDEX 0.45~0.75 100
26
1
0.5
Dimensions are in mm. Drawing not to scale.
25
0.2 +_ 0.07 0.03
GSP2e/LP-13
Figure 12. GSP2e/LP-7450 100 Pin TQFP Package
March 2002
Rev 1.1
21
GSP2e/LP Family GPS Engine with Integrated Processor
Figure 13. GSP2e/LP-7451 144 BGA Package 22
Rev 1.1
March 2002
GSP2e/LP Family GPS Engine with Integrated Processor
Top View
Side View
22.00BSC 20.00BSC 108
73
1.4 + 0.05
1.6 MAX
0.05-0.15
20.00BSC
22.00BSC
72
109
_ 0.15 0.6+
INDEX
37
144
1
0.5
Dimensions are in mm. Drawing not to scale.
36
0.17~0.27
GSP2e/LP-15
Figure 14. GSP2e/LP-7460 144 Pin LQFP Package
March 2002
Rev 1.1
23
GSP2e/LP Family GPS Engine with Integrated Processor ADDITIONAL INFORMATION Item
Description
SiRF Application Notes APNT0003
Troubleshooting Guide
APNT0004
System RF Front-end Requirements for SiRFstar Architectures
APNT0006
PCB Design Guidelines
APNT0007
Open Short Detector
APNT0010
GRF2i QFN Introduction
APNT0015
SiRFstarII S2AR Back-up Power Operation
APNT0014
Connecting GSP2e/LP and ARM Multi-ICE
APNT0017
Board Level Design for GSP2e/LP
APNT0018
SiRFstarIIe Low Power Operating Modes
APNT0019
SSII CPU Clock and Hardware Detection
APNT0020
Implementing User Tasks on the SiRFstarIIe
APNT0021
S2AM Hardware Reference Design Description
APNT0023
Effect of Increasing User Task Duty Cycle on Performance
APNT0028
Battery Backed SRAM Operation at 49MHz with the GSP2e/LP
APNT0029
GSP2e and GSP2e/LP Cache
APNT0030
EHPE and EVPE Calculations
24
Rev 1.1
March 2002
GSP2e/LP Family GPS Engine with Integrated Processor ORDERING INFORMATION Part Number
Description
GSP2e/LP Options GSP2eLP-7450
GSP2e/LP, 16-bit, 100-pin, TQFP
GSP2eLP-7451
GSP2e/LP, 16-bit, 144-pin, BGA
GSP2eLP-7460
GSP2e/LP, 32-bit, 144-pin, LQFP
Compatible Parts GRF2iLP-0214
GRF2i/LP, 32 pin QFN
GRF2iLP-0210
GRF2i/LP, 48-pin, LQFP
Development Tools 9900-0110
SiRFstarIIe/LP Evaluation Kit
9900-1001
SiRFstarIIe/LP System Development Kit (SDK)
March 2002
Rev 1.1
25
GSP2e/LP Family GPS Engine with Integrated Processor
USA SiRF Technology, Inc. 148 E. Brokaw Road San Jose, CA 95112 Tel: +1-408-467-0410 Fax: +1-408-467-0420 Email:
[email protected] Website: http://www.sirf.com EUROPE United Kingdom Office SiRF Technology, Inc. Tel: +44-1344-668390 Fax: +44-1344-668157 Email:
[email protected] TAIWAN SiRF Technology, Inc Room 130, 4F., No. 200, Sec. 1, Keelung Road Taipei, Taiwan, R.O.C. Tel: +886-2-2723-7853 Fax: +886-2-2723-7854 E-mail:
[email protected]
©2001 SiRF Technology, Inc. All rights are reserved. Protected by U.S. Patents #9740398W, #5,897,605, #5,901,171, #5,917,383, #6,018,704, #6,037,900, #6,041,280, #6,047,017 and #6,081,228. Other U.S. and foreign patents are pending. SiRF, the SiRF logo and SiRFstar are registered trademarks of SiRF Technology, Inc. SnapLock, Foliage Lock, TricklePower, SingleSat, SiRFLoc, SiRFDRive, and WinSiRF are trademarks of SiRF Technology, Inc. Other trademarks are property of respective companies. This document contains information on SiRF products. SiRF reserves the right to make changes in its products, specifications and other information at any time without notice. SiRF assumes no liability or responsibility for any claims or damages arising out of the use of this document, or from the use of integrated circuits based on this data sheet, including, but not limited to claims or damages based on infringement of patents, copyrights or other intellectual property rights. No license, either expressed or implied, is granted to any intellectual property rights of SiRF. SiRF makes no warranties, either express or implied with respect to the information and specification contained in this document. Performance characteristics listed in this document do not constitute a warranty or guarantee of product performance. SiRF products are not intended for use in life support systems or for life saving applications. All the terms and conditions of a sale are governed by SiRF Terms and Conditions of a Sale, a copy of which you may obtain from your authorized SiRF sales representative.
Printed in USA - March 2002
Rev 1.1
Part Number: 1055-1024
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