Transcript
\NABCC
~~ An American-Standard Company
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SERVICE MANUAL 6042 B
AVI ASCII INTERFACE PANEL (OPTION #2)
.. ...
May, 1981 A-81-200-2289-2
UNION SWITCH & SIGNAL DIVISION WESTINGHOUSE AIR BRAKE COMPANY Swissvale, PA 15218
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CONTENTS Page
Section I
II
III
IV
GENERAL
1-1
1.1 1.2 1.3
1-1 1-1 1-2
OPERATION
2-1
2.1 2.2 2.3 2.4 2.5
2-1 2-4 2-6 2-15 2-16
THEORY OF OPERATION (Basic) ASCII INTERFACE PROGRAMMING THEORY OF OPERATION (Detailed) ASCII WIRE WRAP PANEL CONNECTIONS ASCII OUTPUTS STATUS BITS
INSTALLATION
3-1/2
3.1 3.2
3-1/2 3-1/'2
MOUNTING INTERCONNECTIONS
TROUBLESHOOTING
4-1
4.1
4-1 4-1 4-1 4-2 4-11 4-11 4-15 4-18 4-21 4-26
4.2
v.
PURPOSE GENERAL DESCRIPTION INDICATIONS
BASIC TROUBLESHOOTING 4.1.1 Special Equipment 4.1.2 Preliminary Set-Up 4.1.3 Basic Diagnostic Procedure DETAILED TROUBLESHOOTING 4.2.1 Incorrect Key On Operation 4.2.2 Incorrect Transmit Indication 4.2.3 No Output At Terminal 4.2.4 rncorrect or No Data At Terminal 4.2.5 Incorrect Format At Terminal
DRAWINGS AND PARTS LIST
5-1/2
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SECTION I GENERAL
1.1
PURPOSE
The purpose of the ASCII Interface Panel, when used in conjunction with the basic AVI Decoder Logic Unit, is to provide a means to output AVI data from the basic Decoder Logic Unit in a standard ASCII code format, compatible with teletype or other serial interface devices (CRT's etc.). The ASCII Interface Panel has the optional capability to generate the necessary characters (carriage return, line feed and spaces) to allow the AVI data from a given train to be outputted to a terminal device in a readable format.
1.2
GENERAL DESCRIPTION
The ASCII Interface Panel N451412-0204 provides an interface from the Decoder Logic Panel N451412-0202 to an ASCII Communication Channel. This ASCII interface is constructed of CMOS integrated circuits on a 60 position wire wrapped panel. It interfaces with the decoder drawer via 26 conductor flat cable connections and is designed to fit into a basic AVI Decoder Logic Unit. Outputs to the communications channel, via opto-isolators, are provided for 20 milliampere current loops for teleprinters and EIA RS232-C data interfaces. External power sources are necessary for these interfaces. Information outputted from the ASCII can be programmed via jumpers to include:
r
1.
Spaces between various digits and between various data words.
2.
Line feed and carriage returns to control a teleprinter.
3.
Selectable bit rate from 75 through 9,600 baud.
4.
Odd, even, fixed or no parity bits.
These jumpers are located in positions Al7, A22, and A27 on the interface panel. The interface also includes two LEDs, KEY ON and TRANSMIT, that indicate when the device is in operation. Provisions have been incorporated into the design to allow for future adaptation to a memory system. In addition, a non-formatted output (Data Only) is available. 6042-B, p. 1-1
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1.3
INDICATIONS
The label on the inside of the cover of the Decoder Logic Unit type N451465-0601 (Figure 1-1) shows the location of two (2) LEDs. The TRANSMIT LED is lit when the ASCII panel is outputting data. The KEY ON LED is lit when the track circuit is occupied and also when the track circuit is unoccupied and the ASCII panel is still outputting data. The KEY ON LED will be lit constantly when the optional constant key on jumper is selected in location A17.
6042-B, p. 1-2
AVI ASCII CONVERTER JUMPER OPTION DESIGNATIONS
Location A17 - Message Parity 12 3 4 5 67 8 -
J6
J7
J6
J7
POWER SUPPLY UJ725836
16 Odd Parity 15 Parity Generator Output 14 Parity Bit =Mark 13 Parity Bit = Space 12 Parity = 8th Bit 11 Constant Key On 10 Inhibit 110 Bits/Sec. 9 110 Bits/Sec.
AC
AC
-
+
II
II
r·1
Location A22 - Output Frequency
TWISTED PAIR
I Io. LEDi
l...i
123 4 5 6 78 -
16 75 Bits/Sec. 15 150 Bits/Sec. 14 300 Bits/Sec. 13 600 Bits/Sec. 12 1200 Bits/Sec. 11 2400 Bits/Sec. 10 4800 Bits/Sec. 9 9600 Bits/Sec.
TRANSMIT
[:] KEY ON
Location A27 - Format
O"'I
0 ,!:::,,
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I
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1 - 16 1 Sign Per Line Format 2 - 15 2 Signs Per Line Formal 3 - 14 4 Signs Per Line Formal 4 - 13 5 - 12 Output 6 Digits 6 - 11 Space Alter Digit 6 7 - 10 Suppress Spaces 8 - 9 Formatted System
"""'SEE TAB. D A17
D A22
D
ERROR MESSAGE CARRIER DETECTOR CAB SIGNAL
I
GOOD ~ O MESSAGE O O TRACK O O KEY ON
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........... ,1:::,,
Figure 1-1.
WTWISTED PAIR
I I DECODER UN451412-0202
I
I RECEIVER U~45.1404-5501
N451465-0601
tO I-' I
j I I
3 TEST RECEIVER
BG3
A27
ASCII INTERFACE PANEL UN451412-0204
I
Decoder Logic Unit Major Component Location
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SECTION II OPERATION
2.1
THEORY OF OPERATION (Basic)
The ASCII interface converts the AVI message data, stored in the decoder shift register, into ASCII characters and serially outputs the ASCII characters to a terminal device. A block diagram is shown in Figure 2-1. This interface is controlled via signals from the basic decoder N451412-0202. When valid message data is received and decoded at the decoder, either a Good or Error Message indication is forwarded to the ASCII device. When a Good Message indication is received by the priority register, the twenty-eight data bits (DBl through DB28), from the decoder are dumped into the data register by a Load Msg signal, and a Cycle Output signal is generated to enable the transmit control logic. The transmit control logic dumps the first four bits of data from the data register into the ASCII output register, along with a 4 bit formatting character from the format generator, to produce the 8 bit ASCII character. The data is shifted out of the ASCII register at a rate determined by the baud rate counter. This rate is selectable from 75 through 9600 baud via program jumpers. ASCII start and two stop bits are automatically added. After data is dumped from the data register to the ASCII output register, the scan counter is advanced one count, gating the next group of 4 data bits out of the data register, When the first ASCII character has been shifted out of the ASCII register, the next character is immediately loaded into the ASCII register from the data register for transmission, The scan counter is then advanced one count more. After all of the 7 characters (4 bits each) have been transferred from the data register to the ASCII register, the Cycle Output signal is removed and data transmission is terminated when the ASCII register is emptied of the last character. The Good Message indication is also cleared and the interface is enabled to accept additional data from the decoder when available. When an Error Message indication is received by the ASCII interface from the decoder, the data bits are not dumped into and out of the data register. The Error Message indication causes the priority register and format generator to dump the ASCII character equivalent to an equal sign"=" into the ASCII output register in place of the seven characters of invalid data. This equal sign character is interpreted as a message received in error at the decoder. 6042-B, p. 2-1
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The Format Generator also generates three additional characters which are useful in arranging hardcopy printout on the terminal device. These characters are: 1. 2. 3.
Space Carriage Return Line Feed
Spaces can be inserted after the first two digits of a message (route number) and between the four digit car number and the status character. They may also be completely eliminated from a message printout. Formatting of these spaces is controlled via programming jumpers. Carriage return and line feed characters can also be used to format data on the terminal device. The format generator contains a counter that counts the number of messages printed out per line in a formatted system. This counter can be programmed, via jumpers, to format between one and seven messages on one line of printout, automatically inserting a carriage return after the set number of messages. When multiple messages are outputted on a line, 3 spaces are inserted after the end of each message to physically separate the hardcopy printout of each message. In addition, in a formatted system, the input from the track circuit interface on the decoder to the ASCII interface will generate a carriage return and line feed whenever the track circuit is occupied and also when the track circuit is unoccupied. This produces a blank line between a group message from one train and the next. Unoccupying of the track circuit generates an additional ASCII character, End Of Transmission (EOT), to indicate the end of data from one train. This EOT character is non-printing on the terminal device, but it can be used by an ASCII compatible interface to a computer terminal to indicate end of data. When using an ASCII compatible computer terminal, a non-formatted system is generally recommended. The non-formatted data consists of only ASCII characters for the message data, without any special formatting characters such as carriage return, line feed and spaces. These "control" characters are more easily serviced by the intelligence in the computer itself. The EOT character is available as a terminator to indicate end of data for a particular sequence of signs. The track circuit input also controls a Key On indication which may be used to control a data set, turning on the carrier device whenever the track circuit is occupied and turning it off whenever the track circuit is unoccupied. The carrier equipment may be keyed on constantly by a jumper option in location Al7.
6042-B, p. 2-2
DATA FROM DECODER 28 BITS
,r SCAU COUNTER
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153.6 KHz._
BAUD RATE SELECTOR COUNTER
-
MSTR
DATA REGISTER
••
BAUD RATE CLOCK
....
......
E xternal A SCII 'B USS
Til1ING LOGIC
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,
OUTPUT SHIFT
...
...
.0
•
EXTERNAL
CONTROL INPUTS
DATA ... OPTICAL COUPLER
..
...
•• 1
CONT!lOL .... REGISTER
1•
ASCII OUTPUT REGISTER
TRANSMIT
EXTERNAL
.
IF
FORMAT LOGIC
•• u GOOD MSG. ERROR I1SG. O'I
0 ~
N
TRACK
.
...
......
PRIORITY
CYCLE_ OUTPUT'"
TRANSMIT CONTROL
KEY-ON
... T
OPTICl\.L COUPLER
REGISTER
....
I
..trJ
.
i-o N
I
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Figure 2-1.
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ASCII Interface Panel Block Diagram
,1 ~8
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2.2
ASCII INTERFACE PROGRAMMING
The ASCII interfaces incorporates an area in location Al?, A22, and A27 that provides a means of programming the format, output baud rate and message parity of the ASCII data. The formatted system is engaged by adding a jumper between location A27, pins 8 and 9. With this jumper installed, the remaining jumpers in location A27 provide the various formatting functions. Jumpers installed in A27, pins 1 to 16, pins 2 to 15, and pins 3 to 14, provide a means of formatting between one and seven signs per line of printout. The jumper between A27, pin 5 and pin 12, will suppress the output of the status digit when installed. Note: (Format XX [ ] XXXX, X indicates a digit,[] indicates a space). The jumper installed in A27, pins 6 and 11, will place a space before the status digit output. (Format xx[] xxxx[]x.} The jumper installed in A27, pins 7 to 10, will suppress all spaces. (Format: XXXXXXX.) These jumpers may be used in any combination to produce the required format. When a jumper is not installed in A27, pins 8 to 9, the output will not be formatted. Line feeds, carriage return and spaces will be automatically suppressed and data will be outputted as a continuous string of digits. However, note that the jumper A27, pin 5 to pin 12, will still be effective, allowing the suppression of the status word transmission. The jumpers in location A22 provide the means of selecting output baud rates from 75 bits/sec. to 9600 bits/sec. In addition, the jumper in Al7, pin 8 to 9, will select 110 bits/ sec. Only one of these baud rate select jumpers must be installed at any time. Also, when NOT using the 110 bit/sec. output rate, a jumper MUST BE INSTALLED in Al?, pin 7 to pin 10, to inhibit the 110 Hz circuit operation; otherwise, improper operation of the output frequency generator will occur. The remaining option available in location Al7 is concerned with the parity bit control of the ASCII data word.
6042-B, p. 2-4
A jumper installed in location Al7, pin 2 to 15, will insert a parity generator on the eighth bit input to the ASCII output register. This generator will then calculate an even parity bit from the first seven bits of ASCII data available on the data buss. If an additional jumper is installed in location Al7, pins 1 to 16, the parity generator will calculate an odd parity bit for the ASCII word. Three other parity options are available. A jumper installed in Al7, pins 3 to 14, will cause the eighth ASCII bit {parity bit) to be a MARK. A jumper installed in Al7, pin 4 to 13, will cause the parity bit to be a space. A jumper installed in Al7 . 5 to 12, will connect the parity bit input of the ASCII ' pin output register to the Bit 8 line on the ASCII data buss. One of the message parity options must be installed for proper operation of the ASCII Interface. A jumper installed in Al7, Pin 6 to 11 will cause the data set output to be keyed on constantly. ASCII Interface Jumper Option Designations Location Al7 - Message Parity 1 2 3 4 5 6 7 8
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16 15 14 13 12 11 10 9
Odd Parity Parity Generator Output Parity Bit= Hark Parity Bit= Space Parity= 8th Bit Constant Key On Inhibit 110 Bits/Sec. 110 Bits/Sec.
Location A22 - Output Frequency 1 2 3 4 5 6 7 8
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16 15 14 13 12 11 10 9
75 Bits/Sec. 150 Bits/Sec. 300 Bits/Sec. 600 Bits/Sec. 1200 Bits/Sec. 2400 Bits/Sec. 4800 Bits/Sec. 9600 Bits/Sec.
Location A27 - Format 1 2 3 4 5 6 7 8
-
16 15 14 13 12 11 10 9
1 Sign Per Line Format 2 Signs Per Line Format 4 Signs Per Line Format Output 6 Digits Space After Digit 6 Suppress Spaces Formatted System 6042-B, p. 2-5
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2.3
THEORY OF OPERATION (Detailed) and 5-3)
(Refer to Figures 5-1, 5-2,
The AVI Interface is controlled by and receives data from the AVI Decoder Logic Panel N451412-0202. The basic control signals received by the ASCII Interface are:
*NOTE:
TRAK, MASTR, TEST, GMST, AND EMST In the following explanations, gates are defined by location and output pin number.
TRAK is a logic 1 level signal whenever the track circuit activating the AVI decoder is occupied. MSTR is a logic O pulse generated by the decoder when power is first applied to the equipment. Its function is to reset the ASCII Interface upon power turn on. TEST is a logic 1 level whenever the decoder is in the test mode. TEST inhibits the ASCII device from outputting the test messages provided in the decoder to keep ~xtraneous data from being transmitted. GHST. and EMST are logic O pulses that indicate a good or error message has been received by the decoder and data is available for transmission. Twenty-eight bits of data are transferred to the ASCII device upon receipt of GMST. The ASCII device develops several timing pulses to synchronously control data flow, based upon the input from the decoder. This timing is controlled by the baud rate generator and timing logic ICs Al3, Al4, Al8 ,. A20, A23 and A24. A 153.6 KHz squarewave input from the decoder on pin BJ2-ll is divided down by the binary counter Al8 to produce frequencies from 9600 to 75 Hertz. One of these frequencies can be selected via program jumpers (Location A22) to provide the proper frequency of operation at the required output baud rate. NAND gate A23 and dual D flip-flop IC24 provides a 110 .Hertz output by dividing the input clock by 1396. When the 110 Hertz output is not selected, the program jumper in location Al7-7 to Al7-10 must be installed to inhibit operation of IC24. Otherwise, improper operation of the binary counter IC18 will result, producing an incorrectly timed clock frequency. This occurs because the output of counter Al8 is decoded by A23 after 698 counts to set flip-flop A24, pin 1 (one-half cycle of a 110 Hertz squarewave is 698 counts). A24, pin 2, resets the counter via gate Al4, pins 1 and 3, causing the counter Al8 to again count from zero to 698 for the next half cycle. If the jumper is not installed in Al7-7 to Al7-10, the 110 Hertz generator is enabled constantly. The reset signal from A24, pin 2, will reset the counter Al8 every 698 counts, causing the lower frequency outputs to be disabled. When the jumper is installed in Al7-7 to Al7-10, the flip-flop A24 will not be 6042-B, p. 2-6
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set after 698 counts, the reset to counter Al8 will be inhibited, allowing it to divide and count properly. If data is not available for transmission, the Baud Rate Clock signal is inverted and gated via NAND/NOR gates A20, pins 3 and 4 (as Transmit Clock} and A3 to the clock enable flip-flop A8, pin 1. The Transmit Clock generates a Clock Enable signal on its positive edge and causes an overlapping clock 1 and clock 2 pulse to be generated on the next two cycles of the 153. 6 KHz clock. (See Figure 5-4, Timing Diagram.} ti/hen Clock 2 occurs, the clock enable flip-flop is reset, and clock 1 and clock 2 are reset on the next two cycles of the 153.6 KHz signal. These two clocks (clock 1 and clock 2), along with clock enable, produce three independent clock signals that are used to synchronize the operation of the ASCII Interface. The ASCII Interface commences operation when the track circuit is occupied (Refer to Figure 5-4, Timing Diagram.} Receipt of a logic 1 TRAK input at BJ2-15 generates an 18 millisecond logic O going KEY+ TRAK pluse, which sets the occupy flipflop (B30, pin 2} on its trailing positive going edge. The track input is also inverted and sets a flip-flop A30-13 that produces an Enable Key pulse from A3, pin 13. Enable Key immediately generates a Key On signal that turns off the optical isolator Al0-15, allowing the external Key On signal to go to EIA + volts, keying on any attached data set. Note that the key on is immediate, while the occupy flip-flop is set 18 milliseconds later. This delay allows the carrier equipment to stabilize. When the constant Key On jumper option is used, the optical isolator Al0-15 is held off by the input on A2, Pin 15. Track Occupancy - Formatted System If the ASCII Interface is configured in the formatted mode by installing a jumper in location A27-8 to A27-9, the CR flipflop B25-15 is set on the next positive (leading~dge} of clock 1 after the occupy flip-flop is set. The CR signal is fed via inverter B26, pin 6, to the priority encoder IC B24, that encodes the input D6 into an octal 6 (110} on its output (QC B24, pin 6, most significant digit} and also sets the cycle output signal B24-14 to a logic 1. The octal 6 outputs on QA to QC of the priority encoder are fed into a decoder IC-B23, that decodes the octal number 6 and outputs a logic 1 on its "6" output B23, pin 7. The output of the decoder chip drives two lines ENCR + LF and ENCR and LF + EOT, that enable two groups of four tri-state, non-inverting gates (via Bl6, pin 1 and Bl7, pin 1}. These gate array loads the eight bit ASCII character for a line feed 01010001 on the tri-state ASCII data buss lines, Bit 1 through Bit 8.
6042-B, p. 2-7
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The Cycle Output logic 1 signal from B24, pin 14, is fed via the Xl input and Zl output on the quad and/or select chip A3 to the transmit flip-flop (A8, pin 11). On the next positive edge of the Transmit Clock (logic O edge of Baud Rate Clock), the transmit flip-flop is set (A8, pin 15) and the output cycle is initiated. Before the output is initiated, the count down counter Al9 is held reset by the transmit flip-flop. The CO output (pin 12) is at a logic 1. Immediately after the transmit flip-flop is set and'the reset to the Counter Al9 is removed, the logic 1 state of CO and the logic O level of the Baud Rate Clock at pin 6 of Al9 cause the counter to be preset to a count of 11. CO then immediately goes to a logic O, generating a two microsecond Dump Pulse from single shot All, pin 6. This Dump Pulse loads the data from the 8 bit ASCII data buss into the output shift register A6 and the "start bit" (space) into flip-flop A7, pin 15. The transmit flip-flop also enables gate Al4, pin 13, allowing the Baud Rate Clock to produce a Shift Clock that moves the data out of the shift register at the selected baud rate. The Transmit signal also gates the data out to the optical isolators in a manner that when the transmit flip-flop is reset, all serial data lines are marking. Note that Clock Enable, Clock 1 and Clock 2 are inhibited by gate A30, pin 4 on the cycle of Transmit Clock when the transmit flip-flop is first set (after start is logic 1, but Transmit is still a logic 0). This prevents extra clocks from skipping over the first word of data. As data is being shifted out of the shift register A6, logic l's are shifted in. After nine shift clock pulses, all ASCII data bits are shifted out and the logic 1 shifted through the register appear as the ASCII stop bits. After eleven shift clock pulses have occurred, the count 11 counter has counted down to zero, causing the CO output Al9, pin 12, to go to a logic 1. This CO signal gated with Transmit through NANO/NOR gates A20, pins 13 and 4, generates a logic 1 Transmit Clock pulse. The Transmit and Transmit Clock signals are gated through the AND/OR select gates X2 and X3 inputs and generate Clock Enable and Clock 1 and Clock 2 pulses. With the CR flip-flop B25, pin 15, set, clock 1 and Empty combine through gate B27, pin 3, to set flip-flop B30, pin 15. This flip-flop through XOR gates B21, pins 3, 12, and 13, changes Bits 1 through 3 of the ASCII data buss producing the ASCII character for a carriage return 10110001 on the ASCII data buss and also generates a reset through gates B22, pin 12, and B27, pin 13, that resets the occupy flip-flop via B30, pin 4.
6042-B, p. 2-8
Since the CR flip-flop is still set, the Cycle Output signal from the priority encoder B24 and the Start signal remain at a logic 1, and the transmit flip-flop remains set. When the Baud Rate Clock goes to a logic O, the CO output of the count 11 counter Al9, presets the counter to 11 and CO then goes to a logic 0, generating another Dump pulse from single shot All, pin 6. The ASCII character for carriage return is dumped into the output shift register A6 and this character is shifted out of the output register. When the count 11 Counter Al9, has again counted down to zero (CO goes to logic 1), indicating that the carriage return character has been outputted, another Transmit Clock, Clock Enable, Clock 1 and Clock 2 are generated. Clock 1, in conjunction with flip-flop B30, pin 5, resets the CR flip-flop B25, pin 15, removing the CR input to the priority register. The Cycle Output and Start signals go to a logic O and the priority encoder output goes to 000 (octal). The decoder B23 "6" output then goes to a logic O (the unused zero output goes to a logic 1) removing the logic OEN CR+ LF and EN CR+ LF + EOT signals from tri-state gates Bl6 and Bl7, pin 1. With all of the tri-state gates disabled, the ASCII data buss is tied to a logic 1 level through lOOK resistors in Al, and no data appears on this buss. When CO goes low, producing a Dump Pulse, all l's are loaded into the ASCII output register A6. The logic O Start and Dump Pulse combine through gates A29, pin 4, and A30, pin 3, to produce a reset signal at pin 12 of the transmit flip-flop A8. The transmit flip-flop resets, ending the transmission and the output lines are held in the marking state. The reset signal at A30, pin 3, also attempts to clear the TRAK flip-flop A30, pin 13; it cannot since the track circuit is still occupied and TRAK is still logic O. The next logic O edge of the Baud Rate Clock generates a Transmit Clock and Clock 1 and 2, to reset flip-flop B30, pin 15. The ASCII Interface is now available to accept another input from the decoder. If the format jumper is removed from A27, pin 8, to A27, pin 9, the ASCII Interface will not generate line feeds and carriage returns. A logic 1 from gate B27, pin 4, holds the CR flipflop reset, preventing the priority encoder B24 from receiving the CR input.
6042-B, p. 2-9
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Data Transmission - Good Message Refer to Figures 5-5 and 5-6, Timing Charts. After a valid message has been received and decoded by the AVI decoder card and data is available for transmission, the decoder outputs a logic 11 0 11 GMST (Good .Message Strobe) pulse to the ASCII Interface. If the ASCII Interface is not currently processing a message, both the good and error message flip-flop BlO are reset and the NO MSG signal B20-4 is a logic 1. The G.MST signal on BJ2-18 sets the Good USG flip-flop Bl0-1 whenever the Clock Enable-Clock 2 cycle is not occurring, via gate A2-6. As soon as the Good MSG flip-flop becomes set, the No HSG signal goes to a logic O, preventing any further message input from being accepted until after the current message has been processed. Since No MSG was initially a logic 1, the scan counter BlS was reset and the empty signal Bl5, pin 2, is a logic 1. The Good MSG flip-flop generates a 2 microsecond Load MSG pulse through single shot All, pin 10, that together with EMPTY Bl4, pin 2, strobes the 28 bits of message information into the data registers B2, 3, 4, 6, 7, 8, 9. These data registers have tri-state outputs and are sequentially strobed by the scan counter to output the data in seven groups of four bits each. The output of the Good MSG flip-flop BlO, pin 1, is fed to the priority encoder B24, Dl input, that produces a logic 1 at the 11 1 11 output of the decoder B23, pin 1. The decoder output generates a logic O NUMBERS signal at Bl8, pin 12, and a logic O ERROR+ NUMBERS signal at B22, pin 3. ERROR+ NUMBERS enables the Scan Counter Bl5 and NUMBERS, together with one of the outputs of the Scan Counter, enables the first 4 bit data register B4. Since the data is in complement BCD form (BCD), the data from the digits is fed to tri-state inverter Bl3, before being tied to the first four bits (Bit 1 through Bit 4) of the ASCII data buss. The ERROR + NUl1BERS signal enables gates Bl6, Bl 7, pin 15, to generate the numbers mode character on Bits 5 through B8 of the ASCII buss. The ASCII buss has the first BCD character on the first four bits (Bit 1 Bit 4). and 1101 on Bits 5 through Bit 8. The Cycle Output signal from the priority encoder B24 generates a Start signal and on the next cycle of the transmit clock, the transmit flip-flop is set and a Dump pulse is generated in the same manner as discussed previously under "Track Occupancy". Note that the Enable Clock, Clock 1 and Clock 2 cycle is inhibited on the transmit clock cycle during which the transmit flip-flop is set. Since Clock 2 does not occur during this cycle, the scan counter remains in the first count (QO output is a logic 1), enabling the first data register B4. After the transmit flip-flop is set, the Shift Clock is enabled and the data is shifted out of the Shift Register A6, to the terminal device. When the CO output goes positive after 11 6042-B, p. 2-10
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'V"Av"'" counts of counter Al9 and a Transmit Clock, Clock Enable, Clock 1 and Clock 2 cycle is generated, the Scan Counter is advanced by one count and the second group of BCD data is placed on the ASCII buss from B9. When CO goes to logic O, a Dump pulse is again produced, loading the next data word into the ASCII output register A6. The transmission cycle continues with the seoond ASCII character. The Scan Counter Ql output is now a logic 1, generating a logic 1 Space signal through gates B20, pins 12 and 13, provided a jumper is not inserted in A27, pin 7, to A27, pin 10 {which disables space). When the next Clock 1 pulse occurs after the second data word is outputted, the Space input flip-flop B25, pin 1, is set, producing another input to the priority encoder that generates the ASCII character for space. Note that both the Space input and Good MSG signals are present at the inputs to the priority encoder B24. This priority encoder chip operates in a manner that a higher number input has priority. The Space input is connected to input D4, while Good MSG is connected to Dl. Therefore, the priority encoder generates an octal 4 output {100) that enables the 4 output of the decoder B23 and disables the 1 output. Since the 1 output is removed, the NU.HEERS and ERROR+ NUUBERS signals go to a logic 1, disabling the tri-state output of the data registers and inverter Bl3. The scan counter is also disabled, preventing it from advancing on the following Clock 2 pulse. The 4 output of the decoder B23 generates logic OEN SPACE signal at Bl2, pin 1, and also holds tri-state gates Bl6 and Bl7 on, through pin 15, producing an ASCII character for space 00000101 on the data buss. When _CO again goes low, the Dump pulse loads the space character into the ASCII register for transmission. After the space character is transmitted, another Clock 1 pulse is generated that resets the Space input flip-flop B25, pin 1. The Space input is removed from the priority register and decoder, and the NUMBERS and ERROR+ NUMBER return to logic O. Clock 2 advances the Scan Counter Bl5 one count, (Bl5, pin 3, is a logical 1) and the next BCD character is placed on the ASCII data buss. The transmission process continues and the remaining characters are loaded and shifted out. An optional space may be included after the 6 digit and before the status bits are loaded by placing a jumper in A27, pin 6 to A27, pin 11. After all of the characters have been transmitted out, Clock 2 causes the scan counter Q7 output Bl5, pin 10, to go to a logic 1, generating a logic zero LAST DIGIT pulse at gate B20 pin 3. This LAST DIGIT pulse triggers a two microsecond single shot that resets the good message flip-flop through gate Bl9, pin 12,removing the good message input from the priority
6042-B, p. 2-11
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encoder. The No MSG signal goes high, enabling the good and error message flip-flops and resetting the scan counter BIS, permitting the interface to accept another message. The Last Digit single shot A21, pin 6, also clocks the message per line counter A28, sets the space flip-flop B25, pin 1, and resets the divide by 3 counter B29. The space input flip-flop and 7 3 counter B29 cause a space to be outputted for 3 character times. This produces three spaces after each message on the terminal device, separating the message. When the last space has been outputted, the space flip-flop is reset by Clock 1. Since there is no input to the priority register, the Cycle Output and Start signals go to logic zero, the transmit flip-flop is reset by the nexc Dump pulse, and data transmission ceases. This .process is repeated completely for every message received. The message per line counter, A28, is programmable via jumpers in A27 to output from 1 to 7 messages per line. When this counter reaches a count of zero, the Line Full signal goes to a logic 1, presetting the Occupy flip-flop B30, pin 2, and resetting Space flip-flop through gate B22, pin 13. Therefore, a line feed and carriage return is generated after the message instead of three spaces. If an error message is received from the decoder, the Error !IBG flip-flop BlO, pin 15, is set and an Error MSG signal is sent to the priority encoder input D2 that generates an ----EN ERROR signal from the decoder. The ASCII character for an equal sign"=" 1011 1101 appears on the ASCII data buss Bit 1 through Bit 8. The ERROR+ NUUBER signal also goes to a logic zero, enabling the Scan counter. However, data is not loaded into the data register (B2, 3, 4, 6, 7, 8, 9). The ASCII "=" character is loaded into the ASCII output register and transmitted out. Timing is otherwise the same for a good or error message. Spaces, line feed and carriage returns are inserted where applicable, since the scan and message per line counters are functioning.
Track Unoccupy - Formatted System When the track circuit becomes unoccupied, the TRAK input to the ASCII Interface goes to a logic O, setting the Unoccupy flip-flop B28, pin 1. When the Empty line is a logic 1, indicating that a message is not being outputted, the next Clock 1 pulse sets both the CR flip-flop B25, pin 15, and the EOT flip-flop, B28, pin 15. The CR and EOT signals are both fed to the priority encoder. Since CR is connected to a higher priority input, a line feed and then a carriage return are outputted by the ASCII device. After completion of the carriage return character, the EOT signal causes the ASCII end of transmission character 0010 0000 to appear on the ASCII buss. After this character is dumped into and transmitted out of the ASCII data register, the next Clock 1 cycle resets the EOT flip-flop. With no further input to the priority 6042-B, p. 2-12
WABCO
~Av' encoder, Cycle Output and Start go to a logic O. When the Dump pulse occurs, the transmit flip-flop is reset because of a logic O Start signal input to gate A29, pin 4. Since TRAK is a logic 0, the signal at A30, pin 3 that resets the Transmit flip-flop, also resets the TR.AK flip-flop A30, pin 13. The Key On signal is removed and the data set key output optical isolator turns on, disabling the data set if the constant Key On option is not selected. No further data transmission will occur until the track circuit is reoccupied. Non-Formatted System If the format jumper in location A27, pins 8 to pin 9, is removed, the carriage return, line feed logic and the space logic are inhibited by resets produced by gates B27, pin 4, and B22, pin 13. Space, carriage returns and line feeds will not be outputted by the ASCII Interface. Good and error message data will be outputted, character by character, until the track circuit is unoccupied. An intelligent terminal such as a minicomputer, etc. should be connected as the terminal device to receive the ASCII characters and format and output them in the desired fashion. The EOT character is still outputted upon track unoccupancy to indicate the end of data from a particular train. (See Figure 5-7, Timing Chart.)
Output Circuitry The ASCII Interface couples to data sets or terminals via optical isolators. Data is available in either EIA RS232-C or current loop outputs. The data outputs are in the marking state, current loop closed and at EIA minus volts whenever data is not being transmitted. The Key On output is at EIA plus volts when the track circuit is occupied and at EIA minus volts whenever the track circuit is unoccupied. When the constant Key On option is selected, the Key On Output is always EIA plus volts. The output connections are listed below. Note power supplies must be supplied externally. Output connections refer to connector J6 on the rear of the decoder drawer.
6042-B, p. 2-13
WABCCI
~
Connector J6
Signal
Pin 6
EIA +V input
1
EIA -V input
3
EIA Data Output
4
EIA Key Output
20
Current Loop Common (-)
22
Current Loop (+). Requires External Resistor to Limit Current and External Power Supply.
24
20 Ma. Current Loop. (Built in 510 Ohm Resistor; Requires 12 voe Series Power Supply. )
External Control Input External control inputs and signal outputs are provided on connector AJl to externally control and monitor operation of the ASCII Interface. These signals interface with the timin~ logic through AND/OR select gates A3 and the priority encoder B24. The 8 bit tri-state ASCII buss is also available for input/output through connector AJl. If the EXT control input AJl-18 is tied to logic O (0 volts), the Z outputs of the AND/OR select gate are fed from the Y inputs rather than the X inputs. EXT data ready replaces cycle output, an EXT clock replaces the transmit clock signal to the clock 1, and clock 2 generators, and an EXT Key On replaces the Track Circuit Key On inputs. A cycle output signal is available to indicate when data is present for output. A Buss Busy signal indicates when the ASCII buss is busy, i.e., when data is being loaded into the ASCII output register. An external inhibit (EXT INH} and EA"T Hand EXT L signals are available into the priority encoder B24 to control this device to disable the output of characters to the ASCII buss, if required. Presently, these inputs are unused but they have been provided for future application. These inputs have been terminated with 100 K resistors to prevent improper operation of the system when they are unused. 6042-B, p. 2-14
WABCO
'V'"4""V"
2.4
ASCII WIRE WRAP PANEL CONNECTIONS AJ2 (J2-9}
AJl (.Jl-8}
DBl
1.
1. Buss Bit 1
2.
DB2
2.
2. Buss Bit 2
BJl (Jl-10}
BJ2 (J2-lll
1.
1.
2. 3.
DB24
3.
DB3
3.
3. Buss Bit 3
4.
DB23
4.
DB4
4.
4. Buss Bit 4
5.
DB22
5.
DBS
5.
5. Buss Bit 5
6.
DB21
6.
DB6
6.
6. Buss Bit 6
7.
DB20
7.
DB7
7.
7. Buss Bit 7
8.
DB19
8.
DB8
8.
9.
DB18
9.
9.
10.
DB17
10.
10.
EIA Data
10.
11.
DB16
11.
153.6KHz
11.
EIA Key
11.
12.
DB15
12.
DB28
12.
13.
DB14
13.
DB27
13.
14.
DB13
14.
MSTR
14.
14.
EXT IN
15.
DB12
15.
TRAK
15.
15.
EXT H
16.
DBll
16.
16.
16.
EXT L
17.
DBlO
17.
TEST
17.
17.
EXT DATA READY
18.
DB9
18.
GUST
18.
18.
EXT CONTROL
19.
19.
EMST
19.
19.
EXT CLOCK
20.
20.
0 Volts IN
20.
20.
EXT KEY-ON
21.
21.
+ Volts IN
21.
21.
Buss Busy
22.
22.
22.
23.
23.
23.
24.
24.
24.
25.
25.
DB25
25.
26.
26.
DB26
26.
Note:
EIA -V
8. Buss Bit 8 9.
12. EIA +V
ICOM
13.
22. 23.
IC OUT
24. 25.
I IN+
Cycle Output
O Volts
26.
Refer to the following page. 6042-B, p. 2-15
WABCCI
~
NOTE BJl connects to AJl on AVI Decoder BJ2 connects to AJ2 on AVI Decoder AJ2 connects to J4 on Interface PCB AJl connects to JS on Interface PCB (only when required) ASCII OUTPUTS STATUS BITS
2.5
The last four information bits, DB25 through DB28, are status bits encoded in binary, that indicate the state of the Lead Car Indications DB25, the Cab Signal Indication DB26, and two spare indications DB27 and DB28. Since these bits are binary, rather than BCD encoded, outputs greater than 9 decimal are possible. The table below gives the possible combinations of these bits and their ASCII equivalent character. DB28
DB27
DB26 Cab Signal
DB25 Lead Car
ASCII Equivalent
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1
0
1
0
1
0
1
1
;
(Semi-Colon)
1
1
0
0
<
(Less than)
1
1
0
1
=
(Equals)
1
1
1
0
>
(Greater than)
1
1
1
1
? (Question Mark)
6042-B, p. 2-16
(Colon)
WABCO ~
USA STANDARD CODE FOR INFORMATION INTERCHANGE BIT NUMBERS
I
I
b,
b"
6
I
bs
b4
bl
''''' 0
0
0
0
0 0
0
0
0 0 0 1
1
1 1
BS
so SI OLE
1
1
1
HT LF VT FF CR
1 1
1
1
NUL SOH STX ETX EQT ENO ACK BEL
0 1
0 0 0 0 1 1 1
1
.
... ! ~ • '
bl
b,
0 0 1
0
1,0
Oo0
Oo 1
o, 0
0
1
2
3
4
5
6
7
o, 1 lo lo 1 0
11
1
NUL
OLE
SP
0
@
p
1
0 1
SOH
DC1
I
1
A
a
'a
q
0
2
STX
DC2
II
2
B
R
b
r
1
1
3
ETX
OC3
#=
3
c
s
c
s
0
0
4
EOT
OC4
$
4
0
T
d
t
0
1
NAK
%
u
SYN
a:
F
u v
e
ACK
5 6
E
0
5 6
ENO
1 1
f
v
1
7
BEL
ETB
I
7
G
w
g
w
0
0 1
8 9
BS
CAN
8
H
x
h
x
HT
EM
( )
i
v
1
0
10
LF
SUB
*
1
1
11
VT
ESC
0
0
12
FF
FS
0 1
1
13
CR
GS
0
14
so
RS
1
1
15
SI
us
0
p
.
I
y
J
z
i
z
+
i
K
(
k
{
<
L
\
I
I
I
=
M
I
m
}
N
A
n
,,...,
0
-
0
DEL
.
./
9
> ?
'
I
CONTROL FUNCTION DEFINITIONS Null, or all zeros OC1 Device control 1 Start of heading Device control 2 DC2 Start of text OCJ Device control 3 End of text OC4 Device control 4 End of transmission NAK Negative acknowledge Enquiry SYN Synchronous idle End of transmission block Acknowledge ETB CAN Cancel Bell, or alarm EM End of medium Backspace Substitute Horizontal tabulation SUB Escape Line feed ESC FS File ~parator Vertical tabulation Group separator Form feed GS Carriage return Record separator RS Shift out Unit separator Shift in Space SP Data link escape Delete DEL
us
Figure 2-2.
USASCII Code
6042-B, p. 2-17/18
WABCD
~
SECTION III INSTALLATION
3.1
MOUNTING
The ASCII Interface Panel, N451412-0204 is mounted in the left front section of the Decoder Logic Unit, type N451465-0601, (Refer to Figure 1-1 for location). Mounting is accomplished by slipping the panel onto five #4x40 screws and securing with five lock washers and nuts.
3.2
INTERCONNECTIONS
Electrical connections to the Decoder Logic Unit circuitry are made through two ribbon cables with connectors. A cabling diagram is attached to the cover of the Decoder Logic Unit and is also shown in Figure 1-1. The cabling from the ASCII Interface Panel is connected as follows: Connector BJl on the ASCII panel connects to AJl on the Decoder Panel. Connector BJ2 on the ASCII panel connects to AJ2 on the Decoder Panel. Connector AJ2 on the ASCII panel connects to J4 on the Power Distribution & Interface PCB. Connectors AJl on the ASCII panel connects to JS on the Power Distribution & Interface PCB. Insure that the connectors are properly aligned before firmly mating the connectors to prevent possible damage due to misalignment.
6042-B, p. 3~1/3-2
SECTION IV TROUBLESHOOTING
4.1
BASIC TROUBLESHOOTING
The procedures listed in this section and accompanying flow charts outline a check and troubleshooting guide to aid in repairing a defective ASCII Interface Panel, N451412-0204. Refer to the detailed circuit operation of the ASCII Interface Panel in Section 2.3 of this manual before performing this procedure: 4.1.1
Special Equipment 1. 2. 3. 4.
4.1.2
ASCII compatible terminal device, teletype, cathode ray terminal (CRT}, etc. Mating connector for J6 on decoder, see Section 5.4.1 in system's manual (6042). Power supply or supplies, ±12 volts D.C. or as required by terminal device. Complete working AVI carborne and wayside system. Preliminary Set-Up
1.
Check the defective ASCII Interface Panel for shorts in the power supply input wiring between connector pins BJ2-21 (+V) and BJ2-20 (OV). The power busses are connected to the conductive layers on top (OV} and bottom (+V) of the wirewrap panel. Visually inspect the panel for broken or shorted wires, and properly inserted integrated circuits and components.
2.
Install the ASCII Interface Panel into the Decoder Logic Unit drawer of a known working AVI system. Refer to the Decoder Logic Unit section in the basic manual to verify operation of decoder before connecting cables to ASCII panel. (See Figure 1-1 for hookup instructions.)
3.
Determine the input requirements of the terminal device, whether EIA or current loop compatible, bit rate and parity bit requirements. Connect the terminal device to the decoder drawer using the mating connector for J6. See Figures 4-1 for EIA connections. See Figure 4-2 for current loop connections.
6042-B, p. 4-1
WABCC
~
4.
Insert jumpers in location Al7 and A22 to program the correct bit rate and parity bit format into the ASCII panel as required by the terminal device. Refer to detailed theory description Section 2.3 for details. Example: A. B.
c.
For 110 hertz operation to a standard teletype
Remove Jumper Al7-7 to Al7-10 Add Jumper Al7-8 to Al7-9 Remove all jumpers from Location A22.
For ODD Parity output: A. B.
Add Jumper Al7-2 to Al7-15 Add Jumper Al7-l to Al7-16
Program the ASCII Interface Panel to output formatted signs, four per line by inserting the following jumpers into Location A27.
5.
A. B.
c.
Add Jumper A27-3 to A27-14 Add Jumper A27-6 to A27-ll Add Jumper A27-8 to A27-9
Remove all other jumpers in Location A27.
4.1.3
Basic Diagnostic Procedure 1.
2.
Energize the terminal device, terminal interface power supplies and decoder drawer. Also insure that the terminal device is operating properly. A.
Current loop is closed and either 20 or 60 milliamperes of current are flowing in the current loop. Adjust power supply for proper current leve 1.
B.
Check EIA circuit for a minus voltage potential (marking condition) at terminal input. If there are any problems, check connections to terminal; refer to Detailed Troubleshooting, Section 4.2.3, No Output At Terminal.
Energize the track circuit power supply to activate the decoder. Check that the TRACK and KEY ON LEDs on the Decoder Logic Panel are lit. Check that the KEY ON LED on the ASCII panel is lit and the TRANSMIT LED blinks on momentarily upon energizing the track circuit power supply.
6042-B, p. 4-2
I
~
INT
RETURN
'\)
- - ' / > - - ~ 7 f 20 MILLIAMPERES \ +v
510
------.+.-_. . . .
AJ2-26
J6-24
+-OR
?-->-----~>~\~\h,,.-R_E_T_u_R_N_::;tl_ _ _ _ _ _.., ...
_r_c_o_u_T_ _
AJ2-24
TO TERMINAL
R EXT
J6-22
.________':_-_, ......r__c~o_M_ _~~~-----).~~---------~ AJ2-22
+
J6-20
+ Figure 4-2 CURRENT LOOP CONFIGURATION
12 VDC POWER SUPPLY
*NOTE: R EXT Selected to meet current loop requirements of terminal.
+v
EIA +V ----------~~~--------~)~~~~~~~~--, AJ2-13
J6-6 I
AS
EIA DATA J6-3
TO TERMINAL AS
COM
~I--~---~~~--------~
L..._ _ _ _ __....,
AJ2-8
Figure 4-1 EIA DATA CONFIGURATION
J6-l
+ 12 VDC POWER SUPPL
+ 12 VDC POWER SUPPL
6042-B, p. 4-3
WABCO
~
The terminal device should upspace one line after receiving a Carriage Return (CR) and Line Feed (LF). If any indication is incorrect, refer to the appropriate heading under Detailed Troubleshooting, Section 4.2, for corrective measures. Key On inoperative--See Incorrect Key On, Section 4.2.1. Transmit inoperative--See Incorrect Transmit Indication, Section 4.2.2. Terminal not responding--See No Output At Terminal, Section 4.2.3. · If multiple problems exist, check the ASCII Panel before the terminal device. 3.
Deenergize the track circuit power supply. Check that the KEY ON LED on the ASCII Panel goes off. The TRANSMIT Light should blink on momentarily. The terminal device should upspace one line (receive CR and LF characters). Troubleshoot per Step 2 if incorrect.
4.
Energize the track circuit power supply and observe LEDs as in Step 2.
5.
Set the switches on the carborne Programmer to Route 19, car number 0123 and the lead car bit switches on the status input test cable to the ON position.
6.
Pass the Transponder Coil over the Wayside Coil at a 12 to 14 inch height and remove it. The TRANSMIT LED on the ASCII Panel should blink on momentarily and the terminal device should record the message; 19[]0123[]1, where[] indicates a space. The GOOD MESSAGE LED on the decoder should be on. If the ERROR MESSAGE LED on the Decoder Logic Panel is on, the terminal should record the message = = [ ] = = = = [ ] = ; = i s equal sign,[] is space. This is correct ASCII interface operation. Troubleshoot basic decoder if errors repeat. If a GOOD MESSAGE is indicated on the Decoder Logic Panel and the terminal receives incorrect data or no data, refer to Detailed Troubleshooting, Section 4.2.4, Incorrect or No Data At Terminal.
7.
Pass the Transponder Coil over the Wayside Coil four more times at a two second interval between passes. The TRANSMIT light should blink four times; the output device should output a total of four messages on one line and the fifth message on a new line.
6042-B, p. 4-4
There should be three spaces between each message. 1900123010
DQ190o12301D DQ19Qo123[Jl
If the number of messages per line are incorrect, refer to Detailed Troubleshooting--Incorrect format at terminal, Section 4.2.5, Part A. If no spaces between messages, refer to Detailed Troubleshooting--Incorrect format at terminal, Section 4.2.5, Part B. 8.
Deenergize the track circuit power supply. The output device will upspace one line. Format the ASCII to print only two messages per line. Remove Jumper A27-3 to A27-14 Add Jumper
A27-2 to A27-15
Also format the ASCII Panel to suppress the space after the sixth digit by removing jumper A27-6 to A27-ll. 9.
Energize the track circuit power supply. Pass the Transponder Coil over the Wayside Coil three times at a two second interval. The output device will upspace to a new line and print two messages in one line and the third on a new line without a space after the sixth digit. 19[)n231D D 0190 01231 19[)H231 If the number of messages per line is incorrect, refer to Detailed Troubleshooting--Incorrect format, Section 4.2.5, Part A. If the space is not suppressed after the. sixth digit, refer to Detailed Troubleshooting--Incorrect format at terminal, Section 4.2.5, Part C.
10.
Deenergize the track circuit power supply. The output device will upspace to a new line. Format the ASCII device to suppress all spaces between characters. Add Jumper A27-7 to A27-10.
11.
Energize the track circuit power supply. device will upspace to a new line.
The output
6042-B, p. 4-5
WABCD ~
Pass the Transponder Coil over the Wayside Coil three times at a two second interval. The output device will output three messages, two on one line and the third on another line with no spaces between characters. 1901230001901231 1901231 If the spaces are not suppressed between the characters, refer to Detailed Troubleshooting--Incorrect format at terminal, Section 4.2.5, Part C. 12.
Deenergize the track circuit power supply. terminal will upspace to a new line.
The
Format one message per line. Remove Jumper A27-2 to A27-15 Add Jumper A27-1 to A27-16 Also format the ASCII device to output only six digits, suppressing the last (status) digit. Remove Jumper A27-7 to A27-10 Add Jumper 13.
A27-5 to A27-12
Energize the track circuit power supply. The terminal will upspace one line. Pass the Trans-ponder Coil three times over the Wayside Coil at a two second interval. The terminal should printout the three, six digit messages each on a separate line. 1900123 1900123 1900123 If the seventh digit is printed, refer to Detailed Troubleshooting--Incorrect or lack of status digit suppression, Section 4.2.5, Part F.
14.
Deenergize the track circuit power supply. terminal will upspace one line.
The
Restore seven digit output with spaces between characters. 6042-B, p. 4-6
~...,...
WABCO
Remove Jumper A27-5 to A27-12 Add Jumper 15.
A27-6 to A27-ll
Energize the track circuit power supply. will upspace one line.
The terminal
Refer to Table 4-1 and enter each switch setting on the programmer per the table. Pass the Transponder Coil over the Wayside Coil once for each switch setting. Verify the output of the data on the terminal for each message, one per line. The status bits setting will be displayed in ASCII format. OlDOOOlDl
Entry 1
100001CIJ2
Entry 2
Etc. If any message is incorrect, refer to Detailed Troubleshooting--Incorrect or no data at terminal, Section 4.2.4, Part B. Connect resistors at Pins B5-7 and B5-8 together to simulate an error input. The terminal device should record an error message in the form ==IJ====IJ= when the Transponder Coil is passed over the Wayside Coil. If not, refer to Detailed Troubleshooting--Incorrect or no data at terminal, Section 4.2.4. 16.
Deenergize the track circuit power supply. terminal device will upspace one line.
The
Change the ASCII Interface Panel to the non-formatted mode. Remove Jumper A27-8 to A27-9. Remove temporary jumper from resistors at B5-7 and B5-8. Set the switches on the Programmer to Route 19, car 0123 and set the lead car switch, on the satus input test cable, to ON. 17.
Energize the track circuit power supply. device should NOT upspace to a new line.
The terminal
Pass the Transponder Coil over the Wayside Coil at a two second interval repeatedly at least 10 times. 6042-B, p. 4-7
WABCO ~
ENTRY NO.
ROUTE SWITCH SETTINGS
CAR NO. SWITCH SETTINGS
EXTRA BIT SWITCH SETTINGS
ASCII EQUIVALENT OF EXTRA BITS
1
0
1
0
0
0
1
1
0
0
0
1
2
1
0
0
0
1
0
0
1
0
0
2
3
2
0
0
1
0
0
0
0
1
0
4
4
1
7
1
0
0
0
0
0
0
1
8
5
0
7
7
0
7
0
0
0
1
1
<
6
1
8
0
8
0
4
0
1
1
1
>
7
0
9
4
0
4
0
1
1
1
1
?
8
1
6
4
7
7
2
1
1
0
0
3
9
0
3
1
2
3
4
1
1
1
0
7
10
0
4
5
6
7
8
1
0
1
0
5
11
1
5
9
7
1
3
1
1
0
0
3
12
0
2
2
2
4
1
1
0
0
1
9
13
7
8
7
8
.7
8
1
1
1
0
7
14
8
7
8
7
8
7
0
0
0
1
8
15
6
9
6
9
6
9
0
1
1
0
6
16
9
6
9
6
9
6
1
0
0
1
9
Table 4-1
6042-B, p. 4-8
WABCO
'V"~ The output on the terminal device should be one continuous line of data without spaces, carriage return or line feed. The terminal will probably overprint characters at the end of a line. If not, refer to Detailed Troubleshooting--Incorrect format at terminal, Section 4.2.5, Part D. 18.
Deenergize the track circuit power supply. The output terminal should not upspace to a new line.
19.
Connect an oscilloscope to the output terminals (EIA or current loop} that are not being used by the terminal device, per Figure 4-1 or 4-2. Connect a second oscilloscope probe to the Shift Clock signal at integrated circuit A9-pin 2. Trigger the oscilloscope externally, using the Transmit signal at A8 pin 15.
20.
Energize the track circuit power supply. should appear on the oscilloscope.
No signals
21.
Deenergize the track circuit power supply. Observe the outputting of an EOT character as shown on Timing Chart, Figure 5-7. Data will be the complement of the Data Out signal as shown on the Timing Chart for Al4 pin 12. Observe the level of the bits relative to the Clock signal on A9 pin 2. The bit that occurs on the 9th clock edge is the parity bit. This bit will be the same level as the pulse during the 4th bit when the jumper is installed for even parity (A17-2 to Al7-15}. When odd parity is selected (Al7-l to Al7-16 and Al7-2 to Al7-15}, this 9th bit will be opposite in phase to Bit 4.
22.
Repeat Steps 20 and 21 to check both parity options, odd and even. If EOT message is incorrect, refer to Detailed Troubleshooting Section 4.2.5, Part E, Incorrect EOT Message.
23.
Connect an oscilloscope probe to the Key Output (J6-4} and to EIA (-V) (J6-1).
24.
Deenergize the track circuit power supply.
25.
Place a jumper in constant Key On at Al7 pin 6 to Al 7 pin 11.
6042-B, p. 4-9
WABCD
~
The KEY ON LED should be on and the output at J6-4 is positive when the jumper is installed. Remove the jumper Al7 pin 6 to Al7 pin 11. KEY ON LED should go off and the output at J6-4 should be at -V potential (off) . If Key On operation is not correct, refer to Detailed Troubleshooting, Section 4.2.1, Incorrect Key On Operation. NOTE:
6042-B, p. 4-10
If every step in this Basic Diagnostic Procedure (Sec. 4.1.3) is passed correctly by the ASCir Interface Panel under test, the interface panel is operational.
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4.2
DETAILED TROUBLESHOOTING
Refer to the Basic Troubleshooting Section 4.1 for a step-bystep check of the ASCII device to pinpoint the failure modes which occur or determine that the ASCII device is operating correctly. A defective ASCII device will usually exhibit one or more of the following malfunctions: A.
Incorrect Key On operation.
B.
Incorrect transmit indication.
c.
No output at terminal.
D.
Incorrect or no data at terminal.
E.
Incorrect format at terminal.
Refer to the sections relating to the malfunctions observed and troubleshoot as required until correct indications are observed. When troubleshooting multiple problems, correct all malfunctions relating to the KEY ON and TRANSMIT LEDs (Sections 4.2.1 and 4.2.2) first, if any. After completing the procedure, and no malfunctions are observed, repeat the Basic Diagnostic Procedure (Section 4.1.3) and verify the ASCII device is operational.
4.2.1
Incorrect Key On Operation
One of the following symptoms will most likely be observed when a malfunction occurs in the Key On circuit: A.
No Key On output to data set with the Key On LED on.
B.
KEY ON LED always off.
C.
KEY ON LED always on with the constant Key On jumper removed.
Refer to the corresponding symptom below and troubleshoot as required. A.
KEY ON LED lights but there is no Key On output to the data set (i.e. +Vat connector J6 pin 4): 1.
Check that the Decoder drawer is wired correctly for EIA Key On output per Figure 4-3. 6042-B, p. 4-11
WABCD ~
~ AJ2-13 2K +v
~ AJ2-ll
EIA +V
). J6-6 I
>}-EIA KEY ON OUTPUT J6-4 I
-v
~ AJ2-8
TO TERMINAL
J6-l +
Figure 4-3 KEY ON OUTPUT CONFIGURATION
6042-B, p. 4-12
12 VDC POWER SUPPLY
+ 12 VDC POWER SUPPL
2.
3.
Check that the cables from the Power Distribution and Interface PCB to the ASCII panel are installed correctly and free from shorts or opens. If the preceeding are correct, there is either a
problem with -the Key On optical isolator AlO er :'ass@ciated components -0n schematic Figure s~1 •
• j
B.
KEY ON LED always of~: 1.
Check if the TRACK LED on the Decoder Logic Panel lights when the track circuit is occupied (i.e. track circuit power supply on).
2.
If the TRACK LED on the Decoder Logic Panel is not lit, check for improper connections to the track circuit input of the decoder drawer and for a shorted TRAK signal at the ASCII panel connector BJ2 pin 15.
3.
If the TRACK LED on the Decoder Logic Panel is not lit, install a jumper between Al7 pin 11 and Al7 pin 6 to generate a constant Key On signal. If the KEY ON LED lights, check the wiring and operation of the following ICs on the ASCII panel on: Schematic (Figure 5-3) Flip Flop A30 pin 13 TRACK FF And/Or select A3 pin 13 ENABLE KEY
Schematic (Figure 5-2) Inverter B26 pin 15 TRAK Trace circuit inputs to other ICs when necessary. 4.
If the KEY ON LED still does not light, check the wiring and operation of the components on: Schematic (Figure 5-3) NOR Gates A2 pin 12 A29 pin 3 Inverter
Al5 pin 10 Al5 pin 15 TEST+ MSTR
LED and Resistor 6042-B, p. 4-13
WABCD ~
Assure that the Receiver PCB Test Switch is in the Normal mode and the MSTR and TEST signals from the Decoder Logic Panel are a Logic 1 and O respectively; otherwise check for shorted signals. Trace circuit inputs to other !Cs when necessary and troubleshoot as required. C.
KEY ON LED always on with the constant Key On jumper removed. 1.
If the KEY ON LED does not go out when either the track circuit is unoccupied or if the Receiver PCB Test Switch is placed in the test mode, check the wiring and operation of the following !Cs on: Schematic (Figure 5-3) Flip Flop A30 pin 13 TRACK FF A8 pin 15 TRANSMIT And/Or Select A3 pin 13 ENABLE KEY NOR Gates A2 pin 12 A29 pin 3 Inverter Al5 pin 15 TEST+ MSTR Trace circuit inputs to other !Cs when necessary.
6042-B, p. 4-14
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4.2.2
Incorrect Transmit Indication
One of the following symptoms will most likely be observed when a malfunction occurs in the Transmit Circuit: A. B.
TRANSMIT LED stays off. TRANSMIT LED comes on and stays on.
Refer to the corresponding symptom below and troubleshoot as required. A.
TRANSMIT LED stays off. 1.
If the terminal is outputting correct numerical or error message data, check the TRANSMIT LED and driver Al5 pin 4 (Figure 5-3).
2.
If the terminal is not responding or printing garbled data, check the state of the Transmit FF A8 pin 15. When the Transmit FF is set, the TRANSMIT LED should light. If not, check LED and driver Al5 pin 4.
3.
If the Transmit FF A8 pin 15 stays reset, assure that the Test Switch on the Receiver PCB is in position 2 (Normal) and check the wiring and operation of the Test+ Master reset circuit on: Schematic (Figure 5-3)
4.
Flip Flop
A8 pin 15 TRANSMIT
NOR Gate
A29 pin 13 TEST+ MSTR
NAND Gate
A30 pin 3
Inverter
A9 pin 4
If the Test+ Master reset circuit is operational; check the Baud Rate Clock (Al4 pin 14) and Transmit Clock (A20 pin 4) signals as per Timing Chart (Figure 5-4). a.
If the Baud Rate Clock signal is incorrect, insure jumpers have been installed for a selected baud rate and check the wiring and operation of the following ICs on: Schematic (Figure 5-3) Counter Al8 NOR Gate A29 pin 12 Flip Flop A24 pin 2, 14 6042-B, p. 4-15
WABCD ~
NANO Gate Al4 pin 3 A23 pin 15 b.
If the Transmit Clock signal is incorrect, check the wiring and operation of the following ICs on: Schematic (Figure 5-3) NANO Gates A20 pins 3 and 4 Inverter
Al5 pin 6
Trace circuit inputs to other ICs when necessary. 5.
If the Baud Rate Clock and Transmit Clock signals are correct, and the TRANSMIT LED still does not light when the track circuit power supply is activated, check that the EXT INHIBIT signal to priority encoder B24 pin 5 is at +V and insert a jumper wire from +V to the EXT H input at B24 pin 4. (See Schematic, Figure 5-2.) a.
If the TRANSMIT LED lights, there is a problem with the carriage return and line feed circuit. (See Incorrect Format Section 4.2.5.)
b.
If the TRANSMIT LED stays off, check the wiring and operation of the following ICs on: Schematic (Figure 5-2) Priority Encoder B24 pin 14 Cycle Output Schematic (Figure 5-3) And/Or Select A3 pin 10 START Inverter
Al5 pin 4
Trace circuit inputs to other ICs when necessary. B.
TRANSMIT LED comes on and stays on. 1.
6042-B, p. 4-16
Check if the Cycle Output signal at the Priority Encoder B24 pin 14 is a logic 1. If so, check the priority encoder input pins 1-4 and 11-13 for a logic 1. If none of these are pins receiving a logic 1 signal, check the Priority Encoder IC B24 on schematic (Figure 5-2).
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2.
If either the EXT Hor EXT L signal at B24 pin 4 and 13 are high, check for any incorrect connections to the external inputs at connector AJl pins 15 and 16 and verify that both signals are tied to O volts through resistors at A26.
3.
If the Cycle Output signal is a logic O or 1, the Start signal at the quad and/or selector A3 pin 10 should be a logic O or 1 respectively. If not, check IC A3 and associated circuits on schematic (Figure 5-3). Assure that the EXT CONTROL signal at A3 pin 9 is pulled up to +V potential.
4.
If the Start signal remains a logic 0, check if the TRANSMIT LED comes on when the decoder drawer only is first turned on. If so, check the wiring and operation of the ICs listed in Part A (TRANSMIT LED stays off), Step 3 and the TRANSMIT LED driver Al5 pin 4.
5.
If the Start signal is a logic 0, and the TRANSMIT LED comes on and stays on after the track circuit power supply is energized, check the wiring and operation of the following ICs on: Schematic (Figure 5-3) Flip Flop AB pin 15 Transmit Counter
A9
Count 11
NAND Gates A20 pins 4 and 13 6.
If the Start signal is a that at least one of the encoder (B24) is a logic proper occurrence of the signals per Timing Chart
logic 1, indicating inputs to the priority 1, check for the following timing (Figure 5-4).
Signal
Location
Baud Rate Clock
Al4 pin 14
Transmit Clock
A20 pin 4
Clock 1
Al3 pin 1
Clock 2
Al3 pin 15
Clock Enable
AB pin 1
Dump Pulse
. All pin 6
6042-B, p. 4-17
WABCD ~
a.
If timing signals are incorrect, check the wiring and operation of the.res listed in Part A (TRANSMIT LED stays off), Steps 4a and 4b, and the following !Cs on: Schematic (Figure 5-3) Counter Al9
Count 11
Flip-Flop
A8 pin 1 Clock Enable Al3 pin 1 Clock 1 Al3 pin 15 Clock 2
Single Shot All pin 6 Dump Pulse NAND Gates
A20 pin 13 Al4 pin 4
Trace circuit inputs to other !Cs when necessary and troubleshoot as required using Timing Chart (Figure 5-4) whenever possible.
4.2.3
b.
If Timing Signals are correct, and the CR, Space Input or EOT signals to the priority encoder remain at a logic 1 level, refer to Incorrect Format, Section 4.2.5.
c.
If the Timing signals are correct and either the Good MSG, or Error MSG signal to the priority encoder are a logic 1, refer to the Incorre_ct or No Data at Terminal, Section 4. 2. 4, if the terminal is outputting data. If not, refer to No Output at Terminal, Section 4.2.3.
No Output at Terminal A.
Terminal device does not respond to track occupancy during the Basic Diagnostic Procedure Section 4.1.3 1.
Check that the baud rate and parity have been correctly selected as per the Preliminary Setup of the Basic Troubleshooting procedure, Section 4.1.2.
2.
Check that the cable from connector J2-9 on the ASCII panel to connector J4 on the Power Distribution and Interface PCB is installed correctly and free of shorts or opens.
6042-B, p. 4-18
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3.
Program the ASCII device for formatted operation by installing a jumper in Location A27 between pins 8 and 9. Energize the track circuit power supply and observe the ASCII Data signal at gate Al4 pin 12. Reference the data levels and bit positions to the Shift Clock signal at inverter A9 pin 2 and trigger the oscilloscope on the positive going Trak signal at B30 pin 5. The ASCII Data signal displayed on the oscilloscope should correspond to the signal listed on Timing Chart (Figure 5-4). a.
4.
If the ASCII Data signal is correct, check inverters A9 pin 6, 10 and 12 and look for shorted or open optical isolators AS or AlO on schematic (Figure 5-3).
If the ASCII Data signal in Step 3 is incorrect, deenergize the track circuit power supply and check for proper occurrence of the following Clock signals per Timing Chart (Figure 5-4). Si9:nal
Location
Transmit Clock
A20 pin 4
Baud Rate Clock
Al4 pin 14
Clock 1
Al3 pin 1
Clock 2
A13 pin 15
Clock Enable
A8 pin 1
If the clock signals are incorrect, troubleshoot as required per timing chart. Replace all defective wiring and ICs. 5.
If the clock signals in Step 4 are correct, energize the track circuit power supply. The CR signal line at priority encoder B24 pin 3 should go to a logic 1. (See Timing Chart, Figure 5-4.) If not refer to Incorrect Format At Terminal, Section 4.2.5. a.
If the CR signal is correct, cycle the track circuit power supply off, then on and check for the proper occurrence of the following timing signals: (Refer to Timing Chart, Figure 5-4.)
6042-B, p. 4-19
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Sig:nal
Location
Cycle Output
B24 pin 14
Transmit
A8 pin 15
Dump Pulse
All pin 6
Buss Busy
A20 pin 12
Shift Clock
A9 pin 2
Transmit Clock
A20 pin 4
Clock Enable
A8 pin 1
Clock 1
Al3 pin 1
Clock 2
Al3 pin 15
Baud Rate Clock
Al4 pin 14
These signals are the basic timing signals in the ASCII panel's logic and they must be present for proper operation. If-riicorrect, troubleshoot as required per timing chart and replace all defective wiring and res. 6.
If all of the basic timing signals in Step 5 are correct and the ASCII Data is still incorrect, check the wiring and operation of the following ICs on: Schematic (Figure 5-1) Shift Register
A6 pin 3
Flip-Flop
A7 pin 15 A7 pin 2 SERIAL ASCII DATA
Parity Generator Al2 Schematic (Figure 5-3) NAND Gate Al4 pin 12
ASCII Data
Also, check the data bus lines (Bits 1-8) for shorted or open wires and assure that no more than one tri-state gate (ICs Bl6, Bl7, Bll, Bl2 and Bl3) are active on any one data line at the same time. Troubleshoot as required and replace all defective wiring and res. 6042-B, p. 4-20
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7.
4.2.4
If the terminal is still not responding, then there is a problem with the carrier detect and line feed generator circuit. Refer to Incorrect Format At Terminal, Section 4.2.5.
Incorrect or No Data at Terminal
One of the following conditions may be observed at the terminal during the ASCII troubleshooting, Basic Diagnostic Procedure, Section 4.1.3: A.
Garbled Data
B.
Incorrect or No Numerical Data.
C.
Incorrect or no Error Message Data.
Refer to the corresponding symptom and troubleshoot as required. A.
Garbled Data 1.
If the terminal displays a continuous string of garbled data, check the Good and Error Message strobe input signals, GMST and EMST (BS pins 7 and 8), from the Decoder Logic Panel. These signals should be at a logic 1 level whenever the corresponding LEDs on the decoder (Good or Error Message) are off. If not, assure that the cables from the ASCII panel to the decoder panel are installed correctly and free from shorts or opens. Also, check the operation of gates A2 pins 11 and 6 on schematic (Figure 5-2). a.
If the GMST and EMST signals are correct, check the wiring and operation of the following ICs on: Schematic (Figure 5-2) Flip-Flops
BlO pin 1
GOOD MSG
BlO pin 15
ERROR MSG
NOR Gate
B20 pin 4
NO MSG
NANO Gate
Bl9 pin 12
Single Shot A21 pin 7 Priority Encoder B24 pins 11 and 12
6042-B, p. 4-21
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Schematic (Figure 5-1) Octal Counter/Decoder Bl5 NOR Gate
B20 pin 3 LAST DIGIT
Troubleshoot as required using Timing Charts Figures 5-4 and 5-5, and also Figures 6-22 and 6-23 in AVI system manual 6042 whenever possible. 2.
If the terminal displays a non-continuous garbled message for either Good or Error Message Data, input a message to the decoder and by triggering on the Transmit signal, check the following ASCII timing signals per Timing Charts (Figures 5-4 -and 5-5): Signal
Location
Transmit
A8 pin 15
Shift Clock
A9 pin 2
Dump Pulse
All pin 6
Clock 1
Al3 pin 1
Clock 2
Al3 pin 15
Clock Enable
A8 pin l
Baud Rate Clock
Al4 pin 14
Transmit Clock
A20 pin 4
If any signals are incorrect, troubleshoot as required per timing charts and replace all defective ICs and wiring. a.
If the timing signals are correct, check for shorts or opens in the ASCII data buss (Bits 1-8) at the output shift register A6 and assure that no more than one tri-state gate (IC Bl6 and Bl7) is active on any one data line at the same time. Check the wiring and operation of the following ICs on: Schematic {Figure 5-1) Shift Register A6 pin 3 Parity Generator Al2
6042-B, p. 4-22
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Flip Flops A7 pin 15 A7 pin 2 SERIAL ASCII DATA NAND Gate
Bl9 pin 13
Inverter
Bl8 pin 2
Octal Counter/Decoder Bl5
Schematic (Figure 5-2) Decade Decoder B23 Exclusive OR Gate B21 pin 4 Tri-State Inverters Bl6 pins 11 and 13 Bl? pins 11 and 13 NOR Gate
B27 pin 1
Inverter
Bl8 pin 12
Single Shot All pin 10
LOAD MSG
Trace circuit inputs to other I Cs when necessary.
B.
Incorrect or No Numerical Data 1.
If the terminal gives no response to Good Message Data, verify the following: a.
The ASCII device outputs a correct carriage return and in the formatted mode, line feed signal to the terminal. If not see Section 4.2.3 and 4.2.5.
b.
The TRANSMIT LED is not on steady. see Section 4.2.2.
If so,
If the above conditions are satisfied, check the wiring and operation of the following ICs on: Schematic (Figure 5-2) NAND Gate
A2 pin 6
Flip-Flop
BlO pin l
GOOD MSG 6042-B, p. 4-23
WABCD ~
Single Shot
A21 pin 7
NAND Gate
Bl9 pin 12
Priority Encoder B24 NOR Gate B20 pin 4 2.
If the terminal displays garbled data for Good Messages only, check the wiring and operation of the following ICs on: Schematic (Figure 5-2) Single Shot
All pin 10
LOAD MSG
Decade Decoder B2.3 pin 14 "l" Output
Schematic (Figure 5-1} NAND Gate
Bl9 pin 13
Tri-State Inverter Bl3
3.
If the terminal displays a message with only a few characters incorrect or missed, check for shorts or opens in the ASCII data buss (Bits 1-4) at tri-state inverter Bl3 and assure that no more than one tri-state gate (ICs Bl3, Bl6, Bl7, Bll and Bl2) is active on any one data line at the same time. Check the wiring and operation of the following ICs on: Schematic (Figure 5-1) Tri-State Latches B2, B3, B4, B6, B7, B8, and B9 Tri-State Inverter Bl3 Octal Counter/Decoder Bl5 Inverters Bl4 pins 2, 4, 6, 10, 12, 15 Bl8 pin 15
6042-B, p. 4-24
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C.
Incorrect or No Error Message Data 1.
If the terminal does not respond to Error Messages, verify the following: a.
The ASCII device outputs a correct carriage return and line feed signal to the terminal. If not, see Section 4.2.3 and 4.2.5.
b.
The TRANSMIT LED is not on steady. see Section 4.2.2.
If so,
If the above conditions are satisfied, check the wiring and operation of the following ICs on: Schematic (Figure 5-2) NAND Gate
A2 pin 11
Flip-Flop
BlO pin 15
ERROR MSG
Single Shot A21 pin 7 NAND Gate Bl9 pin 12 NOR Gate
B20 pin 4
Priority Encoder B24 2.
If the terminal displays garbled data for error messages only, check the wiring and operation of the following ICs on: Schematic (Figure 5-2) Decade Decoder B23 pin 2 "2" Output NOR Gate
B22 pin 3
Inverter
Bl8 pin 10
Tri-State Inverter Bll pins 11 and 13 Bl2 pins 11 and 13
6042-B, p. 4-25
WABCD ~
4.2.5
Incorrect Format at Terminal
One or more of the following symptoms will most likely be observed when a malfunction occurs in the ASCII format circuits: A.
Incorrect number of signs per line.
B.
Continuously repeating spaces, lack of spaces, or incorrect space suppression.
c.
Continuously repeating or lack of carriage return and line feed.
D.
Formatted characters in non-formatted mode or no format.
E.
Incorrect EOT Message.
F.
Incorrect or Lack of Status Digit Suppression.
Refer to the corresponding symptom below and troubleshoot as required: A.
Incorrect number of signs per line. 1.
Check the wiring and operation of the following res on: Schematic (Figure 5-2) Counter A28 Flip-Flop B30 pin 6 Trace circuit inputs to other ICs when necessary.
B.
Continuously repeating spaces, lack of spaces or incorrect space suppression. 1.
If the TRANSMIT LED is on steady, check the logic level of the Space Input signal at priority encoder B24 pin i. If the signal is a constant logic 1, it may cause the ASCII device to continuously output the ASCII character message to generate spaces at the terminal. Check the wiring and operation of the following ICs on: Schematic (Figure 5-2)
6042-B, p. 4-26
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Flip-Flop
B29 pin 1 B29 pin 15 B26 piri 10
Inverter Single Shot
A21 pin 6
Priority Encoder B24 pin 1
Schematic (Figure 5-1) NOR Gates B20 pin 12 SPACE B20 pin 13 Trace circuit inputs to other ICs when necessary.
2.
If no spaces are displayed at the terminal or if an incorrect character is printed in its place, check the wiring and operation of the following ICs on: Schematic (Figure 5-2) Flip-Flop
B25 pin 1
Inverter
B26 pin 10
Single Shot A21 pin 6 Priority Encoder B24 pin 1 Decade Decoder B23 pin 1 "4" Output Exclusive-OR B21 pin 4 Inverter B26 pin 2 Tri-State Inverters Bl2 pins 3,5,7 and 9 Trace circuit inputs to other ICs when necessary.
6042-B, p. 4-27
WABCD ~
3.
When the jumper between A27 pin 6 and A27 pin 11 is removed, the space after the sixth digit of a message should be suppressed. If not, check the wiring and operation of NOR Gate B20 pin 13 on schematic (Figure 5-1). a.
c.
When a jumper is inserted between A27 pin 10 and A27 pin 7, all spaces should be suppressed between characters. If not check the wiring and operation of NOR Gate B20 pin 12 on schematic (Figure 5-1).
Continuously repeating or lack of carriage return and line feed. 1.
If the TRANSMIT LED is on steady, check the logic level of the CR signal at priority encoder B24 pin 3. If the signal is a constant logic 1, it may cause the ASCII device to continuously output the ASCII character message to generate either carriage returns or line feeds at the terminal. Check the wiring and operation of the following ICs on: Schematic (Figure 5-2) Flip-Flop
B30 pins 2 and 15 B25 pin 15
NAND Gates B27 pins 12 and 13 Inverter
B26 pin 6
NOR Gate
B22 pin 12
CR
Priority Encoder B24 pin 3 Counter
A28 pin 3
LINE FULL
Trace circuit inputs to other ICs when necessary.
2.
6042-B, p. 4-28
If no carriage return or line feed are generated at the terminal, check if the CR signal line at priority encoder B24 pin 3 goes to a logic 1 when the track circuit power supply is energized. If not, check the wiring and operation of the ICs listed in Step 1 and the following ICs on:
Schematic (Figure 5-2)
a.
NAND Gate
B27 pins 3 and 4
Inverter
B26 pin 4
If the preceeding circuit is operational and no carriage return or line feed is generated, or if an incorrect character is printed, check the wiring and operation of the following res on: Schematic (Figure 5-2) Exclusive
OR gates B21 pins 3, 12 and 13
NOR Gate B27 pin 4 Inverter Bl8 pin 6 Tri-State Bl6 pins 3' 5' 7 and 9 Bl7 pins 3, 5, 7 and 9 Decade Decoder B23 pin 7
II
6 II Output
Trace circuit inputs to other res when necessary.
D.
Formatted characters in non-formatted mode, or no format. 1.
When a jumper is inserted between A27 pins 8 and 9, the message at the terminal should be in the formatted mode. When the jumper is removed, the message should be non-formatted. If incorrect, check the wiring and operation of the following res on: Schematic (Figure 5-2) NAND Gate
B27 pin 4
NOR Gate
B22 pin 13
Inverter
B26 pin 12
Trace circuit input to other res when necessary.
6042-B, p. 4-29
WABCD ~
E.
Incorrect EOT Message. 1.
If the TRANSMIT LED is on steady, check the logic level of the EOT signal at priority encoder B24 pin 2. If the signal is a constant logic 1, it may cause the ASCII device to output continuous EOT Messages. Check the wiring and operation of the following ICs on: Schematic (Figure 5-2) Flip-Flop
B28 pin 1 B28 pin 15
NANO Gate
B27 pin 13
Inverter
B26 pin 15
EOT
Priority Encoder B24 pin 2 Trace circuit inputs to other ICs when necessary.
2.
If no EOT message is outputted, check if the EOT signal at priority encoder B24 pin 2 goes to a logic 1 level when the track circuit power supply is deenergized. If not, check the wiring and operation of the ICs listed in Step 1. a.
If the preceding circuit is operational and the EOT message is still incorrect, check the wiring and operation of the following ICs on: Schematic (Figure 5-2) Inverter B18 pin 4 NOR Gate B22 pin 4 Decade Decoder B34 pin 6 "5" Output Tri-State Inverters B17 pins 3, 5, 7 and 9 Bll pins 3, 5, 7 and 9
6042-B, p. 4-30
F.
Incorrect or Lack of Status Digit Suppression. 1.
If the status (7th) digit cannot be suppressed by installing a jumper at A27 pin 5 to pin 12, check the wiring and operation of the following rc;s on: Schematic (Figure 5-1) NOR Gate
B20 pin 3
Counter
B15 pins 5 and 10
Resistor
A26 pin 11 (100 KQ to O volts)
Also check jumper wiring A27, pins 5 and 12
2.
If the status digit is always suppressed regardless of jumper installation, check the wiring and operation of the res on: Schematic (Figure 5-1) Counter
B15 pin 5
Inverter
Bl8 pin 15
Buffer
B8
Shift Register
pins 3, 4, 5, 6 A6
pins 1, 13, 14, 15
Also check for short across A27 pins 5 to 12.
6042-B, p. 4-31/32
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SECTION V DRAWINGS AND PARTS LIST
This section contains logic diagrams, timing charts, component locations and parts list for the ASCII Interface Panel.
6042-B, p. 5-1/2
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AJl-5
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AJJ -I 5
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CAB SIGNAL
AJl-14
BJl-15~
AJl-11 } BJl-16 ~ UDlf -·
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BJJ-17
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AJl-16 I
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SPARE 2
AJl•t
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) AJl-10
8Jl•7 AJl-19} AJl-20 TO I ""1.A' ~AJl-21 lie
BJl-8
BJl-1 BJl-10~ BJZ-21
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NOTE: ALL PIN NUMBERS ARE OISIBNATED FOR WIRE WRAP PANEL
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PIN I
PIN 7
+12 VOLT PIN I I
0
AJl-25 (".' '
) AJI -II
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BJl-tO ("V .-
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AJJ-12
.
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Alt£ f
SPARE 5
II
PIN I
PJIN I, 16 PIN I I PIN II PIN 3 0 5 1 7 0 9
PIN 9 10 ll,1i.,'1~ '
PIN I J, 14 1 1 5 , - - - - - - - - - - - - - - - - - - , - - i "
PIN I0,11, 14,15(
INTERfACE PANEL STD. CIRCUIT OIAGRIMS FOR AUTO-VEHICLE IDENTIFICATI~ & VEHICLE TO WAYSIDE Co.t.UIICATl~S SYSTEM
WABCO WtsTIICHOUSI: All llAIE COMPMY
~
I:··~U--4B'"". ~.. , D 11775
INTERFACE PANEL LOGIC DIAGRAM
UNION SWITCH & SICNAL DIYISIOII_IU _
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6042-B, P. 6-1
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