Transcript
2008/12/8
Ken Takeuchi Toshiba, NAND Flash Circuit Designer: ‘93-’07 University of Tokyo, Associate Professor: ‘07Developed 6 world’s highest density NAND (0.7μm 16Mb, 0.4μm 64Mb, 0.25μm 256Mb, 0.16μm 1Gb, 0.13μm 2Gb, 56nm 8Gb) 150 Patents Worldwide (88 U.S.Patents) ISSCC Takuo Sugano Outstanding Paper Award: ’07 ISSCC Program Committee (Memory): ‘0707 Stanford Univ. MBA: ‘03
Solid-state drive (SSD) and memory system innovation Dec.11, 2008 Ken Takeuchi Dept. of Electrical Engineering and Information Systems, University of Tokyo E-mail :
[email protected] http://www.lsi.t.u-tokyo.ac.jp Ken Takeuchi
Ken Takeuchi
Advanced Flash Memory Devices
ISSCC 1999 250nm 256M Flash 1
Ken Takeuchi
IEDM 2000 160nm 1G Flash
ISSCC 2002 130nm 2G Flash
ISSCC 2006 56nm 8G Flash
Advanced Flash Memory Devices
2
Outline
Outline
SSD, Memory System Innovation NAND Overview NAND Circuit Design SSD Overview NAND Controller Design Operating System for SSD Green IT with SSD Summary
SSD, Memory System Innovation NAND Overview NAND Circuit Design SSD Overview NAND Controller Design Operating System for SSD Green IT with SSD Summary
Advanced Flash Memory Devices
3
Definition of SSD
Ken Takeuchi
Advanced Flash Memory Devices
4
NAND Flash Memory and SSD Market
SSD : Solid- State Drive Mass storage to replace HDD of PC/Enterprise Server. Small, robust, low-power and high performance. SSD consists of NAND Flash Memory and NAND controller(+RAM)
PC expected as an emerging application
Gartner Dataquest
J. Elliott, WinHEC 2007, SS-S499b_WH07.
I. Cohen, Flash Memory Summit 2007. Ken Takeuchi
Advanced Flash Memory Devices
5
Ken Takeuchi
Advanced Flash Memory Devices
6
1
2008/12/8
Memory System Bottleneck
SLC NAND as Cache of HDD CPU registers (<1ns)
CPU registers (<1ns) SRAM (<1ns) SRAM (<1ns) DRAM (10ns) (10 ) DRAM (10ns) SLC NAND (20us)
Big Gap
HDD (10ms) HDD (10ms) Ken Takeuchi
Advanced Flash Memory Devices
7
Future Memory System
Advanced Flash Memory Devices
Ken Takeuchi
8
Future Direction: Vertical Integration History of NAND Flash Memory System
CPU registers (<1ns)
Application Software
S/DRAM (<1ns)
Future Block Abstracted SSD
File System (OS)
DRAM (10ns)
NAND Controller
NAND Controller Bad Block Management Wear-leveling ECC
DRAM (10ns) 1bit/cell NAND (20us)
NAND Flash Memory
2-4bit/cell NAND (1~10ms)
MP3 Player SD Card USB Memory
Go vertical integration to improve systemlevel performance.
Smart Media
SSD K. Takeuchi, ISSCC 2008 Tutorial T-7.
Ken Takeuchi
Advanced Flash Memory Devices
9
Ken Takeuchi
Key Challenge of SSD
Advanced Flash Memory Devices
10
Outline SSD, Memory System Innovation NAND Overview NAND Circuit Design SSD Overview NAND Controller Design Operating System for SSD Green IT with SSD Summary
Need to improve device reliability such as endurance, data retention, and disturb. Require co-design of NAND and NAND controller circuits to best optimize both NAND and NAND controllers. OS/Computer architecture innovation essential.
K. Takeuchi, ISSCC 2008 Tutorial T-7. Ken Takeuchi
Advanced Flash Memory Devices
11
Ken Takeuchi
Advanced Flash Memory Devices
12
2
2008/12/8
NAND Flash Memory
Page & Block of NAND Flash Memory Page : program/read unit
Block : Erase unit
Bitline
Bitline
Bitline
43nm 16Gb NAND K. Kanda, ISSCC, 2008.
NAND flash memory chip
2 Select-gate 32 Word-lines
Memory cell : Floating Gate-FET
Memory circuit
Source-line
2 Select-gate 32 Word-lines
Memory cells are sandwiched by select gates. Contactless structure : ideal 4F2 cell size F.Masuoka, IEDM 1987, pp.552-555.
Ken Takeuchi
Advanced Flash Memory Devices
13
Ken Takeuchi
Advanced Flash Memory Devices
Top View of NAND Flash Cell Array
MLC vs. SLC
Source-line (first metal)
Bitline (second metal)
14
SLC : Single-level cell or 1bit/cell MLC : Multi-level cell or >2bit/cell 2bit/cell : Long production record since 2001 3bit/cell or 4bit/cell : Will be commercialized this year.
Most existing SSD uses SLC. MLC based SSD is commercialized this year.
STI Active area SGD SGD Contact to bitline
Word-lines
SGS SGS Contact to source-line
SLC (Single-level cell)
MLC (Multi-level cell)
Number of memory cells “1” “0”
Number of memory cells “0” “1” “2” “3”
Simple structure : High scalability, High yield
Vth
Vth
K. Imamiya, ISSCC 1999, pp.112-113. Ken Takeuchi
Advanced Flash Memory Devices
15
NAND Operation Principle
Ken Takeuchi
Advanced Flash Memory Devices
16
NAND Operation Principle (Cont’)
Read
Program : Electron injection
Bit-line (0.8VÆ0V)
Number of memory cells “1” “0”
18V
Vread (4.5V)
0V
Vth
Selected word-line (Read voltage : 0V)
0V
9 Channel-FN tunneling
Read voltage Vread (4.5V)
Vread (4.5V)
Bit-line voltage
9 High reliability
0V
9 Low L currentt consumption ti
“1”
Erase : Electron ejection
“0” Time
9 After precharging, bit-lines are discharged through the memory cell.
20V
(~pA/cell) 9 Page based parallel program
0V
0V
20V
Typical page size : 2-4kB
9 Unselected cells are biased to the pass voltage, Vread. 9 Small cell read current (~1uA) Æ Slow random access (~50us)
20V
9 Serial access : 30-50ns Æ Fast read = 20-30MB/sec Ken Takeuchi
Advanced Flash Memory Devices
S. Aritome, IEDM 1990, pp.111-114. 17
Ken Takeuchi
Advanced Flash Memory Devices
18
3
2008/12/8
NAND Operation Principle (Cont’)
Outline
Page based parallel programming
SSD, Memory System Innovation NAND Overview NAND Circuit Design SSD Overview NAND Controller Design Operating System for SSD Green IT with SSD Summary
Bit-line Row decoder
Page
Page : 2-4KBytes ・・・
Page P buffer b ff
Page buffer
Memory cell array
T.Tanaka, Symp. on VLSI Circuits 1990, pp.105-106.
All memory cells in a page are programmed at the same time. Program speed = Page size / Programming time = 8KByte / 800us = 10MByte/sec (56nm MLC) Ken Takeuchi
K. Takeuchi, ISSCC 2006,pp.144-145.
Advanced Flash Memory Devices
19
NAND Circuit Design
Ken Takeuchi
Advanced Flash Memory Devices
20
Random Access : High Speed Programming Bit-by-bit Program Verify Scheme Program pulse
Program Algorithm
Random Access High Speed Programming High Speed Read
Program pulse No
21
Program pulse
Program voltage, Vpgm increases by ⊿Vpgm.
Verify read
Constant electric field across the tunnel oxide.
⊿Vpgm
Tpulse Tvfy
Programming time, Tprog = (Tpulse+Tvfy)×Npulse
Number of memory cells “1” “2” “0”
“3”
Vth
Vth shift is constant at ⊿Vpgm.
Program characteristics Npulse = ⊿Vth0/⊿Vpgm
Npulse (Time)
SLC
“1”-program & ”1”verify
“1”-program & ”1”verify
“3”-program & ”3”verify
(⊿Vth0/⊿Vpgm) cycles
Y1 Y2 2‐level cell
MLC
“2”-program & ”2”verify
Slowest cell
⊿Vth0
22
Random Access : High Speed Programming (Cont’)
Constant tunnel current.
1 cycle
Advanced Flash Memory Devices
Ken Takeuchi
Problems of MLC programming
Word-line waveform
# off program pulses: l N Npulse l cycles l
・・・
Page buffer
Incremental Program Voltage Scheme
Fastest cell
Page
During the verify-read, the program data in the page buffer is updated so that the program pulse is applied ONLY to insufficiently programmed cells. T.Tanaka, Symp. on VLSI Circuits 1992, pp.20-21.
Random Access : High Speed Programming (Cont’)
Vth
Verify‐read
End
Advanced Flash Memory Devices
Verify voltage
0V FN tunneling Bit-line
Yes
High Speed Programming High Speed Read
Achieve both fast programming and precise Vth control.
0V
All cells programmed ?
Sequential Access
Ken Takeuchi
18V 0V
Data load
Y1 Y2 4‐level cell
Two bits in a cell are assigned to two column addresses. 3 operations (“1”-, “2”- and “3”-program) required. Long programming.
G. Hemink, Symp. on VLSI Technologies 1995, pp.129-130. K. D. Suh, ISSCC 1995, pp.128-129. Ken Takeuchi
Advanced Flash Memory Devices
23
Ken Takeuchi
Advanced Flash Memory Devices
24
4
2008/12/8
Random Access : High Speed Programming (Cont’)
Random Access : High Speed Programming (Cont’)
Solution : Multi-page Cell Architecture
Program Voltage Optimization
1st page program
X1
Number of memory cells “0” “1”
X1 X2
X2 1st page data : “1”
“0”
Vth
2-level cell
2nd page program Number of memory cells “0” “1” “2”
Two bits in a cell are assigned to two row addresses. In average, 1.5 operations. Twice faster than conventional scheme.
“3” Vth
1st page data : “1” 2nd page data :
“0”
“0”
“1”
4-level cell
“1”
“0”
WL0, 31 : Higher capacitive coupling with word-lines. Initial program voltage is set lower. Optimized program voltage accelerates the programming.
K. Takeuchi, Symp. on VLSI Circuits 1997, pp. 67-68. Advanced Flash Memory Devices
Ken Takeuchi
25
Random Access : High Speed Programming (Cont’)
T. Hara, ISSCC 2005, pp. 44-45. Advanced Flash Memory Devices
Ken Takeuchi
26
Random Access : High Speed Programming (Cont’)
Problems : FG-FG interference
Solution : FG-FG Coupling Compensation [3-step programming]
[Programming order]
Step 1
Step2
Step3 p
Step 1. The memory cell is ROUGHLY programmed. Cells are programmed BELOW the target Vth. Step 2. Neighboring cells are programmed. Step 3. The memory cell is PRECISELY programmed.
FG-FG coupling shifts the Vth of a memory cell as the neighboring cell are programmed. To tighten the Vth distribution, ⊿Vpgm is decreased, causing a slow programming. The Vth modulation becomes significant as the memory cell is scaled down. J.D. Lee, EDL 2002, pp. 264-266.
FG-FG coupling is suppressed by 90%. Large ⊿Vpgm enables a fast programming. N. Shibata, Symp. on VLSI Circuits 2007, pp.190-191.
M. Ichige, Symp. on VLSI Technologies 2003, pp.89-90. Advanced Flash Memory Devices
Ken Takeuchi
27
Random Access : High Speed Read
Solution : Multi-page Cell Architecture Number of memory cells “1” “2” “0”
“3”
Vth
①
②
MLC
SLC “1”-read
“2”-read
Y1 Y2 2-level cell
“3”
X1 Vth
Y1 Y2 4-level cell
1st page data : “1”
“0”
“0”
X2
2nd
page data d t :
Two bits in a cell are assigned to two column addresses. 3 operations (“1”-, “2”- and “3”-read) required. Long random read.
①
③
1st page read : ②, ③ Æ EXOR 2nd page read : ①
“3”-read
4-level cell
“0”
“1” ②
X1 X2
“1” 2-level cell
③
“1”-read
28
Random Access : High Speed Read (Cont’)
Problems of MLC read Number of memory cells “1” “2” “0”
Advanced Flash Memory Devices
Ken Takeuchi
Two bits in a cell are assigned to two row addresses. In average, 1.5 operations. Twice faster than conventional scheme. K. Takeuchi, Symp. on VLSI Circuits 1997, pp. 67-68. S. Lee, ISSCC 2004, pp.52-53.
Ken Takeuchi
Advanced Flash Memory Devices
29
Ken Takeuchi
Advanced Flash Memory Devices
30
5
2008/12/8
Parallel Operation : Increase Page Size
Sequential Access : High Speed Programming
Page size trend
Parallel Operation
By increasing the word-line length, the page size has been extended to increase the write and read throughput.
Increase page size Multi-page operation Multi-chip operation (Interleaving)
9000
Bit-line
8000
Page size e (Byte)
7000
T be To b discussed di d in i “NAND C Controller t ll Circuit Ci it Design” D i ” section ti
Pipeline Operation
Page
6000
・・・
5000 4000
Page buffer
3000 2000
Write/Read Cache Cache Page Copy
1000 0 0.25um 0.16um 0.13um 90nm
70nm
50nm
43nm
Design rule
But, the large page size also causes problems. Noise issue due to the large RC delay of a word-line Advanced Flash Memory Devices
Ken Takeuchi
31
Parallel Operation : Increase Page Size (Cont’)
Ken Takeuchi
Advanced Flash Memory Devices
32
Parallel Operation : Increase Page Size (Cont’) Solution : Raise neighboring SG BEFORE bit-line discharge
Problems : SG-WL noise [Conventional read/verify-read] Bit-line
SG-WL capacitive coupling
SGD
1.5V
Selected WL31
WL bounce WL0
Read failure
SGS Bit-line precharge
Bit-line discharge K. Takeuchi, ISSCC 2006,pp.144-145.
Ken Takeuchi
Advanced Flash Memory Devices
33
Parallel Operation : Increase Page Size (Cont’) Problems : WL-WL noise
K. Takeuchi, ISSCC 2006,pp.144-145. Ken Takeuchi
Advanced Flash Memory Devices
Parallel Operation : Increase Page Size (Cont’) Solution
K. Takeuchi, ISSCC 2006,pp.144-145. Ken Takeuchi
Advanced Flash Memory Devices
34
35
K. Takeuchi, ISSCC 2006,pp.144-145. Ken Takeuchi
Advanced Flash Memory Devices
36
6
2008/12/8
Parallel Operation : Multi-page Operation
Pipeline Operation : Write/Read Cache
Multi-page operation
Pipelining of data-in/out & cell read/write
Operate multi-page simultaneously to increase the write/read throughput. [Multi-page operation]
Implement data cache in NAND Input /output data to the data cache during cell read/program [Write Cache Example : 0.13um 1Gbit NAND]
0.25um 256Mb NAND
Data Cache
K. Imamiya, ISSCC 1999, pp.112-113. Advanced Flash Memory Devices
Ken Takeuchi
37
Outline
Advanced Flash Memory Devices
Random access OS changes such as directory entry and file system metadata Application S/W change 50% of data is < 4KB. R d Random access mainly i l decides the performance of PC.
[Data transfer size in PC application]
K.Grimsrud, IDF2006, MEMS004.
Sequential access Boot Hibernation
39
Ken Takeuchi
Advanced Flash Memory Devices
SSD Performance (Cont’)
40
SSD Performance (Cont’) Sequential access
Random access Read
38
SSD Performance
SSD, Memory System Innovation NAND Overview NAND Circuit Design SSD Overview NAND Controller Design Operating System for SSD Green IT with SSD Summary Ken Takeuchi
H. Nakamura, ISSCC 2002, pp.106-107. Advanced Flash Memory Devices
Ken Takeuchi
NAND : Single chip operation Write
NAND (SLC)
25us
300us
1ms
NAND (MLC)
50us
800us
1ms
HDD
3ms
3ms
N.A.
NAND : 4 chip interleaving
Read
Write
Read
Write
NAND (SLC)
25MB/sec
20MB/sec
100MB/sec
80MB/sec
NAND (MLC)
20MB/sec
10MB/sec
80MB/sec
40MB/sec
HDD
80MB/sec
80MB/sec
‐
‐
Erase
[Block diagram of SSD w w. interleaving function]
Erase are hidden by operating the erase during the idle period.
SSD (SLC) : Comparable read and write performance with HDD. SSD (MLC) : Comparable read performance. By introducing 8chip interleaving, the write performance can be comparable with HDD.
Read : SSD with SLC and MLD has a great advantage over HDD. Write : SSD still has a performance advantage. Write performance can be an issue in the future if the NAND performance degrades by scaling the memory cell or increasing the number of bits per cell.
C. Park, NVSMW 2006, pp.17-20. Ken Takeuchi
Advanced Flash Memory Devices
41
Ken Takeuchi
Advanced Flash Memory Devices
42
7
2008/12/8
SSD Performance (Cont’)
Garbage Collection & Slow Random Write
Slow random write problem Page : program/read unit
System performance degradation of a large block Block : Erase unit
70nm 8G MLC (ISSCC2005)
Bitline
[Frequent block copy]
56nm 8G MLC (ISSCC2006) (This work)
Old block 32WLs
Bitline
32WLs
① Cell read New block
Bitline
2 Select-gate 32 Word-lines
4KB page (max)
8KB page (max)
512KB block
1MB block
Page buffer ② Data-out, ECC, Data-in
System performance degradation
2 Select-gate 32 Word-lines
Source-line
③ Cell program
Block copy time
In case a part of the block is over-written, a block copy operation is performed.
= (T_Cell read+T_Data_out+TECC+T_Cell program) ×(# of pages per block)
Fast block copy required
= 125ms Ken Takeuchi
Advanced Flash Memory Devices
43
Pipeline Operation : Cache Page Copy Step2
Old block Page i
Step3
Old block
Old block
Page i+1
Cell Read
New block
New block
Page buffer
Page buffer
NAND controller
Data-out NAND ECC controller
Cell read
New block
Page buffer
NAND controller
Data-out NAND ECC controller
44
43nm NAND (All bit-line architecture)
56nm NAND (Alternate bit-line architecture)
New block Cell program
Page buffer
K. Takeuchi, ISSCC 2006,pp.144-145.
Advanced Flash Memory Devices
All bit-line architecture # of pages in a block is half. Block copy time is also half.
Step4
Old block
Ken Takeuchi
Smaller Block Size: All Bit-line Architecture
Solution : Fast block copy Step1
NAND controller
Step 4 : Pipelining of programming Page i and data out / ECC of Page i+1.
Fast block copy Ken Takeuchi
Advanced Flash Memory Devices
45
R. Cernea, ISSCC 2008,pp.420-421. K. Kanda, ISSCC 2008, pp.430-431.
K. Takeuchi, ISSCC 2006, pp.144-145.
K. Takeuchi, ISSCC 2006,pp.144-145.
Advanced Flash Memory Devices
Ken Takeuchi
Solution for Slow Random Write
46
SSD Power Consumption
Fast pipeline block copy operation Smaller block size (All bit-line architecture) Page based data allocation Not to overwrite an old page but write data to an empty page. Change the logical-physical address table table.
Power consumption NAND : Single chip operation NAND (SLC)
NAND : 4 chip interleaving
Read
Write
Read
Write
20mA
20mA
80mA
80mA
NAND (MLC)
20mA
20mA
80mA
80mA
HDD
>300mA
>300mA
‐
‐
In SSD, additional current (~100mA) are consumed in the NAND controller, RAM and IO.
Actual Power Consumption
Old page
C. Park, NVSMW 2006, pp.17-20.
New page
In all modes, the power consumption of SSD is smaller than HDD.
D. Barnetson, Electonic Journal 192th Technical Symposium, 2008, pp.91-102. Ken Takeuchi
Advanced Flash Memory Devices
47
Ken Takeuchi
Advanced Flash Memory Devices
48
8
2008/12/8
SSD Reliability
SSD Reliability (Cont’)
SSD is robust. No mechanical parts. Need to be careful in PC/server application Portable consumer electronics application (Digital still cameras, MP3 players, Camcorders) Effective data retention time << 10years Data quickly transferred to PC or DVD through USB drive and memory cards. Most probably data backup in PC PC/Enterprise server application Higher reliability required w.o. backup Need longer data retention time : 5-10 years Ken Takeuchi
Advanced Flash Memory Devices
Failure mechanism of NAND Program disturb During programming, electrons are injected to unselected memory cells. Read disturb During read, read electrons are injected to unselected memory cells. Write/Erase endurance & Data retention As the Write/Erase cycles increase, damage of the tunnel oxide causes a leakage of stored charge. 49
Ken Takeuchi
SSD Reliability (Cont’)
50
SSD Reliability (Cont’)
“Classic” program disturb Program inhibit Bitline (Vcc)
Advanced Flash Memory Devices
“Modern” program disturb
Program Bitline (0V) Vcc Vpgm (18V) Vpass (10V)
Vpgm disturb cell
Vpass disturb cell 10V
18V
D
～8V
S
Vpass (10V) 0V Vcc
J. D. Lee, NVSMW 2006, pp. 31-33. K.T.Park, SSDM 2006, pp.298-299.
D
0V
S
Hot carriers generated at the select gate edge inject into the memory cell causing a Vth shift. The Vth shift can be reduced by increasing SG-WL space.
Both selected and unselected cells suffer from the disturb.
K. D. Suh, ISSCC 1995, pp.128-129.
Ken Takeuchi
Advanced Flash Memory Devices
51
Ken Takeuchi
SSD Reliability (Cont’)
Advanced Flash Memory Devices
52
SSD Reliability (Cont’)
“Modern” program disturb (Cont’)
Read disturb Bitline (0.8VÆ0V) Vread (4.5V)
4.5V
Selected word-line (0V) D
0V
S
Vread (4.5V)
Vread (4.5V)
Select Tr. Dummy Tr. WL0
0V
The Vth shift can be reduced by adding dummy WL.
Weak program bias condition Unselected word-lines suffer from the read disturb.
K.T.Park, SSDM 2006, pp.298-299. Ken Takeuchi
Advanced Flash Memory Devices
53
Ken Takeuchi
Advanced Flash Memory Devices
54
9
2008/12/8
SSD Reliability (Cont’)
SSD Reliability (Cont’) Write/Erase Endurance & Data Retention
Program disturb and read disturb summary Program disturb and read disturb is a “bit error” not a “burst error”.
Endurance : how many times data are written Data retention : how long the data remains valid Clear correlation between endurance and data retention
Page assignment of MLC X1
Two bits in MLC are assigned to different pages. Even if one MLC cell fails, one bit in two pages fails.
X1 X2
Damages to the tunnel oxide during write and erase cause the data retention problems. Traps are generated during write and erase. The unlucky cell with traps results in a leakage path, causing the charge transfer. The leakage current is called SILC (Stress Induced Leakage Current).
X2 2-level cell
ECC(Error correcting code) effectively corrects the bit error.
4-level cell
K. Takeuchi, Symp. on VLSI Circuits 1997, pp. 67-68.
Existing ECC corrects 4-12bit errors per 512Byte sector. K. Prall, NVSMW 2007, pp. 5-10.
Ken Takeuchi
Advanced Flash Memory Devices
55
Ken Takeuchi
To guarantee data retention, Write/Erase cycles are limited to 100K (SLC) or 10K (MLC). Advanced Flash Memory Devices
56
SSD Reliability (Cont’)
Outline
100K (SLC) or 10K(MLC) W/E cycles acceptable?
SSD, Memory System Innovation NAND Overview NAND Circuit Design SSD Overview NAND Controller Design Operating System for SSD Green IT with SSD Summary
W/E cycles estimation for PC 32GB SSD Usage scenario : 2~5GB/day (#) Service for 5years 100% efficient wear leveling g (365 days/year) x 5years / (32GB / 2~5GB/day) = 114~285 W/E cycles 114~285 cycles are far below the NAND limitation of 100K for SLC or 10K for MLC. Actual W/E cycles are higher for the file management such as garbage collection. (#) W.Akin, IDF 2007_4, MEMS003. Y.Kim, Flash Memory Summit 2007. Ken Takeuchi
Advanced Flash Memory Devices
57
Ken Takeuchi
SSD SW Architecture
Advanced Flash Memory Devices
58
HW Architecture
OS File system
Block diagram (Single channel)
Low level driver ATA I/F SSD NAND Controller Host I/F Flash Translation Layer (FTL) Bad block management
Wear-leveling
Address translation from logical address to physical address of NAND
Interleaving ECC
HDD-like architecture : DRAM buffer to hide NAND random access High power consumption High cost
NAND I/F NAND Flash Memory
C. Park, NVSMW 2006, pp.17-20. Ken Takeuchi
Advanced Flash Memory Devices
59
Ken Takeuchi
Advanced Flash Memory Devices
60
10
2008/12/8
HW Architecture (Cont’)
High Speed Technology Interleaving : Sequential Parallel Write
Block diagram (Multi-channel)
DRAM eliminated : Random access of NAND is faster than HDD. Low p power consumption p Low cost Multi-channel Parallel operation High bandwidth 2-channel 4-way interleaving Max write throughput : 80MB/sec for MLC. HW driven automatic operation. C. Park, NVSMW 2006, pp.17-20. Advanced Flash Memory Devices
Ken Takeuchi
C. Park, NVSMW 2006, pp.17-20. 61
High Reliability Technology
Advanced Flash Memory Devices
Ken Takeuchi
62
High Reliability Technology (Cont’)
Wear-leveling Problem Write/Erase cycle of NAND is limited to 100K for SLC and 10K for MLC. Solution Write data to be evenly distributed over the entire storage. Count # of Write/Erase cycles of each NAND block. Based on the Write/Erase count, NAND controller re-map the logical address to the different physical address. Wear-leveling is done by the NAND controller (FTL), not by the host system. Block : Erase unit
Example of wear-leveling If the block is occupied with old data, data is programmed to a new block. If there is no free block, the invalid block are erased.
Old file
Bitline
Block 1 Block 2 Bl k 3 Block Block 4 Block 5 Block 6 Block 7 Block 8 Block 9
Block 1 Block 2 Bl k 3 Block Block 4 Block 5 Block 6 Block 7 Block 8 Block 9
Rewrite old file
Block 4 Æ Invalid
Bitline
Empty block
New File
Bitline
Ken Takeuchi
Advanced Flash Memory Devices
63
High Reliability Technology (Cont’)
Write new file to an empty block
Advanced Flash Memory Devices
Ken Takeuchi
64
High Reliability Technology (Cont’) Dynamic wear-leveling
Static data Data that does not change such as system data (OS, application SW). Dynamic data Data that are rewritten often such as user data.
Write/Erase count
Dynamic wear-leveling Wear-level only over empty and dynamic data. Static wear-leveling Wear-level over all data including static data.
Red : Static data such as system data. Blue : Dynamic data such as user data
Physical block address
Block with static data is NOT used for wear-leveling. Write and erase concentrate on the dynamic data block. N.Balan, MEMCON2007. SiliconSystems, SSWP02.
Ken Takeuchi
Advanced Flash Memory Devices
65
Ken Takeuchi
Advanced Flash Memory Devices
66
11
2008/12/8
High Reliability Technology (Cont’)
High Reliability Technology (Cont’) Bad Block Management Program/Erase characteristics vs. endurance
Static wear-leveling Write/Erase count
Red : Static data such as system data. Blue : Dynamic data such as user data
Physical block address
Wear-level more effectively than dynamic wear-leveling. Search for the least used physical block and write the data to the location. If that location Is empty, the write occurs normally. Contains static data, the static data moves to a heavily N.Balan, MEMCON2007. used block and then the new data is written. SiliconSystems, SSWP02. Ken Takeuchi
Advanced Flash Memory Devices
As the Write/Erase cycles increases, erase failure occurs, resulting in a bad block. The NAND controller detects and isolates the bad block. Y.R. Kim, Flash Memory Summit 2007. 67
Ken Takeuchi
Advanced Flash Memory Devices
High Reliability Technology (Cont’) ECC (Error Correcting Code) To overcome read disturb, program disturb and data retention failure, ECC have to be applied. Since failure pattern is random, BCH is sufficient. Existing NAND controller can correct 4-12bit error per 512Byte sector. NAND with embedded ECC is also published. Ken Takeuchi
68
Outline SSD, Memory System Innovation NAND Overview NAND Circuit Design SSD Overview NAND Controller Design Operating System for SSD Green IT with SSD Summary
R. Micheloni, ISSCC2006, pp.142-143.
Advanced Flash Memory Devices
69
Why OS?
Ken Takeuchi
Advanced Flash Memory Devices
70
New Memory System: NAND/HDD Combo
Motivation
Multi-drive of NAND/HDD
NAND as a cache Intel Robson Microsoft Ready Boost
Existing OS is optimized for magnetic drives. Current SSD based PC uses the conventional OS and just replace HDD with SSD. To achieve the best performance and reliability of SSD, OS especially file system should be optimized. Windows 7 will treat SSD differently from HDD.
H. Pon, NVSMW 2007.
SanDisk Vaulter Disk NAND : OS data HDD : User data
http://www.sandisk.com/Assets/File/pdf/ oem/Vaulter_brochure.pdf
Temporary solution until NAND cost becomes comparable with HDD cost. Ken Takeuchi
Advanced Flash Memory Devices
71
Ken Takeuchi
Advanced Flash Memory Devices
72
12
2008/12/8
MLC/SLC Hybrid SSD
Performance Optimization
Future Direction : Hybrid SSD with SLC and MLC Concept : Right device for the right use. Enjoy the Benefit of both SLC and MLC. SLC : Fast and highly reliable but low capacity. Use SLC as a cache or system data storage. MLC : Large capacity but slow. Use MLC as user data storage. OS support essential: SSD does NOT know the contents of the file.
Sector size optimization Minimum write/read unit of NAND is a page. Typical page size is 4-8KByte. A page is written only ONCE to avoid the Page program disturbance. With current OS having 512Byte sector, one sector write wastes >80% of data in a page.
Toshiba LBA LBA-NAND NAND http://www1.toshiba.com/taec/index.jsp
Samsung Combo SSD J. Elliott, WinHEC2007. SATA-III
MLC
48/64/128/256/512GB
SATA-II
(Multi Level Cell)
32/48/64/128/256GB
SATA-II
SATA-III
16/32/48/64/96/128GB
56/112/224/336/448GB
・・・
SATA-II
1 sector write
28/56/112/168/224GB
SATA-III SATA-II
Combo (SLC+MLC)
32/64/128/192/256GB
Spansion MirroBit Eclipse http://www.spansion.com/products/MirrorBit_Eclipse.html
14/28/56/84/112GB
SATA-II 16/32/64/96/128GB
SATA-II
SATA-I PATA
(Single Level Cell)
4/8/16/32GB
R/W Speed:
57/32
2006
LBD(Long Block Data) sector standard (Windows Vista) : 4KByte sector size fits better with SSD.
SLC
8/16/32/48/64GB
8/16/32/48/64GB
Remaining portion becomes garbage.
64/45
100/80
2007
2008
160/160
800/800
2009
Ken Takeuchi
1300/1300
2010
Advanced Flash Memory Devices
73
Ken Takeuchi
Advanced Flash Memory Devices
Page Size Trend
Frequent Garbage Collection System performance degradation of a large block 70nm 8G MLC (ISSCC2005)
As the page size increases as NAND is shrinking, larger sector size such as 64KByte or 128KByte is required.
[Frequent block copy]
56nm 8G MLC (ISSCC2006) (This work)
Old block 32WLs
1200
9000
32WLs
8000
① Cell read
1000
512KB block
1MB block
Page size (Byte e)
8KB page (max)
③ Cell program Page buffer ② Data-out, ECC, Data-in
System performance degradation
Block size (KBy yte)
7000
New block 4KB page (max)
6000 5000 4000 3000
400 200 0
0 0.25um 0.16um 0.13um 90nm
70nm
50nm
43nm
0.25um 0.16um 0.13um 90nm
Design rule
= 125ms
50nm
43nm
K. Takeuchi, ISSCC 2006,pp.144-145.
Advanced Flash Memory Devices
75
Advanced Flash Memory Devices
Ken Takeuchi
Reliability Optimization
SMART
Decrease write/erase cycles of NAND, extending the NAND lifetime. Control the file allocation to store frequently rewritten file in DRAM and not to access NAND. Enhanced Write Filter (EWF) is located between file system and low level driver interfacing with SSD. OS/Application SW support essential: Again, SSD does NOT know the contents of the file.
(Self-Monitoring, Analysis and Reporting Technology) Monitor the storage and report/predict the failure. SMART for HDD is NOT smart because it is very difficult to predict the mechanical failure. (Google report, report http://209.85.163.132/papers/disk_failures.pdf) http://209 85 163 132/papers/disk failures pdf)
SMART for SSD can be really smart. Product lifetime can be predicted because the failure rate is highly correlated with the write/erase cycles. Predict the SSD lifetime by monitoring the write/erase cycles and replace SSD before the fatal failure occurs.
Enhance Write Filter SSD Low-level Driver
http://www.tdk.co.jp/tefe02/ew_007.pdf
http://msdn2.microsoft.com/en-us/library/ms912909.aspx Advanced Flash Memory Devices
76
Reliability Optimization (Cont’)
Enhanced Write Filter (Windows Embedded)
Ken Takeuchi
70nm
Design rule
×(# of pages per block)
Fast block copy required
File System
600
1000
= (T_Cell read+T_Data_out+TECC+T_Cell program)
Application
800
2000
NAND controller
Block copy time
Ken Takeuchi
74
77
Ken Takeuchi
Advanced Flash Memory Devices
78
13
2008/12/8
Outline
Green IT : Power Crisis of Data Center Data through internet is increasing drastically. In the U.S, power consumption at the data center doubled during last 5 years. (5 nuclear power plants!) In 2025, the data increases by 200 times and the power consumption increases by 12 times.
SSD, Memory System Innovation NAND Overview NAND Circuit Design SSD Overview NAND Controller Design Operating System for SSD Green IT with SSD Summary Ken Takeuchi
Advanced Flash Memory Devices
Data Center
Power increase of HDD
79
Replace HDD with SSD
Ken Takeuchi
Advanced Flash Memory Devices
80
Problems of NAND Flash Memory Reliability Low write/erase cycles: Currently <10K cycles (MLC) and decreasing as scaling down memory cells. Æ >100K cycles required
Power Consumption p Because of the scaling, the parasitic capacitance increases and the power consumption doubles. Æ Low power memory device required
SSD (NAND Flash)
Capacity
HDD
Currently Gbyte Æ TByte required Ken Takeuchi
Advanced Flash Memory Devices
81
Operation Current Trend of NAND
Advanced Flash Memory Devices
82
Fe(Ferroelectric)-NAND Flash Memory NAND Flash Memory w. Ferroelectric Transistor Scalable below 20nm Low voltage/power operation: 20VÆ5V Write/Erase cycles: 10K cyclesÆ100M cycles Æ Most suitable for data server application
In the scaled VLSIs, most power is consumed to charge and discharge signal-lines. Inter signal-line capacitance, Cwire-wire drastically increases to keep the low signal-line resistance. 100 Operation current [mA A]
Ken Takeuchi
8080 6060
2020 00 10 10
Pt SrBi2Ta2O9 Hf-Al-O
M F I
Cwire-wire Cwire-wire
4040
n+ 20
20
30
40
50
60
30 40 size 50 [nm] 60 Feature
70
70
Cwire-wire Cwire-wire
n+ p-Si
MFIS Structure (Metal-FerroelectricInsulator-Semiconductor) S. Sakai, NVSMW 2008, pp.103-104.
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125. Ken Takeuchi
Advanced Flash Memory Devices
83
Ken Takeuchi
Advanced Flash Memory Devices
84
14
2008/12/8
Operation Principle of Fe-NAND Flash
Scalable below 20nm Ferro electricity is maintained in 20nm size.
Low voltage operation BL
M F I
SGD FeFET WL0
SrBi2Ta2O9 (SBT)
5V
0V
BL
TEM Photograph
M F I
n+
Sr
n n+
n+
Bi
n+
p-well Si
p-well Si
Ta
5V
0V
O
WL31
Program
Erase
SGS
a = 0.5506 nm b = 0.5534 nm c = 2.498 nm
SrBi2Ta2O9 ~ 400nm Hf-Al-O ~ 10nm IL Si
c
Source Line
IL: Interfacial layer major component – SiO2
b a
S. Sakai, NVSMW 2008, pp.103-104. Ken Takeuchi
Advanced Flash Memory Devices
85
10 Year Data Retention
S. Sakai, NVSMW 2008, pp.103-104.
Ken Takeuchi
Advanced Flash Memory Devices
86
Excellent W/E Cycles up to 100M 1.1
Fe-NAND Vth (V)
-4
Drain Cu urrent, Id (A)
10
On states 1st 2nd 3rd 4th
-8
10 10
-10 10
10
-12
10
-14
Pt SrBi2Ta2O9
M F I
-6
10
37.0 days
Hf-Al-O n+
n+ n
33 5 d 33.5 days
1.0 0.9
Erased Programmed
0.8 0.7 0.6 0.5 0 5 3 10
p-Si
10 years
4
5
6
7
8
10 10 10 10 10 Number of Cycles S. Sakai, NVSMW 2008, pp.103-104.
Off states 0
10
2
10
10
4
6
8
10
NAND
10
Time, t (s)
Buffer layer improves Si‐ interface characteristics.
Y.R. Kim, Flash Memory Summit 2007. Ken Takeuchi
Advanced Flash Memory Devices
87
Co-design of NAND and Controller Circuits
Ken Takeuchi
Advanced Flash Memory Devices
88
Co-design of NAND and Controller Circuits
By co-designing both NAND and NAND controller circuits, the power consumption of SSD is reduced by 60%. 100 CE2, R/B2
NAND Chip1
NAND Controller
CE3, R/B3
NAND Chip2
NAND Chip3
CE4, R/B4 NAND Chip4
Operation current [mA] O
CE1, R/B1
Power Detect ((PD)) ALE, CLE, RE, WE, WP, IO
系列1 Conventional Selective BL precharge 系列2 Selective BL precharge 系列3
6060 4040
NAND Flash Memory
23% reduction
8080
& Advanced SL program
48% reduction
– Selective bit-line precharge scheme – Advanced source-line program
2020 00 10 10
20
20
30
40
50
60
30 40 size 50 [nm] 60 Feature
70
70
Current waveform of NAND Chip1 Time
Current waveform of NAND Chip2
• Low Power Circuit Technology
• Low Noise Circuit Technology – Intelligent interleaving
Time
Current waveform of NAND Chip3
Time
Current waveform of NAND Chip4
Time
NAND Controller Ken Takeuchi
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125. Advanced Flash Memory Devices
89
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125. Ken Takeuchi
Advanced Flash Memory Devices
90
15
2008/12/8
NAND Bit-line Capacitance Trend
SSD Write Performance • Interleaving: write N NAND chips in parallel Performance_SSD = N × Performance_NAND
• Inter bit-line capacitance, CBL-BL drastically increases to keep the low bit-line resistance.
Channel 1 NAND Chip1
NAND Chip15
NAND Chip16
CBL-BL
・・
NAND Controller
NAND Chip2
Channel 4
CBL-BL
CBL-BL CBL-BL
NAND Chip2
NAND Chip15
Bit-line capacitance [a.u.]
10
NAND Chip1
NAND Chip16
8 6
• Limitation of N N × I_NAND < Icc_constraint • Key NAND design issue: Decrease I_NAND to maximize N
4 2 0
10
10
20
30
20
40
50
60
30 40 size 50[nm] 60 Feature
70
43nm 16Gb NAND
70
K. Kanda, ISSCC, 2008. K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125. Advanced Flash Memory Devices
Ken Takeuchi
91
Advanced Flash Memory Devices
Ken Takeuchi
Multi-level Cell Program
Current & Performance Trend NAND operation current
8080 6060
100 100
Bit-by-bit Program Algorithm
8080
Data load
6060
4040
Number of memory cells “A” “B” Erased state
2020
20
20
30
40
50
60
30 40 size 50 [nm] 60 Feature
70
70
No
0 010 10
20
20
30
40
50
60
30 40 size 50 [nm] 60 Feature
“A”-program & ”A”verify
Verify‐read
“C”-program & ”C”verify
Yes End
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125. 93
Conventional Verify Read
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
Number of memory cells “1” “0”
Bit-line
*
Additional Transistor
Vth
Bit-line
*
N2
* PRE2
*
*
N3
N1
PRE1 N3
Read voltage Bit-line voltage Vread (4.5V)
“1” “0” Time
Vread (4.5V) 0V Ken Takeuchi
94
• During verify, precharge bit-line based on the program data in the page buffer. • Skip unnecessary bit-line precharge and save current during verify. Page Buffer • Area overhead < 1%
Vread (4.5V) Selected word-line (Read voltage : 0V)
Advanced Flash Memory Devices
Ken Takeuchi
Selective Bit-line Precharge Scheme
• All bit-lines are precharged irrespective of the program data. • Page based program Æ 8KByte(Page size) bit-lines are precharged. Æ Total bit-line capacitance > 200nF! Bit-line Bit line (0.8VÆ0V)
“B”-program & ”B”verify
All cells programmed ?
• Low power circuit of NAND required. Advanced Flash Memory Devices
Vth
70
70
C_bit‐line↑ Æ I_NAND ↑ Æ N ↓ Æ Performance_SSD↓
Ken Takeuchi
“C”
VA VB VC 1st page program 2nd page program
Program pulse
4040
2020 00 10 10
SSD performance SSD Perforrmance [MByte/sec]
Operattion current [mA]
100
92
PRE1
PRE2 “High”
“A”-verify
“High”
“B”-verify
“High”
“Low”
“C”-verify
“Low”
“High”
Latch1
IO
CSL
N1 Latch2
N2
/IO
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125. Advanced Flash Memory Devices
95
Ken Takeuchi
Advanced Flash Memory Devices
96
16
2008/12/8
1st Page Program (“A”-verify) Number of memory cells “A” “B” Erased state
2nd Page Program (“B”-verify) Number of memory cells “A” “B” Erased state
“C”
Vth
Vth
VA VB VC 1st page program 2nd page program
1st
[Conventional] [Proposed]
[Conventional] [Proposed]
Bit-line
Bit-line precharge
Time
Bit-line discharge
Bit-line discharge
Bit-line precharge
97
100 23% reduction
Operation current [[mA]
VB VC 2nd page program
Bit-line Word-line Time
Bit-line Bit-line discharge precharge
8080
98
100 100
Conventional 系列1 Selective BL precharge 系列2
Bit-line Bit-line discharge precharge
4040
2020 00 10 10
VC
8080 6060
4040
50% improved Conventional 系列1
2020
20
20
30
40
50
60
30 40 size 50 [nm] 60 Feature
70
70
系列2 Selective BL precharge
0 010 10
20
20
30
40
50
60
30 40 size 50 [nm] 60 Feature
70
70
Time
Advanced Flash Memory Devices
Ken Takeuchi
Time
• 23% current reduction. • 50% performance improvement.
“C”
“B”-program complete / incomplete “C”-program complete Program inhibit “C”-program incomplete
VC
Bit-line Bit-line discharge precharge
Result – Selective BL precharge
[Conventional] [Proposed]
Bit-line Word-line
VB
Advanced Flash Memory Devices
Ken Takeuchi
6060
“B”-program complete / incomplete “C”-program complete / incomplete Program inhibit
Time
Bit-line Bit-line discharge precharge
Vth
VA 1st page program
Word-line
VB
Time
2nd Page Program (“C”-verify) Number of memory cells “A” “B” Erased state
Bit-line
Word-line
VA
Advanced Flash Memory Devices
Ken Takeuchi
“B”-program complete “C”-program complete / incomplete Program inhibit “B”-program incomplete
Bit-line
Word-line
VA
VB VC page program
2nd
SSD Performance [MBy yte/sec]
Bit-line Word-line
VA page program
“B”-program complete / incomplete “C”-program complete / incomplete Program inhibit
“A”-program complete Program inhibit “A”-program incomplete
“A”-program complete / incomplete Program inhibit
“C”
99
Advanced Flash Memory Devices
Ken Takeuchi
100
Capacitance Comparison
Source-line Program (VLSI’99) • Save current during program pulse. • Bias 2.5V from a low capacitance source-line. • Low voltage swing for a high capacitance bit-line
Bit-line Bit-line Bit-line
[Conventional]
[Source-line program]
Bit-line (2.5V)
Bit-line (1V)
SGD (4.5V) Vpgm (18V)
SGD (0VÆ0.7V) V Vpgm (18V)
Vpass (10V)
Vpass (10V)
Inhibit voltage Vpass (10V) SGS (0V)
Source-line (1V)
2 SG, 64 CG
Cbit-line = Cwire(bitline) + Cjunction Csource-line = Cwire(source-line) + Cjunction
Inhibit voltage
Cwire(bitline) >> Cjunction, Cwire(source-line)
Demonstrated in 0.25um NAND
Vpass (10V) SGS (4.5VÆ0V)
Cbit-line >> Csource-line
Source-line (2.5V) K. Takeuchi, Symposium on VLSI Circuits, pp.37-38, 1999.
Ken Takeuchi
Advanced Flash Memory Devices
2 SG, 64 CG Source-line
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125. 101
Ken Takeuchi
Advanced Flash Memory Devices
102
17
2008/12/8
Read Operation
Advanced Source-line Program • Total source-line capacitance in a chip exceeds 20nF for sub-50nm NAND. • Hierarchical source-line structure • Only metal layout change; No area overhead
• All Source-line switch: ON • Minimize the source-line resistance. • Suppress the source-line noise. Sub-array
Sub-array
Sub-array
Sub-array
Bit-line Bit-line Bit-line Bit-line Bit-line Bit-line
Row decoder Row decoder
Row decoder
Row decoder
Row decoder
Row decoder
Row decoder
Row decoder
Row decoder
Row decoder
Local source-line
Source-line decoder
Switch
Local source-line
Local source-line
Source-line decoder
Source-line decoder
Local source-line
ON
Global source-line
Global source-line K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125. Advanced Flash Memory Devices
103
Advanced Flash Memory Devices
Ken Takeuchi
Program Operation
• 60% current reduction. • 250% performance improvement. Sub-array
Sub-array
100 系列1 Conventional 系列2 Selective BL precharge 系列3 Selective BL precharge
8080
Bit line Bit-line
6060
Bit-line
Row decoder
Local source-line
Source-line decoder
ON
Local source-line
6060
48% reduction
00 10 10
OFF
105
Conventional 系列1 Selective BL precharge 系列2 Selective BL precharge 系列3
2020
20
20
30
40
50
60
30 40 size 50 [nm] 60 Feature
70
70
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125. Advanced Flash Memory Devices
Ken Takeuchi
250% improved
4040
2020
Source-line decoder
Global source-line
8080
& Advanced SL program
4040
Row decoder
Row decoder
100 100
23% reduction
Operation current [[mA]
Bit-line
Row decoder
104
Result – Advanced SL program
• Only one of 16 sub-arrays activated • Source-line capacitance: 90% reduced
Row decoder
ON
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
SSD Performance [MBy yte/sec]
Ken Takeuchi
Source-line decoder
00 10 10
& Advanced SL program
20
40
50
60
70
70
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125. Advanced Flash Memory Devices
Ken Takeuchi
Intelligent Interleaving
106
Control Circuit • Introduce Power Detect (PD) signal. • When a NAND starts bit-line precharge & charge pump ramp-up, PD becomes low. • NAND controller issues a write command when PD is high and NAND is ready.
• Disperse the current peak and avoid the power supply noise. Bit-line precharge & charge pump ramp-up cause >100mA current peak.
CE1 R/B1 CE1,
NAND Chip1
CE2, R/B2
CE3, R/B3
Time
NAND Chip2 Time
NAND Controller
NAND Chip3
NAND Chip1
NAND Chip2
NAND Chip3
CE4, R/B4 NAND Chip4
Time
NAND Chip4 ●
30
30 40 size 50 [nm] 60 Feature
20
Power Detect (PD)
Time
●
PD R/B1
Program_Enable1 (Chip1)
PD R/B3
Program_Enable3 (Chip3)
PD R/B2
Program_Enable2 (Chip2)
PD R/B4
Program_Enable4 (Chip4) ●
●
ALE, CLE, RE, WE, WP, IO
[Current waveform during program and verify]
● ●
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125. Ken Takeuchi
Advanced Flash Memory Devices
107
Ken Takeuchi
Advanced Flash Memory Devices
108
18
2008/12/8
Current Waveform
Summary: Co-design of NAND and Controller Circuits • Co-design of NAND and NAND controller.
Current waveform of NAND Chip1
– To improve SSD speed, decrease the NAND current and maximize # of NAND operated in parallel.
Time
Current waveform of NAND Chip2
Time
Current waveform of NAND Chip3
• Two low power circuit technologies proposed.
Time
Current waveform of NAND Chip4 ●
– – – –
Time
● ●
Power Detect (PD)-signal R/B1 (chip1)
Selective bit-line precharge g scheme Advanced source-line program 60% current reduction. 250% SSD performance improvement.
R/B2 (chip2) R/B3 (chip3)
• Intelligent interleaving realizes highly reliable and high-speed SSD.
R/B4 (chip4) ● ● ●
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125. Ken Takeuchi
Advanced Flash Memory Devices
109
Ken Takeuchi
3D-integrated SSD
Advanced Flash Memory Devices
110
Summary
First demonstration of 3D-integrated SSD. With smart Mix & Match, the power decreases by 70%.
New Memory System SLC/MLC Hybrid SSD solves the system bottleneck.
DRAM MPU Core Logic Flash ROM Analog Cache
SoC
Emerging Market: Power Crisis at data center
3D SiP 3D-SiP Analog
SSD is expected to save power at data center. Logic Flash
DRAM
ROM
Device, circuit and OS innovation required. Co-design of NAND and NAND controller circuits OS optimization such as sector size optimization Fe(Ferroelectric)-NAND flash memory device 3D-integrated SSD circuits
Cache MPU Core
To be presented at ISSCC in Feb. 2009@San Francisco. 13.2. “A 1.8V 30nJ Adaptive Program-Voltage (20V) Generator for 3D-Integrated NAND Flash SSD” Ken Takeuchi
Advanced Flash Memory Devices
111
Ken Takeuchi
Advanced Flash Memory Devices
112
Thank you! E-mail :
[email protected] http://www.lsi.t.u-tokyo.ac.jp
Ken Takeuchi
Advanced Flash Memory Devices
113
19
