Transcript
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CPU DC/DC
Spears Intel UMA Block Diagram
2007/08/29
ISL6262A INPUTS
Project code : 91.4W001.001 PCB P/N : 07211 Revision : -1
Intel CPU D
Merom 4M FSB:667MHz/800MHz
CLK GEN ICS9LPRS365 4
DDR I/F
INTEGRATED GRAHPICS
DDR II 667 Channel B
LVDS, CRT I/F
8,9,10,11,12,13
C
1394
1394
26
25,26
Ricoh R5C833
SD/SDIO/MMC MS/MS Pro/xD26
INTEL
PCI
1D8V_S3
LVDS
PCIE x 16
LCD
SVIDEO
S-Vedio (Upsell)
SDVO
SiI 1392 (Upsell)
PCIE x 1
-c
31
PCIE x 1 & USB 2.0 x 1
USB 2.0 x 1
LPC I/F
Azalia CODEC
MIC IN HP1
PCI/PCI BRIDGE
32
Internal Analog MIC
2CH SPEAKER
OP AMP MAX9789A
PATA
SATA
HP2
HDD 33
24
ODD 24
Capacity Button37
New Card
5V_AUX_S5 5V_S5 3D3V_S5
DCBATOUT 16
C
Power SW TI TPS2231
OUTPUTS
SYSTEM DC/DC
28
TPS51100 INPUTS
OUTPUTS
1D8V_S3
0D9V_S3
28
SYSTEM DC/DC LDO INPUTS
Mini-Card X2 802.11a/b/g BT/UWB/Robson
29 30
Mini-Card X1
30
OUTPUTS
3D3V
2D5V
1D8V
1D5V_S0
CAMERA (Option)
SYSTEM DC/DC
USB 2.0 x 1
KBC Winbond WPC8763L
Lift Side: USB x 2
OUTPUTS 3D3V_AUX_S5
DCBATOUT
Right Side: 24 USB x 1 USB x 1(Upsell)
SPI
B
LDO
24
INPUTS
LPC Bus
19,20,21,22
Sigmatel STAC 9228
INPUTS HDMI (Upsell)
WWAN(Upsell)
USB 2.0
ACPI 1.1
Digital Mic Array
TPS51120
RJ45 CONN 28
27
ATA 66/100
VF
B
10/100 NIC
PCIE x 2 & USB 2.0 x 1
High Definition Audio
AZALIA
23
Marvell 88E8040
PCIE
SYSTEM DC/DC
16
PCIE x 1 & USB 2.0 x 1
ETHERNET (10/100/1000Mb)
MDC MODEM 31 (Option)
18
AZALIA
10 USB 2.0/1.1 ports
RJ11 CONN (Option)
OUTPUTS 1D05V_S0
ICH8-M
CardReader
INPUTS
17
DCBATOUT
o-
DMI I/F 100MHz
CRT
cc
Crestline-GM AGTL+ CPU I/F
DDRII Slot 1 15 533/667
D
TPS5117
Host BUS 533/667MHz DDRII 667 Channel A
VCC_CORE
SYSTEM DC/DC
5,6,7
RGB CRT
DDRII Slot 0 14 533/667
OUTPUTS
DCBATOUT
1D5V_S0
MAXIM CHARGER MAX8731A
34
INPUTS
OUTPUTS
AD+
DCBATOUT
BAT+
Touch Pad 37
A
Int. KB37
S/W CIR
Thermal & Fan G792 36
Flash ROM 1MB 35
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
DS2 System Block Diagram Size A3
Document Number
Rev
Spears-Intel
Date: Wednesday, September 12, 2007 5
4
3
2
Sheet 1
-1 1
of
47
5
4
3
2
TI TPS51120 3D3V/5V
CPU_CORE ISL6262A
D
VID0(I / 3.3V)
VID1
1D5V_S0 Input Signal
Output Signal VROK()
VRPWRGD
3V/5V_EN
51120_EN2
VID1(I / 3.3V)
VID2
51120_EN1
VID2(I / 3.3V)
VID3
VID3(I / 3.3V)
VID4
VID4(I / 3.3V)
VID5
VCC_CORE_PWR(O)
5V_S0
EN (I / 3.3V) DCBATOUT
VIN
5V(O)
5V_AUX_S5
3D3V(O)
VCC(I)
Input Signal
VCC(I)
-c PM_SLP_S4#
Input Power
5V_S5 A
VCC(O)
0D9V_DDR_VTT
5V_S5
DCBATOUT
VCC(O)
C
5V_S5
VCNTL
1D8V_S3 PM_SLP_S3#
VOUT(O)
EN
POK
G971
CHARGE_OFF
Input Signal
BAT+SENSE
Output Signal
MAX8731_LDO
LDO (O / 5.4V)
CLS (I / 3.3V)
AD+
BT_SCL
XTAL2/PB4 (O/5V) BATT (I / 3.3V)
B
XTAL1/PB3 (O/5V)
SCL (IO / 5V) SDA (IO / 5V)
Output Signal PGOUT(OD / 5V)
Input Power
CPUCORE_ON
Output Power 1D8V_PWR
1D8V_S3
CPUCORE_ON
Charger_MAX8731A
Output Power VCC(O)
1D5V_S0
VIN
Output Power
DCBATOUT
VCC (O)
Input Signal
AC_IN
AD+
BT+
VCC (O) PB0/MOSI/AIN0 Input Power DCIN (I)
VIN
DDR_VREF_S3
TPS51117_1D05V
VCC(I) PM_SLP_S3#
5V_S5 DCBATOUT
EN_PSV(I / 5V)
VCC
Output Signal
Input Signal
PGOUT(OD / 5V) Output Power
Input Power
1D05V_PWR
A
CPUCORE_ON
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
1D05V_S0 (15A)
Power Block Diagram Size A3
VIN
Document Number
Rev
DS2-Intel
Date: Wednesday, September 12, 2007 5
2D5V_S0
G9131
3D3V_S5 (5A)
BT_SDA
EN_PSV(I / 5V)
VCC
OUT
1D25V_S0
TPS51117_1D8V_S3
Output Power
VCC(I)
INPUT
5V_S5 (6A)
AD_IN
VCC(I)
VF
TI TPS51100 0.9V/DDR_VREF_S3
S3
(O)
VCC(I)
5V_AUX_S5
B
S5
Output Signal
(I)
AD_JK
DCBATOUT
3D3V_S0
Adapter
Input Power
PM_SLP_S3#
CPUCORE_ON
V5FILT(I / 5V)
RGND(I / Vcore)
AD_OFF
PM_SLP_S4#
Output Power
3D3V_AUX_S5
VSEN(I / Vcore)
Input Signal
POK
2D5V_S0
5V_AUX_S5
VCC(I)
3D3V_S0
EN
VIN
Input Power
Input Power DCBATOUT
D
VIN
PM_SLP_S3#
PGOUT2(OD / 3D3V)
o-
VSS_SENSE
FOR 5.0V
CPUCORE_ON(Pull High 3D3V)
1D5V_S0
VOUT(O)
1D8V_S3
APL5915 DCBATOUT
Voltage Sense
C
PGOUT1(OD / 5V)
VCNTL
VCC_CORE_S0(Imax=35A)
Input Signal
VCC_SENSE
FOR 3.3V
5V_S5
Output Power
VID5(I / 3.3V)
CPUCORE_ON
Output Signal
cc
VID Setting
VID0
1
4
3
2
-1 Sheet 1
2
of
47
A
B
C
D
E
INTEL ICH8-M STRAP PIN
20,22 +RTCVCC 5,6,7,8,10,11,12,20,22,34,43,47
Signal
Usage/When Sampled
HDA_SDOUT
XOR Chain Entrance/ PCIE Port Config 1 bit1, Rising Edge of PWROK
4
1D05V_S0
8,11,22,45 1D25V_S0
1D25V_S0
XOR Chain Entrance Strap
Comment Allows entrance to XOR Chain testing when TP3 pulled low at rising edge of PWROK.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers:offset 224h) Sets bit0 of RPC.PC(Config Registers:Offset 224h)
HDA_SYNC
PCIE Port Config 1 bit0, Rising Edge of PWROK.
GNT2#
PCIE Port Config 2 bit0, Rising Edge of PWROK.
Sets bit2 of RPC.PC(Config Registers:Offset 224h)
GPIO20
Reserved
Weak Internal PULL-DOWN.NOTE:This signal should not be pull HIGH.
ICH_RSVDtp3
AZ_DOUT_ICH
0 0 1 1
0 1 0 1
Description RSVD Enter XOR Chain Normal Operation(default) Set PCIE port cofig bit1
27 1D2V_LAN_S5
1D2V_LAN_S5
28 1D5V_NEW_S0
1D5V_NEW_S0
6,11,20,21,22,28,29,30,45
INTVRMEN
3
Boot BIOS Destination Selection. Rising Edge of PWROK. Integrated VccSus1_05 VccSus1_5 and VccCL1_5 VRM Enable/Disable.Always sampled.
Sampled low:Top-Block Swap mode(inverts A16 for all A16 swap override strap cycles targeting FWH BIOS space). PCI_GNT#3 low = A16 swap override enable Note: Software will not be able to clear the high = default Top-Swap bit until the system is rebooted without GNT3# being pulled down. BOOT BIOS Strap PCI_GNT#0 SPI_CS#1 BOOT BIOS Location Controllable via Boot BIOS Destination bit 0 1 SPI (Config Registers:Offset 3410h:bit 11:10). 1 0 PCI GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.
1
Enables integrated VccSus1_05,VccSus1_5 and VccCL1_5 VRM when sampled high
Enables integrated when sampled high
PCIE LAN REVERSAL.Rising Edge of PWROK.
This signal has weak internal pull-up. set bit27 of MPC.LR(Device28:Function0:Offset D8)
SPKR
No Reboot. Rising Edge of PWROK.
If sampled high, the system is strapped to the "No Reboot" mode(ICH8M will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit.(Offset:3410h:bit5)
TP3
XOR Chain Entrance. Rising Edge of PWROK.
This signal should not be pull low unless using XOR Chain testing.
LPC(Default)
LAN100_SLP
High=Enable
3D3V_S0
3D3V_S5
3D3V_S5 5V_AUX_S5
16,17,18,22,24,33,35,36,37,41,45,46,47
5V_S0
5V_S0
5V_S5
5V_S5
Low=Disable
38,39,47 AD+ 18,39,40,41,42,43,44,46,47
Low=Disable
AD+
DCBATOUT
DCBATOUT
14,15,45,47 DDR_VREF_S0
DDR_VREF_S0
8,14,15,45 DDR_VREF_S3
DDR_VREF_S3
18 +LCDVDD
DEFAULE HIGH
3
+LCDVDD
6,7,42 VCC_CORE_S0
VCC_CORE_S0
No Reboot Strap SPKR LOW = Defaule High=No Reboot
Internal Pull-Up.If sampled low,the Flash Descriptor Flash Descriptor Security Security will be overidden.if high,the Security Override Strap measures defined in the Flash Descriptor will be in 8.2K PULL HIGH Rising Edge of PWROK. effect. This should only be used in manufacturing environments
INTEL ICH8-M INTEGRATED PULL-UPS and PULL-DOWNS
-c
GPIO33/ HDA_DOCK_EN#
VccLAN1_05,VccCL1_05 VRM
3D3V_LAN_S5
3D3V_S0
22,24,29,30,31,35,38,40,43,44,45,46,47
integrated VccSus1_05,VccSus1_5,VccCL1_5
SM_INTVRMEN High=Enable
3D3V_AUX_S5
18,39,40,47 5V_AUX_S5
o-
Integrated VccLAN1_05 VccCL1_05 VRM enable /Disable. Always sampled.
SATALED#
SIGNAL
Resistor Type/Value
HDA_BIT_CLK
PULL-DOWN 20K
HDA_RST#
NONE
HDA_SDIN[3:0]
PULL-DOWN 20K
HDA_SDOUT
PULL-DOWN 20K
HDA_SYNC
PULL-DOWN 20K
GNT[3:0]
PULL-UP 20K
GPIO[20]
PULL-DOWN 20K
LDA[3:0]#/FHW[3:0]#
PULL-UP 20K
LAN_RXD[2:0]
PULL-UP 20K
LDRQ[0]
PULL-UP 20K
LDRQ[1]/GPIO23
PULL-UP 20K
PME#
PULL-UP 20K
CFG 20
Normal Operation ★ Reserved Lane Only PCIE or SDVO PCIE and SDVO are is operation ★ operation simultaneous
PWRBTN#
PULL-UP 20K
SATALED#
PULL-UP 20K
SDVO_CTRL_DATA
NO SDVO Card Present ★
SPI_CS1#
PULL-UP 20K
SPI_CLK
PULL-UP 20K
XOR/ALL-Z
SPI_MOSI
PULL-UP 20K
Reserved XOR Mode Enabled All Z Mode Enabled Normal Operation
SPI_MISO
PULL-UP 20K
Wistron Corporation
TACH_[3:0]
PULL-UP 20K
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
SPKR
PULL-DOWN 20K
TP[3]
PULL-UP 20K
USB[9:0][P,N]
PULL-DOWN 15K
CL_RST#
TBD
VF
2
INTEL CRESTLINE STRAP PIN CFG Strap CFG 5 CFG 8
Low Power PCI Express
CFG 9
PCI Express Graphics Lane Reversal
CFG 16
FSB Dynamic ODT
CFG 19
DMI Lane Reserved Concurrent SDVO/PCIE
LOW 0 DMI X 2 Normal★ Lane Reversal
Disabled
SDVO Present
1
1
2D5V_LAN_S5
3D3V_AUX_S5
19,21,22,27,28,31,35,38,40,46,47
integrated VccLan1_05VccCL1_05 LAN100_SLP
1D8V_S3
27,28 3D3V_LAN_S5 4,8,10,11,14,15,16,17,18,19,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,40,41,43,45,46,47
4
1D5V_S0
1D8V_S3
27,28 2D5V_LAN_S5
cc
GNT0# SPI_CS1#
Top-Block Swap Override. Rising Edge of PWROK.
1D5V_S0
8,11,12,14,15,44,45,46,47
20,31,34,35,36,38,39,40,47
GNT3#
+RTCVCC
1D05V_S0
CFG 12 CFG 13 LL(00) LH(01) HL(10) HH(11)
HIGH 1
DMI X 4 ★
Low Power mode
Normal Mode(Lanes★ number in order)
Enabled ★
SDVO Card Present
2
1
Title
Table of Content Size A3
Document Number
Date: Wednesday, September 12, 2007
Rev
DS2-Intel Sheet
3
-1 of
47
3D3V_S0_CK505
4
3
2 3D3V_S0_CK505
1
1
2
CLK_XTAL_OUT
1
D
C211 SC15P50V2JN-2-GP
VDDREF VDD48 VDDPCI VDDSRC VDDCPU VDDPLL3
Output
1
ITP_EN
1 2
4 SRN22-3-GP 3
CLK_PCIE_MINI3 30 CLK_PCIE_MINI3# 30
SRCT7/CR#_F SRCC7/CR#_E
51 50
CLK_PCIE_LAN1 CLK_PCIE_LAN1#
RN28
1 2
4 SRN0J-6-GP 3
SRCT6 SRCC6
48 47
CLK_PCIE_MINI1_1 CLK_PCIE_MINI1_1#
RN29
1 2
4 SRN22-3-GP 3
SRCT10 SRCC10
41 42
CLK_PCIE_NEW1 CLK_PCIE_NEW1#
2 1
3 4
SRCT9 SRCC9
CLK_PCIE_MINI2_1 CLK_PCIE_MINI2_1#
SRCT4 SRCC4
34 35
CLK_MCH_3GPLL1 CLK_MCH_3GPLL1#
SRCT3/CR#_C SRCC3/CR#_D
31 32
CLK_PCIE_ICH1 CLK_PCIE_ICH1#
SRCT2/SATAT SRCC2/SATAC
28 29
CLK_PCIE_SATA1 CLK_PCIE_SATA1#
27MHZ_NONSS/SRCT1/SE1 27MHZ_SS/SRCC1/SE2
24 25
MCH_SSCDREFCLK1 MCH_SSCDREFCLK1#
SRCT0/DOTT_96 SRCC0/DOTC_96
20 21
GND
RN30
RN31
3 4
2 1
3 4
2 1
3 4
2 1
3 4
2 1 RN34 CLK_MCH_DREFCLK1 2 CLK_MCH_DREFCLK1# 1 RN33
3 4
RN36
RN35
SRC8 CPU_ITP
Overclocking of CPU and SRC allowed
1
Overclocking of CPU and SRC not allowed
A
3 4
6 CPU_BSEL2 6 CPU_BSEL1 6 CPU_BSEL0
R360 R353 R386
1
2
1
2
1
2
CLK_PCIE_MINI2 30 CLK_PCIE_MINI2# 30
SRN22-3-GP SRN0J-6-GP
CLK_MCH_3GPLL 8 CLK_MCH_3GPLL# 8
SRN0J-6-GP
CLK_PCIE_ICH 21 CLK_PCIE_ICH# 21
MCH_SSCDREFCLK 8 MCH_SSCDREFCLK# 8
SRN0J-6-GP
CLK_MCH_DREFCLK 8 CLK_MCH_DREFCLK# 8
SRN0J-6-GP
B
1 1 0 1
100M 133M 200M 166M
1
1 R378 10KR2J-3-GP
CPU
2
FS_A
CLK_MCH_DREFCLK#
EC119 SC22P50V2JN-4GP
EC165
DY
FSC
EC166
DY
27_SEL strap 0:For 965GM, 1:For 965PM
2K2R2J-2-GP FSB
27_SEL
PIN 20
PIN 21
0 1
DOT96T SRCT0
DOT96C SRCC0
PIN 24
PIN 25
0R0402-PAD FSA 2K2R2J-2-GP
R385 1
2 0R0402-PAD
MCH_CLKSEL0 8
R352 1
2 0R0402-PAD
MCH_CLKSEL1 8
R359 1
2 0R0402-PAD
MCH_CLKSEL2 8
SRCT1/LCDT_100 27M_NSS
SRCT1/LCDT_100 27M_SS
965GM 965PM
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
SA:0430
Design Note: 1. All of Input pin didn't have internal pull up resistor. 2. Clock Request (CR) function are enable by registers. 3. CY28548 integrated serial resistor of differential clock, so put 0 ohm serial resistor in the schematic.
C
CLK_PCIE_SATA 20 CLK_PCIE_SATA# 20
SRN0J-6-GP
NEWCARD_CLKREQ#
2
0 0 1 1
CLK_PCIE_NEW 28 CLK_PCIE_NEW# 28 3D3V_S0 10KR2J-3-GP NEWCARD_CLKREQ# 28 2 10KR2J-3-GP
CLK_MCH_DREFCLK
1
FS_B
2
SC:08/11 Add EC165,EC166 on CLK_MCH_DREFCLK -/+ pair .
Output
1 0 0 0
SRN0J-6-GP 1 R371 R375 1
ICS9LPRS365BKLFT-GP
27_SEL
FS_C
CLK_PCIE_MINI1 29 CLK_PCIE_MINI1# 29
DY 2 1
RN32
CLK_PCIE_LAN 27 CLK_PCIE_LAN# 27
1
Please place R10 near U1 pin5
RN27
40 39
65
NC#55
GND GNDSRC GNDSRC GNDSRC GNDCPU GND
55
-c
FSLB/TEST_MODE REF0/FSLC/TEST_SEL
CLK_MCH_BCLK 8 CLK_MCH_BCLK# 8
CLK_PCIE_MINI3_1 CLK_PCIE_MINI3_1#
37 38
PCI0/CR#_A PCI1/CR#_B PCI2/TME PCI3 PCI4/27_SELECT PCI_F5/ITP_EN
64 5
1 2
4 SRN0J-6-GP 3
SRCT11/CR#_H SRCC11/CR#_G
CK_PWRGD/PD#
22 30 36 49 59 26
1
C526
33R2J-2-GP
0
2
R380 10KR2J-3-GP
0 1
2
FSB FSC
VF PCI2_TME
ITP_EN
2 33R2J-2-GP 2 33R2J-2-GP 2 33R2J-2-GP
8 10 PCI2_TME 11 PCLK_PCM_R 12 27_SEL 13 ITP_EN 14
CLK_CPU_BCLK 5 CLK_CPU_BCLK# 5
RN26
Main source : 71.09365.A03 ICS9LPRS365CKLFT 2nd source:71.00875.A03 RTM875N-606-LF
R373 10KR2J-3-GP
2
DY
CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8
54 53
SCLK SDATA
SC4D7P50V2CN-1GP
2
C552
1 SC4D7P50V2CN-1GP
2 SC4D7P50V2CN-1GP
2
C545
1
1 PCI2_TME
1
B
C540
2 SC4D7P50V2CN-1GP
1 2
R374 10KR2J-3-GP
58 57
o-
R370 1 R379 1 R382 1
R355
3D3V_S0_CK505
PCI_STOP# CPU_STOP#
GND48 GNDPCI GNDREF
21 CLKSATAREQ# 8 CLKREQ#_B
1
45 44
63
21 CK_PWRGD
21 CLK_14M_ICH
USB_48MHZ/FSLA
7 6
14,15,21 ICH_SMBCLK 14,15,21 ICH_SMBDATA
25 PCLK_PCM 34 PCLK_KBC 19 CLK_PCI_ICH
17
4 SRN0J-6-GP 3
2
33R2J-2-GP
21 H_STP_PCI# 21 H_STP_CPU#
CPUT1_F CPUC1_F
CLK_MCH_BCLK1 CLK_MCH_BCLK1#
X1 X2
1 2
SC47P50V2JN-3GP
R383
FSA
RN25
SC47P50V2JN-3GP
2
CLK_CPU_BCLK1 CLK_CPU_BCLK1#
cc
1
21 CLK_48M_ICH
C
3 2
2
18 15 1
1 2
1 2
1
C550 SCD1U16V2ZY-2GP
2
1
C548 SCD1U16V2ZY-2GP
2
1
C533 SCD1U16V2ZY-2GP
2
C524 SCD1U16V2ZY-2GP
2
C525 SCD1U16V2ZY-2GP
SC10U6D3V5KX-1GP
SC1U10V3KX-3GP
DY
2
1
1
C227
1
61 60
CPUT0 CPUC0
2
C566 SC4D7P50V2CN-1GP
2 1 R128 0R0603-PAD
CLK_XTAL_IN CLK_XTAL_OUT
U24
19 27 43 52 33 56
4 16 9 46 62 23
C214 SC15P50V2JN-2-GP
2
1
X-14D31818M-37GP
3D3V_S0_CK505_IO
C231
3D3V_S0_CK505_IO
X3 CLK_XTAL_IN
2
2
1
3D3V_S0
1
C537 SCD1U16V2ZY-2GP
2
1
C529 SCD1U16V2ZY-2GP
2
1
C523 SCD1U16V2ZY-2GP
2
C549 SCD1U16V2ZY-2GP
2
C527 SCD1U16V2ZY-2GP
2
1
1
C219 SC10U6D3V5KX-1GP
D
C222 SC1U10V3KX-3GP
2
1
2 1 R127 0R0603-PAD
VDD96_IO VDDPLL3_IO VDDSRC_IO VDDSRC_IO VDDSRC_IO VDDCPU_IO
5
3D3V_S0
Title
Clock generator ICS9LPRS365 Size A3
Document Number
Rev
DS2-Intel
Date: Wednesday, September 12, 2007
Sheet
-1 4
of
47
5
4
3
2
1
8 H_A#[3..35] U45A 1 OF 4
B
H_STPCLK# H_INTR H_NMI H_SMI#
TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28
TP14 TP16 TP6 TP12 TP4 TP10 TP5 TP20 TP11 TP18
CPU_RSVD01 CPU_RSVD02 CPU_RSVD03 CPU_RSVD04 CPU_RSVD05 CPU_RSVD06 CPU_RSVD07 CPU_RSVD08 CPU_RSVD09 CPU_RSVD10
A20M# FERR# IGNNE#
D5 C6 B4 A3
STPCLK# LINT0 LINT1 SMI#
M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 B1
RSVD#M4 RSVD#N5 RSVD#T2 RSVD#V3 RSVD#B2 RSVD#C3 RSVD#D2 RSVD#D22 RSVD#D3 RSVD#F6
H_IERR# H_INIT#
LOCK#
H4
H_LOCK#
RESET# RS0# RS1# RS2# TRDY#
C1 F3 F4 G3 G2
H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY#
HIT# HITM#
G6 E4
H_HIT# H_HITM#
BPM0# BPM1# BPM2# BPM3# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
PROCHOT# THRMDA THRMDC THERMTRIP#
HCLK
BCLK0 BCLK1
R235 56R2J-4-GP
H_BR0# 8 H_INIT# 20 H_LOCK# 8 H_RESET# 8 H_RS#0 8 H_RS#1 8 H_RS#2 8 H_TRDY# 8
XDP_BPM#0 AD4 XDP_BPM#1 AD3 XDP_BPM#2 AD1 XDP_BPM#3 AC4 XDP_BPM#4 AC2 XDP_BPM#5 AC1 XDP_TCK AC5 XDP_TDI AA6 XDP_TDO AB3 XDP_TMS AB5 XDP_TRST# AB6 C20 XDP_DBRESET#
D21 A24 B25
CPU_PROCHOT H_THERMDA H_THERMDC
C7
H_THERMTRIP#
A22 A21
CLK_CPU_BCLK CLK_CPU_BCLK#
cc
H_BR0#
1
F1 D20 B3
D
H_DEFER# 8 H_DRDY# 8 H_DBSY# 8
2
CONTROL
H_DEFER# H_DRDY# H_DBSY#
H_HIT# 8 H_HITM# 8 TP15 TP13 TP3 TP9 TP7 TP2 TP8 TP19
1 R236
C
o-
20 20 20 20
A6 A5 C4
H5 F21 E1
1D05V_S0
H_ADS# 8 H_BNR# 8 H_BPRI# 8
THERMAL
ICH
20 H_A20M# 20 H_FERR# 20 H_IGNNE#
H_A20M# H_FERR# H_IGNNE#
A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADSTB1#
BR0# IERR# INIT#
H_ADS# H_BNR# H_BPRI#
2 56R2J-4-GP
1D05V_S0 H_THERMDA 36 H_THERMDC 36
H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil
H_THERMTRIP# 8,20,34,46
CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4
-c
8 H_ADSTB#1
Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1
ADDR GROUP 1
C
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1
REQ0# REQ1# REQ2# REQ3# REQ4#
DEFER# DRDY# DBSY#
H1 E2 G5
1D05V_S0
XDP_TDI R7 XDP_TMS
layout note:Zo =55 ohm , 0.5" MAX for GTLREF
VF
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
K3 H2 K2 J3 L1
ADS# BNR# BPRI#
XDP/ITP SIGNALS
8 8 8 8 8
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB0#
RESERVED
8 H_ADSTB#0
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1
ADDR GROUP 0
D
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0
R5
1
2
1
2
150R2F-1-GP 39R2F-GP
B
KEY_NC
SKT-CPU478P-GP
XDP_TRST# R6 XDP_TCK R4 CPU_PROCHOT R237
2
1
0R2J-2-GP
1
2
1
2
649R2F-GP 27D4R2F-L1-GP
CPU_PROCHOT# 41
DY
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Meron(1/3)-AGTL+/XDP Size A3
Document Number
Rev
-1
DS2-Intel
Date: Wednesday, September 12, 2007
Sheet
5
of
47
5
4
3
2
8 H_D#[0..63]
1
VCC_CORE_S0
VCC_CORE_S0
U45B 2 OF 4
BSEL0 BSEL1 BSEL2
SKT-CPU478P-GP
PLACE C25 close to the TEST4 PIN, make sure TEST3,TEST4,TEST5 trace routing is reference to GND and away other noisy signals
CPU_BSEL
CPU_BSEL2
CPU_BSEL1
0
1
1
200
0
1
0
2
1D05V_S0
R239 1KR2F-3-GP
H_CPUSLP# PSI#
2 2 27D4R2F-L1-GP 2 54D9R2F-L1-GP 2 27D4R2F-L1-GP 54D9R2F-L1-GP
H_DPRSTP# 8,20,41 H_DPSLP# 20 H_DPWR# 8
H_PWRGOOD 20,46
H_CPUSLP# 8 PSI# 41
Resistor Placed within 0.5" of CPU pin. Trace should be at least 25 mils away from any other toggling signal . COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils .
1 1
1
B26 C26
VID0 VID1 VID2 VID3 VID4 VID5 VID6
AD6 AF5 AE5 AF4 AE3 AF3 AE2
CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6
VCCSENSE
AF7
VCC_SENSE
VSSSENSE
AE7
VSS_SENSE
C20 SC10U6D3V5KX-1GP
1D5V_S0
CPU_VID[0..6]
41
C394
VCC_SENSE 41 VSS_SENSE 41
layout note: place C3 near PIN B26 C397 SC10U6D3V5KX-1GP
B
Length match within 25 mils . The trace width/space/other is 20/7/25 .
SKT-CPU478P-GP
VCC_SENSE
1 R201
2
VSS_SENSE
1 R199
2
Close to CPU pin AD26 Z0=55 ohm with in 500mils .
VCC_CORE_S0
100R2F-L1-GP-U 100R2F-L1-GP-U
Close to CPU pin within 500mils
A
V_CPU_GTLREF
Wistron Corporation
R238
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
2KR2F-3-GP
2
SCD1U16V2KX-3GP
2
VCCA VCCA
1
H_DPRSTP# H_DPSLP# H_DPWR#
1 1 1 1
C
VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP
2
E5 B5 D24 D6 D7 AE6
R233 R234 R3 R2
1D05V_S0
G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
C635
Place C635 near R238 and R239
DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#
CPU_BSEL0
166
A
COMP0 COMP1 COMP2 COMP3
VF
B
R26 U26 AA1 Y1
D
1
4 CPU_BSEL0 4 CPU_BSEL1 4 CPU_BSEL2
B22 B23 C21
COMP0 COMP1 COMP2 COMP3
H_DSTBN#3 8 H_DSTBP#3 8 H_DINV#3 8
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20
2
CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
SCD01U16V2KX-3GP
TPAD28 TP85 TPAD28 TP87
MISC
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
cc
GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6
D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3# DINV3#
H_DSTBN#2 8 H_DSTBP#2 8 H_DINV#2 8
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
1
2 C395
DY
AD26 C23 D25 C24 AF26 AF1 A26
TEST1 TEST2 TEST3 TEST4 TEST5 TEST6
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2
2
SCD1U16V2KX-3GP 1
D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1#
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
o-
V_CPU_GTLREF TPAD28 TP21 TPAD28 TP23 TPAD28 TP22
N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24
D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# DSTBN2# DSTBP2# DINV2#
-c
8 H_DSTBN#1 8 H_DSTBP#1 8 H_DINV#1
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1
DATA GRP1
C
D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0#
DATA GRP3
8 H_DSTBN#0 8 H_DSTBP#0 8 H_DINV#0
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25
DATA GRP0
D
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0
DATA GRP2
U45C 3 OF 4
Title
Meron(2/3)-AGTL+/PWR Size A3
Document Number
Rev
-1
DS2-Intel
Date: Wednesday, September 12, 2007
Sheet
6
of
47
5
4
3
2
1
1 2
1 2
1
C349 SC10U6D3V5KX-1GP
2
1
C358 SC10U6D3V5KX-1GP
2
1
C361 SC10U6D3V5KX-1GP
2
1
C371 SC10U6D3V5KX-1GP
2
1
C374 SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
2
C376
D
1
C23
cc
SC10U6D3V5KX-1GP
2
1
C25 SC10U6D3V5KX-1GP
2
1
C24
2
1
C35
SC10U6D3V5KX-1GP
2
1
C17
2
1
C36
SC10U6D3V5KX-1GP
2
1
C33
SC10U6D3V5KX-1GP
2
C34
SC10U6D3V5KX-1GP
Place these capacitors on L1 (North side ,Secondary Layer)
2
1
VCC_CORE_S0
1
C633
C634
C
Mid Frequencd Decoupling
-c
o-
2
2
1
VCC_CORE_S0
SC10U6D3V5KX-1GP
B
2 C45 SCD1U16V2KX-3GP
1
2 C39 SCD1U16V2KX-3GP
1
2 C10 SCD1U16V2KX-3GP
1
2
C12 SCD1U16V2KX-3GP
1
2
C16 SCD1U16V2KX-3GP
1
2
VF
1D05V_S0
1
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
C377
SC10U6D3V5KX-1GP
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
SC10U6D3V5KX-1GP
B
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
C382
SC10U6D3V5KX-1GP
C
A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3
Place these capacitors on L1 (North side ,Secondary Layer)
SC10U6D3V5KX-1GP
D
4 OF 4
SC10U6D3V5KX-1GP
U45D
2
1
VCC_CORE_S0
C37 SCD1U16V2KX-3GP
Place these inside socket cavity on L1 (North side Secondary)
SKT-CPU478P-GP
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Meron(3/3)-GND&Bypass Size A3
Document Number
Rev
-1
DS2-Intel
Date: Wednesday, September 12, 2007
Sheet
7
of
47
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
M14 E13 A11 H13 B12
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_RS#0 H_RS#1 H_RS#2
E12 D7 D8
H_RS#0 H_RS#1 H_RS#2
NB:71.GM965.A0U CRESTLINE-GP-U-NF
2 1 2
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
CFG[17:3] have internal pull up CFG[19:18] have internal pull down
5 5 5 5 5
CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13
TP24
CFG16
TP39 TP36 TP37
CFG18 CFG19 CFG20
21 PM_BMBUSY# 6,20,41 H_DPRSTP# 14 PM_EXTTS#0 15 PM_EXTTS#1
Spec: H_SWING=0.3125 X VTT +/- 1%
2 0R2J-2-GP
1
2
PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PM_POK_R PLT_RST_R# H_THERMTRIP# DPRSLPVR
PM_POK_R
0R2J-2-GP
R255
R52
PLT_RST_R#
H_SWNG
R254
1
2
PLT_RST1# 19,23,24,28,29,30,34
100R2J-2-GP
2
1
Layout Note : Place C32 within 100 mils of NB
1
R87
BE29 DDR_CKE0_DIMMA AY32 DDR_CKE1_DIMMA BD39 DDR_CKE2_DIMMB BG37 DDR_CKE3_DIMMB
DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB
14 14 15 15
SM_CS#0 SM_CS#1 SM_CS#2 SM_CS#3
BG20 DDR_CS0_DIMMA# BK16 DDR_CS1_DIMMA# BG16 DDR_CS2_DIMMB# BE13 DDR_CS3_DIMMB#
DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB#
14 14 15 15
SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3
BH18 BJ15 BJ14 BE16
M_ODT0 M_ODT1 M_ODT2 M_ODT3
SM_RCOMP_VOH SM_RCOMP_VOL
BK31 BL31
SM_RCOMP_VOH SM_RCOMP_VOL
SM_RCOMP SM_RCOMP#
BL15 BK14
SM_RCOMP SM_RCOMP#
SM_VREF#AR49 SM_VREF#AW4
AR49 AW4
P27 N27 N24 C21 C23 F23 N23 G23 J20 C20 R24 L23 J23 E23 E20 K23 M20 M24 L32 N33 L35
G41 L39 L36 J36 AW49 AV20 N20 G36
BJ51 BK51 BK50 BL50 BL49 BL3 BL2 BK1 BJ1 E1 A5 C51 B50 A50 A49 BK2
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20
PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#0 PM_EXT_TS#1 PWROK RSTIN# THERMTRIP# DPRSLPVR
3D3V_S0
Layout Note : Place C33 near pin B3 of NB
RN18
10 TV_DCONSEL0 10 TV_DCONSEL1
M_ODT0 M_ODT1 M_ODT2 M_ODT3
NC#BJ51 NC#BK51 NC#BK50 NC#BL50 NC#BL49 NC#BL3 NC#BL2 NC#BK1 NC#BJ1 NC#E1 NC#A5 NC#C51 NC#B50 NC#A50 NC#A49 NC#BK2
PM_EXTTS#0 PM_EXTTS#1 TV_DCONSEL0 TV_DCONSEL1
1 2 3 4
8 7 6 5
CLK
B42 C42 H48 H47
14 14 15 15
D
14 14 15 15 1D8V_S3
1 R264 1 R261
2 2 20R2F-GP 20R2F-GP DDR_VREF_S3
DDR_VREF_S3
CLK_MCH_DREFCLK CLK_MCH_DREFCLK# MCH_SSCDREFCLK MCH_SSCDREFCLK#
PEG_CLK PEG_CLK#
K44 CLK_MCH_3GPLL K45 CLK_MCH_3GPLL#
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
AN47 AJ38 AN42 AN46
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
AM47 AJ39 AN41 AN45
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
AJ46 AJ41 AM40 AM44
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
AJ47 AJ42 AM39 AM43
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
DFGT_VID0 DFGT_VID1 DFGT_VID2 DFGT_VID3 DFGT_VR_EN
CLK_MCH_DREFCLK 4 CLK_MCH_DREFCLK# 4 MCH_SSCDREFCLK 4 MCH_SSCDREFCLK# 4 CLK_MCH_3GPLL 4 CLK_MCH_3GPLL# 4
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
21 21 21 21
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
21 21 21 21
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
21 21 21 21
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
21 21 21 21
GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VR_EN
E35 A39 C38 B39 E36
CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF
AM49 AK50 AT43 AN49 AM50
PM_POK_R
H35 K36 G39 G40
SDVO_CTRLCLK 23 SDVO_CTRLDATA 23 CLKREQ#_B 4 MCH_ICH_SYNC# MCH_ICH_SYNC#
C
TP38 TP94 TP92 TP93 TP40
B
1D25V_S0
R84 1KR2F-3-GP
CL_CLK0 21 CL_DATA0 21 CL_RST# 21
CL_VREF
R85 392R2F-GP
C182 SDVO_CTRL_CLK SDVO_CTRL_DATA CLKREQ# ICH_SYNC#
C415 SCD1U16V2ZY-2GP
2
1
1 2
R250 24D9R2F-L-GP 100R2F-L1-GP-U
A
C426
SCD1U16V2ZY-2GP
2
2
R262 2KR2F-3-GP
H_RCOMP
21,41 VGATE_PWRGD
DY
1
221R2F-2-GP 2 1
1 1
2
R263 1KR2F-3-GP
H_VREF
R86
21,36 PM_PWROK
1D05V_S0
SM_CKE0 SM_CKE1 SM_CKE3 SM_CKE4
DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK#
RSVD#B44 RSVD#C44 RSVD#A35 RSVD#B37 RSVD#B36 RSVD#B34 RSVD#C34
NC
VF
5,20,34,46 H_THERMTRIP# 21,41 DPRSLPVR
1D05V_S0
MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2
TP33 TP29 TP32 TP26 TP27 TP31 TP34 TP25 TP35
H_RS#0 5 H_RS#1 5 H_RS#2 5
layout note : Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces
Layout Note : H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20
M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3
cc
2
2 1
C442 SCD01U25V2KX-3GP
1
1 6 6 6 6
AW30 M_CLK_DDR#0 BA23 M_CLK_DDR#1 AW25 M_CLK_DDR#2 AW23 M_CLK_DDR#3
DDR MUXING
1
1
C437 SCD01U25V2KX-3GP
2
1 2
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
RSVD#BH39 RSVD#AW20 RSVD#BK20
14 14 15 15
SM_CK#0 SM_CK#1 SM_CK#3 SM_CK#4
DMI
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
4 MCH_CLKSEL0 4 MCH_CLKSEL1 4 MCH_CLKSEL2
6 6 6 6
BH39 AW20 BK20 B44 C44 A35 B37 B36 B34 C34
6 6 6 6
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
RSVD#H10 RSVD#B51 RSVD#BJ20 RSVD#BK22 RSVD#BF19 RSVD#BH20 RSVD#BK18 RSVD#BJ18 RSVD#BF23 RSVD#BG23 RSVD#BC23 RSVD#BD24
PM
B
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
L7 K2 AC2 AJ10
H_ADS# 5 H_ADSTB#0 5 H_ADSTB#1 5 H_BNR# 5 H_BPRI# 5 H_BR0# 5 H_DEFER# 5 H_DBSY# 5 CLK_MCH_BCLK 4 CLK_MCH_BCLK# 4 H_DPWR# 6 H_DRDY# 5 H_HIT# 5 H_HITM# 5 H_LOCK# 5 H_TRDY# 5
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
H10 B51 BJ20 BK22 BF19 BH20 BK18 BJ18 BF23 BG23 BC23 BD24
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3
2
H_AVREF H_DVREF
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
C444 SC2D2U6D3V3KX-GP
R273 1KR2F-3-GP
AV29 BB23 BA25 AV23
1
B9 A9
H_VREF
M7 K3 AD2 AH11
SM_CK0 SM_CK1 SM_CK3 SM_CK4
1
H_CPURST# H_CPUSLP#
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
RSVD#P36 RSVD#P37 RSVD#R35 RSVD#N35 RSVD#AR12 RSVD#AR13 RSVD#AM12 RSVD#AN13 RSVD#J12 RSVD#AR37 RSVD#AM36 RSVD#AL36 RSVD#AM37 RSVD#D20
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3
TEST1 TEST2
A37 TEST1_GMCH R32 TEST2_GMCH1 2 R65 20KR2J-L2-GP
21
1 R64 2 0R0402-PAD
2
B6 E5
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
P36 P37 R35 N35 AR12 AR13 AM12 AN13 J12 AR37 AM36 AL36 AM37 D20
R268 1KR2F-3-GP
R272 3K01R2F-3-GP
SM_RCOMP_VOL
FOR Calero: 80.6 ohm Crestline: 20 ohm
U50B 2 OF 10
1D8V_S3
1
H_RESET# H_CPUSLP#
K5 L2 AD13 AE13
SM_RCOMP_VOH
1
SCD1U16V2KX-3GP 2
H_SCOMP H_SCOMP#
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
C435 SC2D2U6D3V3KX-GP
2
GRAPHICS VID
H_SWING H_RCOMP
W1 W2
H_ADS# G12 H_ADSTB#0 H17 H_ADSTB#1 G20 H_BNR# C8 H_BPRI# E8 H_BR0# F12 H_DEFER# D6 H_DBSY# C10 CLK_MCH_BCLK AM5 CLK_MCH_BCLK# AM7 H_DPWR# H8 H_DRDY# K7 H_HIT# E4 H_HITM# C6 H_LOCK# G10 H_TRDY# B7
3
H_A#[3..35] 5
ME
B3 C2
H_SCOMP H_SCOMP#
4
MISC
5 H_RESET# 6 H_CPUSLP#
H_SWNG H_RCOMP
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
o-
1
54D9R2F-L1-GP
2
R248 R249
H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#
J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19
CFG
54D9R2F-L1-GP 2
1
1D05V_S0
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
-c
C
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
HOST
D
E2 G2 G7 M6 H7 H3 G4 F3 N8 H2 M10 N12 N9 H5 P13 K9 M2 W10 Y8 V4 M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4 W3 N1 AD12 AE3 AD9 AC9 AC7 AC14 AD11 AC11 AB2 AD7 AB1 Y3 AC6 AE2 AC5 AG3 AJ9 AH8 AJ14 AE9 AE11 AH12 AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2 AH13
RSVD
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
2
U50A 1 OF 10
5
6 H_D#[0..63]
CRESTLINE-GP-U-NF
NB:71.GM965.A0U
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
SRN10KJ-6-GP CLKREQ#_B R69
1
2 10KR2J-3-GP
Title
CRESTLINE(1/6)-AGTL+/DMI/DDR2
Size Document Number Custom
Date: Wednesday, September 12, 2007
Sheet
Rev
-1
DS2-Intel 8
of
47
5
4
DDR_A_D[0..63]
14
DDR_A_BS[0..2]
14
DDR_A_DM[0..7]
D
3
2
1
DDR_B_D[0..63]
15
DDR_B_BS[0..2]
15
DDR_B_DM[0..7]
15
14
DDR_A_DQS[0..7]
DDR_B_DQS[0..7] DDR_A_DQS#[0..7]
BL17
DDR_A_CAS#
SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7
AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7 SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7
AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7
SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14
BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16 BJ29
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14
SA_RAS# SA_RCVEN#
BE18 AY20
DDR_A_RAS# SA_RCVEN#
SA_WE#
BA19
CRESTLINE-GP-U-NF
NB:71.GM965.A0U
A
DDR_A_CAS# 14
DDR_A_WE#
AP49 AR51 AW50 AW51 AN51 AN50 AV50 AV49 BA50 BB50 BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43 BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40 BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12 BJ10 BL9 BK5 BL5 BK9 BK10 BJ8 BJ6 BF4 BH5 BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2
SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63
DDR_A_RAS# 14
TP30
DDR_A_WE# 14
DDR SYSTEM MEMORY B
SA_CAS#
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
SB_BS0 SB_BS1 SB_BS2
AY17 BG18 BG36
DDR_B_BS0 DDR_B_BS1 DDR_B_BS2
SB_CAS#
BE17
DDR_B_CAS#
cc
DDR_A_BS0 DDR_A_BS1 DDR_A_BS2
o-
BB19 BK19 BF29
-c
B
15
U50E 5 OF 10
SA_BS0 SA_BS1 SA_BS2
VF
C
SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63
DDR SYSTEM MEMORRY A
U50D 4 OF 10
AR43 AW44 BA45 AY46 AR41 AR45 AT42 AW47 BB45 BF48 BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41 AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11 BE10 BD10 BD8 AY9 BG10 AW9 BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8 AN10 AT9 AN9 AM9 AN11
15
14 DDR_B_MA[0..14]
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
15
14 DDR_B_DQS#[0..7]
DDR_A_MA[0..14]
D
14
SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7
AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7 SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7
AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3
DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7
SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14
BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13 BE24
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14
SB_RAS# SB_RCVEN#
AV16 AY18
DDR_B_RAS# SB_RCVEN#
SB_WE#
BC17
DDR_B_WE#
DDR_B_CAS# 15
C
B
DDR_B_RAS# 15 TP28 DDR_B_WE# 15
CRESTLINE-GP-U-NF
NB:71.GM965.A0U
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
CRESTLINE(2/6)-DDR2 A/B CH
Size A3
Document Number
Rev
-1
DS2-Intel
Date: Wednesday, September 12, 2007
Sheet
9
of
47
4
R74
18 VGA_TXAOUT018 VGA_TXAOUT118 VGA_TXAOUT2-
G51 E51 F49 C48
LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3
18 VGA_TXAOUT0+ 18 VGA_TXAOUT1+ 18 VGA_TXAOUT2+
G50 E50 F48 D47
LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3
18 VGA_TXBOUT018 VGA_TXBOUT118 VGA_TXBOUT2-
G44 B47 B45
LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2
18 VGA_TXBOUT0+ 18 VGA_TXBOUT1+ 18 VGA_TXBOUT2+
E44 A47 A45
LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2
DY
18 LDDC_CLK 18 LDDC_DATA 18 LCDVDD_EN
Chang R68 from 64.24015.6DL to 64.33015.6DL 18 18 18 18
1
2 3K3R2F-2-GP
LVDS_IBG TP41
VGA_TXACLKVGA_TXACLK+ VGA_TXBCLKVGA_TXBCLK+
1 2
R53 150R2F-1-GP
R55 150R2F-1-GP
R54 150R2F-1-GP
2
TV_DCONSEL0 TV_DCONSEL1
8 TV_DCONSEL0 8 TV_DCONSEL1
TVA_DAC TVB_DAC TVC_DAC
F27 J27 L27
TVA_RTN TVB_RTN TVC_RTN
M35 P33
TV_DCONSEL0 TV_DCONSEL1
GMCH_DDCCLK GMCH_DDCDATA GMCH_VSYNC GMCH_HSYNC
RN54
4 3
SRN33J-5-GP-U 1 R60
CRT_VSYNC CRT_HSYNC
CRTIREF 2 1K3R2F-1-GP SA:0428
FOR Calero: 255 ohm Crestline: 1.3k ohm
3D3V_S0
RN55
3 4
2 1
K33 G35 E33 C32 F33
CRT_DDC_CLK CRT_DDC_DATA CRT_VSYNC CRT_TVO_IREF CRT_HSYNC
PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15
J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41
PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15
J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42
PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9 PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15
N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44
NB_SDVOB_RNB_SDVOB_GNB_SDVOB_BNB_SDVOB_C-
PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15
M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43
NB_SDVOB_R+ NB_SDVOB_G+ NB_SDVOB_B+ NB_SDVOB_C+
PEGCOMP trace width and spacing is 20/25 mils.
CRESTLINE-GP-U-NF
1
Strap Pin Table 010 = FSB 800MHz 011 = FSB 667MHz Others = Reserved
CFG[2:0] FSB Freq select CFG5 (DMI select)
SDVOB_INT- 23
0 = DMI x 2 1 = DMI x 4
CFG6
*
D
Reserved 0 = Reserved 1 = Mobile CPU
CFG7 (CPU Strap)
*
0 = Normal mode 1 = Low Power mode
CFG8 (Low power PCIE) CFG9 (PCIE Graphics Lane Reversal)
*
0 = Reverse Lane 1 = Normal Operation
*
SDVOB_INT+ 23
CFG[11:10]
Reserved 00 01 10 11
CFG[13:12] (XOR/ALLZ) CFG[15:14]
CFG[18:17]
0 = No SDVO Device Present * 1 = SDVO Device Present 0 = Normal Operation (Lane number in Order) 1 = Reverse lane
SDVOB_R- 23
1 SCD1U10V2KX-4GP
SDVOB_G- 23
NB_SDVOB_B- C474 2
1 SCD1U10V2KX-4GP
SDVOB_B- 23
NB_SDVOB_C- C480 2
1 SCD1U10V2KX-4GP
SDVOB_C- 23
NB_SDVOB_R+ C470 2
1 SCD1U10V2KX-4GP
SDVOB_R+ 23
NB_SDVOB_G+ C468 2
1 SCD1U10V2KX-4GP
SDVOB_G+ 23
NB_SDVOB_B+ C478 2
1 SCD1U10V2KX-4GP
SDVOB_B+ 23
NB_SDVOB_C+ C484 2
1 SCD1U10V2KX-4GP
SDVOB_C+ 23
*
0 = Only PCIE or SDVO is operational * 1 = PCIE/SDVO are operating simu.
CFG20(PCIE/SDVO consurrent)
1 SCD1U10V2KX-4GP
C
Reversed
SDVO_CTRLDATA
NB_SDVOB_G- C464 2
Reserved XOR Mode Enabled All Z Mode Enabled Normal Operation (Default)*
0 = Disable 1 = Enable *
CFG16 (FSB Dynamic ODT)
NB_SDVOB_R- C469 2
= = = =
Reserved
CFG19(DMI Lane Reversal)
VF
1 2
CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED#
PEGCOMP
-c
1 2
R61 150R2F-1-GP
R57 150R2F-1-GP
1 17 17 17 17
H32 G32 K29 J29 F29 E29
VGA
2
R56 150R2F-1-GP 2 1
M_BLUE M_GREEN M_RED
17 M_BLUE 17 M_GREEN 17 M_RED
B
E27 G27 K27
TV
2
35 M_COMP 35 M_LUMA 35 M_CRMA
1
M_COMP M_LUMA M_CRMA
1
C
SRN10KJ-5-GP
PEG_COMPI PEG_COMPO
N43 M43
2
2 24D9R2F-L-GP
o-
LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK
2 1
PCI_EXPRESS GRAPHICS
L41 L43 N41 N40 D46 C45 D44 E42
RN56
3 4
LVDS
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN
18 LBKLT_CTL 34 GMCH_BL_ON 3D3V_S0
D-1:0908
1
U50C 3 OF 10
J40 H39 E39 E40 C37 D35 K40
R68
3
1D05V_S0
cc
5 For Crestline : 2.4 Kohm For Calero : 1.5Kohm
B
NB:71.GM965.A0U
LDDC_CLK LDDC_DATA
SRN10KJ-5-GP
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3
CRESTLINE(3/6)-VGA/LVDS/TV Document Number
Rev
-1
DS2-Intel
Date: Wednesday, September 12, 2007
Sheet
10
of
47
5 3D3V_S0_DAC_BG
4
3
2
1
3D3V_S0 R58
2
1 3D3V_S0 1D25V_S0_DPLLB
1
1 2
1 2
1 2
1
1 2
1 2
2 1 2
1 2
1 2
1 2
1 2
2
1
D12
1
1D05V_S0_D
3D3V_S0
2
1D25V_S0
C411 BLM18AG121SN-1GP
C407
1
Place C95,C99,C112 near Pin AD51,W50,W51
2
C179
1
1 2
C180
2
3D3V_S0_HV
R70
3 BAS16-1-GP 2
2
1
2
R71 1 0R0402-PAD
1
1
2
1 2
1 2
cc
1
SC1U10V3KX-3GP
1 2 1
1 2
SC4D7U6D3V5KX-3GP
1 2
2
1D05V_S0
R82 2 0R0603-PAD C164 SC1U10V3KX-3GP
1D8V_S3
1
1 R79 2 0R0603-PAD C162
1D8V_S3
VCCA_TVDAC
3D3V_S0
10R2J-2-GP
C144 SCD1U16V2KX-3GP
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
L19
1 2 BLM18PG181SN-3GP
L85 2nd source 68.00214.101/68.00217.141
1
1 2
C169
C447 SC10U6D3V5KX-1GP
Title
2
1
40mil
1
1
C422
B
L17
1D8V_S0_TXLVDS
2
1 2
Place C108,C109 Pin N28
C105near
C406
Place C96 near Pin AN2
1
2
CRESTLINE-GP-U-NF
1D8V_S0_LVDS
2
2
o-
NB:71.GM965.A0U
C404
C60
1D25V_S0_MPLL
1
VCCD_LVDS VCCD_LVDS
1D25V_S0
C492
2
J41 H42
2 L-10UH-11-GP
1D05V_S0
1
VCCD_PEG_PLL
1D8V_S0_LVDS
A7 F2 AH1
C139
C490
2
1D25V_S0_PEGPLL
VTTLF VTTLF VTTLF
SCD47U16V3ZY-3GP
VCCD_HPLL
U48
C
Place C82,C83 near Pin M32,L29
1D25V_S0
1 L25
20mil
1
AN2
VTTLF1 VTTLF2 VTTLF3
SCD47U16V3ZY-3GP 2
1D25V_S0
AH50 AH51
1
VCCD_QDAC
C172
SC1U10V3KX-3GP
1D05V_S0
SCD47U16V3ZY-3GP 2
N28
VCC_RXR_DMI VCC_RXR_DMI
VTTLF
1D5V_S0
DMI
VCCD_CRT VCCD_TVDAC
TV/CRT
M32 L29
SC10U6D3V5KX-1GP
SC4D7U6D3V5KX-3GP
SCD47U16V3ZY-3GP SC10U6D3V5KX-1GP 2 1 2 1
AD51 W50 W51 V49 V50
1
PEG
VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG
C40 B40
1D25V_S0_DPLLA
1
SM CK
HV
A CK TV
VCCA_TVA_DAC VCCA_TVA_DAC VCCA_TVB_DAC VCCA_TVB_DAC VCCA_TVC_DAC VCCA_TVC_DAC
VCC_HV VCC_HV
C96
3D3V_S0_HV
2
AXF
A PEG A SM
1 2
1
2
VCCA_SM_CK VCCA_SM_CK
1D5V_S0
C114
1D8V_S0_TXLVDS
C153
-c
A43
VF
1
1 2
SC1U10V3KX-3GP
VCC_TX_LVDS
LVDS
2 SCD22U10V3KX-2GP SCD1U16V2ZY-2GP
SC10U6D3V5KX-1GP
2 1 2
1 2
1 2
SC1U10V3KX-3GP
SC10U6D3V5KX-1GP
1 2
SC10U6D3V5KX-1GP 2 1
1 2 1 2 1 2
1D8V_S3
C125
SCD1U16V2ZY-2GP
1
BK24 BK23 BJ24 BJ23
C119
SC10U6D3V5KX-1GP
2
VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK
1D25V_S0
1D25V_S0
BLM18PG121SN-1GP
SC10U6D3V5KX-1GP
VCCA_TVDAC
AJ50
1D25V_S0
SC10U6D3V5KX-1GP
1
3D3V_S0_TVDACC
VCC_DMI
SC10U6D3V5KX-1GP
1
3D3V_S0_TVDACB
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD022U16V2KX-3GP
2
3D3V_S0_TVDACA
B23 B21 A21
C176
2
SCD1U16V2ZY-2GP
VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM_NCTF VCCA_SM_NCTF
C25 B25 C27 B27 B28 A28
VCC_AXF VCC_AXF VCC_AXF
DY C181
SCD1U16V2ZY-2GP
AT22 AT21 AT19 AT18 AT17 AR17 AR16
1D5V_S0
3D3V_S0_TVDACB R269 1 2 0R0603-PAD C439
VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM
SCD1U16V2ZY-2GP
VCCA_TVDAC
AW18 AV19 AU19 AU18 AU17
BC29 BB29
C104
SCD022U16V2KX-3GP
SCD1U16V2ZY-2GP C434
SCD022U16V2KX-3GP
R267 1 2 0R0603-PAD C433
C118
C167
SCD1U16V2ZY-2GP
VCCA_TVDAC R271 1 2 C445 0R0603-PAD
C94
AR29
C102
1D5V_S0
L4
1
SC10U6D3V5KX-1GP
C101
SCD1U16V2ZY-2GP
SCD022U16V2KX-3GP
2
C115
VCC_AXD_NCTF
1D25V_S0_PEGPLL
C110 SC10U6D3V5KX-1GP
C126
SCD1U16V2ZY-2GP
VCCA_PEG_PLL
C117
D
Place C75,C76 near Pin BK24,BK23,BJ24,BJ23
1D25V_S0
SCD022U16V2KX-3GP
U51
1D25V_S0
SC1KP50V2KX-1GP
C82
3D3V_S0_TVDACC
C440
VSSA_PEG_BG
AT23 AU28 AU24 AT29 AT25 AT30
SCD1U16V2ZY-2GP
C89
-1:0909
1D25V_S0
A
VCCA_PEG_BG
K49
VCC_AXD VCC_AXD VCC_AXD VCC_AXD VCC_AXD VCC_AXD
2
C399 BLM18AG121SN-1GP
SCD1U16V2ZY-2GP
20mil SCD1U16V2ZY-2GP
1D25V_S0
3D3V_S0_TVDACA
K50
POWER
SC10U6D3V5KX-1GP
C171 SCD1U16V2ZY-2GP 1D25V_S0_PEGPLL
C446
VSSA_LVDS
1
400uA
C
B
VCCA_LVDS
B41
2
SC1KP50V2KX-1GP
VCCA_MPLL
A41
A LVDS
1
C157 3D3V_S0
VCCA_HPLL
1 C396
2
2
1 2
SC22U6D3V5MX-2GP
1D8V_S0_TXLVDS
AL2 AM2
C107 SC1U16V3ZY-GP
L16
SCD1U16V2ZY-2GP
DY
150mA
C99
1D8V_S3 1D25V_S0_HPLL
C76
SC10U6D3V5KX-1GP
1D25V_S0_HPLL 1D25V_S0_MPLL
TC21
2
VCCA_DPLLB
AXD
VCCA_DPLLA
H49
PLL
B49
1D25V_S0_DPLLB
C137
C168
C170
SCD1U16V2ZY-2GP
1D25V_S0_DPLLA
C75
C83
C493
SC10U6D3V5KX-1GP
3D3V_S0
1
VSSA_DAC_BG
Place TC21 near R58 and R59
C106
2
VCCA_DAC_BG
B32
VTT
1
3D3V_S0_DAC_BG
CRT
A30
0R3-0-U-GP C127
SCD1U16V2ZY-2GP
VCCA_CRT_DAC VCCA_CRT_DAC
U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1
Place C69,C70 near Pin B23,B21,A21
1D25V_S0 SC10U6D3V5KX-1GP
3D3V_S0_DAC_CRT
A33 B33
VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT
2 L-10UH-11-GP
SCD1U16V2ZY-2GP
1
VCC_SYNC
SCD1U16V2ZY-2GP
R59
J32
2
U50H 8 OF 10
C124 SCD1U16V2ZY-2GP
3D3V_S0
2
1 L26 SC10U6D3V5KX-1GP
3D3V_S0_DAC_CRT
1D05V_S0
1
SB:07/01 Change R58,R59 from 0602 close pad to 63.00000.00L
2
2
C121
SCD1U16V2ZY-2GP
D
1D25V_S0
1
0R3-0-U-GP
Size A3
CRESTLINE(4/6)-PWR Document Number
Rev
-1
DS2-Intel
Date: Wednesday, September 12, 2007
Sheet
11
of
47
5
4 1D05V_S0
3
2
LIB C 1D05V_S0
U50G 7 OF 10
VSS NCTF
D
VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF
VSS SCB
VSS_SCB VSS_SCB VSS_SCB VSS_SCB VSS_SCB VSS_SCB
A3 B2 C1 BL1 BL51 A51
VSS AXM
POWER
VCC_AXM VCC_AXM VCC_AXM VCC_AXM VCC_AXM VCC_AXM VCC_AXM
AT33 AT31 AK29 AK24 AK23 AJ26 AJ23
NCTF_U56-1
TP89
NCTF_U56-2 NCTF_U56-4 NCTF_U56-3
TP88 TP96 TP95
C
1D05V_S0
B
2
1 2
1 2
1 2
2
1
2
1
-c C156
C155 1
C143 1
1
C93
C62
1
C71
1
T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28
VSS AXM NCTF
o-
cc
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC4D7U6D3V5KX-3GP
VCC NCTF
1
1 2
2
1 2
1 2
1 2
1 2
1 2
ST220U2VBM-3GP
1 2
1
SCD22U10V2KX-1GP
2
1 2
SCD1U16V2ZY-2GP
1
1
C66
VF
A
SC1U10V3KX-3GP
2
SC1U10V3KX-3GP 2
SCD47U16V3ZY-3GP
SCD22U10V2KX-1GP 2
SCD22U10V2KX-1GP 2
2 SCD1U16V2ZY-2GP
NB:71.GM965.A0U
2
2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
VCC GFX NCTF VCC SM LF
1 2
VCC SM
SCD01U16V2KX-3GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC10U6D3V5KX-1GP
1 2
SC1U10V3KX-3GP
VCC GFX
1 2
1
1
2
2
1 2
1 2
ST220U2VBM-3GP
1 2
1 2
AL24 AL26 AL28 AM26 AM28 AM29 AM31 AM32 AM33 AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33
VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC10U6D3V5KX-1GP
C141
C140
VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7
SCD22U10V2KX-1GP
CRESTLINE-GP-U-NF
VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF
CRESTLINE-GP-U-NF SCD1U16V2ZY-2GP
AW45 BC39 BE39 BD17 BD4 AW8 AT6
C92 SC10U6D3V5KX-1GP
C116
VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF
C158
VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG
SCD22U10V2KX-1GP
SC10U6D3V5KX-1GP
C111
SCD1U16V2ZY-2GP
C87
R20 T14 W13 W14 Y12 AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31 AJ20 AN14
AB33 AB36 AB37 AC33 AC35 AC36 AD35 AD36 AF33 AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36 AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35 AP36 AR35 AR36 Y32 Y33 Y35 Y36 Y37 T30 T34 T35 U29 U31 U32 U33 U35 U36 V32 V33 V36 V37
1D05V_S0
C160
A
C129
C100
C134
SCD22U10V2KX-1GP
B
DY SCD22U10V2KX-1GP
1D05V_S0
VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM
C79
C130
C131
C133
C142
C132
DY
C
AU32 AU33 AU35 AV33 AW33 AW35 AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33 BJ34 BK32 BK33 BK34 BK35 BL33 AU30
C120
1D05V_S0
C128
POWER 1D8V_S3
C90
TC15
C402
VCC
T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31
C403
R30
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
C136
D
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCC CORE
-1:0909 AT35 AT34 AH28 AC32 AC31 AK32 AJ31 AJ28 AH32 AH31 AH29 AF32
1
U50F 6 OF 10
TC17
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
CRESTLINE(5/6)-PWR/GND Size A3
Document Number
Rev
-1
DS2-Intel
Date: Wednesday, September 12, 2007
Sheet
12
of
47
5
4
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41
VF
B
VSS
U50J10 OF 10
A
C46 C50 C7 D13 D24 D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36 F4 F40 F50 G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48 G8 H24 H28 H4 H45 J11 J16 J2 J24 J28 J33 J35 J39 K12 K47 K8 L1 L17 L20 L24 L28 L3 L33 L49 M28 M42 M46 M49 M5 M50 M9 N11 N14 N17 N29 N32 N36 N39 N44 N49 N7 P19 P2 P23 P3 P50 R49 T39 T43 T47 U41 U45 U50 V2 V3
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28
D
cc
C
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
9 OF 10
1
VSS VSS VSS VSS VSS VSS VSS VSS
AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50
C
VSS
o-
D
A13 A15 A17 A24 AA21 AA24 AA29 AB20 AB23 AB26 AB28 AB31 AC10 AC13 AC3 AC39 AC43 AC47 AD1 AD21 AD26 AD29 AD3 AD41 AD45 AD49 AD5 AD50 AD8 AE10 AE14 AE6 AF20 AF23 AF24 AF31 AG2 AG38 AG43 AG47 AG50 AH3 AH40 AH41 AH7 AH9 AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51 AL1 AM11 AM13 AM3 AM4 AM41 AM45 AN1 AN38 AN39 AN43 AN5 AN7 AP4 AP48 AP50 AR11 AR2 AR39 AR44 AR47 AR7 AT10 AT14 AT41 AT49 AU1 AU23 AU29 AU3 AU36 AU49 AU51 AV39 AV48 AW1 AW12 AW16
2
-c
U50I
3
CRESTLINE-GP-U-NF
NB:71.GM965.A0U
B
CRESTLINE-GP-U-NF
NB:71.GM965.A0U
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3
CRESTLINE(6/6)-PWR/GND
Document Number
Rev
-1
DS2-Intel
Date: Wednesday, September 12, 2007
Sheet
13
of
47
5
4
3
2
1
DM2
1 2 3 4
8 7 6 5
SRN56J-5-GP
SRN56J-5-GP
RN11
RN50
1 2 3 4
DDR_A_CAS# DDR_A_MA13 M_ODT1 DDR_CS1_DIMMA#
1 2 3 4
8 7 6 5
1 2 3 4
8 7 6 5
SRN56J-5-GP
SRN56J-5-GP
RN9
RN48
8 7 6 5
1 2 3 4
SRN56J-5-GP
8 7 6 5
DDR_A_MA12 DDR_A_BS2 DDR_CKE0_DIMMA
4,15,21 ICH_SMBCLK 4,15,21 ICH_SMBDATA
M_ODT0 DDR_CS0_DIMMA# DDR_A_RAS# DDR_A_BS1
DDR_VREF_S3
8 M_ODT0 8 M_ODT1
C184
SRN56J-5-GP
1 2 3 4
8 7 6 5
2
RN52
A
DDR_A_MA7 DDR_A_MA11 DDR_A_MA14 DDR_CKE1_DIMMA
ICH_SMBCLK ICH_SMBDATA
197 195
SCL SDA
114 119
ODT0 ODT1
1
SA0 SA1
198 200
VDD_SPD
199
SA0 SA1
1 1
R37 R39
1
CS0# CS1# CKE0 CKE1 RAS# CAS# WE#
M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR1 M_CLK_DDR#1
SC10P50V2JN-4GP
110 115 79 80 108 113 109
30 32 164 166
1
DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
CK0 CK0# CK1 CK1#
2
NC#50 NC#69 NC#83 NC#120 NC#163/TEST
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
M_CLK_DDR1 M_CLK_DDR#1
C388
M_CLK_DDR0 8 M_CLK_DDR#0 8 M_CLK_DDR1 8 M_CLK_DDR#1 8
2 0R0402-PAD 2 0R0402-PAD
1
50 69 83 120 163
10 26 52 67 130 147 170 185
D
put near connector
C391
2
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
SC10P50V2JN-4GP 2
5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194
SA:0428
3D3V_S0
1D8V_S3
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
81 82 87 88 95 96 103 104 111 112 117 118
VREF
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
2 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196
GND
GND
202
-c
1
8 DDR_CS0_DIMMA# 8 DDR_CS1_DIMMA# 8 DDR_CKE0_DIMMA 8 DDR_CKE1_DIMMA 9 DDR_A_RAS# 9 DDR_A_CAS# 9 DDR_A_WE#
DDR_A_MA0 DDR_A_MA2 DDR_A_MA4 DDR_A_MA6
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
8 PM_EXTTS#0
SCD1U16V2ZY-2GP
1
DDR_A_MA1 DDR_A_MA10 DDR_A_BS0 DDR_A_WE#
8 7 6 5
BA0 BA1
M_ODT0 M_ODT1 DDR_VREF_S3 C185
C41 SCD1U16V2ZY-2GP
C46 SC2D2U6D3V3KX-GP
DY
C
201
B
SKT-SODIMM200-38GP
2
1 2 3 4
Layout Note: Place these resistors closely DM1,all trace length Max=1.5"
1
DDR_A_MA9 DDR_A_MA5 DDR_A_MA8 DDR_A_MA3
RN15
VF
DDR_VREF_S0 RN13
2
1
change to 8P4R
B
C421 SCD1U16V2ZY-2GP
2
1
C85 SCD1U16V2ZY-2GP
2
1
C427 SCD1U16V2ZY-2GP
2
1
C438 SCD1U16V2ZY-2GP
2
1
C430 SCD1U16V2ZY-2GP
2
1
C423 SCD1U16V2ZY-2GP
2
1
C63 SCD1U16V2ZY-2GP
2
C73 SCD1U16V2ZY-2GP
2
1
C95 SCD1U16V2ZY-2GP
DY
SCD1U16V2ZY-2GP
2
1
DDR_VREF_S0
C112
107 106
SB:0707 For EMI request
C477
o-
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
DDR_A_BS0 DDR_A_BS1
C476
SC10P50V2JN-4GP
1 2
1
C122 SC10U6D3V5KX-1GP
SCD1U16V2ZY-2GP
2
C69
2
1
1
C98 SCD1U16V2ZY-2GP
2
1
C81 SCD1U16V2ZY-2GP
2
C84 SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
2
C77
2
1
C123 SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
C
1
C91
2
1
1D8V_S3
DDR_A_BS2
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7
1
9 DDR_A_BS[0..2]
Layout Note: Place near DM1
13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186
1
9 DDR_A_MA[0..14] D
M_CLK_DDR0 M_CLK_DDR#0
MH2
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#
2
9 DDR_A_DQS[0..7]
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16_BA2
cc
9 DDR_A_DM[0..7]
MH2
102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85
1
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14
9 DDR_A_D[0..63]
2
9 DDR_A_DQS#[0..7]
MH1
SC10P50V2JN-4GP 2
MH1
SC2D2U16V5ZY-2GP A
Main Source:62.10017.E31 2nd Source: 62.10017.A41
SRN56J-5-GP
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
DDRII-SODIMM SLOT1 Size Custom Date: 5
4
3
2
Document Number
Rev
DS2-Intel
Wednesday, September 12, 2007
Sheet 1
-1 14
of
47
5
4
3
2
1
M_CLK_DDR2
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
1
11 29 49 68 129 146 167 186
DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#
DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7
13 31 51 70 131 148 169 188
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7
M_ODT2 M_ODT3
114 119
OTD0 OTD1
1 2
164 166
M_CLK_DDR3 M_CLK_DDR#3
M_CLK_DDR3 8 M_CLK_DDR#3 8
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
10 26 52 67 130 147 170 185
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
SDA SCL
195 197
ICH_SMBDATA ICH_SMBCLK
VDDSPD
199
SA0 SA1
198 200
NC#50 NC#69 NC#83 NC#120 NC#163/TEST
50 69 83 120 163
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
81 82 87 88 95 96 103 104 111 112 117 118
3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196
1 2 3 4
M_ODT3 DDR_CS3_DIMMB# DDR_B_CAS# DDR_B_WE#
1 2 3 4
1 2 3 4
SRN56J-5-GP
8 7 6 5 SRN56J-5-GP
RN12
RN51
8 7 6 5
1 2 3 4
SRN56J-5-GP
8 7 6 5 SRN56J-5-GP
RN47
RN10
8 7 6 5
1 2
4 3 SRN56J-4-GP
DDR_B_MA14 DDR_B_MA6 DDR_B_MA2 DDR_B_MA4
DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5
DDR_B_MA13 M_ODT2
DDR_VREF_S3
8 M_ODT2 8 M_ODT3
DDR_VREF_S3
SRN56J-5-GP C499
RN16
1 2 3 4
8 7 6 5
DDR_CKE3_DIMMB DDR_B_MA7 DDR_B_MA11
SCD1U16V2ZY-2GP
1
DDR_CS2_DIMMB# DDR_B_BS1 DDR_B_RAS# DDR_B_MA0
8 7 6 5
2
1 2 3 4
Layout Note: Place these resistors closely DM2,all trace length Max=1.5"
1
DDR_B_BS0 DDR_B_MA10 DDR_B_MA1 DDR_B_MA3
RN14
2
DDR_VREF_S0 RN49
VF
B
1
DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7
CK1 CK1#
2
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
M_CLK_DDR2 8 M_CLK_DDR#2 8
SC10P50V2JN-4GP
5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194
M_CLK_DDR2 M_CLK_DDR#2
put near connector
D
M_CLK_DDR3 M_CLK_DDR#3
SB:0707 For EMI request C50
ICH_SMBDATA 4,14,21 ICH_SMBCLK 4,14,21
1
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
30 32
C51
2
BA0 BA1
CK0 CK0#
3D3V_S0 R36 R38
1 1
2 0R0402-PAD 2 10KR2J-3-GP SA:0428
C44 SCD1U16V2ZY-2GP
3D3V_S0
PM_EXTTS#1 8
C38 SC2D2U6D3V3KX-GP
DY
1D8V_S3
VREF VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
202
GND
GND
201
MH1
MH1
MH2
MH2
-c
2
1
C74 SCD1U16V2ZY-2GP
2
1
C429 SCD1U16V2ZY-2GP
2
1
C425 SCD1U16V2ZY-2GP
2
1
C97 SCD1U16V2ZY-2GP
2
1
C443 SCD1U16V2ZY-2GP
2
1
C441 SCD1U16V2ZY-2GP
2
1
C419 SCD1U16V2ZY-2GP
2
1
C113 SCD1U16V2ZY-2GP
2
C64 SCD1U16V2ZY-2GP
DY
SCD1U16V2ZY-2GP
2
1
DDR_VREF_S0
C86
107 106
CKE0 CKE1
DDR_CKE2_DIMMB 8 DDR_CKE3_DIMMB 8
C
o-
C
DDR_B_BS0 DDR_B_BS1
DDR_CS2_DIMMB# 8 DDR_CS3_DIMMB# 8
DDR_CKE2_DIMMB DDR_CKE3_DIMMB
C174
SC10P50V2JN-4GP
1 2
1
C108 SC10U6D3V5KX-1GP
2
1
C72 SCD1U16V2ZY-2GP
2
1
C78 SCD1U16V2ZY-2GP
2
1
C103 SCD1U16V2ZY-2GP
2
1
C70 SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
2
C67
2
C109
1
C88 SC2D2U16V5ZY-2GP
2
1
1D8V_S3
DDR_B_BS2
DDR_CS2_DIMMB# DDR_CS3_DIMMB#
79 80
1
9 DDR_B_BS[0..2]
110 115
SC10P50V2JN-4GP 2
Layout Note: Place near DM2
CS0# CS1#
C175
DDR_B_RAS# 9 DDR_B_WE# 9 DDR_B_CAS# 9
1
9 DDR_B_MA[0..14] D
DDR_B_RAS# DDR_B_WE# DDR_B_CAS#
1
9 DDR_B_DQS[0..7]
108 109 113
2
9 DDR_B_DM[0..7]
RAS# WE# CAS#
2
9 DDR_B_D[0..63]
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2
cc
9 DDR_B_DQS#[0..7]
102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85
SC10P50V2JN-4GP 2 1
M_CLK_DDR#2
DM1 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14
C503 SC2D2U16V5ZY-2GP
A
B
A
SKT-SODIMM200-37GP
SRN56J-5-GP
Main Source:62.10017.E21 2nd Source: 62.10017.A51 RN53
1 2
4 3
Wistron Corporation
DDR_CKE2_DIMMB DDR_B_BS2
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
SRN56J-4-GP Title
DDRII-SODIMM SLOT2 Size Custom Date: 5
4
3
2
Document Number
Rev
DS2-Intel
Wednesday, September 12, 2007
Sheet 1
-1 15
of
47
B
C
HDMI I/F & CONNECTOR
D
3D3V_S0 5V_S0
1 R278 1
HDMI_TXD#1_C
23 HDMI_TXD#0
2 0R0603-PAD
HDMI_TXD#0
HDMI_TXD#0_C
R444
1
RN19
DY
2
0R2J-2-GP
SRN2K2J-1-GP
DY 4 3
2 0R0603-PAD
HDMI_TXD#1
SB:06/23 Add R444,R445(63.R0034.1DL)
DY R73 10KR2J-3-GP
2
R288 1 23 HDMI_TXD#1
E
1 2
A
4
4 L21 ACM2012H-900-GP
DY
DY
HDMI_SCLK
R292
HDMI_TXD1_C
1
2
23 HDMI_TXD0
3
2
HDMI_TXD1
2
5
3
4 2N7002SPT
HDMI_TXD0
0R0603-PAD
6
R285
1
2
0R0603-PAD
HDMI_SDATA
CH751H-40PT 5V_S0
connect to 5V_S0 directly.
R445
1
HDMI CONN
HDMI_TXC
TMDS_DATA1TMDS_DATA1+
HDMI_TXD#2_C HDMI_TXD2_C
3 1
TMDS_DATA2TMDS_DATA2+
HDMI_TX#C_C HDMI_TXC_C
12 10
TMDS_CLOCKTMDS_CLOCK+
8 5 2 11
RN17 SRN1KJ-7-GP
0R0603-PAD
SB:06/22 Change R66,R67 from 63.R0034.1DL to ZZ.R0402.ZZZ
18
SDA
16
HDMI_SDATA_C
SCL
15
HDMI_SCLK_C
CEC
13
HDMI_CEC
RESERVED#14
14
HDMI_CNC
TP90 TPAD28
HOT_PLUG_DETECT
19
HDMI_DP_C2
1
DDC/CEC_GROUNG GND TMDS_DATA0_SHIELD GND TMDS_DATA1_SHIELD GND TMDS_DATA2_SHIELD GND TMDS_CLOCK_SHIELD
SB:06/23 Add R444,R445(63.R0034.1DL)
R67
1
2
1
2
R66 TP91 TPAD28
R63
HDMI_SDATA 0R0402-PAD HDMI_SCLK 0R0402-PAD
HDMI_SDATA 23 HDMI_SCLK 23
3
HDMI_HDP 2 1KR2J-1-GP
HDMI_HDP 23
17 20 21 22 23
R62 15K4R2F-GP
-1:0909
SKT-USB-169-GP 62.10027.661
-c
2
DY
1
6 4
HDMI_TXC_C
1 R277
0R0603-PAD
TMDS_DATA0TMDS_DATA0+
2
0R2J-2-GP
2
DY
+5V_POWER
9 7
o-
DY 2
L20 ACM2012H-900-GP
23 HDMI_TXC
HDMI_TXD#0_C HDMI_TXD0_C HDMI_TXD#1_C HDMI_TXD1_C
4
1
HDMI_TX#C_C
L24 ACM2012H-900-GP
HDMI_TXD2_C
2
2 0R0603-PAD
HDMI_TX#C
3
HDMI_TXD2
1 R299
23 HDMI_TX#C
4
1 2
3
23 HDMI_TXD2
R276 1
HDMI_TXD#2_C
2
3 4
2 0R0603-PAD
3
R295 1 HDMI_TXD#2
Add D31 CH751H for HDMI SM bus clock pull up to 5V_S0.
D11
HDMI1
23 HDMI_TXD#2
CH751H-40PT SB:06/21
5V_HDMI_D 1
DY SB:06/21 HDMI1 pin18
HDMI_TXD0_C
2
HDMI_SCLK_C
cc
23 HDMI_TXD1
3
2
HDMI_SDATA_C
1
2 1
1
1
4 L23 ACM2012H-900-GP
5V_HDMI_C
4
5V_S0
D31
1
U16
TV OUT CONN (Optional) Move to Right I/O Board 2
VF
2
1
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
HDMI/TV Connector Size A3
Document Number
Rev
DS2-Intel
Date: Wednesday, September 12, 2007 A
B
C
D
-1 Sheet E
16
of
47
A
B
C
D
E
CRT I/F & CONNECTOR 4
4
5V_CRT_S0
5V_S0
SB:0630 Change CRT1 from 20.20334.015 to 20.20735.015.
Layout Note: Place these resistors
D4 C18 SCD01U16V2KX-3GP
1
CH751H-40PT
2
CRT1
2
5V_CRT_S0
17 2 BLM18BB470SN1-GP
1
CRT_G
6 11
CRT_R
2
TSAHCT125PW-GP
4 3
4 3
3D3V_S0
4 10 5 16
5
2
6
1
DDC_DATA_CON
VIDEO-15-84-GP-U 20.20735.015
1
1
DDC_CLK_CON
SC33P50V2JN-3GP 2 D7
C347
C334
C359
DY
5V_S0
2 CRT_R
3
DY
JVGA_HS JVGA_VS
1
2
BAV99PT-GP-U D5
2 CRT_G
3
DY
1
BAV99PT-GP-U
1 2
D3
2
SRN2K2J-1-GP
3
CRT_B
3
DY
1
BAV99PT-GP-U
DDC_DATA_CON
GMCH_DDCCLK
10
5V @ ext. CRT side
1
3
MH2
DY
U3
4
JVGA_VS
15
3D3V_S0
RN2
DDC_CLK_CON
14
SRN33J-5-GP-U
TSAHCT125PW-GP
CRT_B
3 9
C354 SC33P50V2JN-3GP
VF
U9A
1 2
VSYNC_5
3
10 GMCH_DDCDATA
8
4 3
1
13
RN6
2
7
HSYNC_5
6 U9B
7
1
14
2
10 GMCH_VSYNC
4
14 5
10 GMCH_HSYNC
C47 SCD1U16V2ZY-2GP
2
JVGA_HS
-c
1
5V_S0
Hsync & Vsync level shift
1
o-
SB:07/09 ChangeC14,C15,C26,C27,C9,C30 from 78.3R374.1FL to 78.8R274.1FL
C14
SRN2K2J-1-GP
12
CRT_G
2
2
3
2
1
1
1 2
1
C26
2
2
C29
SC8P250V2CC-GP
150R2F-1-GP
2
C15
RN3
7
CRT_B
SC8P250V2CC-GP
150R2F-1-GP
2
1
1
1
C27
SC8P250V2CC-GP
150R2F-1-GP
2
C30
SC8P250V2CC-GP
R19
SC8P250V2CC-GP
R23
SC8P250V2CC-GP
R32
2 BLM18BB470SN1-GP
1
2
L1
cc
1
10 M_BLUE
1 2
L2
10 M_GREEN
MH1
SC22P50V2JN-4GP
CRT_R
1 1
2 BLM18BB470SN1-GP
1
SC22P50V2JN-4GP 2 2
L3
1
close to the CRT-out connector
10 M_RED
1
2N7002SPT
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
CRT Connector Size A3
Document Number
Rev
DS2-Intel
Date: Wednesday, September 12, 2007 A
B
C
D
-1 Sheet E
17
of
47
C
SC:08/09 Add EC157(78.33034.1FL) for EMI request .Default is DUMMY
EC157 SC33P50V2JN-3GP
DY
2
1 1
DY
2
MLX-CON9-1-GP
EC156 SC33P50V2JN-3GP
2 1 2 1
U49
2
1
34 LCD_TST_EN
R456
BAT54CPT-GP
2
SCD1U16V2ZY-2GP 2 1
C61
IN#1 OUT EN GND
GND IN#8 IN#7 IN#6 IN#5
9 8 7 6 5
G5281RC1U-GP
1
ENVDD
3
1 2 3 4
C417
2
1
100KR2J-1-GP
1
cc
2
SC5D6P50V2CN-1GP
1 2
SC220P50V2KX-3GP
2 0R0603-PAD
2
1
EC155 SC33P50V2JN-3GP
1 R188
SC:08/09 Add EC156(78.33034.1FL) for EMI request .Default is DUMMY
3D3V_S0
D32 10 LCDVDD_EN
-c DY
+LCDVDD
2
SC:08/09 Add EC155(78.33034.1FL) for EMI request .Default is DUMMY
LCD POWER
-1:09/11
3
DMIC_DET# 34
10
SC5D6P50V2CN-1GP
o-
1 2
1
1
AUD_DMIC_CLK_G 32 AUD_DMIC_IN0 32
4
CAMERA_USB1CAMERA_USB1+
2 33R2J-2-GP 2 33R2J-2-GP
3
SC:08/03 Add D32 ,R456 connect to U49 pin3 and delete R46 that are for LCD test function.
SC:08/09 Add EC152(78.22124.2FL) for EMI request .Default is DUMMY
1
R195 1 R196 1
1
1
AUD_DMIC_CLK_G_R AUD_DMIC_IN0_R
2
2 3 4 5 6 7 8 9
EC186
EC152
DY
1 R193
1
2
11
SC:08/13 Add EC167,EC168(78.10034.1FL), R460,R461(63.R0034.1DL) place cross LVDS CLK A,Bpair. Default is DY.This is for RF request.
SC:08/13 Add EC169,EC170,EC171, R462,R463,R464 on LVDS channel A each data pairs. This is for RF request .Default is DY.
VF
V_AUD_DMIC CAMERA1
SC:08/09 Add EC161(78.10491.4FL) for EMI request .Default is DUMMY
-1:08/29 Change LVDS channel A and channel B EMI solution. this is for antena team request.
AUD_DMIC_IN0_R
EC151
DY
SC:08/09 Add EC151(78.22124.2FL) for EMI request .Default is DUMMY
+5V_RUN_CARMERA
EC185
EC184
AUD_DMIC_CLK_G_R
2
DY
SC:08/09 Add EC153(78.10491.4FL) for EMI request .Default is DUMMY
SC220P50V2KX-3GP
1 2
EC153 SCD1U16V2ZY-2GP
SCD1U10V2KX-4GP
C342
2
1 R186 2 0R0603-PAD
EC168
2
2 2 5V_S0
1
1 2
C341 SC4D7U6D3V3KX-GP
1 2
SC:08/09 Add EC154(78.10491.4FL) for EMI request .Default is DUMMY
SCD1U16V2ZY-2GP
EC154
DY 2
+5V_RUN_CARMERA
INVERTER POWER
SC1U16V3ZY-GP
V_AUD_DMIC
SC5D6P50V2CN-1GP
EC171
CAMERA Power
1
VGA_TXAOUT2-
Mic Power
2
4
SC5D6P50V2CN-1GP
EC170
VGA_TXBCLKEC183
2
VGA_TXACLK+ 10
1
VGA_TXBCLK+
VGA_TXAOUT1-
SC5D6P50V2CN-1GP
1 2
VGA_TXAOUT1+
VGA_TXACLK- 10
VGA_TXACLK+
EC167
SC5D6P50V2CN-1GP
VGA_TXAOUT2- 10 VGA_TXAOUT2+ 10
VGA_TXACLK-
1
VGA_TXAOUT2VGA_TXAOUT2+
2
VGA_TXAOUT1- 10 VGA_TXAOUT1+ 10
EC182
SC5D6P50V2CN-1GP
VGA_TXAOUT0- 10 VGA_TXAOUT0+ 10
VGA_TXAOUT1VGA_TXAOUT1+
VGA_TXACLK-
1
VGA_TXAOUT0VGA_TXAOUT0+
34
VGA_TXACLK+
VGA_TXAOUT2+
600ohm 100MHz 200mA 0.5ohm DC
1
FUSE-3A32V-7-GP C58 SCD1U50V3KX-GP
EC161 BRIGHTNESS
0R2J-2-GP
VGA_TXAOUT0EC169
LBKLT_CTL 10
0R2J-2-GP
1
DY
2
VGA_TXBCLK- 10 VGA_TXBCLK+ 10
1
DY
VGA_TXAOUT0+
VGA_TXBOUT2- 10 VGA_TXBOUT2+ 10
VGA_TXBCLKVGA_TXBCLK+
2 R247
SCD1U16V2ZY-2GP
2
VGA_TXBOUT1- 10 VGA_TXBOUT1+ 10
VGA_TXBOUT2VGA_TXBOUT2+
1
1 2
1
VGA_TXBOUT1VGA_TXBOUT1+
DY
2 R245
IPEX-CONN40-2R-GP 20.F1093.040
1 R189 2 0R0603-PAD
DCBATOUT F2
5V_AUX_S5
-1:09/02 Add R460 to prevent power short to GND via "LCD_CBL_DET#"
48
3D3V_S0
VBL19 EC60 SC33P50V2JN-3GP
10KR2J-3-GP
SC5D6P50V2CN-1GP
41
DY
EC59 SC33P50V2JN-3GP
3D3V_S0
R246
-1:08/29 Change LCD1 pin 31 from GND to NC BAT_SDA BAT_SDA 34,38,39 BAT_SCL BAT_SCL 34,38,39 BACKLITEON LCD_TST LCD_TST 34 LDDC_CLK LDDC_CLK 10 LDDC_DATA LDDC_DATA 10 LCD_DET_G R460 1 2100R2J-2-GP VGA_TXBOUT0VGA_TXBOUT0- 10 VGA_TXBOUT0+ VGA_TXBOUT0+ 10
1 50
3
LCD_TST
C56 SC1KP50V2KX-1GP
2
42
+LCDVDD
SC5D6P50V2CN-1GP
43
3D3V_S0
C57
1
44
34
SC5D6P50V2CN-1GP
45
LCD_CBL_DET# 5V_AUX_S5
SC1U10V3KX-3GP
4
LCD_CBL_DET#
2
46
2
VBL19
51 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
SCD1U10V2KX-4GP EC16
47
DY
E
1
BACKLITEON
SC:08/05 Change C57 from 78.10423.5FL to 78.10523.5BL
SC:08/15 Rename "LCD2" to "LCD1"
1
LCD1
49
D
1
B
2
A
SC:08/09 Add LCD2 (20.F1093.040) ,please check LCD1 and LCD 2 layout overlap possibility.
USB_PN6 21
SC:08/13 Change L12 pin connection.pin 1 connect to "USB_PN6", pin4 DY connect to DLW21SN900SQ2LUGP "USB_PP6" . This L12 change is for layout request.
1
Wistron Corporation
USB_PP6 21
2 0R0603-PAD
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
-1:09/11
Title
LCD/Inverter Connector Size Custom Date: A
B
C
D
Document Number
Rev
DS2-Intel
Wednesday, September 12, 2007
Sheet E
-1 18
of
47
4
PCI_AD[0..31]
PCI_GNT1# PCI_REQ1# PCI_REQ2# PCI_FRAME#
SRN8K2J-4-GP RN39 PCI_PIRQG# PCI_SERR# PCI_PIRQA# PCI_PIRQE#
SRN8K2J-4-GP RN41
1 2 3 4
SRN8K2J-4-GP RN42 8 7 6 5
PCI_PIRQB# PCI_PIRQC# PCI_REQ#0 PCI_PIRQH#
1 2 3 4
SRN8K2J-4-GP RN40 8 7 6 5
PCI_GNT3# PCI_TRDY# PCI_REQ3# PCI_PIRQD#
1 2 3 4
SRN8K2J-4-GP RN38 8 7 6 5
PCI_GNT2# PCI_DEVSEL# PCI_PIRQF# PCI_STOP#
25 PCI_PIRQA# 25 PCI_PIRQC#
AG24 B10 G7
PCI_PLTRST# CLK_PCI_ICH
25 25 25 25
Place closely pin B10 CLK_PCI_ICH
PCI_IRDY# 25 PCI_PAR 25
R425 10R2J-2-GP
PCI_DEVSEL# 25 PCI_PERR# 25 PCI_FRAME# 25
DY
PCI_SERR# 25 PCI_STOP# 25 PCI_TRDY# 25
R398 1
C599 SC8P250V2CC-GP
DY
CLK_PCI_ICH 4 ICH_PME# 25
2 10KR2J-3-GP 3D3V_S5
-1:0909
Interrupt I/F PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5
F8 G11 F12 B3
PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#
C
1KR2J-1-GP
PCI_PCIRST#
PCIRST1# 25,27
DY
R415 100KR2J-1-GP
-c SPI_CS#1
B
Boot BIOS Location
0
1
SPI
1
0
PCI
1
1
LPC *
3D3V_S5
PCI_PLTRST#
U33B
4 6
PLT_RST1#
PLT_RST1# 8,23,24,28,29,30,34
5
1
R424
PCI_GNT0#
VF
1
PCI_GNT3#
2
PLTRST# PCICLK PME#
PCI_C/BE#0 PCI_C/BE#1 PCI_C/BE#2 PCI_C/BE#3
Boot BIOS Strap
Low= A16 swap override Enable High= Default *
DY
PIRQA# PIRQB# PIRQC# PIRQD#
PCI_IRDY# PCI_PAR PCI_PCIRST# PCI_DEVSEL# PCI_PERR# PCI_FRAME# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY#
D
TP125
ICH8-M-1-GP-U-NF
A16 swap override Strap PCI_GNT3#
F9 B5 C5 A10
IRDY# PAR PCIRST# DEVSEL# PERR# FRAME# PLOCK# SERR# STOP# TRDY#
C8 D9 G6 D16 A7 A17 B7 F10 C16 C9
TP129
SB:71.ICH8M.C0U
SRN8K2J-4-GP
B
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#
C17 E15 F16 E17
PCI_REQ#0 25 PCI_GNT#0 25
R419 2
DY
SSLVC08APWR-GP
R416 100KR2J-1-GP
2
C
8 7 6 5
C/BE0# C/BE1# C/BE2# C/BE3#
PCI_REQ1# PCI_GNT1# PCI_REQ2# PCI_GNT2# PCI_GNT3# PCI_REQ3#
o-
1 2 3 4
PCI_IRDY# PCI_GNT#0 PCI_PERR# PCI_PLOCK#
A4 D7 E18 C18 B19 F18 C10 A11
1
8 7 6 5
REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 GNT3#/GPIO55 REQ3#/GPIO54
PCI
2
1 2 3 4
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
14
8 7 6 5
D20 E19 D19 A20 D17 A21 A19 C19 A18 B16 A12 E16 A14 G16 A15 B6 C11 A9 D11 B12 C12 D10 C7 F13 E11 E13 E12 D8 A6 E8 D6 A3
7
1 2 3 4
D
U27C 3 OF 6 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
2
RN37
1
1 1
3D3V_S0
2
2
25 PCI_AD[0..31]
3
cc
5
1 33R2J-2-GP
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
ICH8(1/4)-PCI/INT Size A3
Document Number
Rev
5
4
3
2
-1
DS2-Intel
Date: Wednesday, September 12, 2007
Sheet 1
19
of
47
5
4
3
2
1
+RTCVCC
-1:0909 1 R365
LAN100_SLP 2 330KR2J-L1-GP
1 R364
SM_INTRUDER# 2 1MR2J-1-GP
1 R356
ICH_INTVRMEN 2 330KR2J-L1-GP
+RTCVCC U27A1 OF 6
LPC_LAD[0..3]
34 D
2 G26 GAP-OPEN
ICH_RTCRST#
AF23
RTCRST#
SM_INTRUDER#
AD22
INTRUDER#
AF25 AD21
INTVRMEN LAN100_SLP
ICH_INTVRMEN LAN100_SLP
HDA_BITCLK_R HDA_SYNC
233R2J-2-GP 233R2J-2-GP 233R2J-2-GP
233R2J-2-GP
HDA_SDOUT G62 1
2SC3900P50V2KX-2GP 2SC3900P50V2KX-2GP
-1:0912
ICH_RTCX2
2 SC12P50V2JN-3GP
2
2
4
D21 E20 C20
LAN_TXD0 LAN_TXD1 LAN_TXD2
D25 C25
GLAN_DOCK#/GPIO13 GLAN_COMPI GLAN_COMPO HDA_BIT_CLK HDA_SYNC
LPC_DRQ0# LPC_DRQ1#
A20GATE A20M#
AF13 AG26
H_A20M#
DPRSTP# DPSLP#
AF26 AE26
R124 H_FERR#
TP123 TP127
2
KA20GATE 34 H_A20M# 5
HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3
AE13
HDA_SDOUT
AE10 AG14
HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34
AF10
SATALED#
AF6 AF5 AH5 AH6
SATA0RXN SATA0RXP SATA0TXN SATA0TXP
AG3 AG4 AJ4 AJ3
SATA1RXN SATA1RXP SATA1TXN SATA1TXP
AF2 AF1 AE4 AE3
SATA2RXN SATA2RXP SATA2TXN SATA2TXP
AB7 AC6
SATA_CLKN SATA_CLKP
AG1 AG2
SATARBIAS# SATARBIAS
H_DPRSTP#
H_DPRSTP#
FERR#
AD24
CPUPWRGD/GPIO49
AG29
H_PWRGOOD
H_PWRGOOD 6,46
IGNNE#
AF27
H_IGNNE#
H_IGNNE# 5
INIT# INTR RCIN#
AE24 AC20 AH14
H_INIT#
NMI SMI#
AD23 AG28
H_NMI
H_NMI 5 H_SMI# 5
STPCLK#
AA24
H_STPCLK#
H_STPCLK# 5
THRMTRIP#
AE27
THRMTRIP_ICH# 1 R122
TP8
AA23
Within 500 mils
H_DPSLP#
TP108
within 2" from R184
H_INIT# 5 H_INTR 5 KBRCIN# 34
1D05V_S0
R123 56R2J-4-GP
2
C
H_THERMTRIP# 5,8,34,46
24R2J-GP
IDE_PDD[0..15]
IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15
TP105
H_DPRSTP# 6,8,41
H_DPSLP# 6 H_FERR# 5
KBRCIN#
1 56R2J-4-GP
H_DPSLP# H_FERR#
HDA_RST#
AJ17 AH17 AH15 AD13
VF
1
1
2 3
SATA_TXN0_C SATA_TXP0_C
24D9R2F-L-GP
R111 10MR2J-L-GP
X-32D768KHZ-40GPU X1
LAN_RXD0 LAN_RXD1 LAN_RXD2
AE14
4 CLK_PCIE_SATA# 4 CLK_PCIE_SATA R119 1 2
CL=12.5pF
C21 B21 C22
-c
C520 1 C521 1
LAN_RSTSYNC
AJ16 AJ15
HDA_RST#
GAP-OPEN TP101
1 C203
G9 E6
1D05V_S0 LPC_LFRAME# 34
1
GLAN_COMP
35 SATA_LED#
B
LDRQ0# LDRQ1#/GPIO23
IDE
R368 1 R367 1 R366 1
GLAN_CLK
AH21
233R2J-2-GP
1
R348 1
R363 1
24 SATA_RXN0_C 24 SATA_RXP0_C 24 SATA_TXN0 24 SATA_TXP0
LPC_LFRAME#
2
R414 24D9R2F-L-GP
31 ICH_SDIN_MDC 23 ICH_SDIN_S1392 32 ICH_SDIN_CODEC 23,31,32 ICH_SDOUT_CODEC
C4
IHDA
31 ICH_AZ_MDC_RST# 23 ICH_AZ_S1392_RST# 32 ICH_AZ_CODEC_RST#
FWH4/LFRAME#
o-
C
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3
cc
2
2
33R2J-2-GP
23,31,32 ICH_AZ_CODEC_SYNC
E5 F5 G8 F6
CPU
1D5V_S0
R454
1
B24 D22
LAN/GLAN
SB: 0702 Add R454 in "HDA_BITCLK" for EMI request.
23,31,32 HDA_BITCLK
FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3
1
2
C205 SC1U10V3KX-3GP
RTCX1 RTCX2
SATA
2 20KR2J-L2-GP 1
1 R120
AG25 AF24
LPC
ICH_RTCX1 ICH_RTCX2
-1:0909
RTC
D
DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
V1 U2 V3 T1 V4 T5 AB2 T6 T3 R2 T4 V6 V5 U1 V2 U6
DA0 DA1 DA2
AA4 AA1 AB3
IDE_PDA0 24 IDE_PDA1 24 IDE_PDA2 24
DCS1# DCS3#
Y6 Y5
IDE_PDCS1# 24 IDE_PDCS3# 24
DIOR# DIOW# DDACK# IDEIRQ IORDY DDREQ
W4 W3 Y2 Y3 Y1 W5
IDE_PDIOR# 24 IDE_PDIOW# 24 IDE_PDDACK# 24 INT_IRQ14 24 IDE_PDIORDY 24 IDE_PDDREQ 24
placed within 2" from ICH8M
24
B
ICH8-M-1-GP-U-NF
SB:71.ICH8M.C0U
-1: 0904 change to DY
1 C202
2 SC12P50V2JN-3GP
3D3V_AUX_S5
ICH_RTCX1
+RTCVCC
HDA_BITCLK
1
1 R437
DY
1 C625 SC1U10V3ZY-6GP
W=20mils
U60
1 2 MH1 MH2
BATT1.1
W=20mils 2
RTCVCC_R 2 3 100R2J-2-GP W=20mils
R438
1 CH715FPT-GP
BATT_R 1
PWR GND MH1 MH2 BAT-CON2-U3-GP
2
1KR2J-1-GP
2
2 A
SC22P50V2JN-4GP
C636
RTC1
W=20mils
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Please Place C636 near R454 Title
ICH8(2/4) LAN,HD,IDE,LPC Size A3
Document Number
Rev
DS2-Intel
Date: Wednesday, September 12, 2007 5
4
3
2
Sheet 1
-1 20
of
47
5
4
3
3D3V_S0
2
1
3D3V_S5
Place closely pin G5
Place closely pin AG9
RN69 CLK_48M_ICH
RN68 GPIO22 USB_OC#6 USB_OC#4 USB_OC#2
8 7 6 5
SRN10KJ-6-GP RN66 SMLINK0 1 USB_OC#5 2 USB_OC#7 3 USB_OC#9 4
8 7 6 5
SRN10KJ-6-GP RN67 USB_OC#8 1 DBRESET# 2 ECSMI# 3 USB_OC#1 4
SB_SPKR
32 SB_SPKR
AD9
MCH_ICH_SYNC# AJ13
8 MCH_ICH_SYNC#
ICH_RSVD
TP68
AJ21
R102 2
3D3V_S0
3D3V_S0
4 3
Mini Card 2 RN61 SRN2K2J-1-GP
Mini Card 3 3D3V_S0
1
6
2
5
3
4
27 PCIE_RXN1 27 PCIE_RXP1 27 PCIE_TXN1 27 PCIE_TXP1 29 PCIE_RXN2 29 PCIE_RXP2 29 PCIE_TXN2 29 PCIE_TXP2
1C238 1C236
2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP
30 PCIE_RXN3 30 PCIE_RXP3 30 PCIE_TXN3 30 PCIE_TXP3
1C242 1C240
2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP
30 PCIE_RXN4 30 PCIE_RXP4 30 PCIE_TXN4 30 PCIE_TXP4
1C247 1C244
2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP
28 PCIE_RXN5 28 PCIE_RXP5 28 PCIE_TXN5 28 PCIE_TXP5
1C254 1C251
2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP
ICH_SMBCLK 4,14,15
SD
38 38 35 35
3D3V_S5
32K suspend clock output
1
1 2
GPIO
SATA
2 2 R347 10KR2J-3-GP
2 0R0402-PAD
EC_RMRST#
E1
CK_PWRGD 4 CL_PWRGD_R
E3
SLP_M#
CLOCKS
SLP_M#
AJ25
CL_CLK0 CL_CLK1
F23 AE18
CL_CLK0 CL_CLK1
CL_DATA0 CL_DATA1
F22 AF19
CL_DATA0 CL_DATA1
CL_VREF0 CL_VREF1
D24 AH23
CL_VREF0_ICH CL_VREF1_ICH
CL_RST#
AJ23
CLGPIO0/GPIO24 CLGPIO1/GPIO10 CLGPIO2/GPIO14 CLGPIO3/GPIO9
AJ27 AJ24 AF22 AG19
R411 1 TP66
DY
1
2 0R2J-2-GP
VGATE_PWRGD 8,41 PM_PWROK
2
R346
0R2J-2-GP
CL_CLK0 8 TP110
CL_DATA0 8 TP103
R422 1
CL_RST# 8
GPIO24 GPIO10 GPIO14 GPIO9
C598
TP73 TP64 TP99 TP100
2
3D3V_S0
3K24R2F-GP
R423 453R2F-1-GP C
R110
3
ICH_32KHZ
2
1 R93
2 10R2J-2-GP
P27 P26 N29 N28
PERN1 PERP1 PETN1 PETP1
1
C201
2
3D3V_S5
3K24R2F-GP R107 453R2F-1-GP
PCIE_C_TXN4 PCIE_C_TXP4
H27 H26 G29 G28
PERN4 PERP4 PETN4 PETP4
PCIE_C_TXN5 PCIE_C_TXP5
F27 F26 E29 E28
PERN5 PERP5 PETN5 PETP5
D27 D26 C29 C28
PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP
C23 B23 E22
SPI_CLK SPI_CS0# SPI_CS1#
D23 F21
SPI_MOSI SPI_MISO
SPI_CS1#
TP128
USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#8 USB_OC#9
USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3
2
AJ19 AG16 AG15 AE15 AF15 AG17 AD12 AJ18 AD14 AH18
PERN2 PERP2 PETN2 PETP2 PERN3 PERP3 PETN3 PETP3
OC0# OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31 OC8# OC9#
0R2J-2-GP D28
G792_CLK 36
EC_RMRST#
1
TSLVC08APW-1-GP
DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0
8 8 8 8
DMI1RXN DMI1RXP DMI1TXN DMI1TXP
Y27 Y26 W29 W28
DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1
DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1
8 8 8 8
DMI2RXN DMI2RXP DMI2TXN DMI2TXP
AB26 AB25 AA29 AA28
DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2
DMI_RXN2 8 DMI_RXP2 8 DMI_TXN2 8 DMI_TXP2 8
DMI3RXN DMI3RXP DMI3TXN DMI3TXP
AD27 AD26 AC29 AC28
DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3
DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3
T26 T25
DMI_ZCOMP DMI_IRCOMP
Y23 Y24
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P
G3 G2 H5 H4 H2 H1 J3 J2 K5 K4 K2 K1 L3 L2 M5 M4 M2 M1 N3 N2
USBRBIAS# USBRBIAS
F2 F3
ICH8-M-1-GP-U-NF
DY 3
DY
DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0
DMI_CLKN DMI_CLKP
USB
3D3V_S0
V27 V26 U29 U28
DMI0RXN DMI0RXP DMI0TXN DMI0TXP
PCIE_C_TXN3 PCIE_C_TXP3
2
1
2
14
DY
PM_PWRBTN# 34 1 R112
CLPWROK
K27 K26 J29 J28
R327
U20A
7
AG27
PCIE_C_TXN2 PCIE_C_TXP2
R351 2K2R2J-2-GP
1 ICH_SUSCLK
RSMRST#
M27 M26 L29 L28
1
1
3D3V_S5 R91 10KR2J-3-GP
DY
SMB
PCIE_C_TXN1 PCIE_C_TXP1
SMB_DATA 28,29,30
2N7002SPT
3D3V_S0
1C234 1C232
2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP
VF
1 2
New Card U55
28,29,30 SMB_CLK
TP3
C2 AH20
1
U27B 2 OF 6
Mini Card 1
4,14,15 ICH_SMBDATA
MCH_SYNC#
PWRBTN# LAN_RST#
CK_PWRGD
SB:71.ICH8M.C0U
10KR2J-3-GP SB_SPKR 1 2 R361 DY
SB:06/27 Add R450 for "ECSWI#" pull up to 3D3V_S5
LAN
B
PM_BATLOW#_R
ICH8-M-1-GP-U-NF
High--> No boot
DPRSLPVR 1 100KR2J-1-GP GPIO9 1 100KR2J-1-GP
R341 2
AE21
BATLOW#
PM_PWROK 8,36 DPRSLPVR 8,41
2
2 ECSWI# 10KR2J-3-GP
DPRSLPVR
R116 330R2J-3-GP R117 1 0R2J-2-GP
1
R450 1
AJ14
-c
2 USB_OC#3 10KR2J-3-GP
SPKR
Low--> default
SRN10KJ-6-GP R369 1
TP7 TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 GPIO12 TACH0/GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 QRT_STATE0/GPIO27 QRT_STATE1/GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48
PM_PWROK
DPRSLPVR/GPIO16
D
DY
R118 1 0R2J-2-GP
3
C
AJ8 AJ9 AH9 AE16 AC19 GPIO17 AG8 TP98 GPIO18 AH12 TP69 GPIO20 AE11 TP112 GPIO22 AG10 AH25 TP63 AD16 TP111 CLKSATAREQ# AG13 4 CLKSATAREQ# GPIO38 AF9 TP104 GPIO39 AJ11 TP70 IDE_RESET# AD10 TP109
34 ECSCI# 34 ECSMI# 34 ECSWI#
SB:06/27 Change RN68 pin1 define from"ECSWI#" to "GPIO22", pin 8 connection from 3D3V_S5 to 3D3V_S0.
AJ22
GPIO1 GPIO6 ECSCI# ECSMI#
TP72 TP71
GPIO26
AE23
2
CK_PWRGD
2
VRMPWRGD
Q12 2N7002PT-U 1
41 CLK_EN# G
2
1 2 3 4
VRMPWRGD
AH27
PWROK
1
DY
SMB_LINK_ALERT# PCIE_WAKE# ICH_RI# USB_OC#0 SRN10KJ-6-GP
8 7 6 5
AJ20
INT_SERIRQ THRM#
S4_STATE#/GPIO26
o-
3D3V_S0
WAKE# SERIRQ THRM#
DY
2
SRN10KJ-6-GP 8 7 6 5
AE17 AF12 AC13
VRMPWRGD 2 0R2J-2-GP SST_CTL TP67
1 R342
8,41 VGATE_PWRGD
RN65 1 2 3 4
CLKRUN#
C522 SC4D7P50V2CN-1GP
D
1
27,28 PCIE_WAKE# 25,34 INT_SERIRQ 36 THRM#
GPIO26 PM_BATLOW#_R OCP# SMLINK1
8 7 6 5
AH11
25,34 PM_CLKRUN#
RN64 1 2 3 4
STP_PCI# STP_CPU#
DY
PM_SLP_S3# 28,34,43,45,46 PM_SLP_S4# 28,34,40,44,45
2
RSMRST#_KBC 10KR2J-3-GP
SMBALERT#/GPIO11
AE20 AG18
D3 AG23 AF21 AD18
Direct Media Interface
2
AG22
H_STP_PCI# H_STP_CPU#
SUSCLK SLP_S3# SLP_S4# SLP_S5#
PCI-Express
1 R96
OCP#
DY
C589 SC4D7P50V2CN-1GP
ICH_SUSCLK
SPI
DY
BMBUSY#/GPIO0
R349 10R2J-2-GP
DY
CLK_14M_ICH 4 CLK_48M_ICH 4
SCD1U16V2KX-3GP 2 1
1 2 4 H_STP_PCI# 4 H_STP_CPU#
SUS_STAT#/LPCPD# SYS_RESET#
AG12
AG9 G5
CLK14 CLK48
SCD1U16V2KX-3GP 2 1
DY 3D3V_S5
F4 AD15
PM_BMBUSY#
R400 10R2J-2-GP
cc
8 PM_BMBUSY#
RI#
SYSGPIO
RN70 SRN2K2J-1-GP
AF17
PM_SUS_STAT# DBRESET#
SATA0_R0 SATA0_R1 SATA0_R2 SATA0_R3
AJ12 AJ10 AF11 AG11
SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36 GPIO37
POWER MGT
TP124
4 3
ECSCI# 2 10KR2J-3-GP
R449 1
ICH_RI#
SMBCLK SMBDATA LINKALERT# SMLINK0 SMLINK1
GPIO
3D3V_S0
AJ26 AD19 AG21 AC17 AE19
Controller Link
SB:06/27 Delete RN74, add R449 for "ECSCI#" pull up to 3D3V_S0
SMB_CLK SMB_DATA SMB_LINK_ALERT# SMLINK0 SMLINK1
MISC
SRN10KJ-6-GP
D
1 2
SATA0_R0 SATA0_R1 THRM# CLKSATAREQ#
8 7 6 5
1 2
U27D 4 OF 6
SRN10KJ-6-GP RN62 1 2 3 4
CLK_14M_ICH
1
RN63 SRN2K2J-1-GP
2
PM_CLKRUN# SATA0_R3 SATA0_R2 INT_SERIRQ
8 7 6 5
4 3
1 2 3 4
CLK_PCIE_ICH# CLK_PCIE_ICH DMI_IRCOMP 1 R376
USBRBIAS 1 R403
S B
CLK_PCIE_ICH# 4 CLK_PCIE_ICH 4
Within 500 mils 2 24D9R2F-L-GP USB_PN0 USB_PP0 USB_PN1 USB_PP1 USB_PN2 USB_PP2 USB_PN3 USB_PP3 USB_PN4 USB_PP4 USB_PN5 USB_PP5 USB_PN6 USB_PP6 TP118 TP117 USB_PN8 USB_PP8 USB_PN9 USB_PP9
USB_PN7 USB_PP7
8 8 8 8
2 20R2F-GP
1D5V_S0
38 38 38 38 35 35 35 35 30 30 31 31 18 18
USB1 USB2 USB3 USB4 MINICARD2 BlUETOOTH CAMERA
28 28 30 30
New Card MINICARD3 SB:0710 Change R403 from 22.6 Ohm to 22 Ohm
Within 500 mils
SB:71.ICH8M.C0U RSMRST#_KBC 34
2 2
A
SB:06/20 Add 2N7002 Q35 for G792 "G792_CLK"
A
BAS16-1-GP R350 100KR2J-1-GP
1
2
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
G
1
D
3
S
Q35 2N7002PT-U
RUN_POWER_ON
Title
ICH8(3/4) PM,USB,GPIO Size Custom
Document Number
Rev
DS2-Intel
Date: Wednesday, September 12, 2007 5
4
3
2
Sheet 1
-1 21
of
47
5
4
3
2
+RTCVCC
1
U27F 6 OF 6
20 mils
1
VCCSUS1_5
VCC1_5_A VCC1_5_A
D1
VCCUSBPLL
F1 L6 L7 M6 M7
VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A
W23
VCC1_5_A
F17 G18
VCCLAN1_05 VCCLAN1_05
1
1 2
SC1U10V3ZY-6GP
1 2
SC1U10V3ZY-6GP
1 2
1
1 2
SCD1U16V2ZY-2GP 2
1 2
SCD1U16V2ZY-2GP
1 2 1
2
2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
TP120 TP102
AC16
VCCSUS1_5_ICH_1
VCCSUS1_5
J7
VCCSUS1_5_ICH_2
VCCSUS3_3
C3
VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3
AC18 AG20 AC21 AC22 AH28
VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3
P6 P7 N7 C1 P1 R1 P2 P3 R3 P4 P5 R5 R6
VCCCL1_05
G22
VCCCL1_05_ICH
VCCCL1_5
A22
VCCCL1_5_ICH
VCCCL3_3 VCCCL3_3
F20 G21
3D3V_S5
3D3V_S0
C583
C571
TP119
2
TP113
3D3V_S5
SCD1U16V2ZY-2GP C567
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
cc 2
1
1 2
1 2
SCD1U16V2ZY-2GP
1 2
1
SCD1U16V2ZY-2GP
1
AC7 AD7
o-
VCCSUS1_05 VCCSUS1_05
VCC1_5_A VCC1_5_A VCC1_5_A
C536 SCD1U16V2ZY-2GP
1
VCC1_5_A VCC1_5_A
J6 AF20
SCD1U16V2ZY-2GP
2
AC12 AD11
C596
1
VCCHDA VCCSUSHDA
C541
2
G12 G17 H7
SCD1U16V2ZY-2GP
1 2
SCD1U16V2ZY-2GP
3D3V_S0
SCD1U16V2ZY-2GP
C554
C558 SCD1U16V2ZY-2GP
2
VCC1_5_A VCC1_5_A
AA5 AA6
C579
(DMI) C595
(SATA) C600
1
AC10 AC9
3D3V_S0
C546 SCD1U16V2ZY-2GP
1
VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A
1D05V_S0
2
A8 B15 B18 B4 B9 C15 D13 D5 E10 E7 F11
1
VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3
1D5V_S0
2
AA3 U7 V7 W1 W6 W7 Y7
3D3V_S0 3D3V_S0
1
VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3
C273
C228 SC10U6D3V5KX-1GP
SCD1U16V2ZY-2GP 3D3V_S0 SCD1U16V2ZY-2GP
2
CORE
AC8 AD8 AE8 AF8
C272
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
3D3V_S5
C224
VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF
K7 L1 L13 L15 L26 L27 L4 L5 M12 M13 M14 M15 M16 M17 M23 M28 M29 M3 N1 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 N4 N5 N6 P12 P13 P14 P15 P16 P17 P23 P28 P29 R11 R12 R13 R14 R15 R16 R17 R18 R28 R4 T12 T13 T14 T15 T16 T17 T2 U12 U13 U14 U15 U16 U17 U23 U26 U27 U3 U5 V13 V15 V28 V29 W2 W26 W27 Y28 Y29 Y4 AB4 AB23 AB5 AB6 AD5 U4 W24 ICHGND1 A1 A2 A28 A29 ICHGND2 AJ28 AH1 AH29 AJ1 ICHGND3 AJ2 AJ29 ICHGND4 B1 B29
D
C
TP78 TP77
TP65 TP74 B
ICH8-M-1-GP-U-NF
VF
1D5V_S0
C216 SC10U6D3V5KX-1GP
1
C212 SC1U10V3ZY-6GP
1 2
C235 SC10U6D3V5KX-1GP
2
1
2
SCD1U16V2ZY-2GP
1D5V_S0
VCC_LAN1_05_INT_ICH_1 VCC_LAN1_05_INT_ICH_2
2
1 C584
VCC3_3 VCC3_3 VCC3_3 VCC3_3
C195
-c
1D5V_S0 TP126 TP121
AD2
2
AC1 AC2 AC3 AC4 AC5
B
3D3V_S0
AF29
VCC3_3
1
2
2
C574 SCD1U16V2ZY-2GP
VCC3_3
2
1
1
1D5V_S0 C547
AC23 AC24
C196
1D25V_S0 C208
SC4D7U6D3V3KX-GP
1D5V_S0
SCD1U16V2ZY-2GP
V_CPU_IO V_CPU_IO
2
SC1U10V3ZY-6GP
AE28 AE29
C551
L5 1 2 IND-1UH-36-GP
C226 SCD01U16V2KX-3GP
1
1D5V_S0 C199
VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A
VCCPSUS
SC1U10V3ZY-6GP
AE7 AF7 AG7 AH7 AJ7
2
C233
1
1D5V_S0
C200 SC10U6D3V5KX-1GP
1 2
1 2
SC1U10V3ZY-6GP
C198
C573
R29
VCC_DMI VCC_DMI
VCCSATAPLL
C576
1D5V_DMIPLL_S0
1
AJ6
1D5V_S0
C580
2
2
C
C588 SCD1U16V2ZY-2GP
VCCPUSB
3
ICH_V5REF_SUS
1
2
20 mils
ATX
2
D20
100R2J-2-GP
VCCDMIPLL
VCCP CORE
1
C221 SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
1
BAS16-1-GP
2
2 2
1 R147
C197
SC2D2U10V3ZY-1GP 2 1
SC2D2U10V3ZY-1GP
2 3D3V_S5
1
5V_S5
C220
A13 B13 C13 C14 D14 E14 F14 G14 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18
SC10U6D3V5KX-1GP
1
C217
VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B
3D3V_S0
F19 G20
VCCLAN3_3 VCCLAN3_3
A24
VCCGLANPLL
A26 A27 B26 B27 B28
VCCGLAN1_5 VCCGLAN1_5 VCCGLAN1_5 VCCGLAN1_5 VCCGLAN1_5
B25
VCCGLAN3_3
GLAN POWER
3 1
2
20 mils ICH_V5REF_RUN C555 SCD1U16V2ZY-2GP
V5REF_SUS
IDE
R387 100R2J-2-GP
AA25 AA26 AA27 AB27 AB28 AB29 D28 D29 E25 E26 E27 F24 F25 G24 H23 H24 J23 J24 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T23 T24 T27 T28 T29 U24 U25 V23 V24 V25 W25 Y25
V5REF V5REF
PCI
1 2
1 2
1
C213 SC1U10V3ZY-6GP
BAS16-1-GP D18
C262 SC1U10V3ZY-6GP
2
1
1
3D3V_S0
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
5V_S0
C215
2
C260
2
1
1D5V_S0
VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05
VCCA3GP
G4
ARX
ICH_V5REF_SUS
5 OF 6
VCCRTC
SC10U6D3V5KX-1GP
T7 A16
USB CORE
2
SCD1U16V2ZY-2GP
2
SCD1U16V2ZY-2GP
1D05V_S0 U27E
AD25 ICH_V5REF_RUN
SC10U6D3V5KX-1GP
D
A23 A5 AA2 AA7 A25 AB1 AB24 AC11 AC14 AC25 AC26 AC27 AD17 AD20 AD28 AD29 AD3 AD4 AD6 AE1 AE12 AE2 AE22 AD1 AE25 AE5 AE6 AE9 AF14 AF16 AF18 AF3 AF4 AG5 AG6 AH10 AH13 AH16 AH19 AH2 AF28 AH22 AH24 AH26 AH3 AH4 AH8 AJ5 B11 B14 B17 B2 B20 B22 B8 C24 C26 C27 C6 D12 D15 D18 D2 D4 E21 E24 E4 E9 F15 E23 F28 F29 F7 G1 E2 G10 G13 G19 G23 G25 G26 G27 H25 H28 H29 H3 H6 J1 J25 J26 J27 J4 J5 K23 K28 K29 K3 K6
C532
1
C530
TP122 TP79
R399 1 3D3V_S0 2 0R0603-PAD
ICH8-M-1-GP-U-NF
SB:71.ICH8M.C0U
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
ICH8(4/4) POWER&GND Size A2 Date: 5
4
3
2
Document Number
Rev
DS2-Intel Wednesday, September 12, 2007 1
Sheet
-1 22
of
47
A
B
C
D
E
SB:06/22 Change R279,R280,R281,R282 from 63.30134.1DL to 63.12134.1DL HDMI_TXD#1
16 HDMI_TXD#1
16 HDMI_TXD1 4
HDMI_TXD0
HDMI_TXD#1_1 1 2 120R2J-2-GP C455 HDMI_TXD1
1 R281
2 SCD1U10V2KX-4GP
HDMI_TXD#2
16 HDMI_TXD#2
16 HDMI_TXD2
2 SCD1U10V2KX-4GP HDMI_TXD#0 16
HDMI_TXC
HDMI_TXD#2_2 1 2 120R2J-2-GP C456 HDMI_TXD2
1 R282
HDMI_TXD0 16
2 HDMI_TXD#0_0 1 120R2J-2-GP C454 HDMI_TXD#0
1 R280
2 SCD1U10V2KX-4GP
4
HDMI_TXC 16
2 HDMI_TX#C_C1 1 120R2J-2-GP C453 HDMI_TX#C
1 R279
2 SCD1U10V2KX-4GP HDMI_TX#C 16
HDMI_HDP 16
1
1
1
1
PVCC2
1
3D3V_S0
C457 SC10U6D3V5KX-1GP
2
DY
C462 SC1U6D3V2KX-GP
1 2
C451 SCD1U10V2KX-4GP
2
3D3V_S0
1
C495 SC1KP50V2KX-1GP
1 2
C496 SCD1U10V2KX-4GP
R314 1 0R0603-PAD
R311 1 1D8V_S0 0R0603-PAD
C491
2
1
1
2
1
C489 SC1U6D3V2KX-GP
2
o2
2
PVCC1
R287 2 1 0R0603-PAD
2 R283 1 0R0603-PAD
1D8V_S0
R72 2 1 0R0603-PAD
C152 SC1U6D3V2KX-GP
39 37
C150 SCD1U10V2KX-4GP
1
C151 SC1KP50V2KX-1GP
2
1
63
2
SPGND
SPVCC
1
41 45 53 59 62
VF
SII1392CNU-GP-U
1D8V_S0 2
ICH_AZ_S1392_BITCLK 2 0R2J-2-GP
1 R345
1
20,31,32 HDA_BITCLK
2
1
TEST
GND GND SGND SGND SPVCC
SVCC
2
44
50 56
C497 SC10U10V5KX-2GP
SCLROM SDAROM
SVCC SVCC
2
14 13
DY
SC10U6D3V5KX-1GP
-c
SDADDC SCLDDC
1
12 11
C494 SC1KP50V2KX-1GP
SB: 0710 Change R345 from 33 Ohm to 0 Ohm
A1
SPDIF/HDASDO LSCL/DCEN LSDA/PREEMP LINT#
2
8
PVCC2 AVCC33V VCC_PWR
34 4 3 15
16 HDMI_SDATA 16 HDMI_SCLK
A1 2 1KR2J-1-GP HDMI_SDATA HDMI_SCLK
HDASYNC
1 R81
RESET# SDSCL SDSDA
C488
1
31 32 33
1 7 6
PVCC1
2
PVCC2 AVCC3.3 VCC
8,19,24,28,29,30,34 PLT_RST1# 8 SDVO_CTRLCLK 8 SDVO_CTRLDATA
EXT_RES
30mA 1
17
49
OVCC
AVCC33V
2
PVCC1
2 EXT_RES 1KR2J-1-GP
SDC+ SDC-
40
1 R312
60 61
DY
SC10U6D3V5KX-1GP R313 2 1 3D3V_S0 0R0603-PAD
1
OVCC
64
SDVOB_C+ SDVOB_C-
10 SDVOB_C+ 10 SDVOB_C-
3
1D8V_S0
C459 C452 SC1KP50V2KX-1GP SC1KP50V2KX-1GP
18 24 30 65
1 0R0603-PAD
2
AGND AGND AGND GND
R77
2
C154
1
SDB+ SDB-
LAYOUT must support connectors from JAE, Molex, and Acon
C149 SC1KP50V2KX-1GP
57 58
SDVOB_B+ SDVOB_B-
10 SDVOB_B+ 10 SDVOB_B-
AVCC
1D8V_S0
C481 SC10U6D3V5KX-1GP
2
21 27
R309 2 1 0R0603-PAD
2
AVCC AVCC
2
SDG+ SDG-
C466 SCD1U10V2KX-4GP
54 55
2
SDVOB_G+ SDVOB_G-
HDARST# HDASDI
10 SDVOB_G+ 10 SDVOB_G-
35 36
3
C485 SCD1U10V2KX-4GP
5 10
cc
GND GND
C472 SC1KP50V2KX-1GP
SDR+ SDR-
2
51 52
1
SDVOB_R+ SDVOB_R-
HDABCLK HDAVCC
10 SDVOB_R+ 10 SDVOB_R-
2
SDI+ SDI-
2
46 47
550mA
VCC_PWR
SC10U6D3V5KX-1GP
2 43 9 48 38
1
42 16
20 19 TXC+ TXC-
23 22 TX0+ TX0-
VCC VCC VCC VCC VCC
C471 SC100P50V2JN-3GP
2SCD1U10V2KX-4GP S_INT+ 2SCD1U10V2KX-4GP S_INT-
AVCC 2 560R2F-GP
1 R291
SB:06/22 Change R291 from 64.75005.6DL to 64.56005.6DL
HTPLG EXT_SWING
10 SDVOB_INT+ 10 SDVOB_INT-
C482 1 C487 1
TX1+ TX1-
TX2+ TX2-
29 28
U52
26 25
EXT_SWING1
1 2
R304 0R0603-PAD
2
1
DY
1 AUD_SPDIF_OUT 22R2J-2-GP ICH_AZ_S1392_SDOUT
2
ICH_AZ_S1392_SYNC
3D3V_S0
2D5V_S0
AUD_SPDIF_OUT
32
ICH_SDOUT_CODEC ICH_AZ_CODEC_SYNC
4 3
1 4K7R2J-2-GP
RN57 SRN4K7J-8-GP
20,31,32 20,31,32
4K7R2J-2-GP R75
HDAVCC
1
R294
R303
2
R306
DY
2
3D3V_S0
R80 4K7R2J-2-GP
2
1
ICH_AZ_S1392_SDIN2_C 2 R297 ICH_AZ_S1392_RST#
DY
1 33R2J-2-GP
ICH_SDIN_S1392
SDVO_CTRLCLK SDVO_CTRLDATA
20
1 2
DY
ICH_AZ_S1392_RST# 20
4K7R2J-2-GP
2
C161 SCD1U10V2KX-4GP
-1:09/06 Change EC83 from ASM to DUMMY.
1
EC83 SC22P50V2JN-4GP
1
Wistron Corporation
DY
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
2
1
ICH_AZ_S1392_BITCLK
Title
SiI 1392 HDMI Size A3
Document Number
Rev
A
B
C
D
-1
DS2-Intel
Date: Wednesday, September 12, 2007
Sheet E
23
of
47
SATA HD Connector
CD-ROM Connector IDE_PDD[0..15]
HDD1
23 NP1 1
1
1
C253 SCD1U16V2ZY-2GP
DY
2
DY
2
C258 SC10U6D3V5KX-1GP
1
C268 SCD1U16V2ZY-2GP
2
2
-1:09/02 Change HDD power net from "5V-S0" to "ODD_5V_S0" for Sniffer function circuit.
C264 SC10U10V5ZY-1GP
1
HDD_5V_S0
20 IDE_PDDREQ 20 IDE_PDIOR# 20 IDE_PDDACK#
-1:09/02 Change ODD power net from "5V-S0" to "ODD_5V_S0" for Sniffer function circuit.
IDE_PDA2
20 IDE_PDA2 20 IDE_PDCS3#
ODD_5V_S0
C186 SC10U10V5ZY-1GP
SYN-CON22-GP-U
C191
SCD1U16V2ZY-2GP
4 3
RSTDRV#_5 IDE_PDD7 IDE_PDD6 IDE_PDD5 IDE_PDD4 IDE_PDD3 IDE_PDD2 IDE_PDD1 IDE_PDD0
RN23 SRN8K2J-3-GP
1 2
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NP2 24
1
SC3900P50V2KX-2GP 3D3V_S0
2
SATA_RXN0 SATA_RXP0
cc
2 2
3D3V_S0
52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 51
49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15
1
C564 1 C568 1
20 SATA_RXN0_C 20 SATA_RXP0_C
2 3 4 5 6 7
SC3900P50V2KX-2GP
2
20 SATA_TXP0 20 SATA_TXN0
20
CDROM1
IDE_PDIOW#
20 IDE_PDIORDY 20 INT_IRQ14 20
IDE_PDA1 IDE_PDA0
IDE_PDA1 20 IDE_PDA0 20 IDE_PDCS1# 20
ODD_5V_S0 CSEL
-1:09/02 Change ODD power net from "5V-S0" to "ODD_5V_S0" for Sniffer function circuit.
GND : Master Open: Slave
FOX-CONN50-4R-4GP
o-
Main Source:20.80919.022
2
4
3
1
DY
R466 100KR2J-1-GP
DY
2
U68 ODD_5V_EN_R
6
1
5
2
4
3
R462 100KR2J-1-GP
Q38
6
2
5
3
4
2 0R3-0-U-GP
R469 1
2 0R3-0-U-GP
R471 1
2 0R3-0-U-GP
5V_S0
RUN_POWER_ON
DY
ODD_5V_S0
R467 100KR2J-1-GP U35
8 7 6 5
-1:09/02 Add ODD 5V power control circuit for Sniffer function, default is DY
1 2 3 4
SI4800BDY-T1
DY
1
2 0R3-0-U-GP
R468 1
2N7002SPT
HDD_5V_S0
1
DY
R470 1
HDD_5V_EN 34
HDD_5V_EN 34
5V_S0
ODD_5V_S0
5V_S5
-1:09/02 Add HDD 5V power control circuit for Sniffer function, default is DY
RUN_POWER_ON 2N7002SPT
5V_S0
1
5
IDE_PDIOW# 2 4K7R2J-2-GP
1
2
1
R97
TSAHCT125PW-GP
ODD_PWR_EN
-1:0910
HDD_PWR_EN
FDC655BN-GP
-1:0910
-1:0906 Add C639 for "ODD_5V_EN#"
DY
1
6
2 0R3-0-U-GP
2
HDD_5V_EN_R
2 0R3-0-U-GP
R464 1
2 RSTDRV#_5 56R2J-4-GP
C639
2
DY
2
U67
R463 1
U9C
IDE_RST_MOD#1 R100
SCD1U25V3KX-GP
R461 100KR2J-1-GP
VF
1
5V_S5
7
-c HDD_5V_S0
8
D D D D
5V_S0
DY
9
PLT_RST1#
Close to Connector
G S S S
8,19,23,28,29,30,34
3D3V_S0
10
14
5V_S0
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
HD/CDROM/USB Size A3
Document Number
Rev
DS2-Intel
Date: Wednesday, September 12, 2007
Sheet
-1 24
of
47
5
4
3
2
1
3D3V_S0
3D3V_S0
2
DY
C331 SCD1U16V2ZY-2GP
PCI_C/BE#3 19 PCI_C/BE#3 PCI_C/BE#2 19 PCI_C/BE#2 PCI_C/BE#1 19 PCI_C/BE#1 PCI_C/BE#0 19 PCI_C/BE#0 1 2 R5C834_IDSEL R150 10R2J-2-GP
19 PCI_REQ#0 19 PCI_GNT#0 19 PCI_FRAME# 19 PCI_IRDY# 19 PCI_TRDY# 19 PCI_DEVSEL# 19 PCI_STOP# 19 PCI_PERR# 19 PCI_SERR#
GBRST#
19,27 PCIRST1#
4 PCLK_PCM
SHIELD GND
19 ICH_PME#
2
21,34 PM_CLKRUN# R151 10KR2J-3-GP
DY
AGND1 AGND2 AGND3 AGND4 AGND5
124 123 23 24 25 26 29 30 31
REQ# GNT# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR#
71 119
GBRST# PCIRST#
121
PCICLK
R178
2
DY
1 0R2J-2-GP
70
117
PME#
1
1
2
2
cc
GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10
C290 SC10U6D3V5KX-1GP
4 13 22 28 54 62 63 68 118 122 99 102 103 107 111
C
3D3V_S0
1
R177 4K7R2J-2-GP
3D3V_S0
2
MSEN
58
XDEN
55
1 2 3 4
UDIO5
57
UDIO3 UDIO4
65 59
UDIO2
56
UDIO1
60
UDIO0/SRIRQ#
72
1 R164
RN43
8 7 6 5
1
69
DY
2
HWSPND#
EC44 SCD1U16V2ZY-2GP
SRN10KJ-6-GP
2 100KR2J-1-GP
3D3V_S0
B
INT_SERIRQ 21,34
INTA#
115
PCI_PIRQA# 19
INTB#
116
PCI_PIRQC#
19
1394 : INTA# 4in1 : INTB# TEST
66
CLKRUN#
2
1 2
R179
R173 100KR2J-1-GP
1
1
R5C833-GP
1
1 2 0R2J-2-GP
34 GBRST#_KBC
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 PAR C/BE3# C/BE2# C/BE1# C/BE0# IDSEL
C283
86
-c
R180 10KR2J-3-GP
D
VCC_ROUT1 VCC_ROUT2 VCC_ROUT3 VCC_ROUT4 VCC_ROUT5
VF
1
B
PCI_AD25
125 126 127 1 2 3 5 6 9 11 12 14 15 17 18 19 36 37 38 39 40 42 43 44 46 47 48 49 50 51 52 53 33 7 21 35 45 8
67
o-
PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0
C
3D3V_S0
VCC_RIN
VCC_MD
19 PCI_AD[0..31]
19 PCI_PAR
61
VCC_3V
PCI / OTHER
1 2
C280
SCD01U16V2KX-3GP
SCD47U16V3ZY-3GP
C278
SCD47U16V3ZY-3GP
1 2
C319
SCD01U16V2KX-3GP 2 1
1 2
1 2
C297
SCD1U16V2ZY-2GP
VCC_PCI1 VCC_PCI2 VCC_PCI3 VCC_PCI4 VCC_PCI5 VCC_PCI6
16 34 64 114 120
VCC_ROUT C282
10 20 27 32 41 128
SCD01U16V2KX-3GP
C326
SCD01U16V2KX-3GP
1
C312
2
SCD01U16V2KX-3GP
C279
SCD01U16V2KX-3GP 2 1
1
SCD01U16V2KX-3GP 2 1
3D3V_S0
C281
2
SCD01U16V2KX-3GP
1
C288
2
DY
2
D
1
U37B C325 SC10U6D3V5KX-1GP
2
DY
A
C293 SC10P50V2JN-4GP
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
R5C833/PCI Size A3
Document Number
Rev
DS2-Intel
Date: Wednesday, September 12, 2007
Sheet
-1 25
of
47
A
B
C
D
E
3D3V_PHY 3D3V_S0 2 R174 1 0R0603-PAD
1
C303 SCD01U16V2KX-3GP
-1:09/11
2
1
113
94 X4 X-24D576MHZ-70GP
XI
1 R170
XO
RICHO_FILO 2 SCD01U16V2KX-3GP
96
2RICHO_REXT 10KR2F-2-GP
101
REXT
RICHO_VREF 2 SCD01U16V2KX-3GP
100
VREF
FIL0
104
TPB0N
TPBP0
105
TPB0P
TPAN0
108
TPA0N
TPAP0
109
TPA0P
R90
CLOSE TO CHIP
R89
4
C189
3 4 DLW21HN900SQ2LGP
SCD01U16V2KX-3GP
1
TPB0+
R316
2 0R0402-PAD
R321
2 0R0402-PAD
TPBIAS0 TPA0P TPA0N TPB0P TPB0N
SCD33U10V3KX-3GP
-1:09/11 1
CN8
3L28
SB:06/16 change 1394 CONN CN8 from 22.10218.M01 to 22.10218.T41.
TPB0-
2
R95 2 5K1R2F-2-GP 56R2J-4-GP 1394_TPB1_R 1 2 1 2 C192 R94 SC270P50V2JN-2GP 56R2J-4-GP
1 R92
4
DY
1 DLW21HN900SQ2LGP
cc
1 C324
95
IEEE1394/SD
1394_XO 2 SC12P50V2JN-3GP
TPBN0
C190
1
DY TPA0-
6 5 4 3 2 1
GND GND TPA0+ TPA0TPB0+ TPB0-
2 C330 1
1
TPBIAS0
1
SB:06/13 Change X4 from 82.30023.561 to 82.30023.611
TPBIAS0
2
SC12P50V2JN-3GP 1394_XI 2
1
C329 1
2
2
4
TPA0+
1
L27
SKT-1394-4P-26-GP-U
1
SCD1U16V2ZY-2GP
2 0R0402-PAD
R318
2
1
C308
2
GUARD GND
C323 SC10U6D3V5KX-1GP
98 106 110 112
2
AVCC_PHY1 AVCC_PHY2 AVCC_PHY3 AVCC_PHY4
Reserve R547,R548,R550,R551 for co-layout
1
3D3V_PHY
2
U37A
1
R319
2
1
2 0R0402-PAD
SC:08/20 Change R95 from 64.51115.6DL to 64.51015.6DL.
-1:09/11
3D3V_CARD
XD_DATA7
92
XD_DATA6
MDIO15
89
XD_DATA5
MDIO14
91
XD_DATA4
MDIO13
90
SD/XD/MS_DATA3
MDIO12
93
SD/XD/MS_DATA2
MDIO11
81
SD/XD/MS_DATA1
MDIO10
82
SD/XD/MS_DATA0
MDIO05
75
XD_WP#
MDIO08
88
SD/XD/MS_CMD
MDIO19
83
XD_ALE
MDIO18
85
XD_CLE
MDIO02
78
XD_CE#
MDIO03
77
SD_WP#(XDR/B#)
MDIO00
80
MDIO01
79
MS_INS#
MDIO09
84
SD/XD/MS_CLK
3
o-
1
1
1SD/XD/MS_DATA0_1 2SD/XD/MS_DATA1_1 3SD/XD/MS_DATA2_1 4SD/XD/MS_DATA3_1
RN71
XD_ALE 2 SD/XD/MS_CMD 1
3 4
3D3V_CARD
XD_ALE_1 SD/XD/MS_CMD_1
CARD1
23 14 33
SD_VCC MS_VCC XD_VCC
SD/XD/MS_DATA0_1 SD/XD/MS_DATA1_1 SD/XD/MS_DATA2_1 SD/XD/MS_DATA3_1 XD_DATA4_1 XD_DATA5_1 XD_DATA6_1 XD_DATA7_1
8 9 26 27 28 30 31 32
XD_D0 XD_D1 XD_D2 XD_D3 XD_D4 XD_D5 XD_D6 XD_D7
SD_WP#(XDR/B#) SD/XD/MS_CLK_1 XD_CE#_1 XD_CLE_1 XD_ALE_1 SD/XD/MS_CMD_1 XD_WP# XD_SW#
1 2 3 4 5 6 7 34
XD_R/B XD_RE XD_CE XD_CLE XD_ALE XD_WE XD_WP XD_CD_SW
-c
SRN33J-5-GP-U
XD_CE# XD_CLE
3 4
XD_CE#_1 XD_CLE_1
SRN33J-5-GP-U
D19
SD_CD#
SB:06/20 Rename U37 Pin79 from"XD/MS_CD#" to "MS_INS#"
1
2
MS_INS#
1
SD_CD#
2
3
SD/XD/MS_CLK_1
76
MC_PWR_CTRL_0
MDIO06
74
MS_LED#
MDIO07
73
25 29 10 11
SD/XD/MS_DATA0_1 SD/XD/MS_DATA1_1 SD/XD/MS_DATA2_1 SD/XD/MS_DATA3_1
SD_CMD SD_CLK SD_CD_SW SD_WP_SW
12 24 36 35
SD/XD/MS_CMD_1 SD/XD/MS_CLK_1 SD_CD# SD_WP#(XDR/B#)
MS_DATA0 MS_DATA1 MS_DATA2 MS_DATA3
19 20 18 16
SD/XD/MS_DATA0_1 SD/XD/MS_DATA1_1 SD/XD/MS_DATA2_1 SD/XD/MS_DATA3_1
MS_BS MS_INS MS_SCLK
21 17 15
SD/XD/MS_CMD_1 MS_INS# SD/XD/MS_CLK_1
NP2 NP1
4IN1_GND 4IN1_GND
13 22
BAT54CPT-GP
GROUND GROUND
38 37
NP2 NP1
2
1
MDIO04
SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3
RN72
2 1
33R2J-2-GP
TP82 TPAD30
R176 100KR2J-1-GP
CARD-PUSH-36P-1-GP-U1
SB:06/20 Remove U35,R148 and change D19 from 83.R0304.A8H to 83.R2003.E81.
2
RSV
C269 SC2D2U10V3ZY-1GP
SRN47J-5-GP
R175
97
C271 SCD1U16V2ZY-2GP
RN45
SD/XD/MS_DATA08 SD/XD/MS_DATA17 SD/XD/MS_DATA26 SD/XD/MS_DATA35
VF
2
87
MDIO16
DY C261 SCD1U16V2ZY-2GP
2
SRN47J-5-GP
MDIO17
DY C597 SCD1U16V2ZY-2GP
2
XD_DATA4_1 XD_DATA5_1 XD_DATA6_1 XD_DATA7_1
1
1 2 3 4
2
GUARD GND
8 7 6 5
2
3
XD_DATA4 XD_DATA5 XD_DATA6 XD_DATA7
1
RN44
1 C315
R5C833-GP
For SD Card Power
3D3V_CARD
20mil
1 2 3
3D3V_S0
OUT GND SET
IN
5
ON#
4
2
2
1
1
DY
SCD1U16V2ZY-2GP C609
2
1
AAT4610AIGV-GP R426 15KR2J-1-GP
2
R418 C601 10KR2J-3-GP SC1U10V3ZY-6GP
SB:06/20 Remove R427 and change U57 pin4 connect to "MC_PWR_CTRL_0" 1
R426
1
1
U57
-1:08/29 Change R426 default from ASM to DY, because change U57 main source, it don't need R426.
AAT4610AIGV RT9711DPBG G5240D2T1U
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
15K DY
Title
DY
Size A3
R5C832/IEEE1394/SD Document Number
Date: Wednesday, September 12, 2007 A
B
C
D
Rev
DS2-Intel Sheet E
26
-1 of
47
A
B
88E8040
4.7K
2K
DY
DY
DY
DY
DY
DY
LED_LINK# NC#62 LED_SPEED# LED_ACT#
63 62 60 59
PCIE_WAKE# 21,28 PCIRST1# 19,25 CLK_PCIE_LAN 4 CLK_PCIE_LAN# 4 LAN_RXN1 C230 1 LAN_RXP1 C229 1
MDI0+ MDI1+
3D3V_LAN_S5 3D3V_LAN_S5
TPAD30
R394 1
LAN100M_LED#
2
DY
R50 100KR2J-1-GP
C563
VF
LAN10M_LED# 28
C531
1
2
SC1000P50V2JN-GP
1 2
DY DY
2 2 2
MDIS0_LAN 49D9R2F-GP
1
2 C528
SCD01U16V2KX-3GP 49D9R2F-GP MDIS1_LAN 49D9R2F-GP
1
2 C544
SCD01U16V2KX-3GP 49D9R2F-GP
DY
1
1
2 C538 SC1000P50V2JN-GP
1
2 C557 SC1000P50V2JN-GP
1
2 SC1U6D3V2KX-GP
2 SC1U6D3V2KX-GP
2 SC1U6D3V2KX-GP
2 SCD1U10V2KX-4GP
SA:04/23 Change C411 from 78.10523.5FL to 78.10520.5FL
C565
C561
C542
1
2 SC1U6D3V2KX-GP
1
2 C562 SC1000P50V2JN-GP
1
2 SC1U6D3V2KX-GP
1
2 C534 SC1000P50V2JN-GP
1
2 SC1U6D3V2KX-GP
1
2 C535 SC1000P50V2JN-GP
2
1
2
C256 SC4D7U6D3V5KX-3GP SCD1U10V2KX-4GP
3
2
1 CTRL12
Q17 2SB772PT-1-GP 1D2V_LAN_S5
1
1
C592
1
C590
8053:2.5V. 8055:1.8V.
SCD1U10V2KX-4GP
2
1
2D5V_LAN_S5 C246
1
2
DY
2
DY
Q15 2SB772PT-1-GP
1
2
3
2
CTRL25
C593
DY
SCD1U10V2KX-4GP
S
DY
DY 2
1D2V_LAN_S5
1 C543
C553
R417 4K7R2J-2-GP
DY
2
G
R397 4K7R2J-2-GP
SC4D7U6D3V5KX-3GP
SC4D7U6D3V5KX-3GP
C259
8053:CTRL25. 8055:CTRL18.
1
DY
3D3V_LAN_S5
2
1
1
C560
2
1
SCD1U10V2KX-4GP 2 1
G
AO3403-GP
C241 SC10U6D3V5KX-1GP
2 3
Q14
2
1
MDI1-
1 R357 1 R362 1 R372 1 R377
PLACE PNP TO CHIP ACAP CTRL12 PIN TRACE IS 25MIL
3D3V_LAN_S5
D
2
1
SCD1U10V2KX-4GP 2 1
34 PM_LAN_ENABLE
G
Q16 2N7002PT-U
MDI1+
SA:04/23 Change C402,C408 from 78.10523.5FL to 78.10520.5FL
PLACE PNP TO CHIP ACAP CTRL25 PIN TRACE IS 25MIL
D
D
MDI0-
SB:06/13
3D3V_LAN_S5
R139 10KR2J-3-GP
3
MDI0+
2 0R3-0-U-GP
S
R409 0R2J-2-GP
Pull up for AT24C08 another pull low
2D5V_LAN_S5
1 C539
1
DY
E
LED_LINK#
C239
EEWP VPD_CLK VPD_DATA
R408 EEWP
DY
EC160
3D3V_LAN_S5
R49 100KR2J-1-GP
C
R1
R2 PDTC124EU-1-GP
DY
0R2J-2-GP
AT24C08AN-1-GP
2
B
3D3V_S5
8 7 6 5
LAN100M_LED# 28
3D3V_LAN_S5
2
VCC WP SCL SDA
DY
R406 4K7R2J-2-GP
LAN10M_LED#
2 4K7R2J-2-GP 2 4K7R2J-2-GP
R393 1
DY
A0 A1 A2 GND
SC:08/09 Add EC160(78.10234.1F1) for EMI request .Default is DUMMY
GND
TPAD30
1 2 3 4
R407 4K7R2J-2-GP
DY
U31
2 2
ACT_LED# 28
DY
2
DY
LAN100M_LED#
LANX1 LANX2
4
1
TP75
1 1
LED_LINK#
3D3V_LAN_S5
1
Q4
R137 1
C209 SC12P50V2JN-3GP
PCIE_RXN1 21 PCIE_RXP1 21
cc
15 14
XTALI XTALO
VPD_CLK VPD_DATA
DY
2 LANX1
XTAL-25MHZ-96GP C210 SC12P50V2JN-3GP
SB:06/13 Change C209,C210 from 27P to 12P
2SCD1U10V2KX-4GP 2SCD1U10V2KX-4GP PCIE_TXN1 21 PCIE_TXP1 21
TP116
MDI0MDI1-
2SB772PT
DY
DY
X2
C255 SC4D7U6D3V5KX-3GP
DY
R121 1 2 10MR2J-L-GP
1
DY
0.01u
1 PCIE_RXN PCIE_RXP
53 54
Q17
4K7
0.01u
2
88E8040
2SB772PT
49.9
-c
4K7
49.9
2
88E8039
49.9
1
33 39 44 48 58 2 7 13 PCIE_TXN PCIE_TXP
50 49
1
R417
49.9
LANX2 1
WAKE# PERST# REFCLKP REFCLKN
3D3V_LAN_S5
Q15
1.91K
Note:Default is 88E8040
6 5 55 56
SA:4/30
R397
DY
SC1000P50V2JN-GP
28 MDI0+ 28 MDI1+
88E8039
o-
28 MDI028 MDI1-
C544
1
18 21 27 31
88E8039-A0-GP 3
C528
65
RXN TXN NC#27 NC#31
Marvell recommend: 2K Ohm(64.20015.6DL)
R377
VDD VDD VDD VDD VDD VDD VDD VDD
VDD25 AVDD
HSDACP HSDACN
PU_VDDO_TTL#42 PU_VDDO_TTL#43
24 25
R372
SB:06/13
42 43
1LANHP 1LANHN
LOM_DISABLE# VAUX_AVLBL SWITCH_VCC VMAIN_AVLBL SWITCH_VAUX RSET CTRL12 CTRL25
TSTPT TESTMODE
TPAD30 TP115 TPAD30 TP114
10 12 11 47 9 16 3 4
29 46
3D3V_S0
TPAD30 TP106 1LANSC LANPWR 1 R395 2 0R0402-PAD TP107 1LANSV TPAD30 LANRSET 1 2 R354 2KR2F-3-GP CTRL12 CTRL25
NC#36 NC#37
VPD_DATA VPD_CLK
3D3V_LAN_S5 LOM_DISABLE#
36 37
41 38
R358
NC#34 NC#35
RXP TXP NC#26 NC#30
1
17 20 26 30
2 4K7R2J-2-GP
R362
2
3D3V_LAN_S5
34 35
64 23
1 8 40 45 61 VDDO_TTL VDDO_TTL VDDO_TTL VDDO_TTL VDDO_TTL
57 52 51 32 28 22 19 AVDDL AVDDL AVDDL AVDDL AVDDL AVDDL AVDDL
4
E
R357
3D3V_LAN_S5 1D2V_LAN_S5
U25
D
R354
2
2D5V_LAN_S5
C
R394
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
LAN MARVELL Size A3
Document Number
Rev
DS2-Intel
Date: Wednesday, September 12, 2007 A
B
C
D
-1 Sheet E
27
of
47
A
B
C
D
RJ45 Connector 10/100M Lan Transformer XF1
1
RJ45-3
16
RN8 RJ45-1 RJ45-2 RJ45-3 RJ45-6
4
RJ45-6
7
10
RJ45-1
4
3D3V_LAN_S5
XFR_RXC
LAN100M_LED#
SRN0J-5-GP
9 RJ11_1 RJ11_2
2
EC17 SC1KP50V2KX-1GP
A1 A2
RJ45-7 RJ45-4
1
cc 2
5 6 7 8 TPAD30
U58
20 8 9 10 6
330R2J-3-GP ACT_LED# 27
3
1 2
SCD1U16V2ZY-2GP
C620 SCD1U16V2ZY-2GP
PM_SLP_S4# 21,34,40,44,45 RN73 4 3
PERST# CPUSB# CPPE# NRST
NEW1
31 NP1 1
TPAD30 TP144
CPPE# NEWCARD_CLKREQ#
3 5 7 9 11 13 15 17 19 21 23 25 27 29 NP2 32
3D3V_NEW_S0 PERST# 3D3V_NEW_LAN_S5 21,27 PCIE_WAKE# 1D5V_NEW_S0 21,29,30 SMB_DATA 21,29,30 SMB_CLK
DY
1 2
1
4 NEWCARD_CLKREQ#
TPAD30 TP137 TPAD30 TP138
1CONN_TP2 1CONN_TP3
3D3V_S5
SRN100KJ-6-GP
2 R435
TPS2231RGP-GP
2 SC22P50V2JN-4GP
2nd: 74.02231.A73
PLTRST# 1 0R2J-2-GP
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
PCIE_TXP5 21 PCIE_TXN5 21 PCIE_RXP5 21 PCIE_RXN5 21 CLK_PCIE_NEW CLK_PCIE_NEW#
PLT_RST1# 8,19,23,24,29,30,34
1D5V_S0
SB:07/04 For EMI request
EC145
EC144
DY
1 C626
DY
3D3V_S0
1
1
+1.5V_CARD Max. 650mA, Average 500mA. +3.3V_CARD Max. 1300mA, Average 1000mA +3.3V_CARDAUX Max. 275mA
C624
SCD1U16V2ZY-2GP
1
C621
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
LAN connector/NEW CARD/SIM Size A3
Document Number
Rev
DS2-Intel
Date: Wednesday, September 12, 2007 A
B
C
2
USB_PP8 21 USB_PN8 21
3D3V_S0
3D3V_NEW_S0
4 4
CPUSB#
FOX-CONN30A-9GP
2
3D3V_S5 1D5V_NEW_S0
2
RJ45+RJ11-5GP
oC611
DY
3D3V_NEW_LAN_S5
1
1
SHDN# PERST# CPUSB# CPPE# SYSRST#
1
2
1
SCD1U16V2ZY-2GP
C610
SC4D7U6D3V5KX-3GP
Use Card and No Card
C612
2
Test circuit
C613
VF
GND
AUXOUT AUXIN 1.5VOUT 1.5VIN 3.3VOUT 3.3VIN
+1.5VVIN +1.5VOUT +3VOUT +3VIN
15 17 11 12 3 2
1D5V_S0 1D5V_NEW_S0 3D3V_NEW_S0 3D3V_S0
NC#16 NC#14 NC#13 NC#5 NC#4
THERMAL_PAD OC# RCLKEN STBY#
7
21 19 18 1
PM_SLP_S3# 21,34,43,45,46
16 14 13 5 4
RJ45-6_L RJ45-7
2
1
SCD1U16V2ZY-2GP
2
-1:09/01 Change R43,R47 from 63.47134.1DL to 63.33134.1DL
3D3V_NEW_LAN_S5
-c
NEWCARD_OC#
2
SCD1U16V2ZY-2GP
C318
2
1
1 2
C617
TP143
2
DY
SC10U6D3V5KX-1GP
DY
1D5V_NEW_S0
1
3D3V_NEW_S0
1
1D5V_S0
LAN100M_LED# 27
RJ45-1_L RJ45-2_L RJ45-3_L RJ45-4
Place them Near to Connector
Place them Near to Chip 3D3V_S5
2 330R2J-3-GP
1
Green : Link up Blinking : TX/RX activity
2 SC1500P2KV8KX-3GP
SC10U6D3V5KX-1GP
2
LAN_TERMINAL 1 C416
NEWCARD Connector
EC11 SC1KP50V2KX-1GP
DY
RN7 SRN75J-1-GP
2
1
1 2
9 11 12 13
LAN10M_LED# 27 R47
A3 RJ45_1 RJ45_2 RJ45_3 RJ45_4 RJ45_5 RJ45_6 RJ45_7 RJ45_8 B1 R43 B2 10
ACT_LED#
XFORM-257-GP
C392 SCD1U16V2ZY-2GP
3
SCD1U16V2ZY-2GP
C401
RJ45-2 XFR_CMT
4 3 2 1
8 6 4 5
SA:04/23 change CN13 pin3,4 net name from "GND" to NC
RJ1
DY
27 MDI0-
3 MLX-CON2-9-GP-U
1
27 MDI0+
15 14
1
8 RJ45-1_L 7 RJ45-2_L 6 RJ45-3_L 5 RJ45-6_L
1 2 3 4
1
27 MDI1-
2 3
4 2
SC5P50V2CN-2GP
27 MDI1+
CN7
SC5P50V2CN-2GP 2
2D5V_LAN_S5
E
1.route on bottom as differential pairs. 2.Tx+/Tx- are pairs. Rx+/Rx- are pairs. 3.No vias, No 90 degree bends. 4.pairs must be equal lengths. 5.6mil trace width,12mil separation. 6.36mil between pairs and any other trace. 7.Must not cross ground moat,except RJ-45 moat.
D
-1 Sheet E
28
of
47
A
B
C
D
E
Mini Card Connector 1(802.11a/b/g) SB:06/22 Change MINI1,2,3 slot from 62.10043.431 to 62.10043.551(only modify properties)
4
4
MINI1 1D5V_S0
3D3V_S0
53 NP1 1MINI_2_WAKE# 1
TP142 TPAD30
2 30,31 WLAN_ACT
3
30 BT_ACT
5
4 6 1
7 8 9 10
4 CLK_PCIE_MINI1#
11
4 CLK_PCIE_MINI1
13
12 14 15 16 17 18
3
19 20
WIFI_RF_EN
21 24
3D3V_S0
25
21 PCIE_RXP2
26 27 28 29
21 PCIE_TXN2
31
21 PCIE_TXP2
33
30
SMB_CLK
32
SMB_DATA
34 35 38 39
3D3V_S0
40 41 42 43 44 45 46 47
2
48 49
R432
1
SMB_CLK 21,28,30
SMB_DATA 21,28,30
1
TP131TPAD30
WLAN_LED 35
1
TP132TPAD30
2
VF
5V_S5
50
PLT_RST1# 8,19,23,24,28,30,34
-c
36 37
3
o-
PLT_RST1#
22 23
21 PCIE_RXN2
34
cc
TP141 TPAD30
DY
2 0R3-0-U-GP
51
52
NP2 54
SKT-MINI52P-18-GP
Main Source:62.10043.431 2nd Source: 20.F0992.052
3D3V_S0
5V_S5
3D3V_S0
1D5V_S0 WLAN_ACT
1
-1:0909
SC10U6D3V5KX-1GP
2
C603 SCD1U16V2ZY-2GP SC10U6D3V5KX-1GP
1
1
DY
1
C275
2
DY
1
DY
2
1
C284 SCD1U16V2ZY-2GP C291
2
C604 SCD1U16V2ZY-2GP
1
2
2
SCD1U16V2ZY-2GP
2
C616
1
1
DY
Wistron Corporation
EC175 SC220P50V2KX-3GP
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
MINI CARD CONN 1 Size A3
Document Number
Rev
DS2-Intel
Date: Wednesday, September 12, 2007 A
B
C
D
-1
Sheet E
29
of
47
A
B
C
D
Mini Card Connector Mini Card Connector 2(WWAN) TP80 TPAD30
4
1
Mini Card Connector 3(Robson) SB:06/22 Change MINI1,2,3 slot from 62.10043.431 to 62.10043.551(only modify properties)
MINI2 1D5V_S0
3D3V_S0
53
NP1 MINI_WAKE# 1
MINI3
4
1D5V_S0
2
3D3V_S0
53
3D3V_S0
3 TP140 TPAD30
12
UIM_CLK
14
UIM_RESET
16
UIM_VPP
13 15
TP81 TPAD30
UIM_CLK 35
WWAN_RF_EN PLT_RST1#
22 24
34 34 E51_RXD
PLT_RST1# 8,19,23,24,28,29,34
3D3V_S0
34 E51_TXD
26
SMB_CLK
32
SMB_DATA
USB_PN4 21
38
USB_PP4 21
39 40
4
BT_ACT 29
3
PLT_RST1# 8,19,23,24,28,29,34
BT_ACT_1
26
BT_ACT_2
28 30
SMB_CLK
32
SMB_DATA
SMB_CLK 21,28,29 SMB_DATA 21,28,29
34 USB_PN9 21
38
USB_PP9 21
R194
40
41 42
1
44
1
SC:08/11 Add R192,R194 pull low resistor for bluetooth active signal to
TP136TPAD30
43
TP135TPAD30
45 46
BT_ACT_WPAN# 35
47 48 49
R429
1
DY
50 2 0R3-0-U-GP
2
51 52 NP2 54
DY
DY
SCD1U16V2ZY-2GP C285
DY
SC10U6D3V5KX-1GP
C286
DY
C605
DY
SCD1U16V2ZY-2GP SC10U6D3V5KX-1GP
C608
1
C289
3D3V_S0
C606 SCD1U16V2ZY-2GP
2
C615
SCD1U16V2ZY-2GP
1D5V_S0
1
3D3V_S0
5V_S5
DY Place C451 near MINI 3 pin24
SCD1U16V2ZY-2GP
1 2
Main Source:62.10043.431 2nd Source: 20.F0992.052
SKT-MINI52P-18-GP
2
2
SC33P50V2JN-3GP
SC33P50V2JN-3GP
2
1
C607
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP
Place TC35 near MINI 2
36
R192
1
1
VF DY
R160 100KR2J-1-GP
3D3V_S0
39
3D3V_S0
2
1
C277
C602
2
SCD01U16V2KX-3GP 2
ST220U6D3VDM-13GP
2
33
C638
1D5V_S0
2
DY
C287
1
1
1
1
C274
2
3D3V_S0
SCD1U16V2ZY-2GP
31
21 PCIE_TXP4
5V_S5
C637
1
21 PCIE_TXN4
-c
UIM_CLK
Main Source:62.10043.431 2nd Source: 20.F0992.052
2
25
UIM_DATA
54
DY
Y
BLUETOOTH_EN 31,34
PLT_RST1#
24
-1:0905 Add C637,C638 for SIM CLK and DATA.
52
SKT-MINI52P-18-GP
1
20
TP130TPAD30
NP2
C614
GND
18
23
3D3V_S0
TP133TPAD30
50
TC5
2 0R2J-2-GP E51_TXD_R 19
1
1
51
5V_S5
3
5
DY
2
1
46 48
2
R428 1
1
44
49 2 0R3-0-U-GP
A
74LVC1G32GW-1GP
37
TP134TPAD30
47
DY
2 0R2J-2-GP E51_RXD_R17
2
1
45
R430
R431 1
1
WWAN_LED
42 43
1
0R2J-2-GP
VCC
35
41
5V_S5
0R2J-2-GP
16
29
36
2
2
34 35 37
2
27
SMB_DATA 21,28,29
33
2
14
21 PCIE_RXP4
SMB_CLK 21,28,29
B
15
o-
30 31
1
12
21 PCIE_RXN4
29
3D3V_S0
13
BT_ACT_2
22
28
21 PCIE_TXP3
31 BT_ACT_1
21
27
21 PCIE_TXN3
4 CLK_PCIE_MINI3
2
3
11
1
25
4 CLK_PCIE_MINI3#
DY DY U62
8
SC:07/30 Add "WWAN_RF_EN" GPIO pin connect to MINI2 pin20
20 23
7 10
UIM_VPP 35
19
21 PCIE_RXP3
1
9
18
21 PCIE_RXN3
6
UIM_RESET 35
17
21
1 R155 1 R161
5
2
4 CLK_PCIE_MINI2
4
BT_ACT_2
UIM_DATA 35
1
UIM_DATA
100KR2J-1-GP
10
9 11
4 CLK_PCIE_MINI2#
SC:08/09 Delete D21,add U62(73.01G32.AHH) to replace D21
2 3
29,31 WLAN_ACT
UIM_PWR 35
2
UIM_PWR
NP1 MINI_WAKE# 1
1
8
1
cc
7
1
6 1
100KR2J-1-GP
4 5 TP139 TPAD30
2
SB:06/22 Change MINI1,2,3 slot from 62.10043.431 to 62.10043.551(only modify properties)
E
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
MINI CARD CONN 2 & 3 Size A3
Document Number
Rev
DS2-Intel
Date: Wednesday, September 12, 2007 A
B
C
D
-1
Sheet E
30
of
47
5
4
3
2
1
-1:0910
3D3V_S5
3D3V_AUX_S5
OUT VS GND GND
WLAN/BT_BTN#
HDA_BITCLK 20,23,32
1
1
1 2
EC110
DY 2
1 2
EC111
DY
2
C204 SC22P50V2JN-4GP
DY
-c
Main Source:20.F0677.012 2nd Source: 20.F0676.012
R265 100KR2J-1-GP
2
C432
EC115
DY
SC220P50V2KX-3GP
2
0R2J-2-GP
SNIFFER_BLUE#
SC220P50V2KX-3GP
1
EC114
SC220P50V2KX-3GP
ICH_ACZ_MDC_BITCLK
SNIFFER_YELLOW#
C
SC220P50V2KX-3GP
R343
AMP-CONN12A-1GP
Bluetooth Module conn.
B
SNIFFER_PWR_SW#
1
3D3V_S5
1
C428 SC22P50V2JN-4GP
DY
o-
4 6 8 10 12 18 17 MH2
SC4D7U6D3V5KX-3GP 2 1
2
1
1 2 ACSDATAIN1_A R266 39R2J-L-GP
8 MLX-CON6-11-GP
cc
MH1 14 15 2
3 5 7 9 11 16
20,23,32 ICH_SDOUT_CODEC
2 3 4 5 6
34 SNIFFER_YELLOW# 34 SNIFFER_BLUE#
MDC1
20,23,32 ICH_AZ_CODEC_SYNC 20 ICH_SDIN_MDC 20 ICH_AZ_MDC_RST#
1
34 WLAN/BT_BTN# 34 SNIFFER_PWR_SW#
TSOP36136-GP
13 1
D
SNIFFER1
7
5V_S5
C
SC:07/26 Rename "SNIFFER_BD1" to "SNIFFER1"
R458 100KR2J-1-GP
2
4 3 2 1
2
SC4D7U6D3V5KX-3GP
C332
FRIEE_CIRRX SIO_CIRRX_VS
2
R181
1
1
1
2
2
100R2J-2-GP
SCD1U10V2KX-4GP C333
34 CIRRX
1
3D3V_S5
2
2
D
2
U61
1
R182 10KR2J-3-GP
SC:08/12 Add R458 (63.10434.1DL) pull up for "WLAN/BT_BTN#. Because sniffer is option feaature.
C578 SCD1U10V2KX-4GP
R205 10KR2J-3-GP
CIR
1
1
3D3V_AUX_S5
DY
B
BT1
11
VF
1
2 3 4 5 6 7 8 9 10
21 USB_PP5 21 USB_PN5
30 BT_ACT_1 30,34 BLUETOOTH_EN 29,30 WLAN_ACT
3D3V_S0
BT_LED
12
1
1
C424
2
SCD1U10V2KX-4GP
R259 10KR2J-3-GP
FOX-CON10-GP
2
20.F0711.010
USB_PN5
SC:08/14 Add EC173(78.22034.1FL) on "USB_PP5" for EMI team request.
1 EC174
DY 2
SC22P50V2JN-4GP
EC173
DY 2
1 EC62
2
DY
SC22P50V2JN-4GP
SC:08/14 Add EC172(78.22124.2FL) on "BT_ACT1" for EMI team request.
SC220P50V2KX-3GP
EC172
DY
USB_PP5
1
BLUETOOTH_EN
1
R2 PDTC124EU-1-GP R258 10KR2J-3-GP
2
A
B
2
E
R1
1
C
SC220P50V2KX-3GP
BT_ACT_1
Q28
35 BT_ACT_K#
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
SC:08/14 Add EC174(78.22034.1FL) on "USB_PN5" for EMI team request.
Title
MDC&RJ11 CONN Size A3
Document Number
Date: Wednesday, September 12, 2007 5
4
3
2
Rev
DS2-Intel Sheet 1
31
-1 of
47
A
B
C
D
E
+VDDA
1
60ohm 100MHz 3000mA 0.05ohm DC R421 5K1R2F-2-GP
2
AVDD1 AVDD2 SENSE_A SENSE_B
13 34
PORT_A_L PORT_A_R VREFOUT_A
39 41 37
PORT_B_L PORT_B_R VREFOUT_B
21 22 28
PORT_C_L PORT_C_R VREFOUT_C
23 24 29
PORT_D_L PORT_D_R VREFOUT_D
35 36 32
PORTE_L PORTE_R VREFOUT_E
14 15 31
PORTF_L PORTF_R VREFOUT_F
16 17 30
PORTG_L PORTG_R
43 44
PORTH_L PORTH_R
45 46
CD_L CD_GND CD_R
18 19 20
PC_BEEP
12
DVDD_CORE DVDD_CORE DVDD
1 SC1KP50V2KX-1GP
2 R154 5K1R2F-2-GP
SDATA_OUT
20,23,31 ICH_AZ_CODEC_SYNC
10
SYNC
20 ICH_AZ_CODEC_RST#
11
RESET#
AUD_DMIC_CLK_G
18 AUD_DMIC_CLK_G
DY
5
VCC
4
Y
1 2 3
OE# A GND
74LVC1G125DC-GP
2 R149
SB: Change R149 from
AUD_DMIC_CLK
1 33R2J-2-GP
63.R0034.1DL to 63.33034.1DL AUD_DMIC_IN0
18 AUD_DMIC_IN0 R455
2
35 SPDIF_D
AUD_SPDIF_OUT
23 AUD_SPDIF_OUT
2 3
VOLUME UP/DMIC_0/GPIO1 VOLUME DN/DMIC_1/GPIO2
47 48
SPDIF_IN/GPIO0/DMIC_CLK SPDIF_OUT
1 200R2F-L-GP AUD_DMIC_CLK
2
2
STAC9228X5TAEA2-GP
CAP2 VREFFILT
33 27
AVSS1 AVSS2
26 42
1 2
C299
C300
2
From SB
1
2
SB_SPKR 21
47KR2F-GP
R412
R413 1 2 47KR2F-GP
KBC_BEEP 34
From EC 2
SA:0428
Internal Microphone -1:09/06 Change Int. MIC from 23.42132.001 to 23.42143.001
MIC IN
Azalia I/F EMI
ICH_SDOUT_CODEC
3
R141
1AUD_BEEP C267 SCD1U10V2KX-4GP 2
AUD_CAP2 AUD_VREFFLT
71.09228.00G
VF
Azalia I/F EMI
EXT_MIC_JD#
A---> HP1 E---> Ext Mic D---> Speaker F---> HP2 C--->Int Mic
PC BEEP
AUD_PC_BEEP
SB:07/02 Change EC36 from ASM to DUMMY SB:06/26 Add EC129(78.22034.1FL) by EMI request
Port Port Port Port Port
AUD_HP2_OUT_L 33 AUD_HP2_OUT_R 33
2
EC36 SC22P50V2JN-4GP
2
TO Audio OP
10KR2J-3-GP
DY
R157 1 39K2R2F-L-GP
CN4
ICH_AZ_CODEC_BITCLK
INT_MIC
2
DY
2
2
1 R169 1 R168
2 0R3-0-U-GP 2 0R3-0-U-GP
MIC_IN_L_C
6
MIC_IN_R_C
3
2
SB:07/02 Change R168 from 63.R0034.1DL to 63.00000.00L
600ohm 100MHz 200mA 0.5ohm DC
C265 SCD1U10V2KX-4GP
1
1
4
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
5 7 8 9 10
Title
AUDIO CODEC STAC9228 AUDIO-JK89-GP-U
DY
Size A3
Document Number
Date: Wednesday, September 12, 2007 A
B
C
D
MICROPHONE-40-GP-U
2
1 1
MIC1
1
EC49 SC100P50V2JN-3GP
1
EXT_MIC_JD#
1
AUD_EXT_MIC_R
MIC_IN_L_2 2 C306 SC1U10V3KX-3GP MIC_IN_R_2 2 C307 SC1U10V3KX-3GP
C302 SC1U10V3KX-3GP
EC48 SC100P50V2JN-3GP 2 1
1
R163 4K7R2J-2-GP
1 2
AUD_EXT_MIC_L
2
2 1
1 2
C263 SCD1U10V2KX-4GP
2
2
ICH_AZ_CODEC_SDOUT1
1
ICH_AZ_CODEC_BITCLK1
DY
DY
R162 4K7R2J-2-GP
1
R144 47R2J-2-GP
EC52 SC1KP50V2KX-1GP
1
AUD_VREFOUT_E
R145 47R2J-2-GP
33
AUD_EXT_MIC_L AUD_EXT_MIC_R AUD_VREFOUT_E
SC10U10V5KX-2GP
EC129 SC22P50V2JN-4GP
DVSS1 DVSS2
AUD_HP2_JD#
AUD_LINE_OUT_L 33 AUD_LINE_OUT_R 33
SC10U10V5KX-2GP
2
1
ICH_AZ_CODEC_BITCLK
1
AUD_DMIC_CLK_G
AUD_LINE_OUT_L AUD_LINE_OUT_R
-c
4 7
INT_MIC
2
2SC1U10V3KX-3GP R1531 2 4K7R2J-2-GP
o-
3
2SC1U10V3KX-3GP
R158 1 20KR2J-L2-GP
1
U34
C292 1 AUD_INT_MIC_L AUD_INT_MIC_R C294 1 AUD_VREFOUT_B
2
3D3V_S0
AUD_HP1_OUT_L 33 AUD_HP1_OUT_R 33
cc
SDATA_IN
2
20,23,31 ICH_SDOUT_CODEC
BIT_CLK
AUD_HP1_OUT_L AUD_HP1_OUT_R
1
20 ICH_SDIN_CODEC
33
+VDDA AUD_SENSE_A AUD_SENSE_B
1
20,23,31 HDA_BITCLK
2
AUD_HP1_JD#
4
TO Audio OP ICH_AZ_CODEC_BITCLK 6 0R2J-2-GP SB_AZ_CODEC_SDIN0_R 8 2 1 R146 33R2J-2-GP 5
1 R344
2
1
C298
SB:07/10 Change R344 from 33 Ohm to 0 Ohm
1+3V_RUN_DVDD_CORE3 100KR2J-1-GP
R420 1 39K2R2F-L-GP
1
R152 2
25 38
C296 SC1U10V3KX-3GP
1 2 U36
1 9 40
C320 SCD1U10V2KX-4GP
1
C270 SC1U6D3V2KX-GP
2
1 2
1 2 4
C276 SCD1U10V2KX-4GP
+VDDA
C266 SCD1U10V2KX-4GP
3D3V_S0
Rev
-1
DS2-Intel Sheet E
32
of
47
B
C
D
E
3D3V_S0
No ASM
2nd source: MAX9789A
0 Ohm
1
1 2
74.06040.013 74.09789.013
C619 SC1U10V3KX-3GP
1
2
C628 SCD033U16V3KX-GP
SC:08/13 Change R441pin1 connection from"AMP_MUTE#" to 5V_S0
2 2 2 2
0R0603-PAD 0R0603-PAD 0R0603-PAD 0R0603-PAD
AUD_SPK_L2_R AUD_SPK_L1_R AUD_SPK_R2_R AUD_SPK_R1_R
6 MLX-CON4-15-GP
LINE1 OUT 3
AUD_HP2_EN AUD_HP2_JACK_L AUD_HP2_JACK_R
o-
LOUT1
1
6dB
0
1
10dB
1
0
15.6dB
1
1
21.6dB
AUD_HP1_JD# 1 AUD_HP2_JD# 2
3AUD_SPK_ENABLE
NB_SPK_EN#
4
3
AUD_SPK_ENABLE#
5
2
AMP_MUTE#
6
1
BAW56PT-U 2N7002SPT
1
EC51 SC100P50V2JN-3GP
2
1 2
EC50 SC100P50V2JN-3GP
9 11
14 18 GND
OUTL OUTR
SGND PGND
17 2
SA:4/28
AUD_HP1_JD#
5
2
AMP_MUTE#
AUD_HP1_JD
6
1
AUD_HP1_EN
2N7002SPT
AUD_HP2_JD#
32 AUD_HP2_JD# AUD_HP2_JACK_L
1
2 L9 BLM18BD601SN1D-GP AUD_HP2_JACK_R 1 2 L8 BLM18BD601SN1D-GP
600ohm 100MHz 200mA 0.5ohm DC 5V_S0
R457 10MR2J-L-GP
R166 33KR2J-3-GP U39
SC:08/11 Delete Q18, Add U64 circuit for Speaker
DY
2
AUD_HP2_JACK_L2
6
AUD_HP2_JACK_R2
3 4
1
AUD_HP1_JD
3
DY
2
2
U63
4
LOUT2
1
SC:08/11 Delete Q19, Add U63,R457 circuit for HP1
4
3
AUD_HP2_JD
AUD_HP2_JD#
5
2
AMP_MUTE#
SA:4/28
AUDIO-JK89-GP-U
AUD_HP2_JD
6
1
AUD_HP2_EN
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
AUDIO AMP/SPEAKER Size A3
Document Number
Rev
D
-1
DS2-Intel
Date: Wednesday, September 12, 2007 C
5 7 8 9 10
R165 10MR2J-L-GP
B
2
1 R167 100KR2J-1-GP
2N7002SPT
A
AUDIO-JK89-GP-U
EC47 SC100P50V2JN-3GP
GAIN
0
5 7 8 9 10
LINE2 OUT
This pin should be FLOAT. Do NOT connect to GND.
2
1
GAIN2
0
U64
4
EC46 SC100P50V2JN-3GP
D22
3
DY
1
R159 100KR2J-1-GP
6
AUD_HP1_JACK_R1
2
2
R459 100KR2J-1-GP
2
AUD_HP1_JACK_L1
5V_S0
5V_S0
2
R172 100KR2J-1-GP
DY
1
5V_S0
600ohm 100MHz 200mA 0.5ohm DC
2
+VDDA
R436 100KR2J-1-GP
10 19
VF
AUD_AMP_GAIN2
SC2D2U6D3V3KX-GP
SC:08/12 Add R459 (63.10434.1DL) pull up for U64 pin4 "NB_SPK_EN".
1
2
DY
2
R433 100KR2J-1-GP
2
Signal inverter for speaker shutdown
1
1
AUD_AMP_GAIN1
4 6 8 12 16 20
AUD_PVSS
1
1
1 2
R439 100KR2J-1-GP
2 L10 BLM18BD601SN1D-GP AUD_HP1_JACK_R 1 2 L11 BLM18BD601SN1D-GP
2
C304 1 2
R434 100KR2J-1-GP
GAIN1
MAX4411ETP-1-GP
2nd source: MAX4411EPT+ 74.04411.A13
5V_S0 2
DY
74.04411.AE3
21
Main source: TPA4411MRTJ
INL INR
SVSS
SB:70213
GAIN SETTING
13 15
NC#4 NC#6 NC#8 NC#12 NC#16 NC#20
7
1 C305 1 C301
C1P C1N
1
1
SC2D2U6D3V3KX-GP AUD_HP2_OUT_L2 2 AUD_HP2_OUT_R2 2 SC10U10V5KX-2GP SC10U10V5KX-2GP
1 3
PVSS
AUD_HP2_OUT_L AUD_HP2_OUT_R
AMP2_C1P
5
32 AUD_HP2_OUT_L 32 AUD_HP2_OUT_R
C295 1 2
AUD_HP1_JD#
32 AUD_HP1_JD# AUD_HP1_JACK_L
1
AMP2_C1N
No ASM
0.33uF
SHDNR# SHDNL#
-1:0909
-c
C628
U38
SVDD PVDD
No ASM
0.33uF
1
C631
C313 SC1U6D3V2KX-GP
100K
2
No ASM
2
R441
1 2 3 4
DY
EC8 SC100P50V2JN-3GP
5V_S0
DY
1 1 1 1
EC6 SC100P50V2JN-3GP 2 1
R441 2 1 100KR2J-1-GP
DY
EC9 SC100P50V2JN-3GP 2 1
AMP_MUTE# 34
DY
C321 SC1U10V3KX-3GP
1
DY From EC
1 0R2J-2-GP
3D3V_S0
0 Ohm
No ASM
R11 R14 R13 R10
1
R440
2AUD_CPVSS SC1U10V3KX-3GP
AUD_SPK_L2 AUD_SPK_L1 AUD_SPK_R2 AUD_SPK_R1
AUD_LINE_OUT_R 32 AUD_LINE_OUT_L 32
5V_S0
+VDDA
No ASM 1 C316
R171
2 2SCD033U16V3KX-GP SCD033U16V3KX-GP
cc
Main source: TPA6040A
2
C311 SC1U10V3KX-3GP
1 2
1 2
2
R440
C631 SCD033U16V3KX-GP
DY MAX9789A-GP
1
PVSS 14
CPVSS
CPGND 11
21 5
13
HP_INR HP_INL
MAX9789A
100K
R156
2
4
1 C630 1 C629
AUD_SPK_ENABLE# AMP_MUTE#_R R171 2 AUD_HP1_EN DY AMP_REGEN AMP_C1P 1 2 AMP_C1N C317 SC1U10V3KX-3GP AUD_BIAS AUD_SET
0R2J-2-GP
3
SPK1
1
23 25 22 4 10 12 29 24 1
SC:08/11 Change SPK1 pin define that follow ME request
2
SPKR_EN# MUTE# HP_EN REGEN C1P C1N VOUT BIAS SET
60ohm 100MHz 3000mA 0.05ohm DC
EC7 SC100P50V2JN-3GP 2 1
2 3
C618 SC1U6D3V2KX-GP
1 2
SC10U6D3V5KX-1GP
AUD_LIN_R AUD_LIN_L
SPKR_INR SPKR_INL
Default TPA6040A
C627 SCD1U10V2KX-4GP
2
1
C328 SC1U10V3KX-3GP 2 1
30
17
18
9
GAIN1 GAIN2
GND GND
AUD_HP1_OUT_R126 2 2SC10U10V5KX-2GPAUD_HP1_OUT_L1 27 SC10U10V5KX-2GP
1 C309 1 C310
C622
R156 2 1 100KR2J-1-GP
PGND PGND
31 32
U59
VDD
HPR HPL
HPVDD
15 16
CPVDD
8
AUD_HP1_JACK_R AUD_HP1_JACK_L
PVDD
OUTL+ OUTLOUTROUTR+
PVDD
6 7 19 20
AUD_AMP_GAIN1 AUD_AMP_GAIN2
Close to U30.9
32 AUD_HP1_OUT_R 32 AUD_HP1_OUT_L
AUD_SPK_L1 AUD_SPK_L2 AUD_SPK_R2 AUD_SPK_R1
C314 SC1U6D3V2KX-GP
1
2
3D3V_S0
28 33
1
C322 SC1U10V3KX-3GP
1
Close to U37.8
4
Speaker
3D3V_S0 5V_S0
2
2
60ohm 100MHz 3000mA 0.05ohm DC
2
1
5V_S0
C623 SCD1U10V2KX-4GP
C327 SC10U10V5KX-2GP
Close to U27.18
5
A
Sheet E
33
of
47
5
4
3
20 LPC_LAD[0..3]
TP60 LPC_LAD3 LPC_LAD2 LPC_LAD1 LPC_LAD0
TP61
PLACE CAP NEAR PIN46,19,115,76,88,104 TP52 ECRST#
SC:08/03 Change Pin27 from"BLON_OUT" to" LCD_TST_EN", delete TP45 test pad.
WPC8763LDG-1-GP
SB:06/27 Change R98 from 63.10334.1DL to 63.47234.1DL .
2
2 SCD1U16V2ZY-2GP
B C
KBC_THERMTRIP#
1
1
2
2
2
2
SA SB SC -1
10KR2J-3-GP R338
R339 10KR2J-3-GP
VER0 0 0 1 1
R451
2
2
3 2
C507 X-32D768KHZ-40GPU
2
2
7 3 29
75 83 110 111 112 GPO72 GPO76/SHBM GPO82/HGPO00/TRIS# GPO83/SOUT_CR/BADDR1 GPO84/HGPO01/BADDR0
101 105
106 107 GPI96 GPI97
GPI94/DA0 GPI95/DA1
97 98 99 100 GPI90/AD0 GPI91/AD1 GPI92/AD2 GPI93/AD3
126 127 128 1 LAD0 LAD1 LAD2 LAD3
85
4 VDD
AVCC
LRESET# LFRAME# ECSCI#
1 2
RN21
1 2 3 4
DY
KBC_BEEP 32
3D3V_AUX_S5
3 2
SRN10KJ-6-GP RN60 1 2
6
KBC_PWRBTN# INSTEAD_BTN#
R106 1
SNIFFER_PWR_SW# 2 100KR2J-1-GP
R101 1
LID_CLOSE# 2 10KR2J-3-GP
R443 1
LCD_CBL_DET# 2 10KR2J-3-GP
R447 1
KB_DET# 2 10KR2J-3-GP
R448 1
DMIC_DET# 2 10KR2J-3-GP
G792_SCL 36
1
2
R322
0R2J-2-GP
WLAN_TEST:for WKS test WLAN LED CAP_SCL 37
AD_OFF:enable AC adapter power source S5_ENABLE
CHARGE_LED#:for Battery charge LED 2
R331 1
2 10KR2J-3-GP
WLAN/BT_BTN#:from Wlan on/off button GMCH_BL_ON:Sense The Backlight On/Off Status from VGA Chip
D30
1 ECSWI#_KBC
3
WIRELESS_EN:Disable/Enable Wireless Module
ECRST#
3D3V_AUX_S5
BLUETOOTH_EN:Disable/Enable Bluetooth Q30 CH3906PT-GP
2
USB_PWR_EN#:to on/off USB power switch
RN58
BAS16-1-GP
1 2
36,46 PURE_HW_SHUTDOWN#
4 3
ECRST#_C B
SRN10KJ-5-GP
AC_IN#:From Charge 1
C516
ECSCI#_KBC
3
A
2 BAS16-1-GP
Wistron Corporation
D16
DY
21 ECSMI#
C519 SC4D7P50V2CN-1GP
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
1 3
ECSMI#_KBC
Title
KBC_Winbond WPC8763L
2 Size A2
BAS16-1-GP
Document Number
Rev
4
3
2
-1
DS2-Intel
Date: Wednesday, September 12, 2007
5
B
DC_BATFULL#:for Battery charge LED 1 1
CCD_ON:Webcam power on/off 21 ECSCI#
4 3
BAT_IN#:from Battery Conn
D29
PCLK_KBC
KBC_SCL1 KBC_SDA1 BAT_SDA BAT_SCL
SRN10KJ-5-GP
KBC_PWRBTN#:from power button
KBC_SDA1
8 7 6 5
EC32
ACDC_ID:from Adapter Conn
5
KA20GATE KBRCIN#
4 3
3D3V_AUX_S5
ADIA:to Charger
4
E51_RxD
2
4
1
1
36 G792_SDA
2 10KR2J-3-GP
SRN10KJ-5-GP
KBC_XI KBC_XO
C183 SCD1U16V2ZY-2GP
DY RN59
U54
R340 0R2J-2-GP
DY
X5
SC12P50V2JN-3GP
1
KBC_XI
2
10MR2J-L-GP
-1:0912 KBC_XO_R SC12P50V2JN-3GP
2
1
1 R103
2 0R2J-2-GP
PCLK_KBC_RC
R330 33KR2J-3-GP
C510
KBC_XI_R
3D3V_S0
1
1
1 10MR2J-L-GP
TPDATA 37 TPCLK 37
3D3V_S0
KBC CLK EMI
1
R326
A
R323 1
21 ECSWI#
2
KBC_XO
71 72
<-----BATTERY
SC1U10V3KX-3GP
WPC8763L XTAL
PSDAT1 PSCLK1
C SPIDI 35 SPIDO 35 SPICLK 35 SPICS# 35
KBRCIN#
2N7002SPT
VER1 0 1 0 1
BAT_SDA 18,38,39 BAT_SCL 18,38,39
KA20GATE
KBC_SCL1
MB VERSION ID
1
1
DY
FOR Thermal AND Capacity Button Module
MB VERSION ID
10KR2J-3-GP R335
DY
E51_RxD
20 KA20GATE 21,25 INT_SERIRQ 20 KBRCIN# 4 PCLK_KBC
37 CAP_SDA
PCB_VER0 PCB_VER1
ECSMI#_KBC
VF
3D3V_S0
69 70
KBC DEBUG POINT
2
1
29 WIFI_RF_EN
Q34 CH3904PT-GP
R337 10KR2J-3-GP
TP56
33 AMP_MUTE# 30 E51_RxD
1
E
SDA1 SCL1
21,28,40,44,45 PM_SLP_S4# 31 SNIFFER_YELLOW# TPAD30 TP53
C632
5,8,20,46 H_THERMTRIP#
-c TPAD30
R442 2K2R2J-2-GP
B
KCOL17 TP51 KCOL16 TP46 KBC_SCL1 KBC_SDA1 ECSWI#_KBC GPIO64
VBAT KBC_BEEP VCORF
TPAD30 TPAD30
1D05V_S0
86 87 92 90
37
1
2 BLUETOOTH_EN 4K7R2J-2-GP
1
F_SDI F_SDO F_SCK F_CS0#
KCOL[0..16]
2
R98
TPAD28 TPAD28
1
E
HIGH:NO SHARED(internal resistor) LOW:SHARED BIOS memory.
TP44 TP49
37
C
25 GBRST#_KBC
SHBM PIPN83 Shared Host BIOS Memory.
10KR2J-3-GP R88 2 TPAD28 TPAD28 DY TPAD28 TPAD28
1
CLKOUT
TP47 TP42 TP48 TP43
AGND
LCD_TST_EN
KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15
KROW[0..7]
103
TP50
PLT_RST1# 8,19,23,24,28,29,30
KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7
cc
TPAD30
54 55 56 57 58 59 60 61 53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35
GND GND GND GND GND GND
TP57
KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7
1 R336 0R2J-2-GP
KBSOUT0/JENK# KBSOUT1/TCK KBSOUT2/TMS KBSOUT3/TDI KBSOUT4 KBSOUT5/TDO KBSOUT6/RDY# KBSOUT7 KBSOUT8 KBSOUT9 KBSOUT10 KBSOUT11 KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62 KBSOUT15/GPIO61/XOR_OUT
5 18 45 78 89 116
TPAD30
32KX2 32KX1/32KCLKIN
38 PSID_DISABLE# 31 WLAN/BT_BTN# 18 LCD_TST_EN 10 GMCH_BL_ON
79 77
-1: 08/29 change Pin24 from "WWAN_RF_EN" to NC, because pin24 is H/W straping pin. it has H/W concern.
CHARGE_LED
DY
1
1
SB:06/24 Change R104 from 63.10334.1DL to 63.47234.1DL.Base on Winbond FAE recommend to fix system will hang up after Thermal T8 shutdown
LCLK VREF VCORF A_PWM0 RESERVED
2
E51_TxD
R104 4K7R2J-2-GP
NUM_LED CAP_LED
2
2
DY PIN 111
35 NUM_LED 35 CAP_LED 35 LED_MASK# 31 SNIFFER_BLUE# 18 LCD_TST 46 S5_ENABLE 21 RSMRST#_KBC 38 AD_OFF 27 PM_LAN_ENABLE 35 CHARGE_LED 37 CAPA_INT# 35 WLAN_LED_TEST
2 104 44 32 80
R105 10KR2J-3-GP
GA20 SERIRQ KBRST#
1
-1:08/30 Change Pin11 from NC to be"HDD_5V_EN"
GPIO01 GPIO03 GPIO04 GPIO05 GPIO06/HGPIO06 GPIO07/HGPIO07 GPIO10/HGPIO00/LPCPD# GPIO11/HGPIO02/CLKRUN# GPIO12/PSDAT3 GPIO13/B_PWM0 GPIO14/HGPIO04/TB1 GPIO16/HGPIO04 GPIO20/TA2 GPIO21/A_PWM1 GPIO23 GPIO24/HGPIO01 GPIO26/PSCLK2 GPIO27/PSDAT2 GPIO25/PSCLK3 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO36 GPIO40 GPIO42/TCK GPIO43/TMS GPIO44/TDI GPIO45 GPIO46/TRST# GPO47/JEN0# GPIO50/TDO GPIO51 GPIO52/RDY# GPIO53 GPIO55/CLKOUT GPIO56/TA1
121 125 122
-1:08/30 Change Pin10 from NC to be"WWAN_RF_EN"
INSTEAD_BTN#
64 95 96 108 93 94 124 8 13 62 63 114 117 118 119 6 10 11 12 109 120 65 66 14 15 16 17 20 21 22 23 24 25 26 27 28 30 31
o-
BADDR1-0 (PIN 111, 112) I/O Base Address.
C
KBC_PWRBTN# KBC_THERMTRIP#
18 LCD_CBL_DET# 39 AC_IN# 35 LID_CLOSE# 35 INSTEAD_BTN# 21,25 PM_CLKRUN# 38 BAT_IN# 18 BRIGHTNESS 31 CIRRX 35 BATFULL_LED 38 ACDC_ID 35 PWRLED 21 PM_PWRBTN# 35 SCRLK_LED 30 WWAN_RF_EN 24 HDD_5V_EN TPAD30 TP55
10KΩ external pull-down resistor on BADDR1: Core defined 3D3V_S0
102
1 21,28,43,45,46 PM_SLP_S3# 35 KBC_PWRBTN#
Forces the device to float all its output and I/O pins,if an external 10 KΩ pull-down resistor is conected.
D 2
C514
VCC_POR#
10K PD
TRIS#(Pin 110) TRI-STATE
-1:08/29 Change U22 pin110 define from NC to"USB_PWR_EN" or USB power control.
LPC_LFRAME# 20
ECSCI#_KBC
U22
31
PLT_RST1#_1
C517 SC10U6D3V5KX-1GP
46 19 115 76 88
NO PD
Keyboard Scan Keyboard Scan JTAG signals
VCC VCC VCC VCC VCC
GPIO Port JTAG signals GPIO Port
GPIO57/HGPIO03/KBSOUT17 GPIO60/KBSOUT16 GPIO61/SCL2 GPIO62/SDA2 GPIO63/PWUREQ# GPIO64/SMI# GPIO66/SWD GPIO70 GPIO71 GPIO75 GPIO77 GPIO81 GPIO87/SIN_CR
NO PD
Functionality of Pins 47, 48, 50, 51, 52
33 34 67 68 123 9 81 73 74 82 84 91 113
10K PD
DMIC_DET# 18 TPAD28 SNIFFER_PWR_SW#
BLUETOOTH_EN 30,31 USB_PWR_EN# 35,38 E51_TxD 30 TP97 TPAD28
3D3V_S0
Functionality of Pins 17, 20, 21, 23 25, 27
NO PD RES
VBAT
1 R329 2 0R0603-PAD
2
JENK (Pin 53)
USB_PWR_EN# E51_TxD
SCD1U16V2ZY-2GP
D WPC8763L STRAP PIN
AD_IA 39 KB_DET# 37
1
3D3V_AUX_S5
TPAD28 TPAD30
PCB_VER0 PCB_VER1
SC470P50V2KX-3GP
C504
SCD1U16V2ZY-2GP
C512
SCD1U16V2ZY-2GP 2 1
C505
SCD1U16V2ZY-2GP 2 1
1 2
C515
SCD1U16V2ZY-2GP 2 1
1 2
1
1 2
SC1U16V3ZY-GP
2
SCD1U16V2ZY-2GP
C513
PLACE CAP NEAR PIN80 AND PIN102
JEN0 (Pin 24)
1
C518
SCD1U16V2ZY-2GP
2
C193
SC1U16V3ZY-GP
1
C194
2
3D3V_AUX_S5
VBAT
1
Sheet
34
of
47
B
C
D
Power Dash Board to Board CONN
SA:04/22 change C532,C533,C534 connection power from "3D3V_S0" to "3D3V_AUX_S5"
SPI
Q3
3D3V_AUX_S5
R2 PDTC124EU-1-GP
1 2
2
R2 PDTC124EU-1-GP
EMI REQUEST
-c
1
Q37 2N7002PT-U
DY
2
1
VF
Q8
LED_PWR#
E
A
2
SC220P50V2KX-3GP
1 2
1 2
1
3 5 7 9 11 13 15 17 19 21 23 25 27
4 6 8 10 12 14 16 18 20 22 24 26 28
-1:0910 TV_LUMA TV_COMP TV_CRMA
10 M_LUMA 10 M_COMP 10 M_CRMA
-1:0910 USB_PP2 21 USB_PN2 21 UIM_RESET 30
UIM_RESET
USB_PP3 21 USB_PN3 21
5V_USB2_S5 3D3V_S0
MLX-CONN28A-2-GP
-1:08/31 Change CN6 pin26 from "5V_S5" to "5V_USB2_S5" 2
-1:08/29 Add U65 power switch to controll "5V_USB2_S5".
5V_USB2_S5
B
1
DY
2
ST100U6D3VBM-9GP
2 C
at least 80 mil 8 7 6 5
OC1# OUT1 OUT2 OC2#
USB_OC#3 21
TPS2062D-GP
1
1
Wistron Corporation EC27
DY
USB_OC#2 21
EC30
DY
EC128
GND IN EN1# EN2#
34,38 USB_PWR_EN#
WIFI_LED#
1
LED_CHARGE#
1 2 3 4
SCD1U50V3ZY-GP
1
B R1 R2
E
PDTC124EU-1-GP
EC31
DY
at least 80 mil
TC8
SC220P50V2KX-3GP
DY
C
LED_BAT#
EC29
C166 SCD1U16V2ZY-2GP
U65
Q5
2
1
3D3V_S0
C163 SCD1U16V2ZY-2GP
LED_PWR#
2
1 2
2
1
5V_S0
C165 SCD1U16V2ZY-2GP
EC150
SC220P50V2KX-3GP
DY
1
5V_S5
UIM_CLK UIM_DATA
WLAN_LED_TEST 34
1
R2 PDTC124EU-1-GP
2
LED_CHARGE#
E
1
C
R1
1
B
SC:08/09 Add EC150(78.22124.2FL) for EMI request, deault is dummy.
2
E
Q6 34 CHARGE_LED
UIM_VPP
30 UIM_CLK 30 UIM_DATA
5V_S5
3
SC220P50V2KX-3GP
R2 PDTC124EU-1-GP
30 UIM_VPP
WLAN_LED 29
BAW56PT-U 83.00056.E11
SC220P50V2KX-3GP
R1
3
become
LED_MASK#
2
LED_BAT#
2
B
2
SC:08/09 Add EC149(78.22124.2FL) for EMI request, deault is dummy.
1
Q7 34 BATFULL_LED
-1:08/29 Rename CN6 pin2,pin4 power net "5V_USB2_S5".
D14
WIFI_LED#
C
DY
5V_USB2_S5
1
32 SPDIF_D
2
R2 PDTC124EU-1-GP
G
C
R1
EC53
CN6 UIM_PWR
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
SC220P50V2KX-3GP
B
34 PWRLED
DY
CONN 28PIN
EC149
D
3
EC54
30 UIM_PWR
SATA_LED# 20
BAS16-1-GP
2
SC220P50V2KX-3GP
2
3
1
SC:08/11 Add EC163 on "LID_CLOSE" for RF team 20.K0227.012 Request.
DY
1
2
2
14
DRVIE_LED#
SC47P50V2JN-3GP
EC163
DY
SC220P50V2KX-3GP
2
1 G D15
MLX-CON12-11GP
BT_ACT_K# 31
LED_MASK# 34
LID_CLOSE# 34
EC55
Right I/O Board to Board CONN
o-
2
S
LID_CLOSE# DRVIE_LED# WIFI_LED# BT_LED#
1
DY
LED_NUM#
S
3
SC:08/09 Add EC148(78.22124.2FL) for EMI request, deault is dummy.
LED_BAT# LED_CHARGE#
BT_ACT_WPAN# 30
EC2
LED_CAP#
BAW56PT-U 83.00056.E11
Q36 2N7002PT-U
D
LED_PWR#
3
0R2J-2-GP
SC220P50V2KX-3GP
1 2 3 4 5 6 7 8 9 10 11 12
EC3
2
BT_LED#_R
2
LED_SCRLK#
2
2 2
D13
1
EC148
2 1
INSTEAD_BTN#
DY
R446
DY
KBC_PWRBTN#
SPICLK 34
SC220P50V2KX-3GP
2
150R2J-L1-GP-U EC98 SC4D7P50V2CN-1GP
1
SPIDO 34
SC220P50V2KX-3GP
2
DY
3D3V_S5
Main Source:20.K0227.008 2nd Source: 20.K0237.008
1
R333 150R2F-1-GP
BT_LED#
13
MLX-CON8-10-GP-U
20.K0227.008
E
2
R334 1
1
LED Board to Board CONN -1:09/02 Change CN3(LED Board) pin assignment.
4
SPI_HOLD#
1
VCC HOLD# CLK DIO
R1
SC220P50V2KX-3GP
CS# DO WP# GND
8 7 6 5
LED_NUM#
cc
SPI_WP#
150R2J-L1-GP-U
5V_S0 5V_S5
LED_SCRLK# LED_CAP# LED_NUM#
E
C
R2 PDTC124EU-1-GP
1
1 2 3 4
EC97 SC4D7P50V2CN-1GP
CN3
B
34 NUM_LED
U21
W25X80-VSSI-GP
3
LED_CAP#
C
R1
B
SCD1U16V2ZY-2GP
8M Bits 3D3V_AUX_S5
2
EC34 SC4D7P50V2CN-1GP
2
C506 34 CAP_LED
2 3 4 5 6 7 8 10
34 KBC_PWRBTN# 34 INSTEAD_BTN#
Q1
SCD1U16V2ZY-2GP
CN2
9 1
C5 SCD1U16V2ZY-2GP
SPI_HOLD# 4 3 2 1
1
1
5V_S5
-1:09/02 Change CN2(Power Dash Board) pin assignment.
E
Q2
SPICS# SPICS# R99
1
DY
SRN10KJ-6-GP RN24
34 SPICS# 34 SPIDI
C509
2
5 6 7 8
C508 SC10U6D3V5MX-3GP
4
1
3D3V_AUX_S5
LED_SCRLK#
C
R1
B
34 SCRLK_LED
SPI FLASH ROM
E
1
A
Title
FWH and Board to Board CONN Size A3
Document Number
Rev
DS2-Intel
Date: Wednesday, September 12, 2007 D
Sheet E
-1 35
of
47
FAN1_VCC
5V_S0
1 3
1 C8 SC10U10V5ZY-1GP
R187 10KR2J-3-GP
D24 BAS16-1-GP
FAN1_VCC FAN1
4
2
1
2
2
C346 SCD1U16V2ZY-2GP
2
1
*Layout* 15 mil
FAN1_FG1
3 2 1
1 2
G792_SCL G792_SDA
*Layout* 15 mil
1
4 3
cc
RN20
3D3V_S0
2
SRN10KJ-5-GP
C337 SC1KP50V2KX-1GP
5 MLX-CON3-6-GP
SC:08/10 Change C337 from 78.10234.1BL to 78.10224.2FL
SGND1 SGND2 SGND3
8 10 12
-c
H_THERMDA 5 C173 SC2200P50V2KX-2GP
Place on reverse side of CPU G792_DXP2 C178 SC2200P50V2KX-2GP
1
1
8,21 PM_PWROK
G792_RESET# 2 4K7R2J-2-GP SA:4/28
Place near G792 chip as close as possible
1
GAP-CLOSE
Place near CPU and NB (Orignal Q25 location) 1
C
G792_DXP3
C177 SC2200P50V2KX-2GP
Q33 CH3904PT-GP
B
G792_DXN3
2
VF
G51
Place G14 near U36
R298 10KR2J-3-GP
2
Q25 CH3904PT-GP
B
G792_DXN2
R300
DXP1:108 Degree DXP2:H/W Setting (85 Degree) DXP3:88 Degree
H_THERMDC 5
C
5 17
E
DGND DGND
E
1
ALERT# THERM# THERM_SET RESET#
G792SFUF-GP
2
V_DEGREE =(((Degree-72)*0.02)+0.34)*VCC
THRM#_R
V_DEGREE
R301 47KR2F-GP
15 13 3 2
G792_CLK 21 G792_SDA 34 G792_SCL 34
1
2 0R2J-2-GP
G792_SDA G792_SCL
2
DY
DXP1 DXP2 DXP3
1 4 14 16 18 19
2
1
7 9 11
FAN1 FG1 CLK SDA SCL NC#19
2
2
-1:0909 R83 21 THRM# 34,46 PURE_HW_SHUTDOWN#
VCC DVCC
o-
SC4D7U6D3V5KX-3GP
C473 SCD1U16V2ZY-2GP R310 100KR2J-1-GP
2
C479
1
Setting T8 as 85 Degree
3D3V_AUX_S5 SA:4/28
1
1 R305 30KR2F-GP
2
C486 SC1U10V3ZY-6GP
2
1
1
5V_S0
6 20
G64
Place G15 near U36 GAP-CLOSE
1
5V_G792_S0
2
R308 2 200R2F-L-GP
1
U19
*Layout* 30 mil 1
2
5V_S0
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Thermal/Fan Controllor G792 Size A3
Document Number
Rev
DS2-Intel
Date: Wednesday, September 12, 2007
Sheet
-1 36
of
47
SB:06/27 Change K/B connector from 20.F0694.025 to 20.K0291.027 .
TouchPad Connector 5V_S0
2 1 3 4 1 1
FOX-CON4-12-GP
R190
1
R191
1
DY
CAPACITY BUTTON
2 0R3-0-U-GP
CN1
7
2 0R3-0-U-GP
1 2 3 4 5 6
CAP_SCL CAP_SDA
34 CAP_SCL 34 CAP_SDA 34 CAPA_INT#
-1:09/02 Change CN1(Capacity button) pin2 from GND to NC
8 MLX-CON6-11-GP
20.K0227.006 CAP_SCL CAP_SDA
1
Main Source:20.K0227.006 2nd Source: 20.K0228.006
DY
DY
SC220P50V2KX-3GP
EC159
2
EC158
SC:08/09 Add EC158,EC159(78.22124.2FL) for EMI request .Default is DUMMY
VF
5V_S0
1
o-
EC86 SC220P50V2KX-3GP 2
-c
1
EC67
1
EC76
1
EC66
1
EC65
KROW7 KROW6 KROW5 KROW4
SC220P50V2KX-3GP 2 SC220P50V2KX-3GP 2 SC220P50V2KX-3GP 2 SC220P50V2KX-3GP 2
EC81
1
EC88
1
EC87
EC82
1
1
KCOL16
1
EC68
1
EC77
1
EC75
1
EC78
SC220P50V2KX-3GP 2 SC220P50V2KX-3GP 2 SC220P50V2KX-3GP 2 SC220P50V2KX-3GP 2
1
EC80
KROW3 KROW2 KROW1 KROW0
2
KB_DET# 34
KCOL15 KCOL14 KCOL13 KCOL12
SC220P50V2KX-3GP 2 SC220P50V2KX-3GP 2 SC220P50V2KX-3GP 2 SC220P50V2KX-3GP 2
1
EC70
1
EC69
1
C188 SC33P50V2JN-3GP
SA: 04/15 change TPAD conn to 20.K0179.004
1
EC89
1
EC91
1
EC90
SC220P50V2KX-3GP 2 SC220P50V2KX-3GP 2 SC220P50V2KX-3GP 2 SC220P50V2KX-3GP 2
1
EC85
1
EC73
1
EC84
1
EC72
1
SC220P50V2KX-3GP 2 SC220P50V2KX-3GP 2 SC220P50V2KX-3GP 2 SC220P50V2KX-3GP 2 EC79
EC71
1
2 3 4 6
2 2
C187 SC33P50V2JN-3GP
3D3V_S0
SC220P50V2KX-3GP 2 SC220P50V2KX-3GP 2 SC220P50V2KX-3GP 2 SC220P50V2KX-3GP 2
5 1
34 TPCLK 34 TPDATA
for EMI
KCOL7 KCOL6 KCOL5 KCOL4
C135 SC1U10V3ZY-6GP
TPAD1
SB:06/13
Internal KeyBoard Connector
JAE-CON27-GP
KCOL11 KCOL10 KCOL9 KCOL8
C148 SCD1U16V2ZY-2GP
RN22 SRN10KJ-5-GP
28
KCOL3 KCOL2 KCOL1 KCOL0
1
34
2
KCOL10 KCOL11 KCOL9 KCOL14 KCOL13 KCOL15 KCOL16 KCOL12 KCOL0 KCOL2 KCOL1 KCOL3 KCOL8 KCOL6 KCOL7 KCOL4 KCOL5 KROW0 KROW3 KROW1 KROW5 KROW2 KROW4 KROW6 KROW7
2
KCOL[0..16]
5V_S0
SC220P50V2KX-3GP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
34
cc
29
KROW[0..7]
1
KB1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
KeyBoard-CONN Size A3
Document Number
Date: Wednesday, September 12, 2007
Rev
DS2-Intel Sheet
37
-1 of
47
5
4
U66
5V_S5
5V_USB1_S5
DY
5V_S5
3D3V_S5
R206 100KR2J-1-GP
1
1
2
2
USB_OC#1 21
1
2 1 CH3904PT-GP Q21
B
D26 BAV99PT-GP-U
PSID_DISABLE# 34
R225 2K2R2J-2-GP
D
2 3
1
1
G
D
D25 BAV99PT-GP-U
R222 10KR2J-3-GP
3
2
USB_OC#0 21
R221 15KR2J-1-GP EC176 SCD1U16V2ZY-2GP
2
DY TC6 ST100U6D3VBM-9GP
E
DY
TPS2062D-GP
C
OC1# OUT1 OUT2 OC2#
2
GND IN EN1# EN2#
1
at least 80 mil
8 7 6 5
1
34,35 USB_PWR_EN#
2
1
1 2 3 4
2
at least 80 mil
1
5V_S5
3
R220
3
2
ACDC_ID 34
2N7002PT-U Q20
DY1
R1
1 IN
34 AD_OFF
3 OUT
R1
-c
2
1 2
SCD01U50V2KX-1GP
1
DY
Left I/O Board to Board CONN Batt Connecter BATT1
VF
B
11 10 9 8 7 6 5 4 3 2 1
2
R260 47KR3J-L-GP
DY
DDTC124EUA-7F-GP
Place near DCIN1
GND GND GND2 GND1 BAT_ALERT SYS_PRES# BATT_PRS# DAT_SMB CLK_SMB BATT2+ BATT1+
C
C
2 GND
R2
C4 SCD01U50V2KX-1GP
C398 SC10U25V6KX-1GP
R2
AD+_JK
C408
E
PDTA124EU-1-GP
Q27
Id=17A Qg=100~150nC Rdson=5.4~6.5mohm
Q26
B
Reserved for EMI
P2003EVG-GP
C410 SCD01U50V2KX-1GP
2
This cap should be used only as last resort for EMI suppression.
MLX-CONN24A-1-GP
C409
1
R9 240KR3-GP
8 7 6 5
2
C7 SC1U25V5KX-1GP
D D D D
SCD01U50V2KX-1GP
DY
U47 S S S G
1
C3 SCD1U50V3KX-GP
AD+
1 2 3 4
2
1
AD+_JK
2
4 6 8 10 12 14 16 18 20 22 24 29 27
1
3 5 7 9 11 13 15 17 19 21 23 NP2 25
1
CONN 24PIN(AC-In+USB)
28 30 2
2
21 USB_PP1 21 USB_PN1
2
o-
21 USB_PP0 21 USB_PN0
26 NP1 1
1
Left I/O Connector
R207
33R2J-2-GP
cc
CN5
2
5V_USB1_S5
1
2
33R2J-2-GP
SB: 06/27 Change CN5 from 20.F1089.028 to 20.F1134.024
C
1 S
D
PD_ID
-1:08/30 Add U66 power switch to control USB power
3D3V_AUX_S5
D23
BAT_SCL
3 1 BAV99PT-GP-U D1
2 BAT_SDA
3
SB:07/09 Change R21 from 100K to 470K for power team request
PBAT_ALARM#
PBAT_PRES1# R22 PBAT_SMBDAT1 PBAT_SMBCLK1
TP17
R21
2 100R2J-2-GP
1
1
2 470KR2J-2-GP
RN1
1 2
4 3
SRN100J-3-GP R1
2
1 BAV99PT-GP-U
3D3V_AUX_S5 BAT_IN# 34 BAT_SDA 18,34,39 BAT_SCL 18,34,39
D6
2 BAT_IN#
3
BT+
1 0R0603-PAD
B
2
1 BATT_SENSE 39
SYN-CON9-1-GP-U1
BAV99PT-GP-U D2
Battery CONN. Main source:20.80953.009
A
1
C2 SCD1U50V3KX-GP
C1 SC2200P50V2KX-2GP
PBAT_ALARM#
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
3 1
2
2nd source:20.80626.009
1
2
2
A
Title
AD/BATT CONN
BAV99PT-GP-U Size A3
Document Number
Date: Wednesday, September 12, 2007 5
4
3
2
Rev
DS2-Intel Sheet 1
38
-1 of
47
A
B
C
D
E
MAX8731_LDO 1
SB:06/29 Add EC130,EC131,EC132,EC133(78.10494.4BL) for "BT+" by EMI request BT+
1
1
2
2
EC133 4
1
2
EC132
SCD1U50V3ZY-GP
NEAR
5V_AUX_S5
EC131
SCD1U50V3ZY-GP
2
15K4R2F-GP
EC130
SCD1U50V3ZY-GP
2
R45 4
SCD1U50V3ZY-GP
1
1
ACAV_IN
1
2
R44 10KR2F-2-GP
R48 100KR2J-1-GP 2
Adaptor In Soft-Start Circuit
AC_IN#
1 2 R229 D01R2512F-4-GP
1 2
1
CCV CCI CCS REF DAC GND
MAX8731AETI-GP
74.08731.A73
1 2 C373 SC10U25V0KX-3GP 2 1
1 2
C375 SC10U25V0KX-3GP 2 1
18
MAX8731_CSIP
CSIN
17
MAX8731_CSIN
FBSB
16
FBSA
15
U7 SI4800BDY-T1
2nd:FDS8884(84.8884.A37)
BAT_SENSE 1 R228
2 BATT_SENSE 100R2F-L1-GP-U
1 2
68.5R850.101
C335 SC10U25V0KX-3GP 2 1
IND-5D8UH-GP
C13 SC10U25V6KX-1GP
1
1
C32 SCD1U25V3KX-GP
2
1 2 R204 D01R2512F-4-GP
1
19
CSIP
INP
GND
C389 SCD1U16V2ZY-2GP
1 2
C49 SC1U10V3KX-3GP
1 2
C384 SCD01U50V2ZY-1GP
1 2
MAX8731_CCV 6 MAX8731_CCI 5 MAX8731_CCS 4 MAX8731_REF 3 MAX8731_DAC 7 12
2 4K7R2F-GP
C385 SCD01U50V2ZY-1GP
1MAX8731_CCV1
C387 SCD01U50V2ZY-1GP
1
2
1 2
2
10KR2F-2-GP
C393 SCD1U16V2ZY-2GP
1 R230
1 R227
PGND
29
8
2
C336 SC10U25V0KX-3GP
BATSEL
2
14
CHG_AGND
20
1
Layout Trace 300mil
2
DLO
MAX8731_LX1
BT+
CHG_PWR
L14
GAP-CLOSE-PWR-3-GP
SDA
2nd:FDS8884(84.8884.A37)
R224 1R3F-GP 1 2 MAX8731_LX 1 C42 2 SCD1U25V3KX-GP 1 2 C381 SC220P50V2JN-3GP MAX8731_DLO
2
9
1 2 C48 SC1U10V3KX-3GP
1
BAT_SDA
18,34,38 BAT_SDA
34 AD_IA
23
DY
U8 SI4800BDY-T1
MAX8731_DHI
VF
LX
5 6 7 8
24
D D D D
DHI
SCL
2
CHG_AGND
G45
10
25 21
R42 0R3-0-U-GP MAX8731_BST 1 2MAX8731_BST1 1 MAX8731_LDO D8 1SS400PT
GAP-CLOSE-PWR-3-GP
BAT_SCL
CHG_AGND 18,34,38 BAT_SCL
BST LDO
ACOK
MAX8731_VCC
2
13
R223
33R2J-2-GP
1
ACAV_IN
VDD
C380 SC1U10V3KX-3GP
G46
SCD1U25V3KX-GP
CSSN VCC
CHG_AGND
D D D D
1 C390
28
27 26
3
NEAR INPUT AD+
G S S S
NEAR KBC POWER 11
CSSP
ACIN
P2003EVG-GP
G S S S
DCIN
BT+
8 7 6 5
SCD1U25V3KX-GP
2
2
2
o-
22
MAX8731_ACIN
D D D D
2nd:A04433(84.04433.A37)
4 3 2 1
CHG_AGND
MAX8731_DCIN
U5 S S S G
C379
-c
2
3D3V_AUX_S5
2
1 2
2
49K9R2F-L-GP
C383 SCD01U50V2ZY-1GP
2 1
R226
1
U46
ASNS
C43 SC1U25V5KX-1GP
365KR3F-GP
CHG_AGNDCHG_AGND
1
R41
R40
2
1
S 2 0R2J-2-GP
MAX8731_CSSN
2
SCD1U25V3KX-GP
MAX8731_CSSP
C378
G
1
2 S
1
1
Q24 2N7002PT-U
G ACAV_IN
2
1 AD+
1
2 100KR2J-1-GP
5 6 7 8
DCIN_GATE2 1 2 49K9R2F-L-GP R231
3
1 R241
AD+
R18 470KR2J-2-GP
2
DCIN_GATE1 D
Q22 2N7002PT-U
1
3
3
G49
DC_IN_D D
S
1
1
2
2
2nd:A04433(84.04433.A37)
1 2 3 4
4 3 2 1
P2003EVG-GP
R240 10KR2J-3-GP
G
DCBATOUT
Layout Trace 300mil
2 ACAV_IN
1
Layout Trace 300mil
cc
AD+_TO_SYS
1 2 3 4
GAP-CLOSE-PWR-3-GP
3 Q23 2N7002PT-U
U48 S S S G
D D D D
2
8 7 6 5
G50
Trace 250mil
D
GAP-CLOSE-PWR-3-GP
AD+ Layout
C68 SC1U10V3KX-3GP
2
1
34 AC_IN#
DY
BATT_SENSE 38
C386 SCD01U50V2ZY-1GP 1
1 2 G48 GAP-CLOSE-PWR
Wistron Corporation
CHG_AGND
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
CHARGER MAX8731 Size Document Number Custom
Rev
A
B
C
D
-1
DS2-Intel
Date: Wednesday, September 12, 2007
Sheet E
39
of
47
A
B
C
D
E
1 2
1 2
1
1 TC4 ST220U6D3VDM-13GP
2
1
C218 SCD1U10V2KX-4GP
2
2 1
1 1
C581 SC18P50V2JN-1-GP
1
1 2
G32
GAP-CLOSE-PWR 2
G27
GAP-CLOSE-PWR 2
G29
GAP-CLOSE-PWR 2
1
4
GAP-CLOSE-PWR
1
DY
+3.3V_ALWP
1 R132
+VCC_TPS51120
2 0R2J-2-GP
51120_GND
2 0R2J-2-GP
2 0R0402-PAD
C575
DY
R401 13K3R3F-GP
SC330P50V3KX-GP
GAP-CLOSE-PWR 2
G41
GAP-CLOSE-PWR 2
G43
GAP-CLOSE-PWR 2
G40
GAP-CLOSE-PWR 2
1
3
GAP-CLOSE-PWR
1 2
1
1 C248 2
2
1 2 51120_VFB2
1 2 G63 GAP-CLOSE-PWR
+VCC_TPS51120 51120_GND
DY
TC20 ST220U6D3VDM-13GP
51120_GND 2
51120_GND
VF
DY
1
51120_DRVL2
DY 2
51120_VREF2 0R2J-2-GP
R404 30K9R3F-GP
C586 SCD1U10V2KX-4GP
2 0R2J-2-GP
R396
SC18P-GP
DY
G42
1
1
DY
1
1 R390
GAP-CLOSE-PWR 2
1
L7 1 2 IND-3D3UH-57GP
2D2R5F-2-GP
2
U32 AO4712-GP
51120_VREF2 2 0R0402-PAD
2 G44
1
1
5 6 7 8
51120_TONSEL1 R135
1
C587 SC2200P50V2KX-2GP
SA:04/23 Change C733 to DUMMY for power team request
SI4800BDY-T1 U29
51120_DRVH2 51120_LL2
3D3V_S5 G39
2
1 2
1 2
C257 SCD1U50V3KX-GP
+3.3V_ALWP
C252 SC10U25V6KX-1GP
2
5 6 7 8
D D D D
SC:08/13 Change R135 from 63.R0034.1DL to ZZ.R0402.ZZZ
1 R130
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Inductor: 3.3UH CYNTEC 11Arms 14.5Apeak O/P cap: 220U6.3V 6TPE220M 25mOhm 2.4Arms/ 77.22271.17L H/S: AO4468 SO-8/ 30mOhm/ 4.5Vgs L/S: AO4712 SO-8/ 7.3mOhm/ 4.5Vgs
SC:08/13 Change R130 from 63.R0034.1DL to ZZ.R0402.ZZZ
2 0R2J-2-GP
Iout = 5A OCP < 10A
2
2
2
1
51120_DRVH1 51120_DRVH2
CPUCORE_ON 41,43,44,45
-c DY
2
cc
27 14
32 31
24 17 5 33 1
DY
C225 SCD1U50V3KX-GP
2 D D D D 1 DRVH1 DRVH2
1 R131
R126
1
GAP-CLOSE-PWR 2
1
DCBATOUT_TPS51120
2
1 1
RUN_ON
51120_DRVL1 51120_DRVL2
2
2 1
3
G
TPAD30 TP76
DRVL1 DRVL2
25 16
0R2J-2-GP
DY
DY
R391
D
2
D
S 51120_GND
TP0610T-T1-E3-GP R125 3 1
G
DY
G31
7K5R2F-1-GP SC330P50V3KX-GP
S S S G
S
2
R143 100KR2J-1-GP
30 11
1 R134
Q32
51120_DRVL1
D D D D
51120_GND
2
51120_LL2 51120_LL1
15 26
PGOOD1 PGOOD2
51120_GND
R381 Q13 200KR2F-L-GP 2N7002PT-U
51120_VFB1
C570
G S S S
VREF2
+VCC_TPS51120
GAP-CLOSE-PWR 2
1
4 3 2 1
4
C243 SC1KP50V2KX-1GP
2 SC1KP50V2KX-1GP
30KR3F-GP
DY
4 3 2 1
51120_VREF2
51120_CS1 2 12K1R2F-L1-GP 51120_CS2 2 11K3R2F-2-GP
1 C591
4 3 2 1
G S S S VO1 VO2
2 SC1KP50V2KX-1GP
1 R389 1 R405
R392 2D2R5F-2-GP
4 3 2 1
1 8
TI suggest R<=15Kohm
+VCC_TPS51120 1 C572
7 2
LL2 LL1
+5V_ALWP +3.3V_ALWP
DY
G30
1
51120_GND
2
VFB2 VFB1
5 6 7 8
1 6 3
R384
o-
C245 SCD1U10V2KX-4GP
1
DY 2
EN1 EN2 EN3 EN5
2 0R2J-2-GP 51120_VFB2 2 0R2J-2-GP 51120_VFB1
DY DY
1 1
C237 SCD1U10V2KX-4GP 2 1
R138 R136
29 12 10 9
3D3V_S0
COMP2 COMP1
2 0R2J-2-GP R129 51120_EN1 1 2 0R0402-PAD
46 3V/5V_EN
+VCC_TPS51120
VREG3 VREG5
1
21,28,34,44,45 PM_SLP_S4#
2
DY
U56 TPS51120RHBR-GPU1
SKIPSEL TONSEL
1
DY R133
U26 AO4712-GP
5V_S5 G28 1
+5V_ALWP 1 2 IND-3D3UH-57GP
+VCC_TPS51120
51120_SKIPSEL
SC:08/13 Change R129 from 63.R0034.1DL to ZZ.R0402.ZZZ
2
1 2
C249 SC10U10V5KX-2GP
+5V_ALWP
1
S S S G
3D3V_AUX_S5
2
2 51120_VBST1 0R3-0-U-GP
GAP-CLOSE-PWR
3
1 2
51120_LL1 1 2 51120_VBST1_11 C569 R388 SCD1U50V3KX-GP
C559 SC2200P50V2KX-2GP
L6
D D D D
GAP-CLOSE-PWR 2
G36 1
C577 SCD1U50V3KX-GP
Iout =6A OCP < 12A
DY
SA:04/23 Change C746 to DUMMY for power team request
SI4800BDY-T1 U28
51120_DRVH1 51120_LL1
20 22
GAP-CLOSE-PWR 2
G37 1
2 51120_VBST2 0R3-0-U-GP
V5FILT VIN
1
DCBATOUT_TPS51120 51120_LL2 1 2 51120_VBST2_11 C594 R410 SCD1U50V3KX-GP
CS1 CS2
GAP-CLOSE-PWR 2
28 13
G35
1
PGND1 PGND2 GND GND
4
C585 SC1U10V3KX-3GP
VBST1 VBST2
GAP-CLOSE-PWR 2
2 5D1R3J-GP
23 18
G34
1
1 R402
19 21
GAP-CLOSE-PWR 2
2
5 6 7 8 2
G33
C250 SC10U10V5KX-2GP
1
C556 SC10U25V6KX-1GP
+VCC_TPS51120
2
5V_AUX_S5
G38
C582 SC10U25V6KX-1GP
DCBATOUT_TPS51120
1
DCBATOUT
C223 SC10U25V6KX-1GP
DCBATOUT_TPS51120
Vout=1V*(R1+R2)/R2 GND SKIPSEL
AUTOSKIP
COMP TONSEL 1
VFB1 VFB2 EN1,EN2 EN3,EN5
N/A
VREF2 AUTOSKIP /FAULTS OFF N/A
380k/CH1 580k/CH2 N/A
280k/CH1 430k/CH2 not use
N/A
not use
Switcher OFF LDO OFF
not use not use
FLOAT PWM
CURRENT MODE 220k/CH1 330k/CH2 ADJ. ADJ. Swithchr ON LDO ON
V5FILT PWM
D-Cap MODE 180k/CH1 2870k/CH2 5V Fixed Output 3.3V Fixed Output Switcher ON VREG3 on
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
DC to DC 3.3V & 5V Size Custom
Document Number
Rev
Date: Wednesday, September 12, 2007 A
B
C
D
-1
DS2-Intel Sheet E
40
of
47
4
3
6262_AGND 6262_VCC
1
1 2
2 48
27
BOOT2
26
1 C350
19
6262_VSUM
11K3R2F-2-GP
1 2
1 2
6262_AGND
SCD01U25V2KX-3GP
When test without cpu, R483 & R486 change to 0 ohms
1 1
1 R218 2K61R3F-GP
1 2
R215 C372 11KR2F-L-GP SCD068U10V2KX-1GP
R216
1
2 1R3F-GP
6262_ISENN2 42
R214 6262_ISEN1
1
2
10KR3F-L-GP
2
R183 NTC-10K-9-GP B
1
Place close to phase 1 chocke R33 1KR3F-GP
2 0R0603-PAD
C369 SCD01U25V2KX-3GP
2
SB:06/23 Change C372 from 78.47323.2FL to 78.68323.5FL
C363 SCD01U25V2KX-3GP
C364
C368
6262_ISENP2 42
R29
1
6262_AGND
2 3K6R2F-GP
1 C28
C365 SCD22U10V2KX-1GP
2
2
2 0R0603-PAD
6262_VO
1
VF 1
2
1
2
10KR3F-L-GP C370
R20
6262_OCSET
18
2
R217
2
6262_VW
2
SC1KP50V2KX-1GP
VO
C
3K65R3F-GP
1 1
8
1
2 6K81R2F-1-GP
R219 6262_VSUM
SB:06/22 Change R20 from 64.12725.6DL to 64.11325.6DL
1
VSUM
6262_AGND
6262_ISENN1 42
10KR3F-L-GP
6262_PHASE2 42 6262_LGATE2 42
2
COMP
25
1
NC#25
U43
VW
6262_ISEN2
6262_ISEN2
2
FB2
6262_ISENP1 42
2 1R3F-GP R35 1 2
2
28 30 29 23
PHASE2 LGATE2 PGND2 ISEN2
OCSET8
10
1 R34
C356 SCD22U25V3KX-GP
ISL6262ACRZ-T-GP-U
FB
2
10KR3F-L-GP
2 SC4D7U6D3V3KX-GP
1 2 R210 0R3-0-U-GP 1
1
11
C362 SCD22U10V3KX-2GP
6262_UGATE2 42
6262_BOOT2
1
2
cc UGATE2
2
R24
5V_S0
2
6262_FB
6262_COMP
1 R27
SC:08/13 Change R27 from 63.00000.00L to ZZ.R0603.ZZZ
1
VDIFF
2 SC470P50V2KX-3GP
1 R209 C355 1
R28
6 VCC_SENSE
3V3
13
PVCC
31
3K65R3F-GP 6262_VSUM 1 R26
6262_ISEN1
SCD22U10V2KX-1GP
6 VSS_SENSE
PGOOD
DPRSLPVR DPRSTP# CLK_EN#
C357
2
2
45 46 47
9
1
SC220P50V2KX-3GP
20
VID0 VID1 VID2 VID3 VID4 VID5 VID6 VR_ON
o-
C360 2 1 1 2 R212 SC1KP50V2KX-1GP 255R2F-L-GP R213 1 2 1KR2F-3-GP
SC:08/13 Change R28 from 63.00000.00L to ZZ.R0603.ZZZ
ISEN1
24
37 38 39 40 41 42 43 44
6262_VDIFF 6262_FB212
1 2 1KR2F-3-GP
1 R208 2 97K6R2F-GP C351 1
B
33
DFB
6262_VID6 2 0R2J-2-GP
6262_LGATE1 42
PGND1
17
1 R197
6262_VID4 6262_VID5
R211
32
6262_DFB
CPU_VID6
6262_VID1 6262_VID0
34
LGATE1
DROOP
CPU_VID4 CPU_VID5
SRN0J-5-GP RN4 SRN0J-6-GP RN5 1 4 2 3
6 CPU_VID[0..6]
5 6 7 8
PHASE1
VSEN
4 3 2 1
PSI# PMON RBIAS VR_TT# NTC SOFT
1 R200 6262_BOOT1
SCD22U10V3KX-2GP
CPU_VID3 CPU_VID2 CPU_VID1 CPU_VID0
2 3 4 5 6 7
2 0R3-0-U-GP 1 C345 SCD22U25V3KX-GP 2 6262_PHASE1 42
16
C
36
14
If NTC=330Kohm, R10=8.66K
35
BOOT1
6262_VSEN
470K /0402 size
6262_NTC 6262_SOFT 1 2 6262_AGND C19 SCD015U25V3KX-GP SCD01U16V2KX-3GP 6262_VID0 2 6262_VID1 6262_VID2 SB:06/17 Change R12,R16,R17 R198 from 0402 0 6262_VID3 Ohm to 0402 close pad. 6262_VID4 6262_VID5 6262_VID6 R198 1 CPUVCORE_ON_R 2 40,43,44,45 CPUCORE_ON 0R0402-PAD 6262_DPRSLP 1 2 8,21 DPRSLPVR R16 0R0402-PAD 1 2 6262_DPRSTP# 6,8,20 H_DPRSTP# R17 0R0402-PAD 6262_VID3 21 CLK_EN# 6262_VID2
UGATE1
GND_T
RTN
R185 4K02R3F-GP C11 1
1 R184 2 NTC-470K-1-GP
GND
49
15
1
6262_PSI# 6262_PMON 6262_RBIAS
21
6262_RTN
6262_AGND
2
D
6262_UGATE1 42
-c
5 CPU_PROCHOT#
0R0402-PAD 2 147KR2F-GP
VIN
VDD 2 1 R15
VGATE_PWRGD 8,21
C9 SCD01U25V2KX-3GP
2
22
1 1 R12 TPAD30 TP86 6262_AGND
6 PSI#
R203 1K91R2F-1-GP
6262_AGND
6262_AGND
Place close to phase 1 chocke
6262_3V3
R202
1
D
6262_VIN
C366
C367 SC1U10V3KX-3GP
1
1 SCD01U25V2KX-3GP 2 1
2
1 2
R30 10R3J-3-GP
10R3J-3-GP
R25 10R3J-3-GP
SB:06/17 Remove R205,C348,TP86 power monitor circuit.
2
DCBATOUT 3D3V_S0
5V_S0
6262_DROOP
5
2
SB:06/23 Change R29 from 64.32415.55L to 64.36015.6DL
G47
6262_VO
1
2
GAP-CLOSE-PWR
SC180P50V2JN-1GP
6262_AGND
6262_AGND
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
DC-DC VCCCPUCORE 1/2 Size A3
Document Number
Rev
5
4
3
2
-1
DS2-Intel
Date: Wednesday, September 12, 2007
Sheet 1
41
of
47
5
4
3
2
1
DCBATOUT DCBATOUT
1
41 6262_PHASE1
1
1
EC127
2
2
SCD1U50V3ZY-GP
2
SCD1U50V3ZY-GP
2
2
1
1
1
1 2
2
SCD1U50V3ZY-GP
EC126
D
SB:06/26 Add EC120~EC127(78.10494.4BL),total 8 pcs CAP for EMI team request.
Iomax=47A VCC_CORE_S0
2
6262_ISENP1 41
1
ST330U2D5VDM-9GP
2
2
1 2
1
C
PANASONIC 330uF / 2V / V size ESR=6mohm / Iripple=3.7A
1 2
SC10U25V6KX-1GP
C338 SCD1U25V3KX-GP
1 2
2
C344
DY
-c L15
1
41 6262_PHASE2
C40 SCD1U50V3ZY-GP
Panasonic ETQP4LR36WFC 10*11.5*4mm 0.34uH / 24A DCR=1.1mohm
4 3 2 1
4 3 2 1
S S S G
S S S G
41 6262_UGATE2 B
TC1
oC339 SC10U25V6KX-1GP
SC10U25V6KX-1GP
C343
2
SC10U25V6KX-1GP
2
D D D D
D D D D
Id=13A DY Qg=10~14nC Rdson=9.4~12mohm
5 6 7 8
5 6 7 8
C340
1
1
1
DCBATOUT
U42 POWERPAK-8P-GP
TC9 ST330U2D5VDM-9GP
2
6262_ISENN1 41
C
U4 POWERPAK-8P-GP
DY
cc
2
4 3 2 1
4 3 2 1
S S S G
S S S G
C6 SC330P50V3KX-GP
DY
TC10 ST330U2D5VDM-9GP
1 1
Id=14.5A Qg=25~35nC Rdson=5.9~7.25mohm
2
G1
GAP-CLOSE-PWR-3-GP
1
2
G2
GAP-CLOSE-PWR-3-GP
ST330U2D5VDM-9GP
2
2
5 6 7 8
DY
TC12
D D D D
D D D D
U1 POWERPAK-8P-1-GP
R8 2D2R5F-2-GP
1
1
-1:0912 5 6 7 8
-1:0912
1
IND-D36UH-9-GP
U40 POWERPAK-8P-1-GP
B
2
ST330U2D5VDM-9GP
1
1
4 3 2 1
DY TC2
2
2
2
2
G3
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
C31 SC330P50V3KX-GP
DY
2
S S S G
S S S G
4 3 2 1
G4
2 1
U6 POWERPAK-8P-1-GP
1
1
5 6 7 8
DY
TC11
D D D D
D D D D
U44 Id=14.5A Qg=25~35nC POWERPAK-8P-1-GP Rdson=5.9~7.25mohm
R31 2D2R5F-2-GP
ST330U2D5VDM-9GP
-1:0912
VF
-1:0912
1
IND-D36UH-9-GP
5 6 7 8
41 6262_LGATE2
2
1 2
SCD1U25V3KX-GP
2
2
SC10U25V6KX-1GP
SC10U25V6KX-1GP
TC7 SE100U25VM-14GP
1
1
1 2
SC10U25V6KX-1GP
1
1 2
C21
Panasonic ETQP4LR36WFC 10*11.5*4mm 0.34uH / 24A DCR=1.1mohm
4 3 2 1
2
SCD1U50V3ZY-GP
1 2
SCD1U50V3ZY-GP
5 6 7 8
5 6 7 8 4 3 2 1
C352
EC125
L13
41 6262_UGATE1
41 6262_LGATE1
C22
EC124
SCD1U50V3ZY-GP
C353
EC123
SCD1U50V3ZY-GP
S S S G
S S S G
Id=13A DY Qg=10~14nC Rdson=9.4~12mohm
U41 POWERPAK-8P-GP
EC146
EC122
SCD1U50V3ZY-GP
U2 POWERPAK-8P-GP
D D D D
D D D D
D
EC147
EC121 SCD1U50V3ZY-GP
EC120
DY
SCD1U50V3ZY-GP
1
1
SC:08/09 Add EC146,EC147 (78.10492.4BL) for EMI request . Please place EC146 near C352, EC147 near U1
SA: 04/11 Add depend on PW team
If VCC_SENSE and VSS_SENSE pins have pulled resistors to VCC_CORE_S0 ==> Remove R44/R45/R46/R47.
41 6262_ISENP2
41 6262_ISENN2
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
DC-DC VCCCPUCORE 2/2 Size A3
Document Number
Rev
5
4
3
2
-1
DS2-Intel
Date: Wednesday, September 12, 2007
Sheet 1
42
of
47
5
4
DCBATOUT
3
2
1
+1.05V_PWR_SRC G23
1
2
GAP-CLOSE-PWR G22 1 2
Iout = 10A OCP>20A
D
GAP-CLOSE-PWR G21 1 2
+1.05V_SUSP
1
C461 SC2200P50V2KX-2GP
C460 SC10U25V6KX-1GP
cc
1
GAP-CLOSE-PWR G61 2
1
GAP-CLOSE-PWR G60 2
1
GAP-CLOSE-PWR G53 2
1
GAP-CLOSE-PWR G54 2
TPS51117PWR-GP
+1.05V_VFB
1
GAP-CLOSE-PWR G52 2
DY
1
GAP-CLOSE-PWR G56 2
C475
1
GAP-CLOSE-PWR G55 2
1
1
DY
2
2D2R5F-2-GP
TC16 SE220U2D5VDM-6GP
R296 30KR2F-GP
DY
2
SB:06/22 Change R76 from 64.12125.55L to 64.17425.55L
COIL-2D2UH-11-GP R290 12KR2F-L-GP
R302
2
U18 AO4712-GP
SB: 06/27 Change U18 from 84.06676.A37 to 84.04800.D37
4 3 2 1
3D3V_S0
40,41,44,45
1
G S S S
1
CPUCORE_ON
+1.05V_SUSP
SC330P50V3KX-GP
C
GAP-CLOSE-PWR
Vout=0.75V*(R1+R2)/R2
-c
2
+1.05V_SUSP
DY R78 1 2 100KR2J-1-GP
R76 17K4R3F-GP
2
2
7 8
GAP-CLOSE-PWR G57 2
1
GND PGND
TON TRIP
+1.05V_DRVL 1.05V_SUS_PWRGD
1
9 3 6
2
DRVL VOUT PGOOD
L22
1
C448 SCD1U10V2KX-4GP
+1.05V_LL
2
+1.05V_DRVH
12
1
EN_PSV
13
LL
S S S G
SB:06/17 Change R284 from 0402 1K Ohm to 0402 close pad.
1
2 R286
2
VBST VFB
DRVH
D D D D
+1.05V_EN 1 0R0402-PAD +1.05V_TON 2 1 200KR2J-L1-GP +1.05V_TRIP 11
1 R284
21,28,34,45,46 PM_SLP_S3#
V5FILT V5DRV
5 6 7 8
4 10 +1.05V_VBST 14 +1.05V_VFB 5
SB: 06/27 Change L22 from 68.2R210.20C to 84.04800.D37 C467 SC18P50V2JN-1-GP
U17
2
C
SB: 06/27 Change U15 from 84.08880.037 to 84.04800.D37
o-
1
2 R289
D10 CH551H-30PT-GP
Cyntec 10*10 Irating=14A, Isat=16A DCR=7mohm
4 3 2 1
1
SI4800BDY-T1
+1.05V__LL1 2 1 1 0R3-0-U-GP C463 SCD1U16V2KX-3GP
2
2
+1.05V_V5FILT C138 SC1U10V3KX-3GP
1
5 6 7 8
D D D D
GAP-CLOSE-PWR
U15
2
5V_S5
GAP-CLOSE-PWR G59 2
2
2
DY
2
1 2
C147 SCD1U50V3KX-GP
1
1
1 2
1 R293 3D3R3J-L-GP
1
C146 SC10U25V6KX-1GP
GAP-CLOSE-PWR G24 1 2
1
+1.05V_PWR_SRC
GAP-CLOSE-PWR G25 1 2
2
C159 SC1U10V3KX-3GP
1D05V_S0 G58
GAP-CLOSE-PWR G20 1 2 5V_S5
D
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Inductor: 1.5UH M MPL73-1R5 Delta 9Arms 18Apeak / 68.1R510.10I O/P cap: 220U 4V 4TPE220MF 15mOhm 3.1Arms/ 77.22271.161 H/S & L/S: FDS8884 SO-8/ 30mOhm/ 4.5Vgs/ 84.08884.037 L/S: FDS8896 SO-8/ 7.3mOhm/ 4.5Vgs/ 84.08896.037 Ton = 200KOhm --> 330KHz
B
VF
B
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
DCDC 1.05V Size A3
Document Number
Rev
5
4
3
2
-1
DS2-Intel
Date: Wednesday, September 12, 2007
Sheet 1
43
of
47
5
4
DCBATOUT
3
2
1
+1.8V_PWR_SRC G13
1
1
Iout=7A OCP<14A
2 GAP-CLOSE-PWR G12 2
+1.8V_SUSP
1 +1.8V_PWR_SRC
D
GAP-CLOSE-PWR G10 1 2
GAP-CLOSE-PWR G15 2
1
GAP-CLOSE-PWR G19 2
1
GAP-CLOSE-PWR G16 2
1
GAP-CLOSE-PWR G66 2
1
GAP-CLOSE-PWR G67 2
1
1
2 R51
R242 42K2R2F-L-GP
2D2R5F-2-GP
+1.8V_VFB
2
SB: 06/27 Change U12 from 84.04712.037 to 84.06676.A37
1
o-
SB:06/22 Change R243 from 64.12125.55L to 64.17425.55L
1
1 2
U12 FDS6676AS-GP
2
40,41,43,45
2
1
CPUCORE_ON
+1.8V_SUSP C431 SCD1U10V2KX-4GP
4 3 2 1
+1.8V_SUSP
2 TON GND 7 11 TRIP 8 SB:06/17 Change R253 PGND from 0402 1K Ohm to 0402 close pad. TPS51117PWR-GP
C400 SC33P50V2JN-3GP
DRVL VOUT PGOOD
2
+1.8V_DRVL
1
9 3 6
L18 1 2 IND-2D2UH-46-GP-U
2
+1.8V_LL
D
TC3 SE220U2D5VDM-6GP
GAP-CLOSE-PWR C
1
12
R243 9K31R3F-GP
2
1
2 5 6 7 8 LL
GAP-CLOSE-PWR G14 2
C80
R232 30KR2F-GP
SC330P50V3KX-GP
2
EN_PSV
C420 SC10U25V6KX-1GP
cc
1
DRVH
1
VBST VFB
+1.8V_DRVH
S S S G
SB:06/17 Change R253 from 0402 1K Ohm to 0402 close pad.
1
2 R251
+1.8V_EN 0R0402-PAD +1.8V_TON 1 200KR2J-L1-GP +1.8V_TRIP
2
V5FILT V5DRV
14 5
13
5 6 7 8
2
1
4 10
C418 SC2200P50V2KX-2GP
Cyntec 10*10 Irating=14A, Isat=16A DCR=7mohm
D D D D
R253
1
SB: 06/27 Change U13 from 84.04800.D37 to 84.08880.037 2 1 C405 SCD1U16V2KX-3GP
U10
+1.8V_VBST +1.8V_VFB
C
+1.8V_LL1 1 0R3-0-U-GP
4 3 2 1
1
2 R252
DY
S S S G
C53 SC1U10V3KX-3GP
D9 CH551H-30PT-GP
21,28,34,40,45 PM_SLP_S4#
1
U13 FDS8880-NL-GP
+1.8V_V5FILT
2
5V_S5
C65 SCD1U50V3KX-GP
GAP-CLOSE-PWR
1
2
2
1
R244 3D3R3J-L-GP
C59 SC10U25V6KX-1GP
2
GAP-CLOSE-PWR G17 1 2
D D D D
C52 SC1U10V3KX-3GP
GAP-CLOSE-PWR G65 2
2
1
1
1
2
5V_S5
1D8V_S3 G18
GAP-CLOSE-PWR G11 1 2
Vout=0.75V*(R1+R2)/R2
SC:08/13 Change R51(64.2R205.16L) and C80(78.33124.2BL) from No ASM to ASM
-c
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Inductor: 1.5UH M MPL73-1R5 Delta 9Arms 18Apeak / 68.1R510.10I O/P cap: 220U 4V 4TPE220MF 15mOhm 3.1Arms/ 77.22271.161 H/S & L/S: FDS8884 SO-8/ 30mOhm/ 4.5Vgs/ 84.08884.037 L/S: FDS8896 SO-8/ 7.3mOhm/ 4.5Vgs/ 84.08896.037 Ton = 200KOhm --> 330KHz B
VF
B
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
DC/DC 1D8V Size A3 Date: 5
4
3
2
Document Number
Rev
DS2-Intel Wednesday, September 12, 2007 Sheet 44 1
-1 of
47
A
B
1 C500 SC10U10V5ZY-1GP
E
C501 SC10U10V5ZY-1GP
2
2
C498 SC1U10V3ZY-6GP
1
1
1D5V_SB
D
1D8V_S3
2
5V_S0
C
DY 4
2D5V/300mA
1D5V/3A
1
SO-8-P
R317
1K13R2F-1-GP
VOUT
2
GND
1
2
VIN
1
TC19 ST100U4VBM-L1-GP
C458 SCD1U10V2KX-4GP
1
TC18
3
2
1
DY
C465 SC4D7U6D3V5KX-3GP
G9131-25T73UF-GP
-1:0909
cc
1
APL5912-KAC-GP
R320
2
GND
2
ST100U4VBM-L1-GP
1KR2F-3-GP
FB
C502
2
3 4
2D5V_S0 U51
1
VOUT VOUT
3D3V_S0
1D5V_S0
1
5 9
2
EN
Vo=0.8*(1+(R1/R2))
VIN VIN
1
8
21,28,34,43,46 PM_SLP_S3#
POK
SCD01U16V2KX-3GP
7 2 0R0402-PAD
1 R315
2
40,41,43,44 CPUCORE_ON
U53
VCNTL
SB:06/17 Change R315 from 0402 0 Ohm to 0402 close pad.
6
4
2
KEMET 100uF, 4V, B2 Size Iripple=1.1A, ESR=70mohm
3
o-
3
SSID = PWR.Plane.Regulator_0.9V
1D8V_S3
-c
1 2
SB:06/17 Change R275 from 0402 0 Ohm to 0402 close pad.
2
RT9018A-25PSP-GP
GAP-CLOSE-PWR G5 1 2
2
DY R270 C436 1K13R2F-1-GP
2
SO-8-P
Vo=0.8*(1+(R1/R2))
GAP-CLOSE-PWR
TC14
2
R274 2KR2F-3-GP
TC13
1
NC#5 VOUT ADJ GND
1
0R0402-PAD
VDD VIN EN PGOOD
2
2
SCD01U16V2KX-3GP
40,41,43,44 CPUCORE_ON
1 R275
5 6 7 8
1
21,28,34,43,46 PM_SLP_S3#
4 3 2 1
1D25V_S0
1
GAP-CLOSE-PWR G6 1 2 GAP-CLOSE-PWR G7 1 2
1D25V/2A U14
2
1
C450 SC1U10V3ZY-6GP
2
1 C449 SC10U10V5ZY-1GP
DY
1
C413 SC10U4V3MX-GP
1 2
C412 SC10U4V3MX-GP
1 2
11
1 2
U11 TPS51100DGQ-1-GP 74.51110.B79
C145 SC10U10V5ZY-1GP
ST100U4VBM-L1-GP
C414 SCD1U10V2KX-4GP
SA:04/23 Change TC24,TC33 P/N for power team request.
9
2
5V_S0
GND
1 2 3 4 5
DDR_VREF_S0
G8
1
+0.9V_P
1D8V_S3
0.9 Volt +/- 5% Design Current: 1.05A Peak current 1.5A
2
1
VIN VDDQSNS S5 VLDOIN GND VTT S3 PGND VTTREF VTTSNS
2
GAP-CLOSE-PWR
ST100U4VBM-L1-GP
DDR_VREF_S3
10 9 8 7 6
1
VF
21,28,34,43,46 PM_SLP_S3#
DDR_ON_0.9V 0R0402-PAD 0.9V_DDR_VTT_ON_R 2 0R0402-PAD
2
GND
21,28,34,40,44 PM_SLP_S4#
2
5V_S5
2
1 R257 1 R256
TPS51100_LDOIN C54 SCD1U10V2KX-4GP
1 2
SB:06/17 Change R256,R257 from 0402 0 Ohm to 0402 close pad.
C55 SC10U4V3MX-GP
G9
KEMET 100uF, 4V, B2 Size Iripple=1.1A, ESR=70mohm
1
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
DC/DC 1D8V Size A3
Document Number
Rev
Date: Wednesday, September 12, 2007 A
B
C
D
-1
DS2-Intel Sheet E
45
of
47
cc
H_THERMTRIP# 5,8,20,34
E
DY
R328 1 2 1KR2J-1-GP
H_PWRGD_R
B
Q31 CHT2222APT-GP
DY
2
DY C511 SCD1U10V2KX-4GP
C
1
6,20 H_PWRGOOD
2 D27 BAS16-1-GP
3
PURE_HW_SHUTDOWN#
34,36
1
R325 200KR2J-L1-GP
1 R324
-c
2
1
o-
40 3V/5V_EN
Run Power
DY
C207 1
SCD1U25V3KX-GP
VF Q11
Z_12V_D4
8 7 6 5
D D D D
8 7 6 5
AO4468-GP 84.04468.037
K
R108
D17 BZX384-C9V1-GP 83.9R103.B3F
3D3V_S0
3D3V_S5
1 2 3 4
A
1 2
2
C206 R109 10KR2J-3-GP
1
1
G
R114 100KR2J-1-GP
Z_12V_D3 2
U30 S S S G AO4468-GP 84.04468.037
D
DY
3
-1:0909
1 Z_12V_G3 330KR2J-L1-GP
DY
SCD1U25V3KX-GP
2 R115
D D D D
D
100KR2J-1-GP
Z_12V 2 S 10KR2J-3-GP NDS0610-NL-GP 84.S0610.B31
1
1 R113
RUN_POWER_ON
2
DCBATOUT
1 2 3 4
2
S5_ENABLE 34
5V_S5
5V_S0
U23 S S S G
2 1KR2J-1-GP
1D8V_S3
1D8V_S0
Q9 2N7002PT-U
Q29
1 G
Q10 2N7002PT-U
1
G S
6
2
5
3
4
R307
2
Wistron Corporation
10KR2J-3-GP
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
FDC655BN-GP
1
1 2
21,28,34,43,45 PM_SLP_S3#
1
S
2
3
2
D
C483 SCD01U25V2KX-3GP
DY
SA:0329 Add for SiI1392 1.8V_S0
Title
PWRPLANE&RESETLOGIC Size A3
Document Number
Rev
DS2-Intel
Date: Wednesday, September 12, 2007
Sheet
-1 46
of
47
A
B
3D3V_AUX_S5
C
3D3V_S5
D
AD+
5V_S5
E
-1:0904 Add EC187(78.10422.2BL) for DCBATOUT decoupling , this is for 1D05V_S0 EMI request.
DCBATOUT
-1:0909 1
1
1
1
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP 2
1
1
1
1
1
1
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP
1
SCD1U16V2ZY-2GP 2
1 2
1
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP
1
1
7
1
1
1
1
1
1
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP
1
SCD1U16V2ZY-2GP 2
DY DY EC95 EC63 EC4
SPRING-35-GP
1
1
1
1
1
1
1
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP
1
SC:08/15 Add EC177(78.10491.4FL) on 3D3V_S0 ,this is for EMI request. Default is DY
3D3V_S0
DY EC113
DY DY DY DY DY DY DY DY EC35 EC43 EC61 EC40 EC103 EC101 EC92 EC116 EC109 EC104 SCD1U16V2ZY-2GP 2
DY EC137
DY EC42
DY EC177
SCD1U16V2ZY-2GP
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
MISC Size A3
Document Number
Rev
DS2-Intel
Date: Wednesday, September 12, 2007 C
DY EC100
1
DY EC117
SCD1U16V2ZY-2GP 2
1
SCD1U16V2ZY-2GP 2
1
SCD1U16V2ZY-2GP 2
1
1
DY EC33
1
DY EC136
5V_AUX_S5
1
DY EC45
SCD1U16V2ZY-2GP 2
DY EC135
SC:08/11 Change K7 from 34.39S07.001 to 34.41P18.001.This change is for EMI request
B
SCD1U16V2ZY-2GP
1
1 2
SCD1U25V3KX-GP
2
SCD1U16V2ZY-2GP 2
1
1 SCD1U50V3ZY-GP
2
SCD1U50V3ZY-GP
1 2 14
Place this spring near U40(bottom side)
K7
DY EC38
2
DY EC41
1
A
3
3D3V_S0
DY EC134
SPRING-24-GP
K6
1
SPRING-51-GP
K5
1
SPRING-24-GP
1
K2
DY DY EC19 EC25
3D3V_S0
SB:06/29 Add EC134,EC135,EC136,EC137(78.10491.4FL) for EMI request
SC:08/09 Change K5 spring from 34.45T31.001to 34.4B312.002 for ME request
DY EC37
1
DY
DY DY DY DY EC24 EC21 EC23 EC22
SCD1U16V2ZY-2GP 2
VF
1
1
1
1
1
1
1
2
1
DY
H23
SCD1U16V2ZY-2GP 2
1
1
DY
SCD1U16V2ZY-2GP 2
H22
SCD1U16V2ZY-2GP
DY
DY EC28
1
H21
1
1
DY
DY EC12
2
H20
DY EC96
DY EC143
1
DY
DY EC142
2
H19
1
DY
H18
1
1
DY
-c
H17
1
1
DY
SCD1U50V3ZY-GP
2 DY EC141
2
H16
SCD1U16V2ZY-2GP
DY
H15
1
DY
SCD1U16V2ZY-2GP 2
H14
1
DY
2
H13
DY DY EC20 EC18
SB:06/22 Change EC1,EC5 from DUMMY to ASM by EMI request.
SCD1U16V2ZY-2GP
DY
1
H12
SCD1U16V2ZY-2GP 2
DY
DY EC15
5V_S0
1
H11
2
DY
H10
1
DY
5V_S0
TSAHCT125PW-GP
2
H9
2
o-
DY
U9D
1D8V_S3
SB:06/29 Add EC141,EC142,EC143(78.10491.4FL) for EMI request
11
7
1
1
1
1
1
1
1
1
12
DY DY EC13 EC14 SCD1U16V2ZY-2GP 2
H8
1
H7
SCD1U16V2ZY-2GP
H6
1
H5
SCD1U16V2ZY-2GP 2
H4
TSLVC08APW-1-GP
DY
SCD1U16V2ZY-2GP 2
H3
TSLVC08APW-1-GP
DY
13
H2
DDR_VREF_S0
6
2
DY
14
H1
4
5
cc
TSLVC08APW-1-GP
DY
5V_S0 3
SCD1U50V3ZY-GP
SCD1U50V3ZY-GP 2
SC47P50V2JN-3GP
2
SCD1U16V2ZY-2GP
SSLVC08APWR-GP
DY
EC187
U20B
8 10
7
SSLVC08APWR-GP
EC1
4
11 13
7
7
SSLVC08APWR-GP
DY
9
3 2
EC26
3D3V_S5
2
8 10
U20C
12
7
11
3D3V_S5
U20D
14
U33A
1
EC39
DY
for RF
3D3V_S5
14
U33C
9
13
SCD1U16V2ZY-2GP 2
3D3V_S5
14
14
U33D
12
7
SC:08/11 Add EC164 on 5V_S5 team Request.
3D3V_S5
EC57
14
SC:08/11 Add EC162 on 3D3V_S5 for RF team Request. 3D3V_S5
SCD1U16V2ZY-2GP 2
2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP 2
2
2
SC47P50V2JN-3GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP 2
SCD1U16V2ZY-2GP 2
2
SCD1U16V2ZY-2GP 2
EC58
4
DY
1
DY
1
DY
EC164
1
1
DY EC140
1
DY EC139
1
1
DY EC138
1
1
DY DY DY DY EC108 EC107 EC112 EC105
1
EC162
1
1
1
1
1
1
DY DY DY EC56 EC10 EC94 EC118
SCD1U16V2ZY-2GP 2
DY DY DY DY DY DY EC64 EC93 EC74 EC102 EC106 EC99
-1:0909
D
Sheet E
-1 47
of
47
