Transcript
49% 1FPO 721
®
PCM1721
PCM
Stereo Audio DIGITAL-TO-ANALOG CONVERTER WITH PROGRAMMABLE PLL TM
FEATURES
DESCRIPTION
● ACCEPTS 16-, 20-, OR 24-BIT INPUT DATA
The PCM1721 is a complete low cost stereo audio digital-to-analog converter (DAC) with a phase-locked loop (PLL) circuit included. The PLL derives either 256fS or 384fS system clock from an external 27MHz reference frequency. The DAC contains a 3rd-order ∆Σ modulator, a digital interpolation filter, and an analog output amplifier. The PCM1721 can accept 16-, 20-, or 24-bit input data in either normal or I2S formats.
● COMPLETE STEREO DAC: Includes Digital Filter and Output Amp ● DYNAMIC RANGE: 94dB ● MULTIPLE SAMPLING FREQUENCIES: 16kHz, 22.05kHz, 24kHz 32kHz, 44.1kHz, 48kHz 64kHz, 88.2kHz, 96kHz
The digital filter performs an 8X interpolation function and includes selectable features such as soft mute, digital attenuation and digital de-emphasis. The PLL can be programmed for sampling at standard digital audio frequencies as well as one-half and double sampling frequencies.
● PROGRAMMABLE PLL CIRCUIT: 256fS/384fS from 27MHz Master Clock ● NORMAL OR I2S DATA INPUT FORMATS ● SELECTABLE FUNCTIONS: Soft Mute Digital Attenuator (256 Steps) Digital De-emphasis
The PCM1721 is ideal for applications which combine compressed audio and video data such as DVD, DVDROM, set-top boxes and MPEG sound cards.
● OUTPUT MODE: Left, Right, Mono, Mute
Multi-level Delta-Sigma Modulator
BCKIN LRCIN DIN
Serial Input I/F
8X Oversampling Digital Filter with Function Controller
Low-pass Filter
DAC
VOUTL
CAP Multi-level Delta-Sigma Modulator
ML
Low-pass Filter
DAC
VOUTR
MC MD
Mode Control I/F
ZERO BPZ-Cont. 256fS/384fS
Open Drain
RSTB Clock/OSC Manager and PLL
SCKI
MCKI
SCKO
Power Supply
VCP PGND VCC AGND VDD DGND
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ®
© 1996 Burr-Brown Corporation
PDS-1319A 1
PCM1721
Printed in U.S.A. August, 1996
SPECIFICATIONS All specifications at +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, and 16-bit input data, SYSCLK = 384fS, unless otherwise noted. PCM1721 PARAMETER
CONDITIONS
MIN
RESOLUTION DATA FORMAT Audio Data Format Data Bit Length Sampling Frequency (fS)
PLL PERFORMANCE Master Clock Input Frequency Generated Sysclk Frequency Generated Sysclk Jitter Generated Sysclk Transient(1) Generated Sysclk Duty Cycle
Standard fS One-half fS Double fS
32 16 64
THD+N at –60dB Dynamic Range (EIAJ Method) Signal-to-Noise Ratio(3) Channel Separation DC ACCURACY Gain Error Gain Mismatch, Channel-to-Channel Bipolar Zero Error ANALOG OUTPUT Output Voltage Center Voltage Load Impedance
fM = 27MHz fM = 27MHz fM = 27MHz, CL = 15pF
POWER SUPPLY REQUIREMENTS Voltage Range Supply Current: ICC + IDD + ICP ICC + IDD + ICP
UNITS
24
Bits
48 24 96
kHz kHz kHz
40
MHz ±250 20 60
ps ms %
–89 –87 –31 –29 94 91 94 92 92
–80
dB dB dB dB dB dB dB dB dB
±1.0 ±1.0 ±30
±5.0 ±5.0
% of FSR % of FSR mV
50 TTL
fs = 44.1kHz fs = 96kHz fs = 44.1kHz fs = 96kHz fs = 44.1kHz fs = 96kHz fs = 44.1kHz fs = 96kHz fs = 44.1kHz
90 90 88
VOUT = VCC/2 at BPZ Full Scale (–0dB) AC Load
Vp-p VDC kΩ
0.62 x VCC VCC/2 5
DIGITAL FILTER PERFORMANCE Passband Stopband Passband Ripple Stopband Attenuation Delay Time De-emphasis Error INTERNAL ANALOG FILTER –3dB Bandwidth Passband Response
Standard/I2S 16/20/24 Selectable 44.1 22.05 88.2
MAX
27 256fS/384fS
DIGITAL INPUT/OUTPUT LOGIC LEVEL DYNAMIC PERFORMANCE(2) THD+N at fS (0dB)
TYP
16
0.445 0.555 ±0.17 –35 11.125/fS –0.2
+0.55 100 –0.16
f = 20kHz VCC = VDD = VCP fS = 44.1kHz fS = 96kHz
TEMPERATURE RANGE Operation Storage
4.5
0 –55
5 36 49
fS fS dB dB sec dB kHz dB
5.5 43 58
VDC mA mA
+70 +100
°C °C
NOTES: (1) Sysclk transient is the maximum frequency lock time when the PLL frequency is changed. (2) Dynamic performance specs are tested with 20kHz low pass filter and THD+N specs are tested with 30kHz LPF, 400Hz HPF, Average-Mode. (3) SNR is tested at Infinite Zero Detection off.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ®
PCM1721
2
PIN CONFIGURATION
PIN ASSIGNMENTS
TOP VIEW
SSOP
MCKI
1
24 NC
SCKO
2
23 PGND
PIN
NAME
TYPE
1
MCKI
IN
FUNCTION
2
SCKO
OUT
System Clock Out. This output is 256fS or 384fS system clock generated by the internal PLL.
3
VCP
PWR
PLL Power Supply (+5V)
4
SCKI
IN
Master Clock Input.
System Clock (256fS or 384fS) Input.
VCP
3
22 DGND
5
RES
N/A
SCKI
4
21 VDD
6*
ML
IN
Latch for serial control data
7*
MC
IN
Clock for serial control data
Reserved for factory use, do not connect.
RES
5
20
RES
8*
MD
IN
Data for serial control
ML
6
19
TEST
9*
RSTB
IN
Reset Input. When this pin is low, the digital filters and modulators are held in reset.
MC
7
18
LRCIN
10
ZERO
OUT
MD
8
17
DIN
Zero Data Flag. This pin is low when the input data is continuously zero for more than 65, 535 cycles of BCKIN.
RSTB
9
16
BCKIN
ZERO 10
15
CAP
VOUTR 11
14
VOUTL
AGND 12
13
VCC
PACKAGE INFORMATION
11
VOUTR
OUT
Right Channel Analog Output
12
AGND
GND
Analog Ground
13
VCC
PWR
Analog Power Supply (+5V)
14
VOUTL
OUT
15
CAP
16*
BCKIN
IN
Bit clock for clocking in the audio data.
17*
DIN
IN
Serial audio data input
18*
LRCIN
IN
19
TEST
N/A
20
RES
N/A
21
VDD
PWR
Analog Power Supply (+5V) Digital Ground
Left Channel Analog Output Common pin for analog output amplifiers.
DGND
GND
PACKAGE
PACKAGE DRAWING NUMBER(1)
22
PRODUCT
23
PGND
GND
PCM1721
24-Pin SSOP
338
24
NC
—
Left/Right Word Clock. Frequency is equal to fS. Test pin, must be tied “LOW”. Reserved for factory use, do not connect.
PLL Ground No Connection
* These pins include internal pull-up resistors.
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
ABSOLUTE MAXIMUM RATINGS Power Supply Voltage ....................................................................... +6.5V +VCC to +VDD Difference ................................................................... ±0.1V Input Logic Voltage .................................................. –0.3V to (VDD + 0.3V) Power Dissipation .......................................................................... 530mW Operating Temperature Range ............................................. 0°C to +70°C Storage Temperature ...................................................... –55°C to +125°C Lead Temperature (soldering, 5s) .................................................. +260°C Thermal Resistance, θJA ....................................................................................... +70°C/W
®
3
PCM1721
TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = VDD = VCP =+5V, fS = 44.1kHz, 16-bit input data, 384fS, unless otherwise noted. Measurement bandwidth is 20kHz.
DYNAMIC PERFORMANCE DYNAMIC RANGE vs TEMPERATURE and VCC fS = 44.1kHz
–84
86
–86
88
–88 VCC = 4.5V
Dynamic Range (dB)
THD+N (dB)
THD+N vs TEMPERATURE and VCC fS = 44.1kHz
VCC = 5.0V
–90
VCC = 5.5V VCC = 4.5V 5.0V
92 VCC = 5.0V 5.5V 94
VCC = 5.5V –92
96 –25
0
25
50
70
85
100
–25
0
25
50
70
85
Temperature (°C)
Temperature (°C)
THD+N vs TEMPERATURE and VCC fS = 96kHz
DYNAMIC RANGE vs TEMPERATURE and VCC fS = 96kHz
–82
100
82 VCC = 4.5V
THD+N (dB)
Dynamic Range (dB)
VCC = 5.0V
–84
–86
–88
VCC = 5.5V
84
VCC = 4.5V
VCC = 5.0V
86
88 VCC = 5.5V
–90
90 –25
0
25
50
70
85
100
–25
0
25
50
Temperature (°C)
SNR vs TEMPERATURE and VCC fS = 96kHz
SNR vs TEMPERATURE and VCC fS = 44.1kHz
98
98
96
96
VCC = 4.5V VCC = 5.5V VCC = 5.0V
SNR (dB)
SNR (dB)
70
Temperature (°C)
94
92
94
85
100
85
100
VCC = 5.0V
VCC = 5.5V
92 VCC = 4.5V
90
90 –25
0
25
50
70
85
100
–25
Temperature (°C)
25
50
Temperature (°C)
®
PCM1721
0
4
70
TYPICAL PERFORMANCE CURVES
(CONT)
At TA = +25°C, VCC = VDD = VCP =+5V, fS = 44.1kHz, 16-bit input data, 384fS, unless otherwise noted. Measurement bandwidth is 20kHz.
DYNAMIC PERFORMANCE THD+N vs fS
DYNAMIC RANGE vs fS
–76
86
–78 Dynamic Range (dB)
THD+N (dB)
–80 –82 –84 256fS
–86 –88
384fS
–90
256fS
88
92 384fS 94
–92 –94
96 30
40
50
60
70
80
90
100
30
40
50
fS (kHz)
70
80
90
100
80
90
100
fS (kHz)
SNR vs fS
ICC vs fS
98
60
256fS
50 ICC (mA)
96 SNR (dB)
60
94
40
384fS 92
30
90
20 30
40
50
60
70
80
90
100
30
fS (kHz)
40
50
60
70
fS (kHz)
®
5
PCM1721
TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = +5V, RL = 44.1kHz, and fSYS = 384fS, unless otherwise noted.
DIGITAL FILTER OVERALL FREQUENCY CHARACTERISTIC
PASSBAND RIPPLE CHARACTERISTIC 0
–20
–0.2
–40
–0.4
dB
dB
0
–60
–0.6
–80
–0.8
–100
–1
0 0.4536fS
1.3605fS
2.2675fS
3.1745fS
4.0815fS
0
0.1134fS
Frequency (Hz)
5k
10k
15k
20k
25k
0
3628
15k
20k
25k
0
4999.8375
15k
20k
25k
19999.35
0.6 0.4 0.2 0 –0.2 –0.4 –0.6 0
Frequency (Hz)
5442
10884 Frequency (Hz)
®
PCM1721
14999.5125
DE-EMPHASIS ERROR (48kHz) Error (dB)
Level (dB)
DE-EMPHASIS FREQUENCY RESPONSE (48kHz)
10k
9999.675 Frequency (Hz)
0 –2 –4 –6 –8 –10 –12 5k
14512
0.6 0.4 0.2 0 –0.2 –0.4 –0.6
Frequency (Hz)
0
10884
DE-EMPHASIS ERROR (44.1kHz) Error (dB)
Level (dB)
DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz)
10k
7256 Frequency (Hz)
0 –2 –4 –6 –8 –10 –12 5k
0.4535fS
0.6 0.4 0.2 0 –0.2 –0.4 –0.6
Frequency (Hz)
0
0.3402fS
DE-EMPHASIS ERROR (3kHz) Error (dB)
Level (dB)
DE-EMPHASIS FREQUENCY RESPONSE (3kHz) 0 –2 –4 –6 –8 –10 –12 0
0.2268fS Frequency (Hz)
6
16326
21768
TYPICAL CONNECTION DIAGRAM Figure 1 illustrates the typical connection diagram for PCM1721 in a MPEG2 application. The 27MHz master video clock (fM) drives MCKI (pin 1) of PCM1721. A programmable system clock is generated by the PCM1721 PLL, with SCKO used to drive the MPEG2 decoder’s system clock input. The standard audio signals (data, bit clock, and word clock) are generated in the decoder from PCM1721’s system clock, providing synchonization of audio and video signals.
PLL CIRCUIT PCM1721 has a programmable internal PLL circuit, as shown in Figure 2. The PLL is designed to accept a 27MHz master clock and generate all internal system clocks required to operate the digital filter and ∆Σ modulator, either at 256fS or 384fS. The PLL will directly track any variations in the master clock’s frequency, and jitter on the system clock is specified at 250ps maximum. Figure 3 illustrates the timing requirements for the 27MHz master clock.
+5V Analog 23
22
PGND DGND 17
SERO Audio Decoder
16
SCKO
18
LRCKO SYSCKI
2 256fS/384fS CLK 4
21 VDD
3 VCP
VOUTL
DIN BCKIN
CAP
SCKO VOUTR
SCKI
ZERO Master PLL
1 27MHz CLK OUT 19
15
200Ω +
LRCIN
PCM1721
SCR(1) or PCR
14
MCKIN
Lch Analog Out
Post LPF
Analog Mute
Rch Analog Out
10
MC MD RSTB
AGND
Analog Mute
10µF
11
ML
TEST
Post LPF
6
STRB
7
SCKO
8
SDO
9
System Controller
PIO
VCC
12
13 +5V Analog
NOTE: (1) SCR: System Clock Reference PCR: Program Clock Reference
FIGURE 1. External Master Clock Input.
Sampling Frequency Selection 256fS/384fS Selection
DAC Section System Clock Input
N Counter
Frequency Selection ROM
Phase Detector and Loop Filter
VCO
M Counter
4
1
2
System Clock Input for DAC Section
27MHz Master Clock Input
PLL Generated System Clock Out
FIGURE 2. PPL Block Diagram. 1/27MHz or 1/256fS or 1/384fS tCH 2.0V 0.8V
tCH : 13ns (min) tCL : 13ns (min)
tCL
FIGURE 3. MCKI, SCKI Input Timing. ®
7
PCM1721
1/fS L_ch R_ch
LRCIN (pin 4) BCKIN (pin 6) AUDIO DATA WORD = 16-BIT DIN (pin 5)
14 15 16
1
2
MSB
AUDIO DATA WORD = 20-BIT DIN (pin 5)
18 19 20
1
2
23 24
1
18
3
2
15 16
1
2
19 20
1
2
LSB 22
3 MSB
14
3 MSB
LSB
MSB
AUDIO DATA WORD = 24-BIT DIN (pin 5)
14
3
LSB 18
3 MSB
23 24
1
LSB
2
15 16
19 20
LSB 22
3 MSB
23 24
LSB
FIGURE 4. “Normal” Data Input Timing. 1/fS L_ch
LRCIN (pin 4)
R_ch
BCKIN (pin 6) AUDIO DATA WORD = 16-BIT DIN (pin 5)
1
2
MSB
AUDIO DATA WORD = 20-BIT DIN (pin 5)
1
2
15 16
1
2
19 20
1
2
LSB 22
3 MSB
3 MSB
18
3
2
1
LSB
MSB
AUDIO DATA WORD = 24-BIT DIN (pin 5)
14
3
14
1
2
LSB
2
19 20
1
2
23 24
1
2
LSB 18
3 MSB
23 24
1
15 16
LSB 22
3 MSB
LSB
FIGURE 5. “I2S” Data Input Timing. tMLS
tMLH
ML
1.4V tMCH
tMLL
tMCL
MC
1.4V tMCY
MD
1.4V tMDS
tMDH
MC Pulse Cycle Time
: tMCY
: 100ns (min)
MC Pulse Width LOW
: tMCL
: 50ns (min)
MC Pulse Width HIGH
: tMCH
: 50ns (min)
MD Set-up Time
: tMDS
: 30ns (min)
MC Hold Time
: tMDH
: 30ns (min)
ML Low Level Time
: tMLL
: 30ns + 1SYSCLK (min)
ML Set-up Time
: tMLS
: 30ns (min)
ML Hold Time
: tMLH
: 30ns (min)
FIGURE 6. Serial Interface Timing. ®
PCM1721
8
PCM1721’s internal PLL can be programmed for nine different sampling frequencies (LRCIN), as shown in Table I. The internal sampling clocks generated by the various programmed frequencies are shown in Table II. Because of finite limitations in the PLL’s M and N counters, errors associated with specific frequencies are shown.
Sampling Frequencies-LRCIN (kHz) Half of Standard Sampling Freq Standard Sampling Freq Double of Standard Sampling Freq
16 32 64
22.05 44.1 88.2
24 48 96
TABLE I. Sampling Frequencies. HALF OF STANDARD SAMPLING FREQUENCY 256fS (kHz) INTERNAL SYSTEM CLOCK (MHz)
16
4.096
4.0982
5.6448
22.05
STANDARD SAMPLING FREQUENCY
384fS (kHz)
24
16
22.05
256fS (kHz)
24
32
44.1
DOUBLE OF STANDARD SAMPLING FREQUENCY
384fS (kHz)
48
32
44.1
256fS (kHz)
48
64
88.2
FREQ ERROR
384fS (kHz)
96
64
88.2
%
96 0.0537
5.64543
6.144
0.0112 6.13634
6.144
–0.1247 6.13634
8.4672
–0.1247 8.46604
9.216 8.192
–0.0137
9.21426
–0.0189 8.18849
11.2896
–0.0428
11.29087
12.288
0.0112
12.2946
12.288
0.0537 12.2946
16.934
0.0537
16.93215
18.432
–0.0133
18.42851
16.384
–0.0189 16.37699
22.5792
–0.0428
22.58174
24.576
0.0112
24.5892
24.576
0.0537 24.5892
33.8688
0.0537
33.8643
36.864
36.85702
–0.0133 –0.0189
TABLE II. Sampling Frequencies vs Internal System Clock. FUNCTION Input Audio Data Format Selection Normal Format I2S Format Input Audio Data Bit Selection 16/20/24 Bits Input LRCIN Polarity Selection Lch/Rch = High/Low Lch/Rch = Low/High
16 Bits Lch/Rch = High/Low OFF
Soft Mute Control
OFF
Infinite Zero Detection Circuit Control Operation Enable (OPE) Sample Rate Selection Internal System Clock Selection 256fS 384fS Double Sampling Rate Selection Standard Sampling Rate—44.1/48/32kHz Double Sampling Rate—88.2/96/32kHz Half Sampling Rate—22.05/24/16kHz Sampling Frequency 44.1kHz Group 48kHz Group 32kHz Group Analog Output Mode L, R, Mono, Mute
PCM1721 includes several special functions, including digital attenuation, digital de-emphasis, soft mute, data format selection and input word resolution. These functions are controlled using a three-wire interface. MD (pin 8) is used for the program data, MC (pin 7) is used to clock in the program data, and ML (pin 6) is used to latch in the program data. Table III lists the selectable special functions.
Normal Format
De-emphasis Control
Attenuation Control Lch, Rch Individually Lch, Rch Common
SPECIAL FUNCTIONS
DEFAULT MODE
0dB Lch, Rch Individually Fixed OFF Enabled
384fS
Standard Sampling Rate
44.1kHz
Stereo
TABLE III. Selectable Functions.
®
9
PCM1721
MAPPING OF PROGRAM REGISTERS B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
MODE0
res
res
res
res
res
A1
A0
LDL
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
MODE1
res
res
res
res
res
A1
A0
LDR
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
MODE2
res
res
res
res
res
A1
A0
PL3
PL2
PL1
PL0
IW1
IW0
OPE
DEM
MUT
MODE3
res
res
res
res
res
A1
A0
IZD
SF1
SF0
DSR1
DSR0
SYS
ATC
LRP
I2S
PROGRAM REGISTER BIT MAPPING
ATTENUATION DATA LOAD CONTROL, LCH
PCM1721’s special functions are controlled using four program registers which are 16 bits long. These registers are all loaded using MD. After the 16 data bits are clocked in, ML is used to latch in the data to the appropriate register. Table IV shows the complete mapping of the four registers and Figure 7 illustrates the serial interface timing.
Bit 8 (LDL) is used to simultaneously set analog outputs of Lch and Rch. An output level is controlled by AL[0:7] attenuation data when this bit is set to 1. When set to 0, an output level is not controlled and remains at the previous attenuation level. A LDR bit in Register 1 has an equivalent function as the LDL. When one of LDL or LDR is set to 1, the output level of the left and right channel is simultaneously controlled. The attenuation level is given by:
REGISTER NAME
BIT NAME
Register 0
AL (7:0) LDL A (1:0) Res
DAC Attenuation Data for Lch Attenuation Data Load Control for Lch Register Address Reserved
Register 1
AR (7:0) LDL A (1:0) Res
DAC Attentuation Data for Rch Attenuation Data Load Control for Rch Register Address Reserved
X is the user-determined step number, an integer value between 0 and 255.
Register 2
MUT DEM OPE IW (1:0) PL (3:0) A (1:0) res
Left and Right DACs Soft Mute Control De-emphasis Control Left and Right DACs Operation Control Input Audio Data Bit Select Output Mode Select Register Address Reserved
let x = 255
Register 3
I2S LRP ATC SYS DSR (1:0) SF (1:0) IZD A (1:0) Res
DESCRIPTION
ATT = 20 log (y/256) (dB), where y = x, when 0 ≤ x ≤ 254 y = x + 1, when x = 255
Example:
255 + 1 ATT = 20 log = 0dB 256 let x = 254
254 ATT = 20 log = –0. 068dB 256
Audio Data Format Select Polarity of LRCIN (pin 7) Select Attenuator Control System Clock Select Double Sampling Rate Select Sampling Rate Select Infinite Zero Detection Circuit Control Register Address Reserved
let x = 1
1 = –48.16dB ATT = 20 log 256 let x = 0
0 = –∞ ATT = 20 log 256
TABLE IV. Internal Register Mapping. REGISTER 0 (A1 = 0, A0 = 0)
REGISTER 1 (A1 = 0, A0 = 1) B15 B14 B13 B12 B11 B10 B9 B8
B7 B6 B5 B4 B3 B2 B1 B0 B15 B14 B13 B12 B11 B10 B9 B8
res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
res res res res res
Register 0 is used to control left channel attenuation. Bits 0 - 7 (AL0 - AL7) are used to determine the attenuation level. The level of attenuation is given by:
Register 1 is used to control right channel attenuation. As in Register 1, bits 0 - 7 (AR0 - AR7) control the level of attenuation.
ATT = [20 log10 (ATT_DATA/255)] dB
®
PCM1721
B7 B6 B5 B4 B3 B2 B1 B0
A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
10
REGISTER 2 (A1 = 1, A0 = 0) B15 B14 B13 B12 B11 B10 B9 B8 res res res res res A1
B7
B6 B5
B4
B3
B2
B1
Bits 5, 6, 7, and 8 (PL0:3) are used to control output format. The output of PCM1721 can be programmed for 16 different states, as shown in Table VIII.
B0
A0 PL3 PL2 PL1 PL0 IW1 IW0 OPE DEM MUTE
Register 2 is used to control soft mute, de-emphasis, operation enable, input resolution, and output format. Bit 0 is used for soft mute: a “HIGH” level on bit 0 will cause the output to be muted (this is ramped down in the digital domain, so no “click” is audible). Bit 1 is used to control de-emphasis. A “LOW” level on bit 1 disables de-emphasis, while a “HIGH” level enables de-emphasis. Bit 2, (OPE) is used for operational control. Table V illustrates the features controlled by OPE. DATA INPUT
DAC OUTPUT
SOFTWARE MODE INPUT
Zero
Forced to BPZ(1)
Enabled
Other
Forced to BPZ(1)
Enabled
Zero
Controlled by IZD
Enabled
Other
Normal
Enabled
OPE = 1 OPE = 0
PL0
PL1
PL2
PL3
Lch OUTPUT
Rch OUTPUT
NOTE
0
0
0
0
MUTE
MUTE
MUTE
0
0
0
1
MUTE
R
0
0
1
0
MUTE
L
0
0
1
1
MUTE
(L + R)/2
0
1
0
0
R
MUTE
0
1
0
1
R
R
0
1
1
0
R
L
0
1
1
1
R
(L + R)/2
1
0
0
0
L
MUTE
1
0
0
1
L
R
1
0
1
0
L
L
1
0
1
1
L
(L + R)/2
1
1
0
0
(L + R)/2
MUTE
1
1
0
1
(L + R)/2
R
1
1
1
0
(L + R)/2
L
1
1
1
1
(L + R)/2
(L + R)/2
TABLE V. Operation Enable (OPE) Function.
TABLE VIII. Programmable Output Format.
OPE controls the operation of the DAC: when OPE is “LOW”, the DAC will convert all non-zero input data. If the input data is continuously zero for 65, 536 cycles of BCKIN, the output will be forced to zero only if IZD is “HIGH”. When OPE is “HIGH”, the output of the DAC will be forced to bipolar zero, irrespective of any input data.
REGISTER 3 (A1 = 1, A0 = 1)
DATA INPUT
DAC OUTPUT
Zero
Forced to BPZ(1)
Other
Normal
Zero
Zero(2)
Other
Normal
IZD = 1 IZD = 0
DATA INPUT
DAC OUTPUT
Zero
Controlled by OPE and IZD
Enabled
Other
Controlled by OPE and IZD
Enabled
Zero
Forced to BPZ(1)
Disabled
Other
Forced to BPZ(1)
Disabled
RSTB = “HIGH” RSTB = “LOW”
Bit 2 (ATC) is used for controlling the attenuator. When bit 2 is “HIGH”, the attenuation data loaded in program Register 0 is used for both left and right channels. When bit 2 is “LOW”, the attenuation data for each register is applied separately to left and right channels.
NOTE: (1) ∆∑ is disconnected from output amplifier. (2) ∆∑ is connected to output amplifier.
Bit 3 (SYS) is the system clock selection. When bit 3 is “LOW”, the system clock frequency is set to 384fS. When bit 3 is “HIGH”, the system clock frequency is set to 256fS.
Bits 3 (IW0) and 4 (IW1) are used to determine input word resolution. PCM1721 can be set up for input word resolutions of 16, 20, or 24 bits: Bit 3 (IW0)
Input Resolution
0 0 1 0
0 1 0 0
16-bit Data Word 20-bit Data Word 24-bit Data Word Reserved
B3 B2 B1 B0
Bits 0 (I2S) and 1 (LRP) are used to control the input data format. A “LOW” on bit 0 sets the format to “Normal” (MSB-first, right-justified Japanese format) and a “HIGH” sets the format to I2S (Philips serial data protocol). Bit 1 (LRP) is used to select the polarity of LRCIN (sample rate clock). When bit 1 is “LOW”, left channel data is assumed when LRCIN is in a “HIGH” phase and right channel data is assumed when LRCIN is in a “LOW” phase. When bit 1 is “HIGH”, the polarity assumption is reversed.
TABLE VII. Reset (RSTB) Function.
Bit 4 (IW1)
B8 B7 B6
IZD SF1 SF0 DSR1 DSR0 SYS ATC LRP I2S
Register 3 is used to control input data format and polarity, attenuation channel control, system clock frequency, sampling frequency and infinite zero detection.
TABLE VI. Infinite Zero Detection (IZD) Function. SOFTWARE MODE INPUT
MONO
res
A0
B4
STEREO
B15 B14 B13 B12 B11 B10 B9 res res res res A1
B5
REVERSE
Bits 4 (DSR0) and 5 (DSR1) are used to control multiples of the sampling rate: DSR1
DSR0
0 0 1 1
0 1 0 1
Multiple Normal Double One-half Reserved
32/44.1/48kHz 64/88.2/96kHz 16/22.05/24kHz Not Defined
®
11
PCM1721
Bits 6 (SF0) and 7 (SF1) are used to select the sampling frequency: SF1
SF0
0 0 1 1
0 1 0 1
When IZD is “LOW”, the zero detect circuit is off. Under this condition, no automatic muting will occur if the input is continuously zero. When IZD is “HIGH”, the zero detect feature is enabled. If the input data is continuously zero for 65, 536 cycles of BCKIN, the output will be immediately forced to a bipolar zero state (VCC/2). The zero detection feature is used to avoid noise which may occur when the input is DC. When the output is forced to bipolar zero, there may be an audible click. PCM1721 allows the zero detect feature to be disabled so the user can implement an external muting circuit.
Sampling Frequency 44.1kHz group 48kHz group 32kHz group Reserved
22.05/44.1/88.2kHz 24/48/96kHz 16/32/64kHz Not Defined
Bit 8 is used to control the infinite zero detection function (IZD).
ML (pin 6) MC (pin 7) MD (pin 8)
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
FIGURE 7. Serial Interface Timing.
tMLS
tMLH
ML
1.4V tMCH
tMLL
tMCL
MC
1.4V tMCY
MD
1.4V tMDS
tMDH
MC Pulse Cycle Time
: tMCY
: 100ns (min)
MC Pulse Width LOW
: tMCL
: 50ns (min)
MC Pulse Width HIGH
: tMCH
: 50ns (min)
MD Set-up Time
: tMDS
: 30ns (min)
MC Hold Time
: tMDH
: 30ns (min)
ML Low Level Time
: tMLL
: 30ns + 1SYSCLK (min)
ML Set-up Time
: tMLS
: 30ns (min)
ML Hold Time
: tMLH
: 30ns (min)
FIGURE 8. Program Register Input Timing.
®
PCM1721
12
APPLICATION CONSIDERATIONS
INTERNAL ANALOG FILTER FREQUENCY RESPONSE (20Hz~24kHz, Expanded Scale) 1.0
DELAY TIME There is a finite delay time in delta-sigma converters. In A/D converters, this is commonly referred to as latency. For a delta-sigma D/A converter, delay time is determined by the order number of the FIR filter stage, and the chosen sampling rate. The following equation expresses the delay time of PCM1721:
dB
0.5
0
–0.5
TD = 11.125 x 1/fS For fS = 44.1kHz, TD = 11.125/44.1kHz = 251.4µs
–1.0 20
Applications using data from a disc or tape source, such as CD audio, CD-Interactive, Video CD, DAT, Minidisc, etc., generally are not affected by delay time. For some professional applications such as broadcast audio for studios, it is important for total delay time to be less than 2ms.
100
1k Frequency (Hz)
10k
24k
FIGURE 9. Low Pass Filter Frequency Response.
INTERNAL ANALOG FILTER FREQUENCY RESPONSE (10Hz~10MHz)
OUTPUT FILTERING
dB
For testing purposes all dynamic tests are done on the PCM1721 using a 20kHz low pass filter. This filter limits the measured bandwidth for THD+N, etc. to 20kHz. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the specifications. The low pass filter removes out of band noise. Although it is not audible, it may affect dynamic specification numbers. The performance of the internal low pass filter from DC to 24kHz is shown in Figure 9. The higher frequency rolloff of the filter is shown in Figure 10. If the user’s application has the PCM1721 driving a wideband amplifier, it is recommended to use an external low pass filter. A simple 3rdorder filter is shown in Figure 11. For some applications, a passive RC filter or 2nd-order filter may be adequate.
10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 10
100
1k
10k
100k
1M
10M
Frequency (Hz)
FIGURE 10. Low Pass Filter Wideband Frequency Response.
GAIN vs FREQUENCY 6
90
+ VSIN
10kΩ
10kΩ 680pF
OPA604
10kΩ
–14
0
–34
–90
–54
–180
Phase (°)
1500pF
Gain (dB)
Gain
Phase
100pF
– –74
–270
–94
–360 100
1k
10k Frequency (Hz)
100k
1M
FIGURE 11. 3rd-Order LPF.
®
13
PCM1721
2.6V VCC/VDD 2.2V 1.8V Reset Reset Removal Internal Reset 1024 system (= XTI) clocks XTI Clock
FIGURE 12. Internal Power-On Reset Timing.
RSTB
50% of VDD tRST(1)
Reset Reset Removal
Internal Reset 1024 system (XTI) clocks XTI Clock NOTE: (1) tRST = 20ns min
FIGURE 13. RSTB-Pin Reset Timing. Reset
supplies are used without a common connection, the delta between the supplies during ramp-up time must be less than 0.6V. An application circuit to avoid a power-on latch-up condition is shown in Figure 14.
PCM1721 has both internal power-on reset circuit and the RSTB pin (pin 9) which accepts an external forced reset by RSTB = LOW. For internal power on reset, initialize (reset) is done automatically at power on VDD >2.2V (typ). During internal reset = LOW, the output of the DAC is invalid and the analog outputs are forced to VCC/2. Figure 12 illustrates the timing of internal power on reset.
Digital Power Supply
PCM1721 accepts an external forced reset when RSTB = L. During RSTB = L, the output of the DAC is invalid and the analog outputs are forced to VCC/2 after internal initialize (1024 system clocks count after RSTB = H.) Figure 13 illustrates the timing of RSTB pin reset.
VDD DGND
VCP VCC AGND
FIGURE 14. Latch-up Prevention Circuit.
POWER SUPPLY CONNECTIONS
BYPASSING POWER SUPPLIES
PCM1721 has three power supply connections: digital (VDD), analog (VCC), and PLL (VCP). Each connection also has a separate ground return pin. It is acceptable to use a common +5V power supply for all three power pins. If separate
The power supplies should be bypassed as close as possible to the unit. Refer to Figure 17 for optimal values of bypass capacitors. Its is also recommended to include a 0.1µF ceramic capacitor in parallel with the 10µF tantalum capacitor.
®
PCM1721
Analog Power Supply
14
+ In
+
8fS 18-Bit
+ Z–1
+
+
–
+
Z–1
Z–1
–
+ + 5-level Quantizer
+ 4 3
Out 48fS (384fS) 64fS (256fS)
2 1 0
FIGURE 15. 5-Level ∆Σ Modulator Block Diagram.
THEORY OF OPERATION 3rd ORDER ∆Σ MODULATOR
The delta-sigma section of PCM1721 is based on a 5-level amplitude quantizer and a 3rd-order noise shaper. This section converts the oversampled input data to 5-level deltasigma format.
20 0 –20 Gain (–dB)
A block diagram of the 5-level delta-sigma modulator is shown in Figure 15. This 5-level delta-sigma modulator has the advantage of stability and clock jitter sensitivity over the typical one-bit (2 level) delta-sigma modulator.
–40 –60 –80 –100 –120
The combined oversampling rate of the delta-sigma modulator and the internal 8X interpolation filter is 48fS for a 384fS system clock, and 64fS for a 256fS system clock. The theoretical quantization noise performance of the 5-level delta-sigma modulator is shown in Figure 16.
–140 –160 0
5
10
15
20
25
Frequency (kHz)
FIGURE 16. Quantization Noise Spectrum.
®
15
PCM1721
AC-3 APPLICATION CIRCUIT A typical application for PCM1721 is AC-3 5.1 channel audio decoding and playback. This circuit uses PCM1721 to develop the audio system clock from the 27MHz video clock, with the SCKO pin used to drive the AC-3 decoder and two PCM1720 units, the non-PLL version of PCM1721. 10µF + SCKO AC-3 Audio Decoder
+5V Analog
20
LRCKO 14 16
SERO_0 SERO_1
15
SERO_2 2
SYSCKI
19
DGND
VDD VOUTL
BCKIN
DIN
CAP
6 7
Analog Out
Post Low Pass Filter
Analog Mute
Analog Out
13 +
10µF
9
ML MC ZERO
8
Mute Control
MD RSTB AGND
STRB µP
Analog Mute
SCKI
VOUTR
5
Post Low Pass Filter
LRCIN
PCM1720
4
12
VCC
10
11 3.3µF +
SCKO
+5V Analog
SDO 10µF + Three-wire I/F (Serial I/O)
+5V Analog
20
3
19
DGND 14 16 15 2
VDD VOUTL
BCKIN
12
DIN
CAP
6 7
Analog Out
Post Low Pass Filter
Analog Mute
Analog Out
13 +
10µF
SCKI
VOUTR
5
Analog Mute
LRCIN
PCM1720
4
Post Low Pass Filter
9
ML MC ZERO
8
Mute Control
MD RSTB AGND
VCC
10 3.3µF +
11 +5V Analog
10µF + 23
16 Master Clock Generator or PLL
18 17 2 4 1
6 7 8 Reset
9
22
+5V Analog 21
3
PGND DGND VDD
VDP
VOUTL
BCKIN
14
Analog Mute
Analog Out
Post Low Pass Filter
Analog Mute
Analog Out
LRCIN DIN
CAP
15 +
10µF
SCKO SCKI
PCM1721 VOUTR
MCKI
11
ML MC
ZERO
10
Mute Control
MD 19
RSTB AGND
VCC
12
13
+ 3.3µF
FIGURE 17. Connection Diagram for a 6-Channel AC-3 Application. ®
PCM1721
Post Low Pass Filter
16
+5V Analog
