The Pdf Format!

Transcript

Diplomarbeit 900 MHz Power Amplifier Module in Multilayer-Laminate Technology ausgef¨ uhrt zum Zwecke der Erlangung des akademischen Grades eines Diplom-Ingenieurs unter Leitung von Werner Simb¨ urger und Arpad L. Scholtz E389 Institut f¨ ur Nachrichtentechnik und Hochfrequenztechnik eingereicht an der Technischen Universit¨at Wien Fakult¨at f¨ ur Elektrotechnik und Informationstechnik von Thomas Beles 9226945 Hafergrubenweg 22, A-2230 G¨anserndorf G¨anserndorf, im Juni 2005 Contents 1 Introduction 1.1 State-of-the-art power amplifier modules . . . . . . . . . . . . . . 1 1 2 Integrated 900 MHz power amplifier 2.1 A monolithic transformer coupled push-pull type power amplifier in silicon bipolar technology . . . . . . . . . . . . . . . . . . . . . 2.2 Balanced output matching network . . . . . . . . . . . . . . . . . 2.2.1 Transmission-line transformer . . . . . . . . . . . . . . . . 2.3 Optimum load impedance . . . . . . . . . . . . . . . . . . . . . . 4 3 Balun in multilayer-laminate technology 3.1 Functionality of the balun . . . . . . . . 3.2 Substrates of the balun . . . . . . . . . . 3.3 Simulation and design . . . . . . . . . . 3.4 Layout . . . . . . . . . . . . . . . . . . . 4 6 6 9 . . . . 13 14 15 19 26 4 Experimental results 4.1 S-parameter characterization of the balun . . . . . . . . . . . . . 4.2 Power amplifier module . . . . . . . . . . . . . . . . . . . . . . . . 31 31 35 Conclusion 41 A Losses of the multilayer balun A.1 The dielectric loss . . . . . . . A.2 The ohmic losses . . . . . . . A.2.1 DC loss . . . . . . . . A.2.2 Rf loss . . . . . . . . . 43 43 43 43 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B Alternative Implementations 46 Bibliography 54 i List of Abbreviations AC ADS B6HF C CMOS DC DCS1800 ²r ESD f FR4 GSM GaAs GPRS GND IC L LCP λ µ MMIC MOS PA PAC PAE PA2SA PCB PCS1900 RF ρ SKY77324 Si SMA SMD ω Z Alternating Current Advanced Design System, CAD software by Agilent Technologies Infineon silicon bipolar technology with fT = 25 GHz Capacity in [F] Complementary M etal Oxide Semiconductor Direct Current Digital Cellular System (1800 MHz) Relative permittivity Electrostatic Sensitive Device Frequency [Hz] Epoxy Laminate Global System for M obile communications Gallium Arsenide General P acked Radio Service Ground Integrated Circuit Inductance in [H] Liquid Crystalline P olymer, substrate material by Rogers Wavelength in [m] Permeability in [Vs/Am] M onolithical M icrowave Integrated Circuit M etal Oxide Semiconductor P ower Amplifier P ower Amplifier Control P ower Added Efficiency A power amplifier chip in B6HF by Infineon P rinted Circuit Board P ersonal Communication System (1900 MHz) Radio F requency Reflection coefficient A power amplifier module by Skyworks Silicon SubM iniatur A : Standard RF connector up to 18 GHz Surface M ounted Device angular frequency complex impedance in [Ω] ii Chapter 1 Introduction A RF power amplifier is required in every wireless system. However there are several ways to design such a power amplifier depending on the requirements. In this thesis, a push-pull power amplifier for 900 MHz is characterized including a new balun design for output matching. Currently power amplifier for GSM are implemented single-ended. One of the reasons for this is that matching is easier, because a balun is not required. On the other hand the single-ended implementation also has disadvantages. For example the emitter inductance of the bond wires affects negative to the RF performance. State of the art modules will be discussed in section 1.1. This work is looking for an another solution, which is based on the use of a balanced circuit design in silicon. To match the balanced amplifier to 50 Ω unbalanced output, a balun is required. In chapter 2 the integrated power amplifier chip PS2SA is presented, including measurement results of a reference balun design. These results will be used later on to be compared with the multilayer balun presented in chapter 3 and 4. A load pull measurement, which is used for the design of the multilayer balun, is presented as well. Chapter 3 shows the design and realization of a new multilayer balun. Functionality of the balun, used materials and a simulation model is explained in detail. Finally experimental results are presented in chapter 4. The appendix shows the losses of the balun in detail, and closing with an overview about alternative multilayer balun implementations. 1.1 State-of-the-art power amplifier modules Most of today’s power amplifiers for handsets are hybridmodules which work for all four GSM frequency bands. The enterprices Anadigics, Analog Divices, Hitachi, Motorola, Philips, RFMD, Skyworks and TriQuint are offering such quad1 CHAPTER 1. INTRODUCTION 2 Figure 1.1: Schematic diagram of the Skyworks 77324 quad-band power amplifier module. Source: [Skyworks 03] band power amplifier modules. From all these we look are up to the SKY77324 module from Skyworks. The products from other companies are designed in similar ways. The SKY77324 power amplifier module consists of separate GSM850/900 PA and DCS1800/PCS1900 PA blocks, impedance matching circuitry for 50 Ω input and output impedances, and a power amplifier control (PAC) block with an internal current-sense resistor. The custom CMOS integrated circuit provides the internal PAC function and interface circuitry. Fabricated on a single Gallium Arsenide die, one heterojunction bipolar transistor PA block supports the GSM850/900 bands and the other supports the DCS1800 and PCS1900 bands. The GaAs die, the silicon die, and the passive components are mounted on a multilayer laminate substrate. The assembly is encapsulated with plastic overmold. Fig. 1.1 and Tab. 1.1 show more details. CHAPTER 1. INTRODUCTION 3 Applications Class 4 GSM850/900 Class 1 DCS1800/PCS1900 Class 12 GPRS multi-slot operation Input Power Range 0 to 6 dBm Typical Output Power GSM850 35 dBm GSM900 35 dBm DCS 33 dBm PCS 33 dBm Typical PAE GSM850 49 % GSM900 53 % DCS 51 % PCS 53 % Supply Voltage 2.9 - 4.8 V Package 6 mm x 8 mm x 1.2 mm, 22-pin MCM Internal ICC Sense resistor for PAC Input/Output matching 50 Ω internal with DC blocking Table 1.1: Features of the Skyworks 77324 quad-band power amplifier module. Source: [Skyworks 03] Chapter 2 Integrated 900 MHz power amplifier This chapter is based on the paper ”Monolithic Integration of Power Amplifier in Silicon-based Technologies” from Werner Simb¨ urger [Simb¨ urger 99], and presents the integrated power amplifier PA2SA for 900 MHz. To evaluate the performance of the power amplifier MMIC an external output matching network circuit is required. This circuit consists of a partially distributed impedance transformation network and a semi-rigid line balun. The measurement results will be used later on to be compared with the multilayer balun presented in chapter 3 and 4. A detailed description of the PA chip PS2SA is also shown in [Heinz 99], including a load-pull measurement, which is important for the design of the multlayer balun. These measurement results will be presented at the end of this chapter. 2.1 A monolithic transformer coupled push-pull type power amplifier in silicon bipolar technology Fig. 2.1 shows a simplified schematic diagram of a monolithic 2-stage push-pull power amplifier. It consists of an on-chip transformer as input-balun, a driver stage, a transformer as interstage matching network and a power output stage. A current mirror is used to set the bias current of the driver stage and the output stage each. The input-transformer X1 is connected as a parallel resonant device using a MOS-capacitor CIN . The transformer acts as balun as well as input matching network. On-chip transformers are also used successfully by e.g. J.R. Long and M.A. Copeland [Long 95], J. Zhou [Zhou, J.J. 98], D. Cheung [Cheung, D.T. 98]. 4 CHAPTER 2. INTEGRATED 900 MHZ POWER AMPLIFIER 5 VCC RFOUT+ T3 BIAS BIAS R1 R2 X1 RFIN+ T1 X2 D1 D2 CIN CIS RFIN- T2 T4 VEE Substrate RFOUT- Figure 2.1: Basic architecture of a transformer coupled monolithic 2-stage pushpull type power amplifier. There are several outstanding advantages due to the on-chip transformer at the input: • No restrictions to the external dc potential at the input terminals. • No external input dc blocking capacitor is required. • The input signal can be applied balanced or single-ended if one input terminal is grounded. The interstage matching network of the power amplifier consists of the transformers X2. A MOS capacitor CIS are connected in parallel to the primary windings. From this basic idea the circuit shown in Fig. 2.2 was developed. Several experimental results of this MMIC are presented in [Simb¨ urger, 99,a, Simb¨ urger, 99,b]. The amplifier circuit is designed to meet the requirements to the parasitic behavior of the on-chip transformers. Therefore, the interstage matching network of the power amplifier consists of two transformers X2 and X3 with a turn ratio of N=5:2. The primary windings are connected in series and the secondary windings are connected in parallel in order to provide the right values of primary and secondary inductance and to put high base currents into the output power transistors. CHAPTER 2. INTEGRATED 900 MHZ POWER AMPLIFIER 6 Figure 2.2: Schematic diagram of a monolithic push-pull power amplifier [Simb¨ urger, 99,a, Simb¨ urger, 99,b]. The chip is fabricated in a standard 25 GHz-fT , 0.8 µm, 3-layer-interconnect silicon bipolar production technology of Infineon B6HF [Klose, H. 93]. Fig. 2.3 shows a cross section of a typical 0.8 µm BEC transistor module. The production technology offers rf npn, high voltage npn, lateral pnp, p+ /p− /n+ -poly resistors, 2 fF/µm2 MOS capacitors and ESD structures. Fig. 2.4 shows a micrograph of the chip. 2.2 Balanced output matching network The strong impact of the output matching network and the bias operating point on the output power and the PAE of a rf power amplifier is a well known subject ([Sokal, N. O 75] to [Nishiki 87]). The performance of a power amplifier depends on the circuit design as well on the input/interstage/load-line matching network. 2.2.1 Transmission-line transformer A transmission-line transformer circuit can be used to evaluate the performance of a power amplifier MMIC, or as a design basis for a discrete or hybrid-module CHAPTER 2. INTEGRATED 900 MHZ POWER AMPLIFIER Base Contact Al Emitter Contact 7 Collector Contact Al Al + Poly n LOCOS Poly p + Oxide Poly n+ Active Transistor ChannelStop Buried-Layer Buried-Layer Contact 2 µm Figure 2.3: Cross section of a 25 GHz-fT , 0.8 µm silicon bipolar transistor BEC module [Klose, H. 93]. implementation [Motorola 94]. The output matching network circuit, which was used in [Simb¨ urger, 99,a] to evaluate the performance of the power amplifier MMIC consists of a partially distributed impedance transformation network and a semi-rigid line balun. Fig. 2.5 shows the schematic diagram of the test circuit. The input of the amplifier MMIC is connected via a 50 Ω micro-strip line to the input signal. The supply-voltage line of the output stage consists of two 50 Ω λ/4-length lines (at the frequency of operation f1 ) translating a low impedance at 2f1 to the output transistors. The optimum load impedance at the frequency of operation f0 is translated by 25 Ω λ/8-length micro-strip lines. CM determines mainly the real part and CE determines nearly orthogonal the imaginary part of the load impedance at f1 . CA determines the impedance at 3f1 which should be as high as possible. CK are DC blocking capacitors. A λ/4-length 50 Ω semi-rigid line acts as balun. Fig. 2.6 shows a photograph of a test circuit, which was designed at 900 MHz [Simb¨ urger, 99,b]. The printed circuit board (PCB) measures 70 mm×78 mm. A FR4 substrate with a height of h = 0.8 mm is used. Transmission-line transformer experimental Results Fig. 2.7 shows the output power and PAE versus input power, of the power amplifier (Fig. 2.2), at 900 MHz and T = 27 C depending on the supply-voltage at 2.5 V, 3.5 V, 4 V and 4.5 V. The maximum PAE is about 57 % at 3.5 V and 4 V. 37 dBm (5 W) output power is achieved at 4.5 V supply voltage and 900 MHz. The linear gain is 36 dB. CHAPTER 2. INTEGRATED 900 MHZ POWER AMPLIFIER 8 Figure 2.4: Micrograph of the rf power amplifier IC [Simb¨ urger, 99,b]. Size: 2 2×2 mm . Fig. 2.8 shows the output power and PAE versus frequency and supply-voltage at T = 27 C. The input power is +10 dBm. 37 dBm (5 W) is achieved at 800 MHz to 910 MHz and 4.5 V supply voltage. The PAE at the maximum output power is 57 %. At 3.5 V and 4 V the maximum PAE is about 59 %. The collector efficiency of the output stage is 67 % in this case. In general the PAE is > 50 % from 800 MHz to 960 MHz. The driver stage and the output stage forms a push-pull Class AB stage each. At 2.5 V supply voltage the bias current of the driver stage is about 30 mA per transistor. The bias current of the output stage is 260 mA per Transistor. At 4.5 V supply voltage the bias current of the output stage goes up to near 400 mA due to breakdown conditions. CHAPTER 2. INTEGRATED 900 MHZ POWER AMPLIFIER 9 VCC BALUN 50 W l/4 VCC l/8 Power-Down CK 25 W 25 W 50 W PIN CM CA 25 W POUT CE 25 W 50 W l/4 CK Power Amplifier Chip mounted in a TSSOP-16 package with heat sink. VCC Figure 2.5: Schematic diagram of the transmission-line transformer output matching network. 2.3 Optimum load impedance To achieve the best performance of the power amplifier, the right load impedance at the output is required. This process is called power matching. Here, the load is dimensioned exactly conjugate complex to the impedance of the amplifier circuit. As [Gonzales 84] has shown, this strategy warrants the maximum output power. However, power amplifier in most cases do not work in the linear range. This nonlinearity makes the system time variant. Thus, the linear power matching method is not correct any more. In fact, [Jochen 95] showed that the maximum output power for nonlinear power amplifiers is maximized if a certain load impedance is attached to the fundamental frequency and the second and third harmonic frequency. For the second harmonic frequency the load should be close to a short circuit, while for the third harmonic frequency an open circuit is desired. While the real part of the load for the fundamental frequency depends mainly on the power supply voltage and the desired power output the imaginary part is caused by parasitic substrate and transistor capacities, not to forget the inductances of the bonding wires and interconnections. For the design of the multilayer balun the optimum load impedance of the PA2SA is necessary. However, Alexander Heinz [Heinz 99] and W. Balkalski [Bakalski 01] have explained the load-pull measurement setup in detail, therefore this paper only shows the results of these measures based on Alexander Heinz in short: As the limits of the two different measurements differ slightly, one can say that the maximum Pout (Fig. 2.9) and the maximum PAE (Fig. 2.10) are achieved at an optimum load impedance of around 6 Ω. CHAPTER 2. INTEGRATED 900 MHZ POWER AMPLIFIER 10 Figure 2.6: Power amplifier test circuit with a transmission-line transformer. FR4 PCB size: 70×78 mm2 . [Bakalski 01] CHAPTER 2. INTEGRATED 900 MHZ POWER AMPLIFIER 11 Figure 2.7: Transmission-line transformer output power and PAE versus input power and supply voltage. [Heinz 99] Figure 2.8: Transmission-line transformer output power and PAE versus frequency and supply voltage. [Heinz 99] CHAPTER 2. INTEGRATED 900 MHZ POWER AMPLIFIER 12 34 33 33 32.5 Pout in dBm 32 32 31.5 31 31 30 30.5 29 30 29.5 28 29 28.5 27 -4 Im ag inä -2 rte il ( sin 0 gle en de 2 d) in 28 20 15 10 5 Oh 4 m 0 in ed) Ohm nd le e g (sin lteil a e R Figure 2.9: Output power versus complex load impedance measured at 900 MHz. [Heinz 99] 45 40 40 PAE in % 35 35 30 30 25 25 20 15 20 10 15 5 -4 10 Im -2 ag inä rte il 20 (si 0 ng le e 15 hm in O ed) d n e 5 gle (sin lteil a e R 10 nd 2 ed ) in 4 Oh m 0 Figure 2.10: Power added efficiency versus complex load impedance measured at 900 MHz. [Heinz 99] Chapter 3 Balun in multilayer-laminate technology In this chapter a new multilayer balun is presented. The balun has to meet several requirements: It provides a matching for the 6 Ω balanced output (optimum load) of the power amplifier PA2SA to an 50 Ω unbalanced load. The balun is realized in a multilayer laminate board which acts as a carrier for the PA chip as well. The carrier function of the board implies feeding control and power lines to the chip as well as leading the produced heat away from the chip. The schematic diagram of the power amplifier module (power amplifier and balun) is shown in Fig. 3.1. Power Amplifier PS2SA Multilayer Balun Bias Bias VCC X2 RFIN+ X1 T1 T3 R1 R2 VCC CIN CIS RFOUT D1 D2 T2 T4 RFIN- Figure 3.1: Schematic diagram of the power amplifier module. 13 CHAPTER 3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 14 RFOUT 50 Ohm broadside coupled striplines Coupler 2 Coupler 1 CL2botton CL1up CL2up CL1botton l/4 l/4 VCC RFIN+ RFIN6 Ohm 6 Ohm Figure 3.2: Schematic diagram of the multilayer balun. 3.1 Functionality of the balun The basic circuit of the balun is shown in Fig. 3.2. It consist of two λ/4 - couplers which are implemented as broadside coupled striplines. Each of the coupler shifts the phase by 90 degrees. Basic Information concerning of broadside coupled striplines can be found in [Mongia, R. 99] and [Wadell 91]. V CC is the supply for the output circuit of the power amplifier. For the design it is necessary to understand the wave propagation on the striplines. Fig. 3.3 shows the two propagation modes. For a good coupler the ODD mode is desired and the EVEN mode is undesired. This will be reached by a small spacing S and a large spacing B, so that the ODD mode dominates. EVEN - Mode ODD - Mode tan d2 tan d1 tan d1 tan d2 tan d2 B S tan d2 Figure 3.3: The two propagation modes of broadside coupled striplines. CHAPTER 3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY Product Property Construction Type Dielectric Constant, ²r Dielectric Loss Factor, tan δ Moisture Absorption, % LCP Thickness, µm Copper Thickness, µm Melting Temperature, ◦ C Solder Float, ◦ C R/flex 3600 R/flex 3850 single clad laminate 15 R/flex 3958 (R/flex 3800) bond film double clad laminate 2.9 (1-10 GHz) 0.002 (1-10 GHz) 0.04 25, 50, 100 18, others upon request 290 315 260 288 N/A 280 (315) 260 (288) Table 3.1: R/flex 3000 LCP product family. Source: [Rogers 03] The main part of the electrical field is captured between the striplines. This will be improved by a large ²r1 and a small ²r2 . For a good performance of the coupler it is important that the dielectric loss tan δ1 is small, whereas the influence of the dielectric loss tan δ2 is not so relevant. 3.2 Substrates of the balun In reference to previous explanation the basic construction of the multilayer buildup of the balun results as is shown in Fig. 3.4. Metal 2 and 5 serve as groundplanes for coupler 1; metal 6 and 9 for coupler 2. Metal 3 and 4 as well as metal 7 and 8 are the broadside coupled striplines. The top and the bottom metal layers are used for the power and control lines. The dielectric layers ²r2 and ²r3 are made of cheap FR4. Between the striplines a very thin high quality layer is necessary. There are two reasons to use high quality layers instead of FR4. Firstly the dielectric loss of FR4 is higher than the loss of the high quality material. Secondly the minimum thickness of FR4 is 100 µm, whereas the high quality materials are available with a minimum thickness of 25 µm. ´If the module was fabricated only in FR4, the overall size would be significanty larger as the composite buildup with FR4 and high quality materials. The following two high quality substrates were investigated: • Rogers R/flex 3000 LCP by Rogers • Gores Speedboard C by Gore The Rogers R/flex 3000 LCP is a new substrate by Rogers for high frequency applications. LCP is equivalent for ‘Liquid Crystalline Polymer’. It has a dielectric constant ²r of 2.9, and a very small dielectric loss factor tan δ of 0.002. Both values Coupler 1 Coupler 2 CL2bottom CL2up CL1bottom CL1up 25 Micron 200-300 Micron 100 Micron er1, tan d1 er2, tan d2 er3, tan d3 100 Micron er3, tan d3 200-300 Micron 200-300 Micron er2, tan d2 er2, tan d2 25 Micron 200-300 Micron 100 Micron er1, tan d1 er2, tan d2 er3, tan d3 Si IC Metal 10 (Signal) Metal 9 (GND Plane) Metal 7 (Coupled Lines) Metal 8 (Coupled Lines) Metal 6 (GND Plane) Metal 5 (GND Plane) Metal 3 (Coupled Lines) Metal 4 (Coupled Lines) Metal 2 (GND Plane) Metal 1 (Signal) Epoxy Glue Bond Wire VCC CL1up Rfout (~ 46 mm at 900 MHz) l/4 CL2bottom CL2up CL1bottom Rfin- Rfin+ CHAPTER 3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 16 Figure 3.4: Basic construction of the multilayer buildup and schematic diagram of the balun. CHAPTER 3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 17 R/flex 3600 single clad Copper R/flex 3858 bonding film Copper R/flex 3850 double clad Copper Figure 3.5: Rogers R/flex 3850 double clad laminates can be multilayer bonded with the Rogers R/Flex 3958 bondply or Rogers R/flex single clad laminates to make all-LCP multilayer boards. Rogers R/flex circuite materials can also be combined with epoxy, acrylic or cyanate ester to enhanced the properties of a multilayer design as needed. Dielectric constant ²r at 1-40 GHz Dielectric Loss Factor, tan δ at 1-40 GHz Glass transition Temperature Tg, ◦ C Thickness of dielectric, µm Moisture Absorption, % (w/w) 2.6 0.0036 220 38, 51, 57, 86 0.31 - 0.46 Table 3.2: Material Properties of Gores Speedboard C. It’s only available as prepreg. Source: [Gore 02] are nearly constant in a wide range of frequency. The LCP is available as a single copper-clad laminate, as a double copper-clad laminate and as a bonding film, too. Tab. 3.1 and Fig. 3.5 shows more details. The other high frequency substrate is the Speedboard C by Gore. In contrast to the LCP it is only available as prepreg. A prepreg is a dielectric layer without a copper-clad to combine multilayer buildups, such as the bonding film in the case of Rogers R/flex. Gores Speedboard C has a dielectric constant ²r of 2.6, and a dielectric loss factor tan δ of 0.0036, which is also nearly constant in a wide range of frequency. Tab. 3.2 shows the material properties: The thinnest available thickness is the 38 µm speedboard. In contrast to the LCP single and double clad laminate the thickness is becoming smaller after pressing. For the balun application, in which copper laminated cores are pressed from both sides, the thickness decreases to about 25 µm, which is illustrated in Fig. 3.6. We used the following companies as suppliers for test module fabrication: • Aspocomp Group, Ayritie 12 a, P.O. Box 230, 01511 Vantaa, Finland CHAPTER 3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY After Pressing Before Pressing FR4 - Prepeg FR4 - Prepeg Copper Copper Copper LCP - Core, double clad 25 mm 25 mm LCP - Core, double clad 18 Copper FR4 - Prepeg FR4 - Prepeg FR4 - Core FR4 - Core Copper 38 mm Speedboard C - Prepeg Speedboard C - Prepeg ~25 mm Copper Copper Copper FR4 - Core FR4 - Core Figure 3.6: Comparison of Rogers double clad LCP core and Gores Speedboard C prepeg. Sales Manager: Fernando Miranda Phone: +358 9 7597 0720 Fax: +358 9 7597 0720 email: [email protected] • Optiprint, Switzerland Sales Manager: Gerhard Popp Phone: +49 7129 922783 Fax: +49 7129 922784 email: [email protected] • R&D Ciruits, NJ, USA Engineering Manager: Tom Smith Phone: +1 732 549 4559 Ext. 26 Fax: +1 732 549 1388 email: [email protected] • Ruwel, Marburger Strasse 65, D-35083 Wetter/Hessen, Germany Product Manager: Henk Berkel Phone: +49 64 2381 246 Fax: +49 64 23 4385 email: [email protected] CHAPTER 3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 3.3 19 Simulation and design To describe the balun with S-parameters we have used the mixed mode concept. The basics of mixed mode S-parameters can be found in [Agilent 01], [Agilent 97], [Maxim 01] and in [Stengel 99]. In the case of a balun there is a combination of balanced and single ended ports. To define the S-parameters of this device, three modes must be included: differentialand common modes on the balanced port, and a single ended mode on the single ended port (Fig. 3.7). Three-Terminal Devices (3 Modes of Propagation) Single-Ended Mode 2 1 Port 1 (unbalanced) Differential Mode Common Mode Port 2 (balanced) Balun 3 Single Ended Response Port 1 Differential Mode Response Port 2 Common Mode Response Port 2 Single Ended Stimulus Differential Mode Stimulus Common Mode Stimulus Port 1 Port 2 Port 2 Sss11 Ssd12 Ssc12 Sds21 Scs21 Sdd22 Scd22 Sdc22 Scc22 Figure 3.7: To characterise a balun the mixed mode concept is to consider. For a characterization of the balun the single ended S-parameters must be extended by mixed mode S-parameters. For a full description of the balun, with its different modes at input and output, following terms are necessary: • One single-ended port reflection term - Sss11 • Four balanced port reflection terms - Sdd22 , Scc22 , Sdc22 , Scd22 • Two forward transmission terms - Sds21 , Scs21 CHAPTER 3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 20 • Two reverse transmission terms - Sds12 , Scs12 The S-matrix for such a device is arranged with the stimulus conditions in the columns, and the response conditions in the rows. Notice that two columns and two rows describe each balanced port, and one column and one row describe each single-ended port. In this case the four parameters in the lower right corner describe the four types of reflection that are possible on a balanced port, the single parameter in the upper left describes the reflection on the single ended port, and the other four parameters describe the differential and common mode transmission characteristics in the forward and reverse directions. To receive the mixed mode parameters from a 3 port single ended measurement, the following transformation equations are used: Sss11 = S11 (3.1) 1 Ssd12 = √ · (S12 − S13 ) 2 (3.2) 1 Ssc12 = √ · (S12 + S13 ) 2 (3.3) 1 Sds21 = √ · (S21 − S31 ) 2 (3.4) 1 Scs21 = √ · (S21 + S31 ) 2 (3.5) Sdd22 = 1 · (S22 − S23 − S32 + S33 ) 2 (3.6) Scc22 = 1 · (S22 + S23 + S32 + S33 ) 2 (3.7) Sdc22 = 1 · (S22 + S23 − S32 − S33 ) 2 (3.8) CHAPTER 3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY Scd22 = 1 · (S22 − S23 + S32 − S33 ) 2 21 (3.9) In this work we primarily look upon a multilayer balun made of a combination of LCP and FR4 in work with the board producer Ruwel. For the simulation the program ADS 2003A from Agilent Technologies is used. ADS is an abbreviation for ”Advanced Design System”. We start with an estimation of the line width and the line length. They will be calculated with the ADS tool ”LineCalc”. For this calculation the characteristic impedance Z0 of the λ/4 - coupler is required, and can be determined by Z02 = Zin · Zout = Zeven · Zodd . (3.10) With Zin = 6 Ω and Zout = 50 Ω the result is Z0 = 17.32 Ω. So the line width becomes about 500 µm, the line length of the λ/4 - line about 46 mm, Zeven ≈ 65 Ω and Zodd ≈ 4.5 Ω. Next we create a simulation model. For this we start with the schematic tool, where the basic circuit will be assembled. To save space the lines are arranged in spiral structures. Fig. 3.8 shows the details of the schematic. For the simulation we change to the layout tool. There is an efficient 3D-Simulator called ”Momentum” available. Furthermore, in the layout tool there is a possibility to generate composite substrate stacks, which is a problem in the schematic tool. To export the structure from the schematic tool to the layout tool the function ”Generate/Update Layout...” is used. For a successful export, the ground and the port components must be erased. After export the structure is available in the layout tool. At first the layers can be named or renamed with the ”Layer Editor”. Next the substrate stack and the assignment of the layers will be defined. This is possible with the function ”Momentum - Substrate - Create/Modify...”. Furthermore, the structure must be expanded with the ground planes, interlayer connections and the ports for the simulation. One interlayer connection is necessary for coupling the two striplines. Some others are necessary to couple the ground planes. To facilitate the simulation all interlayer connections will be implemented in quadratic structures. With the ”Port Editor...” the three input/output-ports will be defined as single type ports with 50 Ω. The ground reference ports on the ground planes must be assigned to the input/output-ports, and also in alignment with them. Fig. 3.9 shows the layout of the balun for the simulation. However, both the single ended and the balanced port are defined with 50 Ω single ended. For this it is possible to export the S-parameter data to a 3-port blackbox in ADS or into another program. Now the S-parameter is displayed from case to case normalized to 50 Ω for all ports or normalized to 50 Ω for the single ended port and 6 Ω for the balanced port. CHAPTER 3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY S-PARAMETERS S_Param SP1 Start=0.5 GHz Stop=1.5 GHz Step=0.01 GHz SSub SSUB MMix2 Er=2.9 Mur=1 B=361 um T=18 um Cond=5.7E7 TanD=0.002 Cond1="metal3" Cond2="metal4" SMITER Bend45 Subst="MMix1" W=w um Layer=cond2 SMITER Bend28 Subst="MMix2" W=w um Layer=cond1 SSub SSUB MMix1 Er=2.9 Mur=1 B=361 um T=18 um Cond=5.7E7 TanD=0.002 Cond1="metal7" Cond2="metal8" Var Eqn VAR VAR1 s=25 A=2854 B=8087 C=8106 D=6437 E=6562 F=4945 G=5020 H=2583 J=2036 w=600 d=3150 Term Term2 Num=2 Z=50 Ohm SMITER Bend46 Subst="MMix1" W=w um Layer=cond1 Term Term3 Num=3 Z=50 Ohm SBCLIN CLin28 Subst="MMix1" W=w um S=s um L=A um P1Layer=cond1 SMITER Bend23 Subst="MMix2" W=w um Layer=cond2 SMITER Bend15 Subst="MMix2" W=w um Layer=cond1 SBCLIN CLin15 Subst="MMix2" W=w um S=s um L=D um P1Layer=cond1 SMITER Bend22 Subst="MMix2" W=w um Layer=cond2 SBCLIN CLin14 Subst="MMix2" W=w um S=s um L=E um P1Layer=cond1 SMITER SBCLIN Bend16 CLin11 Subst="MMix2" Subst="MMix2" W=w um W=w um Layer=cond2 S=s um L=J um SBCLIN P1Layer=cond1 CLin12 Subst="MMix2" W=w um S=s um L=H um P1Layer=cond1 SMITER Bend20 Subst="MMix2" W=w um Layer=cond2 SMITER Bend19 Subst="MMix2" W=w um Layer=cond1 SBCLIN CLin7 Subst="MMix1" W=w um S=s um L=E um P1Layer=cond1 SBCLIN CLin6 Subst="MMix1" W=w um S=s um L=F um P1Layer=cond1 SMITER Bend9 Subst="MMix1" W=w um Layer=cond2 SMITER Bend2 Term SBCLIN Subst="MMix1" Term1 CLin3 W=w um Num=1 Subst="MMix1" Layer=cond2 Z=50 Ohm W=w um S=s um L=J um P1Layer=cond1 SMITER Bend3 Subst="MMix1" W=w um Layer=cond2 SMITER Bend5 Subst="MMix1" W=w um Layer=cond2 SMITER Bend14 Subst="MMix1" W=w um Layer=cond1 SMITER Bend13 Subst="MMix1" W=w um Layer=cond2 SMITER Bend6 Subst="MMix1" W=w um Layer=cond1 SMITER Bend25 Subst="MMix2" W=w um Layer=cond2 SBCLIN CLin16 Subst="MMix2" W=w um S=s um L=C um P1Layer=cond1 SMITER Bend7 Subst="MMix1" W=w um Layer=cond2 SBCLIN CLin5 Subst="MMix1" W=w um S=s um L=G um P1Layer=cond1 SBCLIN CLin9 Subst="MMix1" W=w um S=s um L=C um P1Layer=cond1 SMITER Bend44 Subst="MMix2" W=w um Layer=cond1 SMITER Bend21 Subst="MMix2" W=w um Layer=cond1 SBCLIN CLin13 Subst="MMix2" W=w um S=s um L=F um P1Layer=cond1 SMITER Bend17 Subst="MMix2" SBCLIN W=w um CLin17 Layer=cond2 Subst="MMix2" W=w um S=s um SMITER L=G um Bend24 P1Layer=cond1 Subst="MMix2" W=w um Layer=cond2 SBCLIN CLin10 Subst="MMix1" W=w um S=s um L=B um P1Layer=cond1 SMITER Bend43 Subst="MMix2" W=w um Layer=cond2 SBCLIN CLin27 Subst="MMix2" W=w um S=s um L=A um P1Layer=cond1 SMITER Bend18 Subst="MMix2" W=w um Layer=cond1 SMITER Bend27 Subst="MMix2" W=w um Layer=cond1 SMITER Bend8 Subst="MMix1" W=w um Layer=cond1 22 SBCLIN CLin18 Subst="MMix2" W=w um S=s um L=B um P1Layer=cond1 SMITER Bend26 Subst="MMix2" W=w um Layer=cond1 SMITER Bend10 Subst="MMix1" W=w um Layer=cond1 SMITER Bend1 Subst="MMix1" W=w um Layer=cond1 SBCLIN CLin4 Subst="MMix1" W=w um S=s um L=H um P1Layer=cond1 SBCLIN CLin8 Subst="MMix1" W=w um S=s um L=D um P1Layer=cond1 SMITER Bend4 Subst="MMix1" W=w um Layer=cond1 SMITER Bend11 Subst="MMix1" W=w um Layer=cond2 SMITER Bend12 Subst="MMix1" W=w um Layer=cond1 Figure 3.8: Schematic of the balun assembled in ADS2003A schematic tool. CHAPTER 3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY CL2 (Metal 6 + 7) RFIN- RFOUT RFIN+ 23 CL1 (Metal 3 + 4) 11.8 mm 460um 13.4 mm Metal 3 - CL1up Metal 6 - CL2up Metal 7 - CL2bottom Figure 3.9: Simulation with the layout tool - top view of the Ruwel multilayer balun version D1. Line length = 46.62 mm, line width = 460 µm. With this information it is possible to determine the exact buildup of the multilayer. To achieve a good performance of the coupled lines, the insertion loss of the differential mode to single ended mode transmission Sds21 should be less than 0.2 to 0.3 dB - for operating conditions (50 Ω single ended port, 2 x 6 Ω balanced port). The simulation shows that with a spacing of 300 µm between the striplines and the ground planes the goal for the insertion loss of Sds21 will be exceeded. It also shows that the reflection coefficients of the balanced port are small in case of differential mode and large for the common mode. Three FR4 prepegs, each with 115 µm thickness, decrease to about 300 µm after pressing. With only CHAPTER 3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 24 Result of Simulation - Ruwel Version D1 Transmission: Balanced -> single ended m1 0.0 Balanced port reflection 0 -10 -1.0 dB(Sdd22) dB(Sds21) m3 freq= 900.0MHz dB(Sdd22)=-32.660 -5 -0.5 -1.5 m1 freq= 900.0MHz dB(Sds21)=-0.125 -2.0 -15 -20 -25 -2.5 m3 -30 -3.0 -35 -28 -0.06 m2 m4 freq= 900.0MHz dB(Scc22)=-0.129 -0.08 -32 -34 dB(Scc22) dB(Scs21) -30 m2 freq= 900.0MHz dB(Scs21)=-29.958 -36 -0.10 m4 -0.12 -0.14 -38 -40 -0.16 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0.6 freq, GHz 0.7 0.8 0.9 1.0 1.1 1.2 freq, GHz Eqn Sds21 = 0.707*(S(2,1)-S(3,1)) (Differential mode --> single ended mode transmission) Eqn Scs21 = 0.707*(S(2,1)+S(3,1)) (Common mode --> single ended mode transmission) Eqn Sdd22 = 0.5*((S(2,2)+S(3,3))-(S(2,3)+S(3,2))) (Differential mode reflection) Eqn Scc22 = 0.5*((S(2,2)+S(3,3))+(S(2,3)+S(3,2))) (Common mode reflection) Figure 3.10: Simulation result for operating contitions (50 Ω single ended port, 2 x 6 Ω balanced port) of the balun with 300 µm spacing between the striplines and the groundplanes. The line width is 460 µm and the line length is 46.62 mm. LCP and FR4 are used for the substrates. The insertion loss of the differential mode to single ended mode transmission Sds21 amounts to 0.125 dB. two prepegs the insertion loss would be significantly larger because the unwanted EVEN mode could be propagated better. Fig. 3.11 shows the resulting multilayer buildup. For the functionality of the balun a separation of metal 5 and 6 would not be necessary. An advantage of this implementation, where metal 5 and 6 are separated, is the symmetrically structure of the buildup. With the specified multilayer buildup now it is possible to determine the line width and the line length exactly. The result of the simulation, which is illustrated in Fig. 3.10, is achieved with a line width of 460 µm and a line length of 46.62 mm. In Fig. 3.12 the 3D view of the simulation is shown. LCP 3850 Core double clad - 25 Micron FR4 Prepeg 2116 - (3x 115 Micron) about 300 Micron after pressing FR4 Core double clad - 100 Micron FR4 Prepeg 2116 - (3x 115 Micron) about 300 Micron after pressing LCP 3850 Core double clad - 25 Micron FR4 Prepeg 2116 - (3x 115 Micron) about 300 Micron after pressing FR4 Core double clad - 100 Micron er=2.9, tan d=0.02 er=4.2, tan d=0.002 er=4.3, tan d=0.002 er=4.2, tan d=0.002 er=2.9, tan d=0.02 er=4.2, tan d=0.002 er=4.3, tan d=0.002 0.4 mm (before plating) FR4 Prepeg 2116 - (3x 115 Micron) about 300 Micron after pressing er=4.2, tan d=0.002 Metal 10 (Signal) Metal 9 (GND Plane) Metal 7 (Coupled Lines) Metal 8 (Coupled Lines) Metal 6 (GND Plane) Metal 5 (GND Plane) Metal 3 (Coupled Lines) Metal 4 (Coupled Lines) Metal 2 (GND Plane) Metal 1 (Signal) Design rules used in the layout: min 125um metal to metal distance min 100um annual ring for the catch pads FR4 Core double clad - 100 Micron Si IC Epoxy Glue Bond Wire er=4.3, tan d=0.002 Project: GSM PA - Ruwel Process: Metalization: 18 Micron Copper Foil Finish: Metal 1 and Metal 10 - Gold plating Via 1 CHAPTER 3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 25 Figure 3.11: The detailed multilayer buildup from Ruwel with LCP and FR4. CHAPTER 3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 26 CL2 (Metal 7 + 8) CL1 (Metal 3 + 4) Vias GND Plane (Metal 5 + 6) Figure 3.12: Simulation with the ADS layout tool - 3D view. 3.4 Layout Now the simulation model in ADS will be upgraded to a complete layout. The first step is to design the connection area for the chip. The chip will be glued on grounded metal areas. Vias below the chip lead the heat which is produced away. In this design only through vias are in use. The electrical connection between the chip and the board will be achieved with bond wires. There are separated grounds for the driver stage and the output stage. All control and power lines lead to the outside of the board, where they are routed CHAPTER 3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 27 D GND via d GND via D Impedance controlled via GND via GND via Figure 3.13: To control the impedance of a via a coaxial structure is necessary. with vias to the bottom side of the multilayer. To compensate the inductivity of the power lines pads are provided for capacitors. The RF in and the RF out lines are performed in 50 Ω lines. The vias for this lines are implemented in 50 Ω coaxial vias. They are calculated with the following equation (Fig. 3.13): 173 D Z = √ · log ² 0.933 · d (3.11) On the bottom side V CC and RF out are leading to the pads on the outside, whereas V CC has a line length of λ/4. So unwanted crosstalk at fundamental frequency is suppressed due to the transformation characteristic of the λ/4 line. The spacing between the V CC line and the RF out line is maximized, so that crosstalk is minimized. It is important that the groundplanes are cutting out behind the RF -pads, otherwise the pads will work as capacitors. In Fig. 3.14 the top and the bottom view of the Ruwel multilayer balun is shown. The balun was produced in various versions. So the line length and the line width are varying. For S-parameter measurements all versions are also produced with test pads. An overview of the different versions is shown in Tab. 3.3. In Fig. 3.15 a section of the profile of the Ruwel multilayer balun is shown. The four groundplanes and the coupled lines are clearly identifiable. Also, a via is shown in its profile. In the picture we recognize that a small lateral off-set of the layers exists. Important is that the spacing between the line is only about 18 µm instead of the 25 µm which was simulated. CHAPTER 3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 28 Figure 3.14: The top and a bottom view of the Ruwel multilayer balun. The size of the board is 13.4 mm x 11.8 mm. CHAPTER 3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY Version line length [mm] A1 46.62 A1m 46.62 B1 46.62 B1m 46.62 C1 46.62 C1m 46.62 D1 46.62 D1m 46.62 E1 46.62 E1m 46.62 F1 46.62 F1m 46.62 G1 46.62 G1m 46.62 A2 44.3 A2m 44.3 B2 44.3 B2m 44.3 C2 44.3 C2m 44.3 D2 44.3 D2m 44.3 E2 44.3 E2m 44.3 F2 44.3 F2m 44.3 G2 44.3 G2m 44.3 line width [µm] 300 300 350 350 400 400 460 460 500 500 550 550 600 600 300 300 350 350 400 400 460 460 500 500 550 550 600 600 note with test pads with test pads with test pads result of simulation with test pads with test pads with test pads with test pads with test pads with test pads with test pads with test pads with test pads with test pads with test pads Table 3.3: Different versions of the Ruwel balun 29 CHAPTER 3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 500 um 100 um 30 0 0 Figure 3.15: The profile of the Ruwel multilayer balun - version B1. The height of the board is 1.6 mm and the line width is 350 µm. A small lateral off-set of the layers is observed. The spacing between the line is only about 18 µm instead of 25 µm which was simulated. Chapter 4 Experimental results 4.1 S-parameter characterization of the balun For S-parameter measurements specific multilayer baluns with pads for measurements are produced. Fig. 4.1 shows the details. This results in a 3 port single ended measurement, which can be converted into mixed mode S-parameter with the equations 3.1 to 3.9. To illustrate the simulation and measurement results in a smith chart, a transformation of the 3-port S-parameter to a 2-port single ended S-parameter characterization is necessary. Fig. 4.2 shows the schematic diagram for this transformation, which is conformed with the equations 3.1 to 3.9. In Fig. 4.3 the simulation and the measurement results of Ruwel multilayer balun version D1 is shown in a smith chart. All ports are normalized to 50 Ω. It shows that the fundamental wave of S22 is close to the desired 6 Ω. For these dimensions the balun should transform the 6 Ω balanced input into a 50 Ω unbalanced output. For a good PAE of the power amplifier/balun system it is necessary that the second order harmonic is close to the short circuit point and the third order harmonic is close to the open circuit point. The simulation shows that with this design, the requirements for higher order harmonics can not be achieved. For this, additional arrangements are necessary. Fig. 4.4 compares the simulation and measurement results of all produced versions of the Ruwel multilayer balun. In the smith chart only the fundamental wave is illustrated. It shows that version D1 and D2 are close to the simulation result. Also a phase offset appears. We determined two reasons for this divergence. The first reason is that the thickness of the high quality layer is about 18 µm after pressing, whereas the simulation used a thickness of 25 µm. This results in a shift of the characteristic impedance and modifies the transformation properties of the λ/4 - coupler. The consequence of this is a mismatch of impedance. Secondly ²ef f , which is calculated from the simulation program, is too small. The reason 31 CHAPTER 4. EXPERIMENTAL RESULTS GND Signal GND 32 GND Signal GND GND Signal GND Figure 4.1: For S-parameter measurements specific multilayer baluns with pads for measurements are produced. The picture shows the position of the three measurement pins (each with GND-Signal-GND, 200 µm pitch) for the 3-port single ended S-parameter characterization. 2 T= 1/ 2 : 1 50 Ohm 50 Ohm 1 Balun 3 T= -1/ 2 : 1 Figure 4.2: Schematic diagram to transform the 3-port S-parameter to a 2port single ended S-parameter for illustrating in a smith chart. T = turns ratio (T1/T2). CHAPTER 4. EXPERIMENTAL RESULTS 33 +j0.5 +j2.0 Ruwel D1 Simulation and Measurement 5.0 2.0 1.0 0.5 0.2 0 S22 Simulation fo S22 Simulation 2 fo S22 Simulation 3 fo S22 Measurement fo S22 Measurement 2 fo S22 Measurement 3 fo 0 -j0.5 -j2.0 Figure 4.3: Comparison of simulation and measurement results of the Ruwel multilayer balun version D1. for this is that the details of the real buildup is difficult to transfer in the used simulation program. Both upper reasons add to the detected divergences. Now we consider the mixed mode S-parameter. In Fig. 4.5 simulation and measurement results of the differential mode to single ended mode transmission Sds21 are illustrated in case of the Ruwel D1 version and for operating conditions (50 Ω single ended port, 2x 6 Ω balanced port). In comparison to the simulation the insertion loss of the measurement result is greater. But the important factor is the frequency shift of the transmission maximum, which is now about 700 MHz. Fig. 4.6 confirms this fact. In this figure simulation and measurement results of the differential mode reflection Sdd22 are compared at operating conditions. The reflection minimum is also frequency shifted to about 700 MHz. These frequency CHAPTER 4. EXPERIMENTAL RESULTS 34 +j0.5 0.0 0.5 0.2 +j0.2 1.0 Ruwel D1 simulation Ruwel A1 measurement Ruwel B1 measurement Ruwel C1 measurement Ruwel D1 measurement Ruwel E1 measurement Ruwel F1 measurement Ruwel G1 measurement Ruwel A2 measurement Ruwel B2 measurement Ruwel C2 measurement Ruwel D2 measurement Ruwel E2 measurement Ruwel F2 measurement Ruwel G2 measurement -j0.2 Figure 4.4: Comparison of the simulation and the measurement results of all produced Ruwel versions. The results are shown from 800 MHz to 1000 MHz. shifts are also a result of the two reasons manifested before. CHAPTER 4. EXPERIMENTAL RESULTS 35 0.0 -0.5 -1.0 dB(Sds21) -1.5 -2.0 -2.5 -3.0 db(Sds21) - Simulation db(Sds21) - Measurement -3.5 -4.0 0.6 0.7 0.8 0.9 1.0 1.1 1.2 Frequency [GHz] Figure 4.5: Ruwel D1 - simulation and measurement of the differential mode to single ended mode transmission Sds21 . 4.2 Power amplifier module Next, the complete power amplifier module (power amplifier and balun) is considered. To characterize the balun the well known power amplifier PA2SA [see chapter 2] is used. It is mounted and bonded on the top side of the multilayer. The multilayer is soldered on a testboard. The assembled testboard carrying the PA-Module is shown in Fig. 4.7 and in Fig. 4.8. For blocking, small capacitors are soldered directly on the multilayer and large tantal capacitors are soldered on the testboard. The setup for the following measurements is illustrated in [Bakalski 01]. The first measurement is output power versus frequency, which is illustrated in Fig. 4.9. The supply voltage for the driver stage and the power stage is 3.5 V. As well as in previous measurements it also shows a frequency shift of output power maximum to 700 MHz. In the specifications for GSM a maximum output power of 35 dBm and 50 % PAE at least is required. In this case the maximum output power of CHAPTER 4. EXPERIMENTAL RESULTS 36 0 dB(Sdd22) - Simulation dB(Sdd22) - Measurement -5 dB(Sdd22) -10 -15 -20 -25 -30 -35 0.6 0.7 0.8 0.9 1.0 1.1 1.2 Frequency [GHz] Figure 4.6: Ruwel D1 - simulation and measurement of the differential mode reflection Sdd22 . 34 dBm is achieved by the Ruwel D2 module at 720 MHz. In comparison to the D2 version, the maximum output power of version D1 is about 0.5 dB greater and about 30 MHz closer to the desired 900 MHz. The line length of version D2 is about 5 % less than in version D1. In comparison to the reference balun of chapter 2 (Fig. 2.8), in which an output power of 35 dBm is achieved at 3.5 V, the Pout of the multilayer balun is 1 dB less. Fig. 4.10 and Fig. 4.11 show the power transfer characteristic and the PAE versus input power at 700 MHz. The supply voltage is 3.5 V; respectively 4V. The figures show that the different versions have similar performances and confirm previous measurement results. The D2 version achieves 35 dBm and 43 % PAE at 4 V. The reason for the frequency shift is the same as in the section before. A further reason for the bad performance of the overall module is that the power amplifier is optimized for 900 MHz. A comparison with the semi-rigid line balun of chapter 2 shows Tab. 4.1, which CHAPTER 4. EXPERIMENTAL RESULTS VCC Driver Stage C2 NC C3 19.08.04 DB VCC Power down Driver Stage 37 RFin C1 RUWEL - FR4 h = 0.46 mm er = 4.5 C0=C1=1-2nF C2-C4=4.7uF Tantal RFout C0 C4 VCC output stage PB Figure 4.7: The multilayer balun is soldered on the testboard. The size of the testboard is 30 mm x 30 mm. characterizes that the output power of the multilayer balun is 1 dB less than the output power of the other balun. The power added efficiency is about 44 % in case of the multilayer balun, whereas with the semi-rigid line balun a PAE of 57 % is achieved. CHAPTER 4. EXPERIMENTAL RESULTS 38 Figure 4.8: Picture of the assembled test buildup. Size: 30 mm x 30 mm supply voltage 3.5 V 4V Semi-rigid line balun at 900 MHz PAE Pout 57 % 35 dBm 57 % 36 dBm Multilayer balun D2 at 700 MHz PAE Pout 44 % 34 dBm 43 % 35 dBm Table 4.1: Comparison of the multilayer balun (Fig. 4.8) and the semi-rigid line balun (Fig. 2.6) [Heinz 99]. Both measurements work with Pin = 10 dBm. CHAPTER 4. EXPERIMENTAL RESULTS 39 34 Output Power [dBm] 33 32 31 30 29 Ruwel D1 Ruwel C1 Ruwel D2 28 27 0.6 0.7 0.8 0.9 1.0 Frequency [GHz] Figure 4.9: The maximum output power of the modul with the power amplifier PA2SA is achieved at 700 MHz. The supply voltage is 3.5 V for the driver and the power stage. Pin = 10 dBm CHAPTER 4. EXPERIMENTAL RESULTS 40 45 Output Power [dBm] / PAE [%] 40 35 30 25 20 15 Pout Ruwel D1 PAE Ruwel D1 Pout Ruwel C1 PAE Ruwel C1 Pout Ruwel D2 PAE Ruwel D2 10 5 0 -40 -30 -20 -10 0 10 Input Power [dBm] Figure 4.10: Power transfer characteristic of the PA-module at 700 MHz. The supply voltage is 3.5 V. 45 Output Power [dBm] / PAE [%] 40 35 30 25 20 15 Pout Ruwel D1 PAE Ruwel D1 Pout Ruwel C1 PAE Ruwel C1 Pout Ruwel D2 PAE Ruwel D2 10 5 0 -40 -30 -20 -10 0 10 Input Power [dBm] Figure 4.11: Power transfer characteristic of the PA-module at 700 MHz. The supply voltage is 4 V. Conclusion In this thesis a new multilayer balun for 900 MHz has been developed and evaluated. It consists of two λ/4 - couplers, which are implemented as broadside coupled striplines. For the important layer between the striplines, the new thin high quality substrate LCP by Rogers is used. S-parameter measurements for the fundamental wave show that the balun transforms the 6 Ω balanced input into a 50 Ω unbalanced output. For a good PAE of the power amplifier/balun system, it would be necessary that the second order harmonic is close to the short circuit point and the third order harmonic is close to the open circuit point, which could not be achieved with this design. The measurement result of the transmission coefficient Sds21 shows that the frequency of the transmission maximum is shifted to about 700 MHz. For the PAE and output power measurements, the well known power amplifier PA2SA, which is optimized for 900 MHz, was used. With this amplifier/balun module an output power of 34 dBm and a PAE of 44 % was achieved at 700 MHz. In comparison, the reference balun of chapter 2 achieves an output power of 35 dBm and a PAE of 57 % at 900 MHz. We determined two reasons for this divergence. The first reason is that the thickness of the high quality layer is about 18 µm after pressing, whereas the simulation used a thickness of 25 µm. These results in a shift of the characteristic impedance and modifies the transformation properties of the λ/4 - coupler. The consequence of this is a mismatch of impedance. Secondly ²ef f , which is calculated from the simulation program, is too small. The reason for this is that the details of the real buildup is difficult to transfer in the used simulation program. Both upper reasons add to the detected divergences. If a redesign is done, the simulation model should be adapted to reality better. Then, the thickness of the high quality layer should be 18 µm, the buildup should be better modeled so that the calculated ²ef f is correct and the copper lines should be none-ideal. The appendix shows that the ohmic losses are not negligible. It should be considered if the program ADS/Momentum is the right tool for this job. Also the influence of process tolerances should be analyzed. One further goal is to minimize the whole design. This is possible by folding the lines in a better way. The size is proportional to the spacing between the lines (smaller spacing ⇒ smaller line width ⇒ smaller overall size). In conflict with this 41 CHAPTER 4. EXPERIMENTAL RESULTS 42 goal are the ohmic losses, which are growing if the copper area will be smaller. Therefore a compromise between minimizing the module and ohmic losses has to made. Appendix A Losses of the multilayer balun The different forms of losses which appear in the multilayer balun will be considered her. The losses are divided into: • the dielectric loss • the ohmic losses – DC loss – Rf loss A.1 The dielectric loss The simulation in chapter 3.3 with ideal (lossless) lines shows the dielectric losses of the multilayer balun. In Fig. 3.10 these results are illustrated. A.2 The ohmic losses The ohmic losses divide into Rf and DC losses. Under the assumption of P AE = 50 %, Pin = 10 dBm (10 mW ), Pout = 35 dBm (3.16 W ) and the line length of the balun of l = 46.62 mm we determine the ohmic losses as follows: A.2.1 DC loss The assuming DC current is IDC = 2 A, which divides symmetrical to 1 A per brace. The area of current is ADC = 8.28 · 10−3 mm2 . So the impedance results in 43 CHAPTER A. LOSSES OF THE MULTILAYER BALUN RDC = 44 %Cu · l = 0.097 Ω, ADC (A.1) and the power loss per brace results in UDC = IDC · RDC = 0.097 V. A.2.2 (A.2) Rf loss R2 = 50 W RFout RRf= 0.324 W Rrf= 0.324 W Rrf= 0.324 W Rrf= 0.324 W VCC RFin- RFin+ R1 = 6 W R1 = 6 W Figure A.1: Schematic diagram for calculate the Rf loss. Fig. A.1 shows the schematic diagram to calculate the Rf loss. The assuming Rf √ current is IRf = 2 A · P AE = 1.41 A, which divides symmetrical to 0.707 A per brace. At 900 M Hz the skin depth is about 2.6 µm and the area of current is ARf = 2.5 · 10−3 mm2 , which is illustrated in Fig. A.2. So, the impedance results in RRf = %Cu · l = 0.324 Ω, ARf (A.3) and the power loss per brace results in URf = IRf · RRf = 0.229 V. (A.4) CHAPTER A. LOSSES OF THE MULTILAYER BALUN 45 18 mm Area of skin depth: ARf ~ 2,5 10-3 mm2 Skin depth for 900 Mhz: Conductor 2.6 mm 460 mm Figure A.2: The skin depth of the conductor at 900 MHz is 2.6 µm. The line length is 0.046 m. Appendix B Alternative Implementations Simultaneous to the development of the Ruwel balun (FR4 + Rogers LCP substrate), other implementations have been realized. The following comments will give a short overview about these developments. The implementations use the same circuit like the Ruwel balun. However, for the substrate layers between the striplines here Speedboard C by Gore, and the Rogers 4350 is used for the other substrate layers. Produced independently by three different enterprises (Aspocomp, Optiprint and R&D) an identical layout was realized. In Fig. B.1 the buildup, which was used in the process, is shown. In contrast to the Ruwel design the stack is unsymmetrical. In Fig. B.2, Fig. B.3 and Fig. B.4 the S-parameter measurements are presented. They show that the fundamental wave of the multilayer balun by R&D is close to the desired 6 Ω. Fig. B.5 and Fig. B.6 illustrate the mixed mode S-parameter measurement results of all three implementations. They show that the transmission maximum of Sds21 is close to 900 MHz. In comparison to the Ruwel balun, here the insertion loss is greater. The modules produced by Aspocomp and R&D have better performances than the one which was produced by Optiprint. 46 10 mils Ro4350 10 mils Ro4350 Er=3.48, tan d= 0.005 10 mils Ro4350 Er=3.48, tan d= 0.005 10 mils Ro4350 2.2 mils Speedboard C Metal 9 (Signal) 55um (can be omited if no empty catch pads are required) Metal 2 (GND Plane) Metal 10 (Empty Catch Pads) Metal 6 (Coupled Lines) Metal 7 (Coupled Lines) (can be omited if no empty catch pads are required) Metal 2 (GND Plane) Metal 10 (Empty Catch Pads) Metal 3 (Coupled Lines) Metal 4 (Coupled Lines) (can be omited if no empty catch pads are required) Metal 2 (GND Plane) Metal 10 (Empty Catch Pads) Metal 1 (Signal) 55um Epoxy Glue Bond Wire Design rules used in the layout: min 150um metal to metal distance for Metal1, min 200um for the other layers, min 150um annual ring for the catch pads 0.21mm (before plating) 2.2 Er=3.48, tan d= 0.005 2.2 mils Speedboard C (not critical, can be other type as well) 2.2 mils Speedboard C 10 mils Ro4350 Er=2.6, tan d=0.0036 Er=3.48, tan d= 0.005 2.2 mils Speedboard C (not critical, can be other type as well) 2.2 mils Speedboard C 10 mils Ro4350 Er=2.6, tan d=0.0036 Er=3.48, tan d= 0.005 2.2 mils Speedboard C (not critical, can be other type as well) Er=3.48, tan d= 0.005 Si IC 1+ - 0.2 Via 1 Project: GSM PA - Aspocomp, R&D and Optiprint Process: Metalization: ½ oz. Copper Foil Finish: Metal1 - Gold plating APPENDIX B. ALTERNATIVE IMPLEMENTATIONS 47 Figure B.1: Alternative multilayer buildups with Gores Speedboard C from Aspocomp, R&D and Optiprint. APPENDIX B. ALTERNATIVE IMPLEMENTATIONS 48 +j1.0 +j0.5 +j2.0 Aspocomp D1 Measurement +j5.0 5.0 2.0 1.0 0.5 0.0 0.2 +j0.2 S22 Measurement fo S22 Measurement 2*fo S22 Measurement 3*fo -j0.2 -j0.5 -j5.0 -j2.0 -j1.0 Figure B.2: Smith Chart from Aspocomp version C1. APPENDIX B. ALTERNATIVE IMPLEMENTATIONS 49 +j1.0 +j2.0 +j0.5 Optiprint D1 Measurement +j5.0 5.0 2.0 1.0 0.0 0.5 0.2 +j0.2 S22 Measurement fo S22 Measurement 2.fo -j0.2 -j5.0 S22 Measurement 3 .fo -j2.0 -j0.5 -j1.0 Figure B.3: Smith Chart from Optiprint version D1. APPENDIX B. ALTERNATIVE IMPLEMENTATIONS 50 +j1.0 +j0.5 +j2.0 R&D D1 Measurement +j0.2 5.0 2.0 1.0 0.0 0.5 0.2 +j5.0 S22 Measurement fo S22 Measurement 2.fo S22 Measurement 3.fo -j0.2 -j0.5 -j5.0 -j2.0 -j1.0 Figure B.4: Smith Chart from R&D version D1. APPENDIX B. ALTERNATIVE IMPLEMENTATIONS 51 -0.5 -1.0 dB(Sds21) -1.5 -2.0 -2.5 -3.0 db(Sds21) Aspocomp C1 db(Sds21) Optiprint D1 db(Sds21) R&D D1 -3.5 -4.0 0.6 0.7 0.8 0.9 1.0 1.1 1.2 Frequency [GHz] Figure B.5: Differential mode to single ended mode transmission Sds21 versus frequency of the different implementations. -4 -6 dB(Sdd22) -8 -10 -12 -14 dB(Sdd22) Aspocomp C1 dB(Sdd22) Optiprint D1 dB(Sdd22) R&D D1 -16 -18 0.6 0.7 0.8 0.9 1.0 1.1 1.2 Frequency [GHz] Figure B.6: Differential mode reflection Sdd22 versus frequency of the different implementations. Acknowledgements The work presented was supported by INFINEON Technologies AG, Corporate Research, Department for High Frequency Circuits (CPR HF), Munich. My gratitude goes to my colleague Dr. Werner Simb¨ urger for the initial ideas leading to this paper. I would also like to thank Dr. Winfried Bakalski and DI Nikolay Ilkov for their assistance during the whole development of this thesis. Special thanks go to Prof. Arpad L. Scholtz who supported me in the final stages of my studies. I would like to take this opportunity to thank my parents who helped me in any situation during my studies. 53 Bibliography [Agilent 97] Agilent, Balanced Device Characterization, Agilent Technologies, 1997. [Agilent 01] Agilent, Mixed Mode S-Parameters and Multiport Measurements, Agilent Technologies, 2001. [Bakalski 01] Winfried Bakalski, “Integrated 2.45 Ghz Power Amplifer”, Master’s thesis, Technical University of Vienna, September 2001. [Cheung, D.T. 98] Cheung, D.T.S., Long, J.R., Hadaway, R.A., and Harame, D.L., “Monolithic transformers for silicon rf ic design”, in 1998 Bipolar/BiCMOS Circuits and Technology Meeting, pp. 105–108, Minneapolis, 27-29 Sept. 1998. IEEE. [Chiba 83] K. Chiba and N. Kanmuri, “GaAs FET power amplifier modul with high efficiency”, Elecronics Letters, vol. 19, pp. 1025–1026, November 1983. [Dietsche 93] S. Dietsche, C. Duvanaud, G. Pataut, and J. Obregon, “Design of high power-added efficiency FET amplifiers operating with very low drain bias voltage for use in mobile telephones at 1.7 GHz”, in European Microwave Conference, pp. 252–254, 1993. [Duvanaud 93] C. Duvanaud, S. Dietsche, P. Pataut, and J. Obregon, “Highefficient class F GaAs FET amplifiers operating with very low bias voltages for use in mobile telephones at 1.75 GHz”, IEEE Microwave and Guided Wave Letters, vol. 3, pp. 268–270, August 1993. [El-Hamamsy 94] S. A. El-Hamamsy, “Design of High-Efficiency RF Class-D Power Amplifier”, IEEE Transactions on Power Electronics, vol. 9, pp. 297–308, May 1994. [Gonzales 84] G. Gonzales, Microwave Transistor Amplifiers Analysis and Design, Prentice Hall, Englewood Cliffs, NJ 07632, 1984. 54 [Gore 02] Gore, “Data sheet of Speedboard C High Performance Prepeg”, 2002. [Heinz 99] Alexander Heinz, “Anpaßnetzwerke f¨ ur monolithisch integrierte HF-Leistungsverst¨arker f¨ ur den Mobilfunk”, Master’s thesis, Technical University of Vienna, January 1999. [Ingruber 96] B. Ingruber, W. Pritzl, and G. Magerl, “High efficiency harmonic control amplifier”, Technical report, Department of Communication and Radio-Frequency Engineering, Vienna University of Technology, Gusshausstrasse 25/389, A-1040 Vienna, Austria, 1996. [Jochen 95] Peter Jochen, “Die neue c-klasse: Schalterbetrieb von transistoren in senderendstufen mit lc-kreisen”, ELRAD, vol. 12, pp. 80–85, 1995. [Kazimierczuk 83] M. K. Kazimierczuk, “Effects of the Collector Current Fall Time on the Class-E Tuned Power Amplifier”, IEEE Journal of Solid-State Circuits, vol. SC-18, pp. 181–193, April 1983. [Kazimierczuk 86] M. K. Kazimierczuk, “Class-E Tuned Power Amplifier with Nonsinusoidal Output Voltage”, IEEE Journal of Solid-State Circuits, vol. SC-21, pp. 575–581, August 1986. [Kazimierczuk 87] M. K. Kazimierczuk and K. Putczko, “Exact analysis of ClassE tuned power amplifier at any Q and switch duty cycle”, IEEE Trans. Circ. Syst., vol. CAS-34, pp. 149–159, February 1987. [Klose, H. 93] Klose, H., Lachner, H., Sch¨on, K., Mahnkopf, R., Malek, K., Kerber, M., Braun, H., v. Felde, A., Popp, J., Cohrs, O., Bertagnolli, E., and Sehrig, P., “B6hf: A 0.8 micron 25ghz/25ps bipolar technology for ”mobile radio” and ”ultra fast data link” ic products”, in IEEE Bipolar Circuits and Technology Meeting, pp. 125–127. IEEE, 1993. [Koch 89] M. J. Koch and R. E. Fisher, “A high efficiency 835MHz linear power amplifier for digital cellular telephony”, in IEEE Veh. Technol. Conf. Proc., pp. 17–18, 1989. [Lohrmann 66] D. R. Lohrmann, “Amplifier has 85% efficiency while providing up to 10 watts power over a wide frequency band”, Electronic Design, vol. 14, pp. 38–43, March 1, 1966. [Long 95] J. R. Long and M. A. Copeland, “A 1.9 ghz low-voltage silicon bipolar receiver front-end for wireless personal communications systems”, IEEE of Solid-State Circuits, vol. 30, pp. 1438–1448, Dec 1995. [Mader 95] T. B. Mader and Z. B. Popovic, “The transmission-line high efficiency class-E amplifier”, IEEE Microwave and Guided Wave Letters, vol. 5, pp. 290–292, September 1995. [Maxim 01] Maxim, “Single-ended and differential s-parameter”, in HFAN5.1.0. Maxim Integrated Products, 2001. [Mitzlaff 88] T. B. Mitzlaff, “High efficiency RF power amplifier”, United States Patent, January 1988. [Molnar 84] B. Molnar, “Basic limitations of waveforms achievable in singleended switching-mode (Class E) power amplifiers”, IEEE Journal of Solid-State Circuits, vol. SC-19, pp. 144–146, February 1984. [Mongia, R. 99] Mongia, R., Bahl, I., and Bhartia, P., RF and Microwave Coupled-Line Circuits, Artech House, Norwood,MA 02062, first edition, 1999. [Motorola 94] Motorola, RF Device Data Book DL110/D REV 5, Motorola, 1994. [Murai 93] S. Murai, T. Sawai, T. Yamaguchi, and Y. Harada, “A high power-added efficiency GaAs power MESFET and MMIC operating at very low drain bias for use in Personal Handy Phones”, IEICE Trans. Electron., vol. E76-C, pp. 901–906, February 1993. [Nishiki 87] S. Nishiki and T. Nojima, “Harmonic reaction amplifier - a novel high-efficieny and high-power microwave amplifier”, in IEEE MTT-S Digest, International Microwave Symposium Digest, pp. 963–966. IEEE, 1987. [Raab 75] F. H. Raab, “High efficiency amplification techniques”, IEEE Circuits Syst. Newslett., vol. 7, pp. 3–11, December 1975. [Raab 77] F. H. Raab, “Idealized operation of the Class E tuned power amplifier”, IEEE Trans. Circ. Syst., vol. CAS-24, pp. 725–735, December 1977. [Raab 78] F. H. Raab and N. O. Sokal, “Transistor power losses in the Class E tuned power amplifiers”, IEEE Journal of Solid-State Circuits, vol. SC-13, pp. 912–914, December 1978. [Rogers 03] Rogers, “Product summary, R/flex 3000 LCP product family”, May 2003. [Simb¨ urger 99] W. Simb¨ urger, “Monolithic integration of power amplifiers in silicon-based technologies”, in EUMW-Workshop, 1999, ”Silicon and Sige Technologies and Circuits, 1999. [Simb¨ urger, 99,a] Simb¨ urger, W., Wohlmuth, H.D., and Weger, P., “A monolithic 3.7w silicon power amplifier with 59% pae at 0.9ghz”, in IEEE International Solid-State Circuits Conference, pp. 230– 231, San Francisco, February 1999. IEEE. [Simb¨ urger, 99,b] Simb¨ urger, W., Wohlmuth, H.D., Weger, P., and Heinz, A., “A monolithic transformer coupled 5w silicon power amplifier with 59% pae at 0.9ghz”, IEEE Journal of Solid-State Circuits, Special Issue on ISSCC’99, vol. , t.b.p. December 1999. [Skyworks 03] Skyworks, “Product summary, SKY77324”, September 2003. [Snider 67] D. M. Snider, “A theoretical analysis and experimental confirmation of the optimally loaded and overdriven RF power amplifier”, IEEE Trans. Electron Devices, vol. ED-14, pp. 851–857, December 1967. [Sokal 77] N. O. Sokal and F. H. Raab, “Harmonic output of class E RF power amplifiers and load coupling network design”, IEEE Journal of Solid-State Circuits, vol. SC-12, pp. 86–88, February 1977. [Sokal, N. O 75] Sokal, N. O. and Sokal, A. D., “Class e - a new class of high-efficiency tuned single-ended switching power amplifiers”, IEEE Journal of Solid-State Circuits, vol. 10, pp. 168–176, June 1975. [Stengel 99] Bob Stengel and Bruce Thompson, “Neutralized differential amplifiers using mixed-mode s-parameter”, in IFTU-99. Motorola Labs, 1999. [Toyoda 93] S. Toyoda, “High efficieny single and push-pull power amplifiers”, in IEEE MTT-S Digest, International Microwave Symposium Digest, pp. 277–280. IEEE, 1993. [Tyler 58] V. J. Tyler, “A new high efficiency high power amplifier”, Marconi Rev., vol. 21, pp. 96–109, 1958. [Wadell 91] Brian C. Wadell, Transmission line design handbook, Artech House, Boston - London, 1991. [Zhou, J.J. 98] Zhou, J.J. and Allstot, D.J., “Monolithic transformers and their application in a differential cmos rf low-noise amplifier”, IEEE Journal of Solid-State Circuits, vol. 33, pp. 2020–7, 1998.