Transcript
Thursday, December 1 Scaife Hall Auditorium Room 125 at 4:30 p.m. Refreshments at 4:00 p.m.
Linda Milor Associate Professor of ECE Georgia Tech Dr. Milor has worked in the fields of yield analysis, reliability, and testing since the mid-1980s. She has over 100 publications in these areas. She has a Ph.D. from U.C. Berkeley in Electrical Engineering. She is currently an Associate Professor of Electrical and Computer Engineering at Georgia Tech. She has worked both in academia and industry. In academia she received the prestigious NSF Career Award and the 2004 Best Paper in the IEEE Transactions on Semiconductor Manufacturing for M. Orshansky, L. Milor, and C. Hu, "Characterization of Spatial Intra-Field Gate CD Variability, Its Impact on Circuit Performance, and Spatial Mask-Level Correction," published in February 2004. She received a best paper award from the International Conference on Computer Design in 2009 for F. Ahmed and L. Milor, "Reliable Cache Design with Detection of Gate Oxide Breakdown Using BIST." She received the best interactive presentation award from Design and Test in Europe in 2010 for M. Bashir and L. Milor, "Towards a Chip Level Reliability Simulator for Copper/Low-K Backend Processes." In industry, she worked as a Product Engineering Manager at Advanced Micro Devices (AMD), where she was responsible for yield and wafer quality.
ECE Seminar Hosts Gabriela Hug
[email protected] Lujo Bauer
[email protected] Soummya Kar
[email protected] Jeff Weldon
[email protected]
Digital IC Wearout Modeling, Detection, and Compensation Technology scaling to processes that are approaching fundamental structural and material limitations, with transistors having fewer than 20 atoms in the channel (projected for 2020), has resulted in exponential increases in variability in circuit performance, power, and leakage, due to the inability to control the exact placement of the atoms in the device. However, the initial placement of atoms is not the only source of variation. Another source of variation relates to reliability, where circuits degrade parametrically in the field, due to wearout. Wearout is exacerbated with technology scaling because it is highly sensitive to the supply voltage, which is not scaled proportionally, resulting in increased stress of components together with higher temperatures. Hence, products produced with the newest technologies are much more vulnerable to parametric degradation in the field. Given the increase in parametric variability due to wearout, designers need to be able to design in the presence of variation due to wearout, and circuits need to be able to detect and correct parametric degradation in the field. This talk will focus on our efforts to estimate the lifetime of chips based on test structure data on low-k dielectric breakdown. Methods to detect wearout due to gate oxide breakdown and negative bias temperature instability in SRAMs will also be discussed. We conclude by presenting a few areas for future work relating to wearout modeling, detection, and compensation.
