Transcript
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Compal confidential Low Cost Los Angeles 10AL+
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NBWAE LA-5831P Schematics Document Mobile AMD S1G2 RS780MN & RS780MC / SB700 2009-08-12 Rev. 1.0
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Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc. Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
1
of
44
A
B
Compal Confidential
C
Fan Control
Thermal Sensor ADM1032ARMZ
Dual Channel
uFCPGA-638 Package
File Name : LA-5831P
E
Memory BUS(DDRII)
AMD S1G2 CPU
page 5
Model Name : NBWAE
D
Clock Generator
page 7
SLG8SP626
page 16
1.8V DDRII 667/800MHZ
page 5,6,7.8
200pin DDRII-SO-DIMM X2
Hyper Transport Link 2.6GHz 16X16
1
CRT
page 9,10
BANK 0, 1, 2, 3
1
ATI
page 17
RTL8103E LAN 10/100M
RS780MN RS780MC
LCD Conn.
page 18
PCIe port 3
RJ45
page 26
page 26
PCIe 4x 1.5V 2.5GHz(250MB/s)
PCIe Mini Card WLAN HDMI Conn.
PCIe Port 2
PCIE-Express 4X
USB Port 8
page 19
page 27
page 11,12,13,14.15
2
2
A-Link Express II 4X PCI-E
USB/B Right
USB/B Left
USB port 0,1
USB port 2
page 25
USB
page 25
3IN1 Card Reader RTS5159-VDD
5V 480MHz
Int. Camera USB port 9 page 18
USB port 4
ATI
page 28
SB700
SATA port 1 5V 1.5GHz(150MB/s)
SATA port 3 5V 1.5GHz(150MB/s)
SATA HDD
page 25
SATA ODD
page 25
page 20,21,22,23,24 3
3
HD Audio
LPC BUS
3.3V 24.576MHz/48Mhz
3.3V 33 MHz
HDA Codec ALC272
MDC 1.5 Conn Debug Port page 31
ENE KB926D3
page 31
page 29
page 32
RTC CKT. page 20
RJ11
NBWAE Sub-boards Power On/Off CKT. page 33
DC/DC Interface CKT. 4
page 34
Power Circuit DC/DC
Touch Pad page 33
Power/B LS-4574P
page 31
SPI ROM page 31
page 31
MIC Conn page 30
page 30
page 30
page 30
SPK Conn page 30
4
33
page 25
page 35,36,37,38 39,40,41.42
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
AMP. TPA6017
Int. MIC Conn HP Conn
page 33
Cap Sensor/B LS-5822P page USB/B LS-5821P
Int.KBD
B
C
D
Block Diagram Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
2
of
44
5
4
3
2
DESIGN CURRENT 100mA
B+
DESIGN CURRENT 100mA
+3VL +5VL +5VALW
DESIGN CURRENT 5A
+5VS
Ipeak=5A, Imax=3.5A, Iocp min=7.9
1
SUSP#
N-CHANNEL SI4800BDY D
D
Ipeak=5A, Imax=3.5A, Iocp min=7.7
+3VALW
SUSP#
TPS51125RGER
N-CHANNEL
DESIGN CURRENT 5A
+3VS
SI4800BDY
UMA_ENVDD
P-CHANNEL AO-3413
DESIGN CURRENT 1.0A
+LCD_VDD
DESIGN CURRENT 2A
+1.5VS
DESIGN CURRENT 330mA
+3V_LAN
DESIGN CURRENT 500mA
+2.5VS
SUSP
LDO APL5331KAC WOL_EN#
P-CHANNEL AO-3413 C
C
LDO APL5508
POK
Ipeak=5A, Imax=3.5A, Iocp min=7.78
+1.2VALW
VLDT_EN DESIGN CURRENT 4.5A
N-CHANNEL
+1.2V_HT
IRF8113PBF
TPS51124RGER Ipeak=7A, Imax=4.9A, Iocp min=9.32
+NB_CORE (+1.1VS)
SUSP#
CPU_VCORE_ENABLE
Ipeak=18A, Imax=12.6A, Iocp min=30
B
Ipeak=18A, Imax=12.6A, Iocp min=30
ISL6265
DESIGN CURRENT 4A
+CPU_CORE0 +CPU_CORE1 +VDDNB
B
SYSON
Ipeak=8A, Imax=5.6A, Iocp min=8.87
+1.8V SUSP#
TPS51117RGYR
N-CHANNEL
DESIGN CURRENT 1A
+1.8VS
DESIGN CURRENT 2A
+0.9V
IRF8113PBF SYSON#
LDO APL5331KAC
A
A
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Power Map Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet 1
3
of
44
A
B
C
D
E
Voltage Rails O : ON
Platform
X : OFF
CPU S1G2 S1G2 S1G3 S1G3
PUMA@ TIGRIS@
1
NB RS780MC RS780MN RS880MC RS880M
SB SB700 SB700 SB710 SB710
+5VS
power plane
1
+3VS +2.5VS +1.8VS B+
+5VALW
+1.8V
+3VL
+3VALW
+0.9V
+5VL
State
+1.5VS +1.2V_HT
+1.2VALW
+RTCVCC
@ : just reserve , no build
+1.1VS
BTO (Build-To-Order)
+VDDNB
+3V_LAN
Option Table
+CPU_CORE_0 +CPU_CORE_1
Function Description
Modem (R)
HDMI (Y)
Explain
S0
O
O
O
O
S1
O
O
O
O
S3
O
O
O
X
S5 S4/AC
O
O
X
X
S5 S4/ Battery only
O
X
X
X
S5 S4/AC & Battery don't exist
X
X
X
X
BTO
MDC@
CAMERA & MIC
HDMI@
(X) CAMERA
MIC
CAM@
MIC@
2
2
SMBUS Control Table SOURCE
INVERTER
BATT
HDMI CEC
CPU THERMAL SENSOR
EC_SMB_CK1
SB700 SM Bus0 Address
3
SB700 SM Bus1 Address
Power
Device
HEX
Address
Power
Device
+3VS
DDR SO-DIMM 0
A0 H
1010 0000 b
+3VALW
WLAN/WIMAX
+3VS
DDR SO-DIMM 1
A4 H
1010 0100 b
+3VS
Clock Generator
D2 H
1101 0010 b
HEX
Address
EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2
RS780MN
I2C_DATA
RS780MC
DDC_CLK0
RS780MN
DDC_DATA0
RS780MC
DDC_CLK1
RS780MN
DDC_DATA1
RS780MC
Power +3VL
Device
HEX
Smart Battery
16 H
Address 0001 011X b
KB926 SM Bus2 Address Power +3VS
Device
HEX
Address
CPU_ADM1032-1
98 H
1001 100X b
SCL2
LCD DDC ROM
HDMI DDC ROM
NEW CARD
V
3
V
V
SB700
SDA1
WLAN
V
SB700
SDA0 SCL1
I / II
CLK GEN
V
KB926
I2C_CLK
SCL0
KB926 SM Bus1 Address
KB926
SODIMM
V V
SB700
SDA2 SCL3
SB700
SDA3
KB926 ESB Address 4
Power
Device
+3VL
Cap. Sensor
HEX
Address
4
Virtual I2C
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Notes List Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
4
of
44
A
B
+1.2V_HT
C
VLDT CAP.
D
E
Near CPU Socket
250 mil 1
2
PUMA@ C1 4.7U_0805_10V4Z
1
TIGRIS@ C1 10U_0805_10V6K
2
PUMA@ C2 4.7U_0805_10V4Z
1
TIGRIS@ C2 10U_0805_10V6K
2
1
C3 0.22U_0603_16V4Z
2
1
C4 0.22U_0603_16V4Z
2
1
C5 180P_0402_50V8J
2
C6 180P_0402_50V8J
1
1
<11> H_CADIP[0..15] <11> H_CADIN[0..15]
H_CADIP[0..15]
H_CADOP[0..15]
H_CADIN[0..15]
H_CADON[0..15]
+1.2V_HT
VLDT=500mA
2
< From NB >
3
H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15
H_CADOP[0..15]
<11>
H_CADON[0..15]
<11>
JCPUA D1 D2 D3 D4
E3 E2 E1 F1 G3 G2 G1 H1 J1 K1 L3 L2 L1 M1 N3 N2 E5 F5 F3 F4 G5 H5 H3 H4 K3 K4 L5 M5 M3 M4 N5 P5
<11> <11> <11> <11>
H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1
J3 J2 J5 K5
<11> <11> <11> <11>
H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1
N1 P1 P3 P4
VLDT_A0 VLDT_A1 VLDT_A2 VLDT_A3
HT LINK
L0_CADIN_H0 L0_CADIN_L0 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H15 L0_CADIN_L15
VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3
L0_CADOUT_H0 L0_CADOUT_L0 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H15 L0_CADOUT_L15
L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKIN_H1 L0_CLKIN_L1
L0_CLKOUT_H0 L0_CLKOUT_L0 L0_CLKOUT_H1 L0_CLKOUT_L1
L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLIN_H1 L0_CTLIN_L1
L0_CTLOUT_H0 L0_CTLOUT_L0 L0_CTLOUT_H1 L0_CTLOUT_L1
AE2 AE3 AE4 AE5
+VLDT_B
H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7 H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15
AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3
PUMA@ C7 2 4.7U_0805_10V4Z
1
< VLDT_A & VLDT_B : HyperTransport I/O ring power >
TIGRIS@ C7 10U_0805_10V6K
2
< To NB >
Y1 W1 Y4 Y3
H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1
<11> <11> <11> <11>
R2 R3 T5 R5
H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1
<11> <11> <11> <11>
3
@
6090022100G_B
< FAN Control Circuit : Vout = 1.6 x Vset > +5VS
1
1A
D1
< From EC ><32> EN_DFAN1
@
10U_0805_10V4Z
1SS355_SOD323-2
U6 1 2 3 4
2
D2
EN VIN VOUT VSET
GND GND GND GND
8 7 6 5
@
C9
@ BAS16_SOT23-3
1
1 2 3
1000P_0402_25V8J
4 5
1 2 3
R12
GND GND
10K_0402_5% 2
10U_0805_10V4Z
+3VS
JFAN @ +FAN1
1 1
C192
2
2
2
2
C183 1
1
+FAN1
ACES_85204-0300N
FAN_SPEED1 <32> 2
APL5607KI-TRG_SO8 4
1
4
Compal Secret Data
Security Classification 2009-02-12
Issued Date
< To EC >
C8 @ 0.01U_0402_25V7K
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc. AMD CPU S1G3 HT I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
5
of
44
A
B
C
D
E
< Processor DDR2 Memory Interface >
+1.8V
< DDR2 VREF is 0.5 ratio >
< PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH > DDR_A_CLK0
2
< From/To SO_DIMMB > 1
C10
C14
R1 DDR_A_CLK#0 2
1
1K_0402_1%
1.5P_0402_50V9C
DDR_B_CLK#0 2
1.5P_0402_50V9C
+MCH_REF
2
1
1
R2 1K_0402_1% 1
2
1
C12 0.1U_0402_16V7K
2
DDR_A_CLK1 C13
DDR_B_CLK1 1
1
C11
C15
1000P_0402_25V8J DDR_A_CLK#1 2
1.5P_0402_50V9C
DDR_B_CLK#1 2
+0.9V
1.5P_0402_50V9C
+0.9V JCPUB
Place them close to CPU within 1"
2
+1.8V
R4 1 R3 1
2 39.2_0402_1% 2 39.2_0402_1% T2
MEM_P MEM_N
<10> DDR_A_ODT0
VTT1 VTT2 VTT3 VTT4
AF10 AE10
MEMZP MEMZN
H16
PAD
< To SO_DIMMA > <10> DDR_A_ODT1
D10 C10 B10 AD10
DDR_A_ODT0 DDR_A_ODT1
T19 V22 U21 V19
< To SO_DIMMA > <10> DDR_CS1_DIMMA#
DDR_CS0_DIMMA# T20 DDR_CS1_DIMMA# U19 U20 V20
<10> DDR_CKE0_DIMMA
DDR_CKE0_DIMMA J22 DDR_CKE1_DIMMA J20
<10> DDR_CS0_DIMMA#
< To SO_DIMMA > <10> DDR_CKE1_DIMMA
<10> DDR_A_CLK0
< To SO_DIMMA > <10> DDR_A_CLK#0 <10> DDR_A_CLK1 <10> DDR_A_CLK#1
< To SO_DIMMA > <10> DDR_A_MA[15..0] 3
<10> DDR_A_BS#0
< To SO_DIMMA > <10> DDR_A_BS#1 <10> DDR_A_BS#2
< To SO_DIMMA >
<10> DDR_A_RAS# <10> DDR_A_CAS# <10> DDR_A_WE#
MEM:CMD/CTRL/CLK VTT5 VTT6 VTT7 VTT8 VTT9
RSVD_M1 MA0_ODT0 MA0_ODT1 MA1_ODT0 MA1_ODT1 MA0_CS_L0 MA0_CS_L1 MA1_CS_L0 MA1_CS_L1 MA_CKE0 MA_CKE1
VTT_SENSE MEMVREF RSVD_M2 MB0_ODT0 MB0_ODT1 MB1_ODT0 MB0_CS_L0 MB0_CS_L1 MB1_CS_L0 MB_CKE0 MB_CKE1
W10 AC10 AB10 AA10 A10
< VTT regulator voltage >
Y10
VTT_SENSE
W17
+MCH_REF
B18 W26 W23 Y26
DDR_B_ODT0 DDR_B_ODT1
V26 W25 U22
DDR_CS0_DIMMB# DDR_CS1_DIMMB#
J25 H26
DDR_CKE0_DIMMB DDR_CKE1_DIMMB
P22 R22 A17 A18 AF18 AF17 R26 R25
DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15
DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1
N19 N20 E16 F16 Y16 AA16 P19 P20
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15
N21 M20 N22 M19 M22 L20 M24 L21 L19 K22 R21 L22 K20 V24 K24 K19
MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15
MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15
P24 N24 P26 N23 N26 L23 N25 L24 M26 K26 T26 L26 L25 W24 J23 J24
DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2
R20 R23 J21
MA_BANK0 MA_BANK1 MA_BANK2
MB_BANK0 MB_BANK1 MB_BANK2
R24 U26 J26
DDR_B_BS#0 DDR_B_BS#1 DDR_B_BS#2
DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
R19 T22 T24
MA_RAS_L MA_CAS_L MA_WE_L
MB_RAS_L MB_CAS_L MB_WE_L
U25 U24 U23
DDR_B_RAS# DDR_B_CAS# DDR_B_WE#
MA_CLK_H0 MA_CLK_L0 MA_CLK_H1 MA_CLK_L1 MA_CLK_H2 MA_CLK_L2 MA_CLK_H3 MA_CLK_L3
MB_CLK_H0 MB_CLK_L0 MB_CLK_H1 MB_CLK_L1 MB_CLK_H2 MB_CLK_L2 MB_CLK_H3 MB_CLK_L3
JCPUC
<9> DDR_B_D[63..0]
DDR_B_CLK0 1
PAD
T1
PAD
T3
DDR_B_ODT0 <9> DDR_B_ODT1 <9>
< To SO_DIMMB >
DDR_CS0_DIMMB# <9> DDR_CS1_DIMMB# <9> <
To SO_DIMMB >
DDR_CKE0_DIMMB <9> DDR_CKE1_DIMMB <9> <
To SO_DIMMB >
DDR_B_CLK0 <9> DDR_B_CLK#0 <9> DDR_B_CLK1 <9> DDR_B_CLK#1 <9>
< To SO_DIMMB > <9> DDR_B_DM[7..0]
DDR_B_MA[15..0] <9>
< To SO_DIMMB >
DDR_B_BS#0 <9> DDR_B_BS#1 <9> DDR_B_BS#2 <9>
< To SO_DIMMB >
DDR_B_RAS# <9> DDR_B_CAS# <9> DDR_B_WE# <9>
< To SO_DIMMB >
< To SO_DIMMB >
<9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9>
DDR_B_DQS0 DDR_B_DQS#0 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS7 DDR_B_DQS#7
MEM:DATA DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23 G24 AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11 Y11 AE14 AF14 AF11 AD11
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
A12 B16 A22 E25 AB26 AE22 AC16 AD12
DDR_B_DQS0 DDR_B_DQS#0 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS7 DDR_B_DQS#7
C12 B12 D16 C16 A24 A23 F26 E26 AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12
< From/To SO_DIMMB >
MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63
MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8 MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63
MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7
MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7
MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7
MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7
6090022100G_B
G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24 J19 E21 E22 H20 H22 Y24 AB24 AB22 AA21 W22 W21 Y22 AA22 Y20 AA20 AA18 AB18 AB21 AD21 AD19 Y18 AD17 W16 W14 Y14 Y17 AB17 AB15 AD15 AB13 AD13 Y12 W11 AB14 AA14 AB12 AA12
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
E12 C15 E19 F24 AC24 Y19 AB16 Y13
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
G13 H13 G16 G15 C22 C21 G22 G21 AD23 AC23 AB19 AB20 Y15 W15 W12 W13
DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7
DDR_A_D[63..0]
<10>
< From/To SO_DIMMA >
1
2
DDR_A_DM[7..0]
<10>
< To SO_DIMMA >
3
DDR_A_DQS0 <10> DDR_A_DQS#0 <10> DDR_A_DQS1 <10> DDR_A_DQS#1 <10> DDR_A_DQS2 <10> DDR_A_DQS#2 <10> DDR_A_DQS3 <10> DDR_A_DQS#3 <10> DDR_A_DQS4 <10> DDR_A_DQS#4 <10> DDR_A_DQS5 <10> DDR_A_DQS#5 <10> DDR_A_DQS6 <10> DDR_A_DQS#6 <10> DDR_A_DQS7 <10> DDR_A_DQS#7 <10>
< From/To SO_DIMMA >
@
@
4
4
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc. AMD CPU S1G3 DDRII I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
6
of
44
A
B
C
D
E
JCPUD
< Close to CPU >
+CPU_CORE_0 1
2
R487 10_0402_5%
1
2
R486 10_0402_5%
PUMA@
1
1
2
R489 10_0402_5%
2
R488 10_0402_5%
F8 F9
CPU_CLKIN_SC_P CPU_CLKIN_SC_N
A9 A8
LDT_RST# H_PWRGD LDT_STOP# CPU_LDT_REQ_R#
B7 A7 F10 C6
CPU_VDD0_RUN_FB_L
Un-Mount R488 & R489 For Caspian
+CPU_CORE_1
+2.5VDDA CPU_VDD0_RUN_FB_H
< Sideband-Temperature Sensor Interface Clock & Data>
AF4 AF5 AE6
CPU_VDD1_RUN_FB_H < Sideband-Temperature Sensor Interface interrupt >
PUMA@
1
CPU_VDD1_RUN_FB_L
< Compensation Resistor to VSS > < Compensation Resistor to VLDT >
R13 R14
+1.2V_HT
2 44.2_0402_1% 2 44.2_0402_1%
1 1
<42> CPU_VDD0_RUN_FB_H <42> CPU_VDD0_RUN_FB_L
< 200-MHz PLL Reference Clock > 1
<16> CLK_CPU_BCLK
C20 2 3900P_0402_50V7K
<42> CPU_VDD1_RUN_FB_H <42> CPU_VDD1_RUN_FB_L
CPU_CLKIN_SC_P
1
< Debug ready >
T9 T10 T11 T12 T19
< JTAG debug port >
R8 169_0402_1% 2 <16> CLK_CPU_BCLK#
Address:100_1100
CPU_TEST21_SCANEN CPU_TEST20_SCANCLK2 CPU_TEST24_SCANCLK1
< Filtered PLL Supply Voltage > +2.5VS
+2.5VDDA
VDDA=300mA L1 1 2
2 FBM_L11_201209_300L_0805 1 C17
1 + C16 @ 100U_D2_10VM 2
1
C124 @ 0.1U_0402_16V7K
2
2
4.7U_0805_10V4Z
+2.5VDDA 1
2
1
C18 3300P_0402_50V7K
2
C19
2 R25 0_0402_5%
1
E9 E8
For EMI
H6 G6
CPU_VDDNB_RUN_FB_H CPU_VDDNB_RUN_FB_L
E10
CPU_DBREQ#
DBRDY TMS TCK TRST_L TDI
DBREQ_L TDO
TEST23
A3 A5 B3 B5 C1
RSVD1 RSVD2 RSVD3 RSVD4 RSVD5
2
CPU_SVC
2
R23 1 1K_0402_5%
CPU_SVD
PAD PAD
< Differential feedback for VDDIO > < VDDIO : DDR SDRAM I/O ring power supply> < Differential feedback for VDDNB >
< Debug request >
AE9
PAD T20
TEST17 TEST16 TEST15 TEST14
D7 E7 F7 C7
CPU_TEST17_BP3 CPU_TEST16_BP2
TEST7 TEST10
C3 K8
TEST8
C4
TEST29_H TEST29_L
C9 C8
RSVD10 RSVD9 RSVD8 RSVD7 RSVD6
T22 T21
CPU_VDDNB_RUN_FB_H <42>< Northbridge power supply > CPU_VDDNB_RUN_FB_L <42>
CPU_TEST28_H_PLLCHRZ_P CPU_TEST28_L_PLLCHRZ_N
TEST25_H TEST25_L
TEST9 TEST6
< Thermal diode cathode & anode >
J7 H8
TEST28_H TEST28_L
TEST18 TEST19
PAD PAD
T5 T6
PAD PAD
T7 T8
@
route as differential as short as possible testpoint under package
R32 1 300_0402_5% +1.2V_HT
CPU_TEST10_ANALOGOUT 2
CPU_TEST29_H_FBCLKOUT_P CPU_TEST29_L_FBCLKOUT_N
PAD PAD
T13 T14
2
H18 H19 AA7 D5 C5
@
6090022100G_B
0718 AMD --> 1K ohm
R22 1 1K_0402_5%
1
VDDNB_FB_H VDDNB_FB_L
C2 AA6
< Thermal Sensor Trip output > < HTC-active state indication or command >
+1.8V
THERMDC_CPU THERMDA_CPU
VDD1_FB_H VDD1_FB_L
TEST21 TEST20 TEST24 TEST22 TEST12 TEST27
< Serial VID Interface clock & data >
+1.8V sense no support
< Serial VID Interface clock & data > +1.8VS
AF6 CPU_THERMTRIP#_R AC7 CPU_PROCHOT#_1.8 R42 AA8 2 1 PUMA@ 300_0402_5%
W9 Y9
AB8 AF7 AE7 AE8 AC8 AF8
0.22U_0603_16V4Z
CPU_SVC <42> CPU_SVD <42>
VDDIO_FB_H VDDIO_FB_L
Y6 AB6
CPU_TEST25_H_BYPASSCLK_H CPU_TEST25_L_BYPASSCLK_L
CPU_SVC CPU_SVD
VDD0_FB_H VDD0_FB_L
CPU_VDD1_RUN_FB_H CPU_VDD1_RUN_FB_L
H10 G9
A6 A4
W7 W8
HT_REF0 HT_REF1
AD7
THERMTRIP_L PROCHOT_L MEMHOT_L
M11 W18
THERMDC THERMDA
F6 E6
G10 AA9 AC9 AD9 AF9
SVC SVD
SIC SID ALERT_L
CPU_VDD0_RUN_FB_H CPU_VDD0_RUN_FB_L
CPU_CLKIN_SC_N
Place close to CPU wihtin 1.5"
RESET_L PWROK LDTSTOP_L LDTREQ_L
R6 P6
PAD PAD PAD PAD PAD
KEY1 KEY2
CLKIN_H CLKIN_L
CPU_HTREF0 CPU_HTREF1
CPU_TEST23_TSTUPD
C21 2 3900P_0402_50V7K
1
VDDA1 VDDA2
< HDT Connector > JP3
< R41 Close to CPU > < R494 Close to CPU >
1 3 5 7 9 11 13 15 17 19 21 23
CPU_DBREQ#
+1.8VS
@
2
+1.8V T23 PAD R15
1
300_0402_5% LDT_RST#
1
3
+1.8V T24 PAD
LDT_RST# C22
2
220_0402_5% 220_0402_5% 220_0402_5% 220_0402_5%
R493 510_0402_5%
@
R965 2 510_0402_5%
1 <12,20> LDT_STOP#
CPU_TEST25_H_BYPASSCLK_H
1
@
R966 510_0402_5%
CPU_TEST25_L_BYPASSCLK_L
TIGRIS@ R492 1 2 510_0402_5%
2
LDT_STOP#
1
C23
C25
+1.8V
1
2
< To power circuitry>
R10 10K_0402_5%
@ 1
D12 2 CH751H-40PT_SOD323-2
@ 0.1U_0402_16V7K
2
0.01U_0402_25V7K 2
R5 300_0402_5%
< Thermal Sensor >
<36,38>
+3VS 1
Q3
E
CPU_THERMTRIP#_R
ENTRIP2
1
C
3
1
D16 2 CH751H-40PT_SOD323-2
< To SB710 ACPI block>
H_THERMTRIP# <21>
C26 0.1U_0402_16V7K
2
MMBT3904_NL_SOT23-3
1
2
1
THERMDA_CPU
2
THERMDC_CPU 2 C27 2200P_0402_50V7K
3 4
< noise filter cap >
R30
1
PUMA@
CPU_LDT_REQ#
1 1
C24 4
@ 330P_0402_50V7K
R967 2 0_0402_5%
Add R29 and R31 for Caspian CPU_LDT_REQ_R#
TIGRIS@ R968 2 1 300_0402_5% TIGRIS@ R969 1 2 300_0402_5%
CPU_TEST23_TSTUPD
2
R26 1 300_0402_5%
CPU_TEST21_SCANEN
1
R28 2 300_0402_5%
CPU_TEST24_SCANCLK1
+VDDNB
< To SB700 CPU block>
@ 1
R11 2 0_0402_5%
VDD D+
SDATA
D-
ALERT#
THERM#
GND
8
EC_SMB_CK2
7
EC_SMB_DA2
B
EC_SMB_DA2 <32>
6 5
2
R484 1 10_0402_5% CPU_VDDNB_RUN_FB_H
2
R485 1 10_0402_5% CPU_VDDNB_RUN_FB_L
Compal Secret Data 2009-02-12
Issued Date
4
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc. AMD CPU S1G3 CTRL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
H_PROCHOT# <20>
EC_SMB_CK2 <32>
Close to CPU
Date:
A
SCLK
ADM1032ARM-1 ZREEL_MSOP8
< Differential feedback for VDDNB >
Security Classification
R9 2 300_0402_5%
CPU_PROCHOT#_1.8
CPU_TEST20_SCANCLK2
Un-Mount R27 For Caspian
2
< From EC >
U2 B
1
300_0402_5%
1
3
SAMTEC_ASP-68200-07
300_0402_5%
H_PWRGD
+1.8VS
+1.8V
LDT_RST#
R36
@
<12,20> CPU_LDT_REQ#
2 4 6 8 10 12 14 16 18 20 22 24 26
NOTE: HDT TERMINATION IS REQUIRED FOR REV. Ax SILICON ONLY.
2
2 1
2 2 2 2
+1.8V
TIGRIS@ 1 2
1
300_0402_5%
2
1 1 1 1
+1.8VS
R21
1
R40 R39 R38 R37
R494 2 0_0402_5%
1
0.01U_0402_25V7K
+1.8VS
<20,42> H_PWRGD
@ @ @ @
2 300_0402_5%
1
+1.8V
Add R497 and R500 for Caspian
@
2
<20>
R41
@
C
D
Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
7
of
44
A
B
C
D
E
JCPUE
+CPU_CORE_0
VDD decoupling : +CPU_CORE +CPU_CORE_0
+CPU_CORE_0
1
1
+
330U_X_2VM_R6M
2
1
+
C30
+VDDNB
G4 H2 J9 J11 J13 J15 K6 K10 K12 K14 L4 L7 L9 L11 L13 L15 M2 M6 M8 M10 N7 N9 N11
+1.8V
K16 M16 P16 T16 V16
+CPU_CORE_0
1
C32
1
C33
1
C34
1
C35
1
C40
1
C41
C42
C28 330U_X_2VM_R6M
2
Near CPU Socket
2
22U_0805_6.3V6M
2
22U_0805_6.3V6M
2
22U_0805_6.3V6M
2
22U_0805_6.3V6M
Under CPU Socket
2
0.22U_0603_16V4Z
2
0.01U_0402_25V7K
2
180P_0402_50V8J
Under CPU Socket
1
+CPU_CORE_1
+CPU_CORE_1
1
1
+
330U_X_2VM_R6M
2
1
+
C31
+CPU_CORE_1
1
C36
1
C37
1
C38
1
C39
1
C43
1
C44
C45
C29 330U_X_2VM_R6M
2
Near CPU Socket
2
22U_0805_6.3V6M
2
22U_0805_6.3V6M
2
22U_0805_6.3V6M
2
22U_0805_6.3V6M
Under CPU Socket
2
0.22U_0603_16V4Z
2
0.01U_0402_25V7K
2
180P_0402_50V8J
Under CPU Socket
VDDIO decoupling : DDR SDRAM I/O ring power
2
1
C46 22U_0805_6.3V6M
2
1
C47 22U_0805_6.3V6M
2
1
C48 0.22U_0603_16V4Z
2
1
C49 0.22U_0603_16V4Z
2
1
C50 180P_0402_50V8J
2
VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5
H25 J17 K18 K21 K23 K25 L17 M18 M21 M23 M25 N17
+1.8V
1
VDD0_1 VDD0_2 VDD0_3 VDD0_4 VDD0_5 VDD0_6 VDD0_7 VDD0_8 VDD0_9 VDD0_10 VDD0_11 VDD0_12 VDD0_13 VDD0_14 VDD0_15 VDD0_16 VDD0_17 VDD0_18 VDD0_19 VDD0_20 VDD0_21 VDD0_22 VDD0_23
C51 180P_0402_50V8J
Under CPU Socket
VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12
+1.8V
6090022100G_B 2
1
2
1
C55 0.22U_0603_16V4Z
2
1
C56 0.22U_0603_16V4Z
2
1
C57 0.22U_0603_16V4Z
2
@ C58 0.22U_0603_16V4Z
AA4 AA11 AA13 AA15 AA17 AA19 AB2 AB7 AB9 AB23 AB25 AC11 AC13 AC15 AC17 AC19 AC21 AD6 AD8 AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23 B4 B6 B8 B9 B11 B13 B15 B17 B19 B21 B23 B25 D6 D8 D9 D11 D13 D15 D17 D19 D21 D23 D25 E4 F2 F11 F13 F15 F17 F19 F21 F23 F25 H7 H9 H21 H23 J4
+1.8V
2
1
C60 0.01U_0402_25V7K
2
C61 0.01U_0402_25V7K
Between CPU Socket and DIMM
+1.8V 180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch>
1
2
1
C62 180P_0402_50V8J
2
1
C63 180P_0402_50V8J
2
1
C64 180P_0402_50V8J
2
C65 180P_0402_50V8J
Between CPU Socket and DIMM +1.8V
Change to B2 size
3
1 1
2
1
C74 4.7U_0805_10V4Z
2
1
C75 4.7U_0805_10V4Z
2
1
C76 4.7U_0805_10V4Z
2
C77
@
4.7U_0805_10V4Z
+ C78 220U_B2_4VM_R45M 2
Between CPU Socket and DIMM
+0.9V
VTT decoupling.
1
1
2
C66 4.7U_0805_10V4Z
2
1
C67 4.7U_0805_10V4Z
2
1
C68 0.22U_0603_16V4Z
2
1
C69 0.22U_0603_16V4Z
2
1
C70 1000P_0402_25V8J
2
C71 1000P_0402_25V8J
1
2
C72 180P_0402_50V8J
1
2
C73 180P_0402_50V8J
Near CPU Socket Right side
+0.9V
1. Near Power Supply 2. Change to B2 size
1
+0.9V
+ C59 220U_B2_4VM_R45M 1
C79 4.7U_0805_10V4Z
2
1
C80 4.7U_0805_10V4Z
2
1
C81 0.22U_0603_16V4Z
2
1
C82 0.22U_0603_16V4Z
2
1
C83 1000P_0402_25V8J
2
1
C84 1000P_0402_25V8J
2
1
2
C85 180P_0402_50V8J
1
C86 180P_0402_50V8J
2
2
Near CPU Socket Left side 4
+VDDNB decoupling : Northbridge power
Add 22uF for Caspaian
+VDDNB
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 6090022100G_B @
1
2
C52 22U_0805_6.3V6M
1
2
1
C53 22U_0805_6.3V6M
VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 VDD1_8 VDD1_9 VDD1_10 VDD1_11 VDD1_12 VDD1_13 VDD1_14 VDD1_15 VDD1_16 VDD1_17 VDD1_18 VDD1_19 VDD1_20 VDD1_21 VDD1_22 VDD1_23 VDD1_24 VDD1_25 VDD1_26
P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4 AD2
VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13
Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18
+1.8V
Athlon 64 S1 Processor Socket
2
C54
2009-02-12
Issued Date
2009-02-12
Deciphered Date
J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6
3
4
Athlon 64 S1 Processor Socket
Compal Secret Data
Security Classification
22U_0805_6.3V6M 2 TIGRIS@
VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129
Title
Compal Electronics, Inc. AMD CPU S1G3 PWR & GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
1
JCPUF
Between CPU Socket and DIMM
1
+CPU_CORE_1
B
C
D
Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
8
of
44
A
B
C
DDR_B_D[0..63] +1.8V
DDR_B_D[0..63]
+1.8V DDR_B_DM[0..7]
<10> +V_DDR_MCH_REF
1
2
C104 1000P_0402_25V8J
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
DDR_B_D0 DDR_B_D1 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_D2 DDR_B_D3 DDR_B_D8 DDR_B_D9 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D10 DDR_B_D11
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
<6>
+1.8V
+0.9V
DDR_B_MA[0..15] <6>
DDR_B_DQS#[0..7]
VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS
<6>
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
1
E
DDR_B_DM[0..7] <6>
DDR_B_DQS[0..7]
JDDRH
D
DDR_B_DQS#[0..7]
DDR_B_D4 DDR_B_D5
<6>
RP8 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_RAS#
1 2 3 4
DDR_B_DM0
8 7 6 5
C105 2
1 0.1U_0402_16V7K
C106 2
1 0.1U_0402_16V7K
C108 2
1 0.1U_0402_16V7K
C107 2
1 0.1U_0402_16V7K
C109 2
1 0.1U_0402_16V7K
C110 2
1 0.1U_0402_16V7K
C111 2
1 0.1U_0402_16V7K
C112 2
1 0.1U_0402_16V7K
C114 2
1 0.1U_0402_16V7K
C113 2
1 0.1U_0402_16V7K
C116 2
1 0.1U_0402_16V7K
C115 2
1 0.1U_0402_16V7K
C118 2
1 0.1U_0402_16V7K
C117 2
1 0.1U_0402_16V7K
1
47_0804_8P4R_5% DDR_B_D6 DDR_B_D7
RP9 DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6
DDR_B_D12 DDR_B_D13
1 2 3 4
DDR_B_DM1
8 7 6 5
47_0804_8P4R_5% DDR_B_CLK0 DDR_B_CLK#0
DDR_B_CLK0 <6> DDR_B_CLK#0 <6>
RP10 DDR_CKE0_DIMMB 8 DDR_B_BS#2 7 DDR_B_MA15 6 DDR_CKE1_DIMMB 5
DDR_B_D14 DDR_B_D15
1 2 3 4
47_0804_8P4R_5%
DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 DDR_B_D24 DDR_B_D25 2
DDR_B_DM3 DDR_B_D26 DDR_B_D27 <6> DDR_CKE0_DIMMB <6> DDR_B_BS#2
DDR_CKE0_DIMMB DDR_B_BS#2 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1
<6> DDR_B_BS#0 <6> DDR_B_WE# <6> DDR_B_CAS# <6> DDR_CS1_DIMMB# <6> DDR_B_ODT1
DDR_B_MA10 DDR_B_BS#0 DDR_B_WE# DDR_B_CAS# DDR_CS1_DIMMB# DDR_B_ODT1 DDR_B_D32 DDR_B_D33 DDR_B_DQS#4 DDR_B_DQS4
3
DDR_B_D34 DDR_B_D35 DDR_B_D40 DDR_B_D41 DDR_B_DM5 DDR_B_D42 DDR_B_D43
DDR_B_D56 DDR_B_D57 DDR_B_DM7 DDR_B_D58 DDR_B_D59 4
<10,16,21> SMB_CK_DAT0 <10,16,21> SMB_CK_CLK0 +3VS
SMB_CK_DAT0 SMB_CK_CLK0 1
2
DDR_B_D20 DDR_B_D21
RP11 DDR_B_MA3 DDR_B_MA8 DDR_B_MA12 DDR_B_MA9
DDR_B_DM2 DDR_B_D22 DDR_B_D23
8 7 6 5
1 2 3 4
47_0804_8P4R_5% RP12
DDR_B_D28 DDR_B_D29
DDR_B_BS#0 DDR_B_MA10 DDR_B_MA1 DDR_B_MA5
DDR_B_DQS#3 DDR_B_DQS3
8 7 6 5
1 2 3 4
2
47_0804_8P4R_5% DDR_B_D30 DDR_B_D31
RP13
DDR_CKE1_DIMMB
DDR_CS1_DIMMB# DDR_B_ODT1 DDR_B_CAS# DDR_B_WE#
DDR_CKE1_DIMMB <6>
DDR_B_MA15 DDR_B_MA14
8 7 6 5
1 2 3 4
47_0804_8P4R_5% DDR_B_MA11 DDR_B_MA7 DDR_B_MA6
RP14 DDR_B_BS#1 DDR_CS0_DIMMB# DDR_B_MA13 DDR_B_ODT0
DDR_B_MA4 DDR_B_MA2 DDR_B_MA0
1 2 3 4
8 7 6 5
47_0804_8P4R_5% DDR_B_BS#1 DDR_B_RAS# DDR_CS0_DIMMB#
DDR_B_BS#1 <6> DDR_B_RAS# <6> DDR_CS0_DIMMB# <6>
DDR_B_ODT0 DDR_B_MA13
DDR_B_ODT0 <6>
DDR_B_D36 DDR_B_D37 DDR_B_DM4 3
For EMI
DDR_B_D38 DDR_B_D39
+1.8V DDR_B_D44 DDR_B_D45 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 DDR_B_CLK1 DDR_B_CLK#1
DDR_B_CLK1 <6> DDR_B_CLK#1 <6>
DDR_B_DM6
1 @ C120
1 @ C121
1 @ C122
1 @ C123
2
2
2
2
0.1U_0402_16V7K
DDR_B_D50 DDR_B_D51
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
0.1U_0402_16V7K
DDR_B_DQS#6 DDR_B_DQS6
VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1
0.1U_0402_16V7K
DDR_B_D48 DDR_B_D49
VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD
0.1U_0402_16V7K
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
DDR_B_D16 DDR_B_D17
DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 4
+3VS
C119 0.1U_0402_16V7K
P-TWO_A5692B-A0G16-P @
DIMM0 STD H:9.2mm (Bot)
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc. DDRII SO-DIMM 0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
9
of
44
A
B
C
D
E
2
+1.8V
R43 1K_0402_1% 1
DDR_A_D[0..63] +V_DDR_MCH_REF
<9> +V_DDR_MCH_REF 2
1
2
0.1U_0402_16V7K
DDR_A_DM[0..7]
1
2
DDR_A_DQS[0..7]
C95 1000P_0402_25V8J
DDR_A_MA[0..15]
1
R44 1K_0402_1%
C96
1
+1.8V
+1.8V
DDR_A_DQS#[0..7]
DDR_A_D[0..63]
<6>
DDR_A_DM[0..7] <6> DDR_A_DQS[0..7]
<6>
DDR_A_MA[0..15] <6> 1
DDR_A_DQS#[0..7]
<6>
JDDRL 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
DDR_A_D0 DDR_A_D1 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D10 DDR_A_D11
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 2
DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_DM3 DDR_A_D26 DDR_A_D27 DDR_CKE0_DIMMA
<6> DDR_CKE0_DIMMA
DDR_A_BS#2
<6> DDR_A_BS#2
DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDR_A_MA10 DDR_A_BS#0 DDR_A_WE#
<6> DDR_A_BS#0 <6> DDR_A_WE#
DDR_A_CAS# DDR_CS1_DIMMA#
<6> DDR_A_CAS# <6> DDR_CS1_DIMMA# 3
DDR_A_ODT1
<6> DDR_A_ODT1
DDR_A_D32 DDR_A_D33 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49
DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 4
DDR_A_DM7 DDR_A_D58 DDR_A_D59 SMB_CK_DAT0 SMB_CK_CLK0
<9,16,21> SMB_CK_DAT0 <9,16,21> SMB_CK_CLK0 +3VS
1
2
VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
DDR_A_D4 DDR_A_D5 DDR_A_DM0 DDR_A_D6 DDR_A_D7 DDR_A_D12 DDR_A_D13 DDR_A_DM1 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_D14 DDR_A_D15
DDR_A_D20 DDR_A_D21
DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29
DDR_A_MA6 DDR_A_MA14 DDR_A_MA7 DDR_A_MA11
1 2 3 4
DDR_A_D30 DDR_A_D31
DDR_CKE0_DIMMA DDR_A_BS#2 DDR_CKE1_DIMMA DDR_A_MA15
DDR_A_BS#1 DDR_A_MA2 DDR_A_MA0 DDR_A_MA4
47_0804_8P4R_5% RP3 1 8 2 7 3 6 4 5
DDR_A_MA5 DDR_A_MA8 DDR_A_MA9 DDR_A_MA12
47_0804_8P4R_5% RP4 8 1 7 2 6 3 5 4
DDR_A_BS#0 DDR_A_MA10 DDR_A_MA3 DDR_A_MA1
47_0804_8P4R_5% RP5 8 1 7 2 6 3 5 4
DDR_A_ODT1 DDR_CS1_DIMMA# DDR_A_CAS# DDR_A_WE#
47_0804_8P4R_5% RP6 8 1 7 2 6 3 5 4
DDR_A_MA13 DDR_A_ODT0 DDR_A_RAS# DDR_CS0_DIMMA#
47_0804_8P4R_5% RP7 1 8 2 7 3 6 4 5
DDR_CKE1_DIMMA <6>
DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA# DDR_A_ODT0 DDR_A_MA13
DDR_A_BS#1 <6> DDR_A_RAS# <6> DDR_CS0_DIMMA# <6> DDR_A_ODT0 <6>
8 7 6 5
47_0804_8P4R_5% RP2 8 1 7 2 6 3 5 4
DDR_A_DQS#3 DDR_A_DQS3
DDR_A_D36 DDR_A_D37
C87
1
2 0.1U_0402_16V7K
C88
1
2 0.1U_0402_16V7K
C90
1
2 0.1U_0402_16V7K
C89
1
2 0.1U_0402_16V7K
C91
2
1
2 0.1U_0402_16V7K
C92
1
2 0.1U_0402_16V7K
C93
1
2 0.1U_0402_16V7K
C94
1
2 0.1U_0402_16V7K
C98
1
2 0.1U_0402_16V7K
C97
1
2 0.1U_0402_16V7K
C100 1
2 0.1U_0402_16V7K
C99
1
2 0.1U_0402_16V7K
C102 1
2 0.1U_0402_16V7K
C101 1
2 0.1U_0402_16V7K
DDR_A_D38 DDR_A_D39 DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_CLK1 DDR_A_CLK#1
DDR_A_CLK1 <6> DDR_A_CLK#1 <6>
DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 4
DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63
PTI_A5652D-A0G16-P @
DIMM0 STD H:5.2mm (Bot)
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
B
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
3
47_0804_8P4R_5%
DDR_A_DM4
C103 0.1U_0402_16V7K
RP1
DDR_A_DM2
DDR_CKE1_DIMMA
+1.8V
+0.9V DDR_A_CLK0 <6> DDR_A_CLK#0 <6>
C
D
DDRII SO-DIMM 1 Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
10
of
44
A
B
C
D
E
U3B
1
< To WLAN > < To LAN >
<27> <27> <26> <26>
PCIE_PTX_C_IRX_P2 PCIE_PTX_C_IRX_N2 PCIE_PTX_C_IRX_P3 PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P2 PCIE_PTX_C_IRX_N2 PCIE_PTX_C_IRX_P3 PCIE_PTX_C_IRX_N3
2
< From SB710 : x4 PCIE A-link >
<20> <20> <20> <20> <20> <20> <20> <20>
SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N
SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N
AE3 AD4 AE2 AD3 AD1 AD2 V5 W6 U5 U6 U8 U7 AA8 Y8 AA7 Y7 AA5 AA6 W5 Y5
GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P GFX_RX4N GFX_RX5P GFX_RX5N GFX_RX6P GFX_RX6N GFX_RX7P GFX_RX7N GFX_RX8P GFX_RX8N GFX_RX9P GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N GPP_RX4P GPP_RX4N GPP_RX5P GPP_RX5N
HDMI_TXD2+ HDMI_TXD2HDMI_TXD1+ HDMI_TXD1HDMI_TXD0+ HDMI_TXD0HDMI_CLK0+ HDMI_CLK0-
DP0
GFX_TX0,TX1,TX2 and TX3 AUX0 and HPD0
DP1
GFX_TX4,TX5,TX6 and TX7 AUX1 and HPD1
C156 C157 C158 C159
1 1 1 1
2 2 2 2
0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K
SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N
AD7 AE7 AE6 AD6 AB6 AC6 AD5 AE5
SB_TX0P_C SB_TX0N_C SB_TX1P_C SB_TX1N_C SB_TX2P_C SB_TX2N_C SB_TX3P_C SB_TX3N_C
C162 C163 C164 C165 C166 C168 C169 C167
1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2
0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K
PCE_CALRP(PCE_BCALRP) PCE_CALRN(PCE_BCALRN)
AC8 AB8
PCIE_CALRP PCIE_CALRN
PCIE I/F SB
RS780M_FCBGA528
1
RS880M Display Port Support (muxed on GFX)
PCIE_ITX_PRX_P2 PCIE_ITX_PRX_N2 PCIE_ITX_PRX_P3 PCIE_ITX_PRX_N3
GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N
<19> <19> <19> <19> <19> <19> <19> <19>
< If integrated GFX is used, some PCIE pairs are used as HDMI signal pairs >
AC1 AC2 AB4 AB3 AA2 AA1 Y1 Y2 Y4 Y3 V1 V2
PCIE I/F GPP
SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N
HDMI_TXD2+ HDMI_TXD2HDMI_TXD1+ HDMI_TXD1HDMI_TXD0+ HDMI_TXD0HDMI_CLK0+ HDMI_CLK0-
A5 B5 A4 B4 C3 B2 D1 D2 E2 E1 F4 F3 F1 F2 H4 H3 H1 H2 J2 J1 K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2
GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N
PART 2 OF 6
PCIE I/F GFX
D4 C4 A3 B3 C2 C1 E5 F5 G5 G6 H5 H6 J6 J5 J7 J8 L5 L6 M8 L8 P7 M7 P5 M5 R8 P8 R6 R5 P4 P3 T4 T3
PCIE_ITX_C_PRX_P2 PCIE_ITX_C_PRX_N2 PCIE_ITX_C_PRX_P3 PCIE_ITX_C_PRX_N3
<27> <27>< <26> <26><
To WLAN > To LAN >
2
R55 R56
1 1
SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N
1.27K_0402_1% 2K_0402_1%
2 2
<20> <20> <20> <20> <20> <20> <20> <20>
< To SB710 : x4 PCEI A-link>
< TX Impedance Calibration. Connect to GND > < RX Impedance Calibration. Connect to VDDPCIE >
+1.1VS
RS780MCR3@
U3A H_CADON[0..15]
3
H_CADOP[0..15]
<5>
H_CADON[0..15]
<5>
H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7
< From S1G3 CPU : x16 HT>
<5> <5> <5> <5>
H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1
<5> <5> <5> <5>
H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1
301_0402_1%1
Y25 Y24 V22 V23 V25 V24 U24 U25 T25 T24 P22 P23 P25 P24 N24 N25
H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15
2 R57
AC24 AC25 AB25 AB24 AA24 AA25 Y22 Y23 W21 W20 V21 V20 U20 U21 U19 U18
PART 1 OF 6
HT_RXCAD8P HT_RXCAD8N HT_RXCAD9P HT_RXCAD9N HT_RXCAD10P HT_RXCAD10N HT_RXCAD11P HT_RXCAD11N HT_RXCAD12P HT_RXCAD12N HT_RXCAD13P HT_RXCAD13N HT_RXCAD14P HT_RXCAD14N HT_RXCAD15P HT_RXCAD15N
H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1
T22 T23 AB23 AA22
HT_RXCLK0P HT_RXCLK0N HT_RXCLK1P HT_RXCLK1N
H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1
M22 M23 R21 R20
HT_RXCTL0P HT_RXCTL0N HT_RXCTL1P HT_RXCTL1N
HT_RXCALP HT_RXCALN
C23 A24
HT_RXCALP HT_RXCALN RS780M_FCBGA528
0718 Place within 1" layout 1:2
4
HT_RXCAD0P HT_RXCAD0N HT_RXCAD1P HT_RXCAD1N HT_RXCAD2P HT_RXCAD2N HT_RXCAD3P HT_RXCAD3N HT_RXCAD4P HT_RXCAD4N HT_RXCAD5P HT_RXCAD5N HT_RXCAD6P HT_RXCAD6N HT_RXCAD7P HT_RXCAD7N
HYPER TRANSPORT CPU I/F
H_CADOP[0..15]
HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N
D24 D25 E24 E25 F24 F25 F23 F22 H23 H22 J25 J24 K24 K25 K23 K22
H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7
F21 G21 G20 H21 J20 J21 J18 K17 L19 J19 M19 L18 M21 P21 P18 M18
H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15
HT_TXCLK0P HT_TXCLK0N HT_TXCLK1P HT_TXCLK1N
H24 H25 L21 L20
H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1
HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N
M24 M25 P19 R18
H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1
B24 B25
HT_TXCALP HT_TXCALN
HT_TXCALP HT_TXCALN RS780MCR3@
/
H_CADIP[0..15] H_CADIN[0..15]
H_CADIP[0..15]
<5>
H_CADIN[0..15]
<5>
3
< To S1G3 CPU : x16 HT>
H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1
<5> <5> <5> <5>
H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1
<5> <5> <5> <5>
R58
1
2 301_0402_1%
< Transmitter Calibration Resistor to HT_TXCALN >
0718 Place within 1" layout 1:2
4
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc. RS780M HT / PCIE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
11
of
44
B
C
UMA_CRT_R
<17> UMA_CRT_R
UMA_CRT_G
<17> UMA_CRT_G
UMA_CRT_B
<17> UMA_CRT_B
UMA_CRT_HSYNC UMA_CRT_VSYNC UMA_CRT_CLK UMA_CRT_DATA
UMA_CRT_HSYNC UMA_CRT_VSYNC UMA_CRT_CLK UMA_CRT_DATA R65 1
2 R71 4.7K_0402_5% 1
RED(DFT_GPIO0) REDb(NC) GREEN(DFT_GPIO1) GREENb(NC) BLUE(DFT_GPIO3) BLUEb(NC)
A11 B11 F8 E8
DAC_HSYNC(PWM_GPIO4) DAC_VSYNC(PWM_GPIO6) DAC_SCL(PCE_RCALRN) DAC_SDA(PCE_TCALRN)
G14
+VDDA18HTPLL
H17
+VDDA18PCIEPLL
VDDA18HTPLL VDDA18PCIEPLL1 VDDA18PCIEPLL2
D8 A10 C10 C12
SYSRESETb POWERGOOD LDTSTOPb ALLOW_LDTSTOP
CLK_NBHT CLK_NBHT#
C25 C24
HT_REFCLKP HT_REFCLKN
NB_OSC_14.318M
E11 F11
REFCLK_P/OSCIN(OSCIN) REFCLK_N(PWM_GPIO3)
NBGFX_CLK NBGFX_CLK#
<16> NBGFX_CLK <16> NBGFX_CLK#
<18> UMA_LCD_DDC_CLK <18> UMA_LCD_DDC_DAT <19> HDMIDAT_UMA <19> HDMICLK_UMA
T2 T1
GFX_REFCLKP GFX_REFCLKN
U1 U2
GPP_REFCLKP GPP_REFCLKN
CLK_SBLINK_BCLK CLK_SBLINK_BCLK#
V4 V3
GPPSB_REFCLKP(SB_REFCLKP) GPPSB_REFCLKN(SB_REFCLKN)
UMA_LCD_DDC_CLK UMA_LCD_DDC_DAT HDMIDAT_UMA HDMICLK_UMA
B9 A9 B8 A8 B7 A7
I2C_CLK I2C_DATA DDC_DATA0/AUX0N(NC) DDC_CLK0/AUX0P(NC) DDC_CLK1/AUX1P(NC) DDC_DATA1/AUX1N(NC)
2
<16> CLK_SBLINK_BCLK <16> CLK_SBLINK_BCLK#
@ +3VS
R88 2
1 10K_0402_5%
B10
Strap pin
<15>
AUX_CAL
B18 A18 A17 B17 D20 D21 D18 D19
TXCLK_LP(DBG_GPIO1) TXCLK_LN(DBG_GPIO3) TXCLK_UP(PCIE_RESET_GPIO4) TXCLK_UN(PCIE_RESET_GPIO1)
B16 A16 D16 D17
VDDLT18_1(NC) VDDLT18_2(NC) VDDLT33_1(NC) VDDLT33_2(NC)
E
UMA_LCD_TXCLK_ACLK+ UMA_LCD_TXCLK_ACLK-
A15 B15 A14 B14
+VDDLT18
LVDS_DIGON(PCE_TCALRP) LVDS_BLON(PCE_RCALRP) LVDS_ENA_BL(PWM_GPIO2)
E9 F7 G12
UMA_LCD_TXOUT0_A0+ <18> UMA_LCD_TXOUT0_A0- <18> UMA_LCD_TXOUT0_A1+ <18> UMA_LCD_TXOUT0_A1- <18> UMA_LCD_TXOUT0_A2+ <18> UMA_LCD_TXOUT0_A2- <18>
1
+VDDLTP18
C14 D15 C16 C18 C20 E20 C22
UMA_LCD_TXCLK_ACLK+ <18> UMA_LCD_TXCLK_ACLK- <18>
UMA_ENVDD UMA_ENBKL
UMA_ENVDD <18> UMA_ENBKL <32> 2
< LVDS backlight enable > 2
1 100K_0402_5%
Reserve for INVT_PWM
TMDS_HPD(NC) HPD(NC)
D9 D10
HPD
SUS_STAT#(PWM_GPIO5)
D12
SUS_STAT#
MIS.
THERMALDIODE_P THERMALDIODE_N TESTMODE
HPD
< HDMI hot-plug detection >
<19,21>
< Strap option pin or gate side-port memory IO >
SUS_STAT# <15,21>
AE8 AD8 D13
R80
2 1.8K_0402_5%
1
AUX_CAL(NC) RS780MCR3@
RS780M_FCBGA528 < Dedicated power for the DAC which can affect display quality >
< Dedicated power for the DAC which can affect display quality >
+1.8VS +3VS
2 300_0402_5% NB_PWRGD
R371 1
+1.8VS 1
3
< LVDS digital power enable >
R73 PAD T17
RSVD
C8
UMA_LCD_TXOUT0_A0+ UMA_LCD_TXOUT0_A0UMA_LCD_TXOUT0_A1+ UMA_LCD_TXOUT0_A1UMA_LCD_TXOUT0_A2+ UMA_LCD_TXOUT0_A2-
A13 B13
VSSLT1(VSS) VSSLT2(VSS) VSSLT3(VSS) VSSLT4(VSS) VSSLT5(VSS) VSSLT6(VSS) VSSLT7(VSS)
STRP_DATA
G11 AUX_CAL
TXOUT_U0P(NC) TXOUT_U0N(NC) TXOUT_U1P(PCIE_RESET_GPIO3) TXOUT_U1N(PCIE_RESET_GPIO2) TXOUT_U2P(NC) TXOUT_U2N(NC) TXOUT_U3P(PCIE_RESET_GPIO5) TXOUT_U3N(NC)
VDDLTP18(NC) VSSLTP18(NC)
PLLVDD(NC) PLLVDD18(NC) PLLVSS(NC)
D7 E7
<16> NB_OSC_14.318M
A22 B22 A21 B21 B20 A20 A19 B19
DAC_RSET(PWM_GPIO1)
NB_RESET# 2 0_0402_5% NB_PWRGD LDT_STOP# CPU_LDT_REQ#
<16> CLK_NBHT <16> CLK_NBHT#
R72 4.7K_0402_5%
G18 G17 E18 F18 E19 F19
A12 D14 B12
1 2
C_Pr(DFT_GPIO5) Y(DFT_GPIO2) COMP_Pb(DFT_GPIO4)
+NB_PLLVDD +NB_HTPVDD
R67 1
<15,20,26,27,31,32> PLT_RST# <21> NB_PWRGD <7,20> LDT_STOP# <7,20> CPU_LDT_REQ#
+1.1VS
2 715_0402_1%
E17 F17 F15
TXOUT_L0P(NC) TXOUT_L0N(NC) TXOUT_L1P(NC) TXOUT_L1N(NC) TXOUT_L2P(NC) TXOUT_L2N(DBG_GPIO0) TXOUT_L3P(NC) TXOUT_L3N(DBG_GPIO2)
PART 3 OF 6
PM
<15,17> <15,17> <17> <17>
AVDD1(NC) AVDD2(NC) AVDDDI(NC) AVSSDI(NC) AVDDQ(NC) AVSSQ(NC)
CRT/TVOUT
+AVDDQ
F12 E12 F14 G15 H15 H14
PLL PWR LVTM
+AVDD1 +AVDD2
1
D
U3C
AVDD=100mA
CLOCKs
A
L2 2 BLM18PG121SN1D_0603
L4 0_0603_5%
+AVDD1 1
2
+AVDD2 1
C170 2.2U_0603_6.3V4Z
2
1
C172 2.2U_0603_6.3V4Z
2
R62 1
2 140_0402_1% UMA_CRT_R
R63 1
2 150_0402_1% UMA_CRT_G
R64 1
2 150_0402_1% UMA_CRT_B
3
C198 0.1U_0402_16V7K
< DAC Bandgap Reference Voltage > < 1.8V power for system PLLs >
< Power for integrated DVI/HDMI PLL macro >
+1.8VS 1
+1.8VS
L6 2 BLM18PG121SN1D_0603
+1.8VS
+AVDDQ 1
2
+NB_HTPVDD
L7 2 BLM18PG121SN1D_0603
1 C175
2 1
L3 1 BLM18PG121SN1D_0603
+VDDLTP18 1
C176
C171
2.2U_0603_6.3V4Z 2
2.2U_0603_6.3V4Z
2
2.2U_0603_6.3V4Z
< IO power for HyperTransport PLL > < 1.1V Power for system PLLs >
+1.8VS
< 1.8V IO power for the integrated DVI/HDMI interface >
+VDDA18HTPLL 1
L10 2 BLM18PG121SN1D_0603 1
+1.1VS
+1.8VS
C179
2
4
+NB_PLLVDD
L9 2 BLM18PG121SN1D_0603
1 2.2U_0603_6.3V4Z
2 1
L5 1 BLM18PG121SN1D_0603
+VDDLT18 1
C178
1
C174
4
C173
< 1.8V IO power for PCI-E PLLs >
2
+1.8VS 1
2.2U_0603_6.3V4Z
2
2
C180 2.2U_0603_6.3V4Z
/
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc. RS780M VEDIO/CLK GEN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
B
2
0.1U_0402_16V7K
+VDDA18PCIEPLL
L11 2 BLM18PG121SN1D_0603 1
A
4.7U_0805_10V4Z
C
D
Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
12
of
44
2
1
U3D
AD16 AE17 AD17 W12 Y12 AD18 AB13 AB18 V14
B
V15 W14 AE12 AD12
MEM_A0(NC) MEM_A1(NC) MEM_A2(NC) MEM_A3(NC) MEM_A4(NC) MEM_A5(NC) MEM_A6(NC) MEM_A7(NC) MEM_A8(NC) MEM_A9(NC) MEM_A10(NC) MEM_A11(NC) MEM_A12(NC) MEM_A13(NC) MEM_BA0(NC) MEM_BA1(NC) MEM_BA2(NC)
SBD_MEM/DVO_I/F
PAR 4 OF 6 AB12 AE16 V11 AE15 AA12 AB16 AB14 AD14 AD13 AD15 AC16 AE13 AC14 Y14
MEM_RASb(NC) MEM_CASb(NC) MEM_WEb(NC) MEM_CSb(NC) MEM_CKE(NC) MEM_ODT(NC) MEM_CKP(NC) MEM_CKN(NC)
MEM_DQ0/DVO_VSYNC(NC) MEM_DQ1/DVO_HSYNC(NC) MEM_DQ2/DVO_DE(NC) MEM_DQ3/DVO_D0(NC) MEM_DQ4(NC) MEM_DQ5/DVO_D1(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7/DVO_D4(NC) MEM_DQ8/DVO_D3(NC) MEM_DQ9/DVO_D5(NC) MEM_DQ10/DVO_D6(NC) MEM_DQ11/DVO_D7(NC) MEM_DQ12(NC) MEM_DQ13/DVO_D9(NC) MEM_DQ14/DVO_D10(NC) MEM_DQ15/DVO_D11(NC) MEM_DQS0P/DVO_IDCKP(NC) MEM_DQS0N/DVO_IDCKN(NC) MEM_DQS1P(NC) MEM_DQS1N(NC) MEM_DM0(NC) MEM_DM1/DVO_D8(NC) IOPLLVDD18(NC) IOPLLVDD(NC) IOPLLVSS(NC)
MEM_COMPP(NC) MEM_COMPN(NC) RS780M_FCBGA528
MEM_VREF(NC)
AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21 Y17 W18 AD20 AE21
B
W17 AE19 AE23 AE24
+1.8VS +1.1VS
AD23 AE18
RS780MCR3@
A
A
/
Compal Secret Data
Security Classification Issued Date
2008/04/14
Deciphered Date
2009/04/14
Title
Compal Electronics, Inc. RS780M SIDE PORT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
2
1
Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet
13
of
44
0.1U_0402_16V7K
2
0.1U_0402_16V7K
Change L16, L18, L19 and L22 to bead for EMI 2A 2
+1.8VS
1
L22
FBMA-L11-201209-221LMA30T_0805 1 1 1 C235 C246 C236 2
4.7U_0805_10V4Z
2
4.7U_0805_10V4Z
2
< 1.8V IO power for PCI-E graphics, SB, and GPP interfaces > 1
0.1U_0402_16V7K
2
1
C237 0.1U_0402_16V7K
2
C238 0.1U_0402_16V7K
1
2
+VDDA18PCIE
C239 0.1U_0402_16V7K
2
VDDHTTX_1 VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5 VDDHTTX_6 VDDHTTX_7 VDDHTTX_8 VDDHTTX_9 VDDHTTX_10 VDDHTTX_11 VDDHTTX_12 VDDHTTX_13
J10 P10 K10 M10 L10 W9 H9 T10 R10 Y9 AA9 AB9 AD9 AE9 U10
VDDA18PCIE_1 VDDA18PCIE_2 VDDA18PCIE_3 VDDA18PCIE_4 VDDA18PCIE_5 VDDA18PCIE_6 VDDA18PCIE_7 VDDA18PCIE_8 VDDA18PCIE_9 VDDA18PCIE_10 VDDA18PCIE_11 VDDA18PCIE_12 VDDA18PCIE_13 VDDA18PCIE_14 VDDA18PCIE_15
< 1.8V IO transform power > +1.8VS 1
2
C251
+1.8VS
L89
2
0_0603_5%
1
1U_0402_6.3V4Z
F9 G9 AE11 AD11
< 1.8V power for side-port memory interface >
1
2
C252 @ 1U_0402_6.3V4Z
K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16
VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8 VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22
C211
C212
10U_0805_10V4Z
10U_0805_10V4Z
C221
C222
C219
C220
VDD_CORE:GM=5A/PM=10A 1
2
+1.1VS
FBMA-L11-201209-121LMA40T_0805
2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
1
2
1
1
2
1
2
1
PJP3
+
1
2 PAD-OPEN 4x4m
2
< Isolated power for side-port memory interface >
H11 H12
VDD33_1(NC) VDD33_2(NC)
RS780M_FCBGA528
L90
< Core power >
AE10 AA11 Y11 AD10 AB10 AC10
VDD_MEM1(NC) VDD_MEM2(NC) VDD_MEM3(NC) VDD_MEM4(NC) VDD_MEM5(NC) VDD_MEM6(NC)
VDD18_1 VDD18_2 VDD18_MEM1(NC) VDD18_MEM2(NC)
Change L90 to bead for EMI +NB_CORE
C234
2
AE25 AD24 AC23 AB22 AA21 Y20 W19 V18 U17 T17 R17 P17 M17
330U_D2E_2.5VM
0.1U_0402_16V7K
+VDDHTTX
C229
C245
2
1
C228
10U_0805_10V4Z
0.1U_0402_16V7K
1
C233
2
< IO power for HyperTransport transmit interface >
+1.1VS
1
10U_0805_10V4Z
4.7U_0805_10V4Z
0.1U_0402_16V7K
C232
2
FBMA-L11-201209-221LMA30T_0805 1 1 C225 C226 C227
2
2
0.1U_0402_16V7K
1
0.1U_0402_16V7K
2
C244
L19
1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1U_0402_6.3V4Z
2
1
C231
0.1U_0402_16V7K
1
0.1U_0402_16V7K
2A 2
+1.2V_HT
2
1
1U_0402_6.3V4Z
10U_0805_10V4Z
VDDHTRX_1 VDDHTRX_2 VDDHTRX_3 VDDHTRX_4 VDDHTRX_5 VDDHTRX_6 VDDHTRX_7
1
C230
H18 G19 F20 E21 D22 B23 A23
1
0.1U_0402_16V7K
+VDDHTRX
C218
1
1U_0402_6.3V4Z
1
C217
2
1U_0402_6.3V4Z
1
1
2
C243
0.1U_0402_16V7K
C242
2
C223
0.1U_0402_16V7K
VDDA_12=2.5A
0.1U_0402_16V7K
FBMA-L11-201209-221LMA30T_0805 1 1 C214 C216
2
< IO power for HyperTransport receive interface >
C224
0.1U_0402_16V7K
L17 1 2 FBMA-L11-201209-221LMA30T_0805
+VDDA11PCIE
0.1U_0402_16V7K
2
C210
PART 5/6
A6 B6 C6 D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9
VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8 VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17
C241
C215
0.1U_0402_16V7K
C208
VDDHT_1 VDDHT_2 VDDHT_3 VDDHT_4 VDDHT_5 VDDHT_6 VDDHT_7
0.1U_0402_16V7K
L18
1
2
1
J17 K16 L16 M16 P16 R16 T16
0.1U_0402_16V7K
2
4.7U_0805_10V4Z
1
< Main IO power for PCI-E graphics, SB, and GPP interfaces >
U3E +VDDHT
0.1U_0402_16V7K
2
2A
< Digital IO power for HyperTransport interface >
C240
FBMA-L11-201209-221LMA30T_0805 1 1 1 C209 C206 C207
E
C247
L16
D
0.1U_0402_16V7K
1
C
0.1U_0402_16V7K
2A 2
+1.1VS
B
POWER
A
2
< 3.3V IO power > +3VS 1
RS780MCR3@
2
C250 0.1U_0402_16V4Z
1
2
C253 0.1U_0402_16V4Z
U3F
3
VSSAHT1 VSSAHT2 VSSAHT3 VSSAHT4 VSSAHT5 VSSAHT6 VSSAHT7 VSSAHT8 VSSAHT9 VSSAHT10 VSSAHT11 VSSAHT12 VSSAHT13 VSSAHT14 VSSAHT15 VSSAHT16 VSSAHT17 VSSAHT18 VSSAHT19 VSSAHT20 VSSAHT21 VSSAHT22 VSSAHT23 VSSAHT24 VSSAHT25 VSSAHT26 VSSAHT27
L12 M14 N13 P12 P15 R11 R14 T12 U14 U11 U15 V12 W11 W15 AC12 AA14 Y18 AB11 AB15 AB17 AB19 AE20 AB21 K11
4
VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34
PART 6/6
GROUND
A25 D23 E22 G22 G24 G25 H19 J22 L17 L22 L24 L25 M20 N22 P20 R19 R22 R24 R25 H20 U22 V19 W22 W24 W25 Y21 AD25
RS780M_FCBGA528
/
VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8 VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30 VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10
3
AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15
4
RS780MCR3@
Compal Secret Data
Security Classification 2009-02-12
Issued Date
A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc. RS780M PWR / GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
14
of
44
A
B
C
< RS780 DFT_GPIO5 mux at CRT_VSYNC pull High to 3K >
E
< DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb > Enables the Test Debug Bus using GPIO.
SI2: Change to 3K pull high 2
1
R101 3K_0402_5%
@ 2
1
R102 3K_0402_5%
<12,17> UMA_CRT_VSYNC
D
+3VS
1 : Enable (RX780, RS780) 0 : Disable (RX780, RS780) PIN: RS740-->RS780_AUX_CAL; RX780-->NB_TV_C; RS780--> VSYNC#
1
< RS780 use register to control PCI-E configure >
1
< DFT_GPIO[4:2] : STRAP_PCIE_GPP_CFG[2:0] > These pin straps are used to configure PCI-E GPP mode. 000 : 00001 001 : 00010 010 : 01011 011 : 00100 100 : 01010 101 : 01100 111 : 01011 < DFT_GPIO1 : LOAD_EEPROM_STRAPS >
< RS780 DFT_GPIO1 >
Selects Loading of STRAPS from EPROM @ 1
<12> AUX_CAL
2
R104 150_0402_1%
1 : Bypass the loading of EEPROM straps and use Hardware Default Values 0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected
2
<12,21> SUS_STAT#
@ 2
2
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT
D4 1 CH751H-40PT_SOD323-2
PLT_RST# <12,20,26,27,31,32>
< DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb >
< RS780 use HSYNC to enable SIDE PORT (internal pull high) >
RX780: Enables the Test Debug Bus using PCIE bus <12,17> UMA_CRT_HSYNC
2
1
R125 3K_0402_5%
+3VS
1 : Disable ( Can still be enabled using nbcfg register access ) 0 : Enable RS780: Enables Side port memory ( RS780 use HSYNC#) 1. Disable (RS780) 0 : Enable (RS780)
3
3
4
4
/
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc. RS780M STRAPS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
15
of
44
A
B
C
+1.2V_HT
R167 1 R168 1
D
2 0_0805_5% 1
2 0_0805_5% 1
2
1 C452 22U_0805_6.3V6M
2
1 C453 0.1U_0402_16V4Z
2
1 C454 0.1U_0402_16V4Z
2
1 C455 0.1U_0402_16V4Z
2
1 C444 22U_0805_6.3V6M
1 C456 0.1U_0402_16V4Z
2
E
+3VS_CLK
+3VS
+VDDCLK_IO
2
C457 0.1U_0402_16V4Z
2
1
C445 0.1U_0402_16V7K
2
1
C446 0.1U_0402_16V7K
CLK_48M_CR_R
R970
1
2
33_0402_5%
CLK_48M_USB_R
R170
1
2
33_0402_5%
NB_OSC_14.318M_R
R379
1
2
158_0402_1%
R971
TIGRIS@ 1 2
2
1
C447 0.1U_0402_16V7K
2
1
C448 0.1U_0402_16V7K
+3VS_CLK 1
1
C458
C459
1
1
C460
C461
1
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
2
1
C449 0.1U_0402_16V7K
2
1
C450 0.1U_0402_16V7K
2
C451 1U_0402_6.3V4Z
CLK_48M_CR <28>
< To Card Reader >
CLK_48M_USB <21>
< To SB700 USB host >
1
0.1U_0402_16V4Z NB_OSC_14.318M
R380 1
CLK_XTAL_OUT CLK_XTAL_IN
2 90.9_0402_1%
33_0402_5%
SB_14.318M <20>
CLK_NBHT
CLK_NBHT <12>
< To RS780 Clock block >
CLK_NBHT#
1 14.31818MHZ_20P_6X1430004201 1 C465
1
CLK_NBHT# <12> R174
+3VS_CLK +3VS_CLK
C464
+3VS_CLK
Y2 2
1
C629
2 1
2
CLK_CPU_BCLK_R 2
8.2K_0402_5%
+3VS_CLK
1U_0402_6.3V4Z R946
1
0_0402_5%
2
CLK_CPU_BCLK <7>
22P_0402_50V8J
2
22P_0402_50V8J 2
<12> < To RS780 Clock block >
GND SMB_CK_CLK0 SMB_CK_DAT0
<9,10,21> SMB_CK_CLK0 <9,10,21> SMB_CK_DAT0
+3VS_CLK
CLK_SBLINK_BCLK# CLK_SBLINK_BCLK
<12> CLK_SBLINK_BCLK# <12> CLK_SBLINK_BCLK
SB LINK
+VDDCLK_IO CLK_PCIE_MCARD2# CLK_PCIE_MCARD2
<27> CLK_PCIE_MCARD2# <27> CLK_PCIE_MCARD2
WLAN 3
2
1
0_0402_5%
2
1
R945
2
CLK_CPU_BCLK# <7>
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
SCL SDA VDD_DOT SRC_7#/27M SRC_7/27M_SS VSS_DOT SRC_5# SRC_5 SRC_4# SRC_4 VSS_SRC VDD_SRC_IO SRC_3# SRC_3 SRC_2# SRC_2 VDD_SRC VDD_SRC_IO
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
+3VS_CLK
< To CPU >
261_0402_1%
VSS_SRC SRC_1# SRC_1 SRC_0# SRC_0 CLKREQ_0# ATIGCLK_2# ATIGCLK_2 VSS_ATIG VDD_ATIG_IO VDD_ATIG ATIGCLK_1# ATIGCLK_1 ATIGCLK_0# ATIGCLK_0 SB_SRC_1# SB_SRC_1 VSS_SB_SRC
+3VS_CLK +VDDCLK_IO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
@ CLK_CPU_BCLK_R#
VSS_48 48MHz_0 48MHz_1 VDD_48 XTAL_OUT XTAL_IN VSS_REF REF_0/SEL_HTT66 REF_1/SEL_SATA REF_2/SEL_27 VDD_REF VDD_HTT HTT_0/66M_0 HTT_0#/66M_1 VSS_HTT PD# CPU_K8_0 CPU_K8_0#
U10
73
2
SEL_SATA 27M_SEL
CLK_XTAL_OUT CLK_XTAL_IN
R186
VDD_CPU VDD_CPU_I/O VSS_CPU CLKREQ_1# CLKREQ_2# VDD_A VSS_A VSS_SATA SRC_6/SATA SRC_6#/SATA# VDD_SATA CLKREQ_3# CLKREQ_4# SB_SRC_SLOW# SB_SRC_0 SB_SRC_0# VDD_SB_SRC VDD_SB_SRC_IO
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
+3VS_CLK
Reserve Clock Request for NewCard
+3VS_CLK +VDDCLK_IO CLKREQ_NCARD# CLKREQ_MCARD2#
CLKREQ_NCARD# CLKREQ_MCARD2# <27>
+3VS_CLK
CLKREQ_MCARD2# CLKREQ_LAN#
CLK_SBSRC_BCLK CLK_SBSRC_BCLK#
CLK_SBSRC_BCLK <20> CLK_SBSRC_BCLK# <20> SB
1 R324 1 R325 1 R390
2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5%
SRC
+3VS_CLK R372 1
2 10K_0402_5%
+3VS_CLK
+3VS_CLK +VDDCLK_IO 3
SLG8SP626VTR_QFN72_10x10
R179 8.2K_0402_5% @
OSC_14M_NB
1
RS780
2
R181 8.2K_0402_5%
NBGFX_CLK <12> NBGFX_CLK# <12>
NB CLOCK INPUT TABLE
NB GFX
NB CLOCKS
RX780
RS780
1
1
R180 8.2K_0402_5%
+3VS_CLK
+VDDCLK_IO
+3VS_CLK
2
SEL_SATA
1.1V 158R/90.9R
HT_REFCLKP 27M_SEL HT_REFCLKN
100M DIFF 100M DIFF
100M DIFF 100M DIFF
REFCLK_P 1
CLKREQ_LAN# CLK_PCIE_LAN CLK_PCIE_LAN#
configure as SATA output
SEL_SATA
1 * 0 * configure as normal SRC(SRC_6) output * default
configure as 27M and 27M_SS output
27M_SEL 0 configure as SRC_7 output * default
CLKREQ_LAN# <26> CLK_PCIE_LAN <26> CLK_PCIE_LAN# <26>
LAN
REFCLK_N
14M SE (1.8V) NC
14M SE (1.1V) vref
GFX_REFCLK
100M DIFF
100M DIFF(IN/OUT)*
GPP_REFCLK
100M DIFF
NC or 100M DIFF OUTPUT
GPPSB_REFCLK
100M DIFF
100M DIFF
4
4
Use voltage divider resistor R379 & R380 to pull low 1
/
configure as single-ended 66MHz output
0* configure as differential 100MHz output * default
Compal Secret Data
Security Classification 2009-02-12
Issued Date
NB_OSC_14.318M
2009-02-12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
Compal Electronics, Inc.
B
C
D
Clock Generator Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
16
of
44
A
B
C
D
E
+5VS
< CRT CONNECTOR >
+R_CRT_VCC
D36
+CRT_VCC F2 2 1.1A_6V_MINISMDC110F-2
2 1
1
3
1 RB491D_SOT23-3
C475 0.1U_0402_16V4Z
1
1
1
2
D35 DAN217_SC59 @
@
D37 DAN217_SC59 @
D34 DAN217_SC59
1
1
JCRT 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5
3
2
3
2
3
2
+3VS
RED_L D_DDCDATA GREEN_L
L47 <12> UMA_CRT_R
1
<12> UMA_CRT_G
1
<12> UMA_CRT_B
1
2 NBQ100505T-800Y_0402
RED_L
2 NBQ100505T-800Y_0402
GREEN_L
2 NBQ100505T-800Y_0402
BLUE_L
HSYNC BLUE_L
L48 +CRT_VCC
VSYNC
L49
R217 150_0402_1%
C471 6P_0402_50V8D
2
1
C859 6P_0402_50V8D
2
1
1
C469 6P_0402_50V8D
2
C858 6P_0402_50V8D
2
1
1
C476 6P_0402_50V8D
2
C472 6P_0402_50V8D
220P_0402_50V7K
1
D_DDCCLK
G G
16 17
ALLTO_C10532-11505-L_15P-T
2
2
2
R211 150_0402_1%
2
2
R214 140_0402_1%
1
1
1
C706 1
6 11 1 7 12 2 8 13 3 9 14 4 10 15 5
@
+CRT_VCC 2
2 0.1U_0402_16V4Z
2
R972 2 10K_0402_5%
1
2
A
Y
G
<12,15> UMA_CRT_HSYNC
P OE#
5 1
C473 1
D_HSYNC
4
L84 1
2 10_0402_5%
HSYNC
L83 1
2 10_0402_5%
VSYNC
3
U14 SN74AHCT1G125GW_SOT353-5
< SYNC SIGNAL >
+CRT_VCC 2 0.1U_0402_16V4Z
1
R973 2 10K_0402_5%
1
@
2
A
3
G
<12,15> UMA_CRT_VSYNC
P OE#
5 1
C477 1
C474 10P_0402_50V8J @
2 Y
1
C470 10P_0402_50V8J
2
D_VSYNC
4 U13 SN74AHCT1G125GW_SOT353-5
+CRT_VCC +3VS
2
3
1
3
+3VS
R238 4.7K_0402_5%
R100 6.8K_0402_5% Q10B 3 2N7002DW-7-F_SOT363-6
4 1
<12> UMA_CRT_DATA
D_DDCDATA
C177 33P_0402_50V8K
2
@
R218 6.8K_0402_5%
1
2
5
R237 4.7K_0402_5%
< Display Data Channel >
2
+3VS
Q10A 6 2N7002DW-7-F_SOT363-6
1 1
<12> UMA_CRT_CLK C181 33P_0402_50V8K
@
2
@
D_DDCCLK 1
C857 470P_0402_50V8J
2
1 @
C856 470P_0402_50V8J
2
RS780 DAC_SCL & SDA is 5V tolerance FOR EMI
4
4
/
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc. CRT Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
17
of
44
A
B
C
D
E
< Int. Camera, USB port 9 >
1
1
Int. Camera
< EMI require >
+5V_CAM
CAM@ 0_0402_5%
1 R103
2
R1009 2 1 0_0603_5% @
+5VS L60 2 <21> <21>
USB20_N9 USB20_P9
3
@
2
1
3
4
1
USB20_N9_R USB20_P9_R
4
0_0402_5% 2 2 0_0402_5%
@ @
R1004 1 1 R1005
USB20_N9_R_R USB20_P9_R_R
reserve for test, close to JLVDS
1 2 3 4 5 GND1 GND2
CAM@ 2
1
C888 @ 1 2 0.1U_0402_16V4Z
JCAM
WCM-2012-900T_0805 0_0402_5%
W=20mils
R99
1 2 3 4 5 6 7
USB20_N9_R_R USB20_P9_R_R
ACES_88266-05001 @
2
2
+5V_LVDS_CAM
LVDS & CAMERA
R146 10K_0402_5%
2 L8 1 0_0805_5% C265 0.1U_0402_16V4Z
2
C266 4.7U_0805_10V4Z
+LCD_VDD
+LCDVDD_R +3VS +LCD_INV
Rated Current MAX:3000mA 1
C268 68P_0402_50V8J
2
+3VS
L12 2 1 B+ FBMA-L11-201209-221LMA30T_0805
1
C269 0.1U_0402_25V4Z
2
1
2
+3VS
R142
R143
150_0603_5%
100K_0402_5%
2
2N7002DW-T/R7_SOT363-6
2
1
2
2 4.7K_0402_5%
UMA_LCD_DDC_CLK
1
2 4.7K_0402_5%
UMA_LCD_DDC_DAT
INVT_PWM
AO3413_SOT23
W=60mils
3
Inrush current = 0A
R668 2 0_0402_5%
Q1B ENVDD
2N7002DW-T/R7_SOT363-6
C708 1 2
1
C263
C264
@
5
1
1
2
4.7U_0805_10V4Z
2
0.1U_0402_16V7K
4
<12> UMA_ENVDD
R144 100K_0402_5%
220P_0402_50V7K BKOFF#
0.01U_0402_25V7K
2
1
R69
+LCD_VDD
C875
1
C707 1 2 220P_0402_50V7K
R68
Q2
2 1
47K_0402_5%
2
+3VS
0.1U_0402_16V7K
R140 C267 0.1U_0402_16V4Z
W=60mils 3
1
Q1A
For EMI DAC_BRIG
C874
3
2
1
UMA_LCD_DDC_CLK <12> UMA_LCD_DDC_DAT <12>
+LCD_VDD 1
1
1
ACES_88242-4001
1
LCD/PANEL BD. Conn.
1.5A
DAC_BRIG <32> INVT_PWM <32>
1
BKOFF#
2
<32>
BKOFF#
+5V_LVDS_CAM UMA_LCD_TXCLK_ACLK+ <12> UMA_LCD_TXCLK_ACLK- <12>
2
3
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41
6 2
USB20_P9_R USB20_N9_R
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 GND
1
+5V_LVDS_CAM
@
G
<12> UMA_LCD_TXOUT0_A2+ <12> UMA_LCD_TXOUT0_A2-
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND
C882 CAM@ 1 2
W=20mils0.1U_0402_16V4Z
D
<12> UMA_LCD_TXOUT0_A1+ <12> UMA_LCD_TXOUT0_A1-
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42
+5VS
S
JLVDS <12> UMA_LCD_TXOUT0_A0+ <12> UMA_LCD_TXOUT0_A0-
R1006 2 1 0_0603_5% CAM@
C709 1 2 220P_0402_50V7K
4
4
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc. LCD CONN. / Camera
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
18
of
44
A
B
C
D
E
+HDMI_5V_OUT_M
+HDMI_5V_OUT
HDMI@ 1
<11> <11> <11> <11> <11> <11>
HDMI_TXD0+ HDMI_TXD0HDMI_TXD1+ HDMI_TXD1HDMI_TXD2+ HDMI_TXD2-
<11> HDMI_CLK0+ <11> HDMI_CLK0-
HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@
C189 C188 C190 C184 C187 C191
HDMI@ HDMI@
C185 1 C186 1
1 1 1 1 1 1
0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K
HDMI_TX0+ HDMI_TX0HDMI_TX1+ HDMI_TX1HDMI_TX2+ HDMI_TX2-
2 0.1U_0402_16V7K 2 0.1U_0402_16V7K
HDMI_CLK+ HDMI_CLK-
2 2 2 2 2 2
D53 1 PMEG2010AEH_SOD123
2
+5VS
1
HDMI@ F3 1 1.1A_6V_MINISMDC110F-2
2
1
Vf=0.25V when If=55mA 2
C258 HDMI@ 0.1U_0402_16V7K
< Place MOSFET close to HDMI connector > < HDMI DDC channel to device > +3VS
+3VS
+HDMI_5V_OUT
< HDMI Connector >
1
R616 0_0402_5%
2
HDMI_R_CK-
HDMI_R_D2+
2
2 1
1
2
2
1
<12> HDMICLK_UMA
HDMI_SCLK
D
@ HDMI_CLK-
3 S
HDMI_R_D1+ HDMI_R_D2-
2
HDMI_SDATA
HDMI@ Q140 BSH111_SOT23-3 1
G
< EMI solution >
HDMI@ R236 2.2K_0402_5%
D
HDMI_R_D0+ HDMI_R_D1-
HDMI@ R210 2.2K_0402_5%
HDMI@ Q139 BSH111_SOT23-3 1
3
<12> HDMIDAT_UMA
20 21 22 23
S
HDMI_R_CK+ HDMI_R_D0-
HDMI@ R209 4.7K_0402_5%
2
HDMI_R_CK-
HDMI@ R176 4.7K_0402_5%
1
2
@
HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+
G
HDMI_SDATA HDMI_SCLK
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
2
JHDMI HDMI_HPD +HDMI_5V_OUT
TYCO_1939864-1_19P
3
2
R618 0_0402_5%
HDMI@ HDMI@
@ 1
1
HDMI_R_CK-
1
HDMI_R_D0-
R307 2 715_0402_1% 2 715_0402_1% R315
HDMI@ L86
3
1
2
2 +5VS
2
WCM-2012-900T_0805 @ HDMI_TX0+
1
2
R619 0_0402_5%
HDMI_R_D0+
2
R620 0_0402_5%
HDMI_R_D1-
@ HDMI_TX1-
1
L87 1 4
HDMI@ HDMI_R_D0-
1
HDMI_R_D0+
1
R304 2 715_0402_1% 715_0402_1% R172
4
3
3
1
HDMI_R_D1+
1
R297 2 715_0402_1%
R621 0_0402_5%
1
HDMI_R_D1+
2
R623 0_0402_5%
HDMI_R_D2-
715_0402_1% R173
3
3
1
2
2
HPD
+5VS
HDMI_R_D2+
1
R141 2 715_0402_1%
HDMI_R_D2-
1
2 HDMI@
1
R588 2.2K_0402_5% HDMI@
+5VS
Q137B 3
HPD
<12,21>
715_0402_1% R139
R977 100K_0402_5%
4 2N7002DW-7-F_SOT363-6
HDMI@
4
+3VS Q137A 1 2N7002DW-7-F_SOT363-6
6
2
HDMI@ L88
C850 HDMI@ 0.1U_0402_16V4Z
2
2 @
1
5
@
4
U39 SN74AHCT1G125GW_SOT353-5 HDMI@
HDMI@ HDMI@ HDMI_R_D1-
2
R628 HDMI@ 100K_0402_5%
HPD
Y
HDMI@
2
2
1
4
4 2N7002DW-7-F_SOT363-6
4
A
HDMI@
1
HDMI@
HDMI_TX2-
2
2 HDMI@
WCM-2012-900T_0805 HDMI_TX1+
1
C851 HDMI@ 0.1U_0402_16V4Z
Q136B 3
3
HDMI_HPD
3
1
1
4
2
4
+HDMI_5V_OUT +5VS
HDMI@
5
3
< Hot-plug detection & level shift >
Q136A 1 2N7002DW-7-F_SOT363-6
6
HDMI@
4
1
HDMI_TX0-
HDMI_R_CK+
2
2
< Termination resistor > HDMI_R_CK+
1
1
R617 0_0402_5%
5 1
@ HDMI_CLK+
P OE#
3
WCM-2012-900T_0805
G
2
4
3
1
2
2
4
HDMI@
2
L85 1
WCM-2012-900T_0805 @ HDMI_TX2+
1
2
R624 0_0402_5%
Compal Secret Data
Security Classification HDMI_R_D2+
2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
HDMI Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
19
of
44
A
B
C
D
E
+3VALW C506 1 0.1U_0402_16V4Z
U16 NC7SZ08P5X_NL_SC70-5
2
B
Y
1
R303 2 100_0402_5%
@ 1
C501 2 100P_0402_50V8J
A
4
PLT_RST#
PLT_RST# <12,15,26,27,31,32>
CLK_PCI_SIO2 @ 1
R369 2 100_0402_5%
@ 1
C503 2 100P_0402_50V8J
3
G
NB_RST#_R
@ 1
CLK_PCI_EC
P
5
2
1 33_0402_5%
U15A N2
< x4 PCIE A-link To NB >
< x4 PCIE A-link from NB >
<11> <11> <11> <11> <11> <11> <11> <11>
SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N
<11> <11> <11> <11> <11> <11> <11> <11>
SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N
C492 C493 C494 C495 C496 C497 C498 C499
R305 R306
+PCIE_VDDR +1.2V_HT
1 1 1 1 1 1 1 1
L53 1
2 2 2 2 2 2 2 2
0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K
SB_RX0P_C SB_RX0N_C SB_RX1P_C SB_RX1N_C SB_RX2P_C SB_RX2N_C SB_RX3P_C SB_RX3N_C
V23 V22 V24 V25 U25 U24 T23 T22
SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N
U22 U21 U19 V19 R20 R21 R18 R17
1 562_0402_1% 1 2.05K_0402_1%
2 2
2 BLM18PG121SN1D_0603 1 C504 2.2U_0603_6.3V4Z
T25 T24
SB700 A_RST#
Part 1 of 5
PCI CLKS
@
PCIE_TX0P PCIE_TX0N PCIE_TX1P PCIE_TX1N PCIE_TX2P PCIE_TX2N PCIE_TX3P PCIE_TX3N
PCIRST#
PCIE_RX0P PCIE_RX0N PCIE_RX1P PCIE_RX1N PCIE_RX2P PCIE_RX2N PCIE_RX3P PCIE_RX3N PCIE_CALRP PCIE_CALRN
+SB_PCIEVDD P24
PCIE_PVDD
P25
PCIE_PVSS
PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5/GPIO41
PCI EXPRESS INTERFACE
R312 2 1
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 CBE0# CBE1# CBE2# CBE3# FRAME# DEVSEL# IRDY# TRDY# PAR STOP# PERR# SERR# REQ0# REQ1# REQ2# REQ3#/GPIO70 REQ4#/GPIO71 GNT0# GNT1# GNT2# GNT3#/GPIO72 GNT4#/GPIO73 CLKRUN# LOCK#
2
2
Close to SB
K23 K22 M24 M25 P17 M18 M23 M22 J19 J18 L20 L19 M19 M20 N22 P22
3
SB_14.318M
<16> SB_14.318M
L18 J21
C643 2 18P_0402_50V8J
Close to SB
GPP_CLK0P GPP_CLK0N GPP_CLK1P GPP_CLK1N GPP_CLK2P GPP_CLK2N GPP_CLK3P GPP_CLK3N 25M_48M_66M_OSC 25M_X1
25M_X2
IN
NC
3
NC
2
SB_32KHI
32.768KHZ_12.5P_1TJS125BJ4A421P SB_32KHO
CPU_LDT_REQ# H_PROCHOT# H_PWRGD LDT_STOP# LDT_RST#
A3
B3
F23 F24 F22 G25 G24
X1
X2
ALLOW_LDTSTP PROCHOT# LDT_PG LDT_STP# LDT_RST#
LPC
OUT
<7,12> CPU_LDT_REQ# <7> H_PROCHOT# <7,42> H_PWRGD <7,12> LDT_STOP# <7> LDT_RST#
H_PROCHOT#
SLT_GFX_CLKP SLT_GFX_CLKN
INTE#/GPIO33 INTF#/GPIO34 INTG#/GPIO35 INTH#/GPIO36 LPCCLK0 LPCCLK1 LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ0# LDRQ1#/GNT5#/GPIO68 BMREQ#/REQ5#/GPIO65 SERIRQ RTCCLK INTRUDER_ALERT# VBAT
RTC
1 10K_0402_5%
CPU_HT_CLKP CPU_HT_CLKN
CPU
R319 2
+3VS
1
2
C652 2 18P_0402_50V8J
NB_HT_CLKP NB_HT_CLKN
RTC XTAL
4 R389 20M_0603_5%
1
J20
NB_DISP_CLKP NB_DISP_CLKN
Y3
1
1
PCIE_RCLKP/NB_LNK_CLKP PCIE_RCLKN/NB_LNK_CLKN
PCI INTERFACE
N25 N24
CLOCK GENERATOR
CLK_SBSRC_BCLK CLK_SBSRC_BCLK#
<16> CLK_SBSRC_BCLK <16> CLK_SBSRC_BCLK#
4
+SB_VBAT
+RTCVCC R316 2 120_0402_5%
1
R317 2 120_0402_5%
N1 U2 P7 V4 T1 V3 U1 V1 V2 T2 W1 T9 R6 R7 R5 U8 U5 Y7 W8 V9 Y8 AA8 Y4 Y3 Y2 AA2 AB4 AA1 AB3 AB2 AC1 AC2 AD1 W2 U7 AA7 Y1 AA6 W5 AA5 Y5 U6 W6 W4 V7 AC3 AD4 AB7 AE6 AB6 AD2 AE4 AD5 AC6 AE5 AD6 V5
2
PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PAD T18 PAD T26
PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28
<24> <24> <24> <24> <24> <24>
PAD T15
3
PAD T16
AD3 AC4 AE2 AE3 R308 G22 CLK_PCI_EC1 1 2 E22 CLK_PCI_SIOC R310 1 2 LPC_AD0 H24 LPC_AD0 LPC_AD1 H23 LPC_AD1 LPC_AD2 J25 LPC_AD2 LPC_AD3 J24 LPC_AD3 H25 LPC_FRAME#_SB PUMA@ 1 H22 AB8 R979 1 AD7 TIGRIS@ V15 SERIRQ SERIRQ C3 C2 B2
RTC_CLK
22_0402_5% CLK_PCI_EC <24,32> 22_0402_5% CLK_PCI_SIO2 <24,31> <31,32> <31,32> <31,32> <31,32> D84 PUMA@ R978 2 CH751H-40PT_SOD323-2 2 1 300_0402_5%
EC & TPM &Debug
2 0_0402_5%
+3VS
LPC_FRAME# <31,32>
<31,32>
RTC_CLK <24>
STRAP PIN
+SB_VBAT
SB700R3@ 4
D10
R184 1 1K_0402_5%
2
<24> <24> <24> <24>
3
C510 1U_0402_6.3V4Z
2
1 2
@ 1
0.1U_0402_16V7K
W=20mils
1
PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5
218S7EALA11FG_BGA528_SB700
+RTCBATT
J1 JUMP_43X39
C297 0.1U_0402_16V7K
1
2
C509
1
PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5
2
1 1
P4 P3 P1 P2 T4 T3
1
2009-02-12
Issued Date
2
Compal Secret Data
Security Classification
2
2009-02-12
Deciphered Date
Title
SB700 - PCIE / PCI / ACPI / LPC / RTC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CHGRTC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Date:
A
B
Compal Electronics, Inc.
BAS40-04_SOT23-3
C
D
Document Number
Rev 1.0
LA-5831P Wednesday, August 12, 2009
Sheet E
20
of
44
A
B
C
D
E
+3VALW R320 2.2K_0402_5%
SB_TEST2
2
R321 2.2K_0402_5%
SB_TEST1
1
@
@
1
2
R322 2.2K_0402_5%
Reserve for EMI request U15D
E1 E2 H7 PM_SLP_S3# F5 PM_SLP_S5# G1 PBTN_OUT# H2 SB_PWRGD H1 SUS_STAT# K3 SB_TEST2 H5 SB_TEST1 H4 SB_TEST0 H3 GATEA20 Y15 KB_RST# W15 EC_SCI# K4 EC_SMI# K24 F1 J2 LAN_WAKE# H6 F2 H_THERMTRIP# J6 NB_PWRGD W14
SB_TEST0
2
1
R561 1K_0402_5%
LAN_WAKE#
2
1
R330 100K_0402_5%
EXP_CPPE#
<32> <32> <32> <32,42> <12,15>
PM_SLP_S3# PM_SLP_S5# PBTN_OUT# SB_PWRGD SUS_STAT#
Reserve pull-high for EXP_CPPE# <32> <32> <32> <32>
+3VS 1 1
2
R328 1.2K_0402_5%
SMB_CK_CLK0
2
R329 1.2K_0402_5%
SMB_CK_DAT0
GATEA20 KB_RST# EC_SCI# EC_SMI#
<26> LAN_WAKE#
<7> H_THERMTRIP# <12> NB_PWRGD
EC_RSMRST#
<32> EC_RSMRST#
D3
PCI_PME#/GEVENT4# RI#/EXTEVNT0# SLP_S2/GPM9# SLP_S3# SLP_S5# PWR_BTN# PWR_GOOD SUS_STAT# TEST2 TEST1 TEST0 GA20IN/GEVENT0# KBRST#/GEVENT1# LPC_PME#/GEVENT3# LPC_SMI#/EXTEVNT1# S3_STATE/GEVENT5# SYS_RESET#/GPM7# WAKE#/GEVENT8# BLINK/GPM6# SMBALERT#/THRMTRIP#/GEVENT2# NB_PWRGD
USBCLK/14M_25M_48M_OSC USB_RCOMP
USB_FSD13P USB_FSD13N
USB_HSD9P USB_HSD9N
RSMRST#
SMB_CK_CLK1
1
2
R332 2.2K_0402_5%
SMB_CK_DAT1
< S0~ S5 ASF only >
2
1
<29> SB_SPKR <9,10,16> SMB_CK_CLK0 <9,10,16> SMB_CK_DAT0 <27> SMB_CK_CLK1 <27> SMB_CK_DAT1
EC_RSMRST#
@ 1
+3VS +3VS
HDMI@
1
R388 2 4.7K_0402_5%
AE18 AD18 AA19 W17 V17 W20 SB_SPKR W21 SMB_CK_CLK0 AA18 SMB_CK_DAT0 W18 SMB_CK_CLK1 K1 SMB_CK_DAT1 K2 AA20 Y18 C1 Y19 G5
1
<12,19> HPD
R400 2 4.7K_0402_5% R980 2 0_0402_5%
SATA_IS0#/GPIO10 CLK_REQ3#/SATA_IS1#/GPIO6 SMARTVOLT1/SATA_IS2#/GPIO4 CLK_REQ0#/SATA_IS3#/GPIO0 CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40 SPKR/GPIO2 SCL0/GPOC0# SDA0/GPOC1# SCL1/GPOC2# SDA1/GPOC3# DDC1_SCL/GPIO9 DDC1_SDA/GPIO8 LLB#/GPIO66 SMARTVOLT2/SHUTDOWN#/GPIO5 DDR3_RST#/GEVENT7#
USB_HSD7P USB_HSD7N
USB 2.0
R331 2.2K_0402_5%
GPIO
2
2
USB_HSD11P USB_HSD11N USB_HSD10P USB_HSD10N
+3VALW
R327 100K_0402_5%
USB_FSD12P USB_FSD12N
USB_HSD8P USB_HSD8N
1
R311 2 100_0402_5%
1
SUS_STAT#
For BIOS utility support
<31> HDA_SYNC_MDC <29> HDA_SYNC_CODEC
3
STRAP
<29> HDA_RST#_CODEC <31> HDA_RST#_MDC PIN<24> HDARST#
For EMI Close to U15
R333 R334 R335 R336
1 2 33_0402_5% 1 MDC@ 2 33_0402_5% 1 MDC@ 2 33_0402_5% 1 2 33_0402_5%
HDA_BITCLK HDA_SDOUT HDA_SDIN0 HDA_SDIN1
R337 R338
1 MDC@ 2 33_0402_5% 1 2 33_0402_5%
HDA_SYNC
R339 R340
1 2 33_0402_5% 1 MDC@ 2 33_0402_5%
HDARST#
1
M1 M2 J7 J8 L8 M3 L6 M4 L5
AZ_BITCLK AZ_SDOUT AZ_SDIN0/GPIO42 AZ_SDIN1/GPIO43 AZ_SDIN2/GPIO44 AZ_SDIN3/GPIO46 AZ_SYNC AZ_RST# AZ_DOCK_RST#/GPM8#
C619 100P_0402_50V8J
H19 H20 H21 F25 D22 E24 E25 D23
IMC_GPIO0 IMC_GPIO1 SPI_CS2#/IMC_GPIO2 IDE_RST#/F_RST#/IMC_GPO3 IMC_GPIO4 IMC_GPIO5 IMC_GPIO6 IMC_GPIO7
INTEGRATED uC
2
218S7EALA11FG_BGA528_SB700
1
2 11.8K_0402_1%
H11 J10 E11 F11 A11 B11
USB20_P9 USB20_N9
C10 D10
USB20_P8 USB20_N8
USB20_P9 <18> USB20_N9 <18>
USB-9 Int Camera
USB20_P8 <27> USB20_N8 <27>
USB-8 WLAN
G11 H12
B12 A12
USB_HSD3P USB_HSD3N
G12 G14
IMC_GPIO26 IMC_GPIO27 IMC_GPIO28 IMC_GPIO29 IMC_GPIO30 IMC_GPIO31 IMC_GPIO32 IMC_GPIO33 IMC_GPIO34 IMC_GPIO35 IMC_GPIO36 IMC_GPIO37 IMC_GPIO38 IMC_GPIO39 IMC_GPIO40 IMC_GPIO41
USB_RCOMP
F7 E8
USB_HSD4P USB_HSD4N
IMC_GPIO18 IMC_GPIO19 IMC_GPIO20 IMC_GPIO21 IMC_GPIO22 IMC_GPIO23 IMC_GPIO24 IMC_GPIO25
CLK_48M_USB <16>
E6 E7
C12 D12
IMC_GPIO8 IMC_GPIO9 IMC_PWM0/IMC_GPIO10 SCL2/IMC_GPIO11 SDA2/IMC_GPIO12 SCL3_LV/IMC_GPIO13 SDA3_LV/IMC_GPIO14 IMC_PWM1/IMC_GPIO15 IMC_PWM2/IMC_GPO16 IMC_PWM3/IMC_GPO17
INTEGRATED uC
HDA_BITCLK_CODEC HDA_BITCLK_MDC HDA_SDOUT_MDC HDA_SDOUT_CODEC HDA_SDIN0 HDA_SDIN1
USB OC
<29> <31> <31> <29> <29> <31>
USB_OC6#/IR_TX1/GEVENT6# USB_OC5#/IR_TX0/GPM5# USB_OC4#/IR_RX0/GPM4# USB_OC3#/IR_RX1/GPM3# USB_OC2#/GPM2# USB_OC1#/GPM1# USB_OC0#/GPM0#
HD AUDIO
<32> EC_LID_OUT# <25,32> USB_OC#2 <25,32> USB_OC#0
G8
USB_HSD5P USB_HSD5N
USB_HSD0P USB_HSD0N
CLK_48M_USB R323
E12 E14
USB_HSD1P USB_HSD1N B9 B8 A8 A9 E5 F8 E4
C617 2 100P_0402_50V8J 1
C8
USB_HSD6P USB_HSD6N
USB_HSD2P USB_HSD2N
HPD_R
EC_LID_OUT# EXP_CPPE#
1
Part 4 of 5
SB700
USB MISC
1
2
USB 1.1
@
1
ACPI / WAKE UP EVENTS
@
2
USB20_P4 USB20_N4
H14 H15
USB20_P2 USB20_N2
A13 B13
USB20_P1 USB20_N1
B14 A14
USB20_P0 USB20_N0
A18 B18 F21 D21 F19 E20 E21 E19 D19 E18
GPIO16 GPIO17
USB20_P4 <28> USB20_N4 <28>
USB-4 Card Reader (3 IN 1)
USB20_P2 <25> USB20_N2 <25>
USB-2 Left USB
USB20_P1 <25> USB20_N1 <25>
USB-1 Right side
USB20_P0 <25> USB20_N0 <25>
USB-0 Right side
GPIO16 <24> GPIO17 <24>
STRAP PIN STRAP PIN
G20 G21 D25 D24 C25 C24 B25 C23
3
B24 B23 A23 C22 A22 B22 B21 A21 D20 C20 A20 B20 B19 A19 D18 C18
SB700R3@
4
4
/
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
SB700 USB / AC97 Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
21
of
44
A
B
C
D
E
U15B
<25> SATA_RXN3_C <25> SATA_RXP3_C
AE10 AD10
SATA_TX1P SATA_TX1N
SATA_RXN1_C SATA_RXP1_C
AD11 AE11
SATA_RX1N SATA_RX1P
AB12 AC12
SATA_TX2P SATA_TX2N
AE12 AD12
SATA_RX2N SATA_RX2P
SATA_STX_DRX_P3 SATA_STX_DRX_N3
AD13 AE13
SATA_TX3P SATA_TX3N
SATA_RXN3_C SATA_RXP3_C
AB14 AC14 AE14 AD14 AD15 AE15 AB16 AC16 AE16 AD16
+3VS 2
2
R342 1 1K_0402_1%
1
R343 2 10K_0402_5%
SATA_CAL V12
<33> SATA_LED# +1.2V_HT
L54 BLM18PG121SN1D_0603 2
SATA_X1
Y12
SATA_X2
AA12
SATA_LED#
W11
+PLLVDD_SATA AA11
1 2
2 W12
C522 2.2U_0603_6.3V4Z
+3VS
L55 BLM18PG121SN1D_0603 2
C523 1
C524 1U_0402_6.3V4Z
SATA_RX3N SATA_RX3P SATA_TX4P SATA_TX4N SATA_RX4N SATA_RX4P
2
1
2
IDE_D0/GPIO15 IDE_D1/GPIO16 IDE_D2/GPIO17 IDE_D3/GPIO18 IDE_D4/GPIO19 IDE_D5/GPIO20 IDE_D6/GPIO21 IDE_D7/GPIO22 IDE_D8/GPIO23 IDE_D9/GPIO24 IDE_D10/GPIO25 IDE_D11/GPIO26 IDE_D12/GPIO27 IDE_D13/GPIO28 IDE_D14/GPIO29 IDE_D15/GPIO30
SATA_TX5P SATA_TX5N SATA_RX5N SATA_RX5P SATA_CAL SATA_X1
PLLVDD_SATA XTLVDD_SATA
LAN_RST#/GPIO13 ROM_RST#/GPIO14
U15 J1
C625 0.1U_0402_16V4Z
P5 P8 R8
TEMP_COMM TEMPIN0/GPIO61 TEMPIN1/GPIO62 TEMPIN2/GPIO63 TEMPIN3/TALERT#/GPIO64
C6 B6 A6 A5 B5
AVDD AVSS
218S7EALA11FG_BGA528_SB700
SPK_SEL EC_THERM#
A4 B4 C4 D4 D5 D6 A7 B7
ACIN_SB
F6
+SB_AVDD 1
G7 2
SPK_SEL <29> EC_THERM# <32>
L56 1
C525 0.1U_0402_16V4Z
2
2
D41 1 CH751H-40PT_SOD323-2
ACIN
1
R562 2 150K_0402_5%
+3VALW
2
1 0_0603_5%
+3VALW
<32,33,35>
C526 2.2U_0603_6.3V4Z
3
SATA_X1
1
R341
25MHz_20pF_6X25000017 SATA_X2
1
10M_0402_5% 2
2
Y4 C517 10P_0402_50V8J 2
SB700R3@
2
1
C516 10P_0402_50V8J 2
1
3
M8 M5 M7
FANIN0/GPIO50 FANIN1/GPIO51 FANIN2/GPIO52
VIN0/GPIO53 VIN1/GPIO54 VIN2/GPIO55 VIN3/GPIO56 VIN4/GPIO57 VIN5/GPIO58 VIN6/GPIO59 VIN7/GPIO60
1
AD24 AD23 AE22 AC22 AD21 AE20 AB20 AD19 AE19 AC20 AD20 AE21 AB22 AD22 AE23 AC23
G6 D2 D1 F4 F3
FANOUT0/GPIO3 FANOUT1/GPIO48 FANOUT2/GPIO49
SATA_ACT#/GPIO67
AA24 AA25 Y22 AB23 Y23 AB24 AD25 AC25 AC24 Y25 Y24
SPI_DI/GPIO12 SPI_DO/GPIO11 SPI_CLK/GPIO47 SPI_HOLD#/GPIO31 SPI_CS1#/GPIO32
SATA_X2
1 0.1U_0402_16V4Z
+XTLVDD_SATA 1
1
ATA 66/100/133
<25> SATA_STX_DRX_P3 <25> SATA_STX_DRX_N3
SATA_STX_DRX_P1 SATA_STX_DRX_N1
IDE_IORDY IDE_IRQ IDE_A0 IDE_A1 IDE_A2 IDE_DACK# IDE_DRQ IDE_IOR# IDE_IOW# IDE_CS1# IDE_CS3#
Part 2 of 5
SPI ROM
ODD
<25> SATA_RXN1_C <25> SATA_RXP1_C
SATA_RX0N SATA_RX0P
HW MONITOR
1
<25> SATA_STX_DRX_P1 <25> SATA_STX_DRX_N1
AB10 AC10
SERIAL ATA
HDD
SB700 SATA_TX0P SATA_TX0N
SATA PWR
AD9 AE9
4
4
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc. SB700 SATA / IDE / SPI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
22
of
44
B
C
D
E
U15E
U15C
2
1
22U_0805_6.3V6M
@ C531 @ C530 @ C533 @ C536 @ C535
1 1 1 1 1
2 2 2 2 2
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
@ C539 @ C541 @ C542
1 1 1
2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12
Y20 AA21 AA22 AE25
VDD33_18_1 VDD33_18_2 VDD33_18_3 VDD33_18_4
Part 3 of 5
CORE S0
@ C528
PCI/GPIO I/O
+3VS
1
SB700
L9 M9 T15 U9 U16 U17 V8 W7 Y6 AA4 AB5 AB21
VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9
L15 M12 M14 N13 P12 P14 R11 R15 T16
+1.2V_HT_R
1
R593 0_0805_5%
2
SB700
+1.2V_HT
10U_0805_6.3V6M
1
2
C529
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
2 2 2 2
1 1 1 1
C532 C534 C538 C537
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2
1 1
C527 C540
T10 U10 U11 U12 V11 V14 W9 Y9 Y11 Y14 Y17 AA9 AB9 AB11 AB13 AB15 AB17 AC8 AD8 AE8
No IDE device unmount CAP
1
4.7U_0805_10V6K
C553 C555 C554 C558
2 @ 2 2 2
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1 1 1 1
C557 1 C560 1
P18 P19 P20 P21 R22 R24 R25
PCIE_VDDR_1 PCIE_VDDR_2 PCIE_VDDR_3 PCIE_VDDR_4 PCIE_VDDR_5 PCIE_VDDR_6 PCIE_VDDR_7
AA14 AB18 AA15 AA17 AC18 AD17 AE17
AVDD_SATA_1 AVDD_SATA_4 AVDD_SATA_2 AVDD_SATA_3 AVDD_SATA_5 AVDD_SATA_6 AVDD_SATA_7
2
2
L63 1 0_0805_5% 2 C566
1 22U_0805_6.3V6M
C567 1 C568 1
2 1U_0402_6.3V4Z 2 1U_0402_6.3V4Z
C571 1 C572 1
2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z
SATA I/O
+1.2V_SATA +1.2V_HT
+1.2V_HT
+1.2V_HT
1
POWER
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2
L21 L22 L24 L25
+S5_3V
3.3V_S5 I/O
C552 2
CLKGEN I/O
L61 1 0_0805_5%
CKVDD_1.2V_1 CKVDD_1.2V_2 CKVDD_1.2V_3 CKVDD_1.2V_4
CORE S5
2
IDE/FLSH I/O
+PCIE_VDDR +1.2V_HT
A-LINK I/O
+3VS
S5_3.3V_1 S5_3.3V_2 S5_3.3V_3 S5_3.3V_4 S5_3.3V_5 S5_3.3V_6 S5_3.3V_7
A17 A24 B17 J4 J5 L1 L2
R564 0_0805_5%
2
1
2 @ C556
2.2U_0603_6.3V4Z 2.2U_0603_6.3V4Z
2 2
1 1
C559 C561
1U_0402_6.3V4Z
2
1
C562
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2
1 1 1
C563 C564 C565
L64 0_0603_5%
+S5_1.2V
1U_0402_6.3V4Z 2 1U_0402_6.3V4Z 2 S5_1.2V_1 S5_1.2V_2
USB_PHY_1.2V_1 USB_PHY_1.2V_2
+3VALW
22U_0805_6.3V6M
A15 B15 C14 D8 D9 D11 D13 D14 D15 E15 F12 F14 G9 H9 H17 J9 J11 J12 J14 J15 K10 K12 K14 K15
+1.2VALW C569 C570
1 1
G2 G4 L65 0_0603_5% A10 B10
+1.2_USB
+1.2VALW
10U_0805_10V4Z 1
2 @ C573
1U_0402_6.3V4Z
2
1
C574
0.1U_0402_16V4Z
2
1
C575
AVSS_SATA_1 AVSS_SATA_2 AVSS_SATA_3 AVSS_SATA_4 AVSS_SATA_5 AVSS_SATA_6 AVSS_SATA_7 AVSS_SATA_8 AVSS_SATA_9 AVSS_SATA_10 AVSS_SATA_11 AVSS_SATA_12 AVSS_SATA_13 AVSS_SATA_14 AVSS_SATA_15 AVSS_SATA_16 AVSS_SATA_17 AVSS_SATA_18 AVSS_SATA_19 AVSS_SATA_20
AVSS_USB_1 AVSS_USB_2 AVSS_USB_3 AVSS_USB_4 AVSS_USB_5 AVSS_USB_6 AVSS_USB_7 AVSS_USB_8 AVSS_USB_9 AVSS_USB_10 AVSS_USB_11 AVSS_USB_12 AVSS_USB_13 AVSS_USB_14 AVSS_USB_15 AVSS_USB_16 AVSS_USB_17 AVSS_USB_18 AVSS_USB_19 AVSS_USB_20 AVSS_USB_21 AVSS_USB_22 AVSS_USB_23 AVSS_USB_24
+AVDD_USB
3
L66 1 0_0805_5% C576 1 C577 1
2 10U_0805_10V4Z 2 10U_0805_10V4Z
C580 1 C581 1
2 1U_0402_6.3V4Z 2 1U_0402_6.3V4Z
C583 1 C582 1 C584 1
2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z
A16 B16 C16 D16 D17 E17 F15 F17 F18 G15 G17 G18
AVDDTX_0 AVDDTX_1 AVDDTX_2 AVDDTX_3 AVDDTX_4 AVDDTX_5 AVDDRX_0 AVDDRX_1 AVDDRX_2 AVDDRX_3 AVDDRX_4 AVDDRX_5
V5_VREF AVDDCK_3.3V
PLL
2
USB I/O
+3VALW
AVDDCK_1.2V AVDDC
AE7
+V5_VREF
J16
+AVDDCK_3.3V
K17
+AVDDCK_1.2V
E9
+AVDDC
2
1
2
2
C578 0.1U_0402_16V4Z
0.1U_0402_16V4Z
+AVDDCK_1.2V
+AVDDCK_3.3V
R346 1 1K_0402_5%
+5VS
1
D14 2 CH751H-40PT_SOD323-2
+3VS
1U_0603_10V4Z
L67 1 0_0603_5%
2.2U_0603_6.3V4Z
218S7EALA11FG_BGA528_SB700 SB700R3@
1
2 C579
H18 J17 J22 K25 M16 M17 M21 P16 F9
+3VALW
PCIE_CK_VSS_1 PCIE_CK_VSS_2 PCIE_CK_VSS_3 PCIE_CK_VSS_4 PCIE_CK_VSS_5 PCIE_CK_VSS_6 PCIE_CK_VSS_7 PCIE_CK_VSS_8 AVSSC
GROUND
A
VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50
PCIE_CK_VSS_9 PCIE_CK_VSS_10 PCIE_CK_VSS_11 PCIE_CK_VSS_12 PCIE_CK_VSS_13 PCIE_CK_VSS_14 PCIE_CK_VSS_15 PCIE_CK_VSS_16 PCIE_CK_VSS_17 PCIE_CK_VSS_18 PCIE_CK_VSS_19 PCIE_CK_VSS_20 PCIE_CK_VSS_21
Part 5 of 5
AVSSCK
2
1
C585
218S7EALA11FG_BGA528_SB700
2
1
C586
SB700R3@
L68 1 0_0603_5%
2 2.2U_0603_6.3V4Z
2
1
C587
0.1U_0402_16V4Z
2
1
C588
L69 1 0_0603_5%
2 2.2U_0603_6.3V4Z
2
1 C589
0.1U_0402_16V4Z
2
1 C590
A2 A25 B1 D7 F20 G19 H8 K9 K11 K16 L4 L7 L10 L11 L12 L14 L16 M6 M10 M11 M13 M15 N4 N12 N14 P6 P9 P10 P11 P13 P15 R1 R2 R4 R9 R10 R12 R14 T11 T12 T14 U4 U14 V6 Y21 AB1 AB19 AB25 AE1 AE24
1
2
P23 R16 R19 T17 U18 U20 V18 V20 V21 W19 W22 W24 W25 L17
3
+1.2V_HT
+3VS
4
4
/
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
SB700 Power / GND Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
23
of
44
B
C
REQUIRED STRAPS
NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLK5
LPC_CLK0
LPC_CLK1
RTC_CLK AZ_RST_CD#
BOOTFAIL TIMER ENABLED
USE DEBUG STRAPS
RESERVED
RESERVED
ENABLE PCI MEM BOOT
CLKGEN ENABLED
INTERNAL RTC
EC ENABLED
DEFAULT
DEFAULT
+3VALW
1 R352
R353
@
@
+3VALW
+3VALW
R355
R356
2.2K_0402_5%
2.2K_0402_5%
@
10K_0402_5% 2
10K_0402_5%
L,H = LPC ROM (Default) L,L = FWH ROM
R354
@
10K_0402_5%
2
2
+3VALW
1 R351
@ 10K_0402_5%
DEFAULT
10K_0402_5% 2
R350 @
10K_0402_5%
2
2
1
1 R349
@ 10K_0402_5%
+3VALW
2
R348 @
10K_0402_5%
+3VALW
2
R347 @
+3VS
1
1
+3VS
DEFAULT
EC DISABLED
2
DEFAULT
H,L = SPI ROM
EXT. RTC (PD on X1, apply 32KHz to RTC_CLK)
CLKGEN DISABLED
H,H = Reserved
1
DISABLE PCI MEM BOOT
+3VS
1
+3VS
IGNORE DEBUG STRAPS
GP16
Internal pull up
1
DEFAULT
BOOTFAIL TIMER DISABLED
GP17
1
1
PULL LOW
E
2
PULL HIGH
D
1
A
SI2: mount 2.2K
R358
@
10K_0402_5%
10K_0402_5%
R359
@
R361
R362
10K_0402_5%
10K_0402_5%
10K_0402_5%
1
1
1
1
1
1 R360
R363
R364
R365
2.2K_0402_5%
10K_0402_5%
2.2K_0402_5% 2
2
@ 2
2
2
2
2
2
2
@ 10K_0402_5%
R366 2.2K_0402_5% 2
R357
1
1
2
1
2
PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5 CLK_PCI_EC CLK_PCI_SIO2 RTC_CLK HDARST# GPIO17 GPIO16 1
<20> <20> <20> <20> <20,32> <20,31> <20> <21> <21> <21>
Need to confirm if SB SPI ROM will mount
DEBUG STRAPS SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]
PCI_AD28 PULL HIGH 3
PULL LOW
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
USE PCI PLL
USE ACPI BCLK
USE IDE PLL
USE DEFAULT PCIE STRAPS
RESERVED
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
USE SHORT RESET
BYPASS PCI PLL
BYPASS ACPI BCLK
BYPASS IDE PLL
USE EEPROM PCIE STRAPS
3
1
1
1 R376
R377
@
R378
@
2.2K_0402_5% 2
2
2
R375 @
2.2K_0402_5%
@
2.2K_0402_5%
2.2K_0402_5% 2
@ 2.2K_0402_5%
2.2K_0402_5% 2
R374
@
2
R373
1
1
PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 1
<20> <20> <20> <20> <20> <20>
PCI_AD27
USE LONG RESET
4
4
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
SB700 STRAPS Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
24
of
44
A
B
C
D
SATA HDD Conn. +5VS
SATA ODD Conn
Place closely JHDD0 SATA CONN. 1.2A
1
E
1
C387
2
1
C388
+5VS
1
C389
C390
1.1A JHDD0
10U_0805_10V4Z 2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
@
0.1U_0402_16V4Z GND A+ AGND BB+ GND
1
24 23
V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 V12
GND GND
1 2 3 4 5 6 7
SATA_TXP1 SATA_TXN1 SATA_IRX_DTX_N1 SATA_IRX_DTX_P1
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
C512 1 C513 1
1
2 0.01U_0402_25V7K 2 0.01U_0402_25V7K
C410 1 C412 1
SATA_STX_DRX_P1 <22> SATA_STX_DRX_N1 <22>
2 0.01U_0402_25V7K 2 0.01U_0402_25V7K
2
SATA_RXN1_C <22> SATA_RXP1_C <22>
1
1 C416 @ 10U_0805_10V4Z 1U_0402_6.3V4Z 2 2
C414 10U_0805_10V4Z
C415
1
2
1 C417 0.1U_0402_16V4Z
2
1
C418 0.1U_0402_16V4Z
+3VS
JODD
@
+5VS
GND A+ AGND BB+ GND DP +5V +5V MD GND GND
OCTEK_SAT-22SO1G_RV 15 14
GND GND
1 2 3 4 5 6 7
SATA_TXP3 SATA_TXN3
C518 C519
1 1
2 0.01U_0402_25V7K 2 0.01U_0402_25V7K
SATA_IRX_DTX_N3 C424 SATA_IRX_DTX_P3 C425
1 1
2 0.01U_0402_25V7K 2 0.01U_0402_25V7K
8 9 10 11 12 13
SATA_STX_DRX_P3 <22> SATA_STX_DRX_N3 <22> SATA_RXN3_C <22> SATA_RXP3_C <22>
+5VS
SANTA_206401-1_RV 2
2
USB Right Board
USB Left Conn W=60mils
2A
+5VALW
<32>
USB_EN#0
USB_EN#0
8 7 6 5
GND VOUT VIN VOUT VIN VOUT EN FLG
RT9715BGS_SO8 3
+USB_VCCB
U19
U25 1 2 3 4
W=60mils
2A
+5VALW
+USB_VCCA
1 2 0_0402_5% 1 R422 C438 @ 4.7U_0805_10V4Z 2
1 2 3 4
USB_EN#2
<32> USB_EN#2 USB_OC#0 <21,32>
GND VOUT VIN VOUT VIN VOUT EN FLG
8 7 6 5
1 R584 2 0_0402_5%
RT9715BGS_SO8
1
2
USB_OC#2 <21,32>
C367 4.7U_0805_10V4Z @ 3
For ESD +USB_VCCA
W=60mils R1026
<21>
USB20_N0
1
<21>
USB20_P0
4
1
0_0402_5%
2
L50
@
1
2
4
3
2 3
WCM-2012-900T_0805 R1027
1
USB20_N0_R USB20_P0_R USB20_N1_R USB20_P1_R
JUSBB 1 2 3 4 5 6 7 8 9 10 11 12
1 2 3 4 5 6 7 8 9 10 11 12
@
2 3
1
+
C352
1
C351 2
220U_6.3V_M 2 1000P_0402_50V7K R95 GND GND
1
2 0_0402_5%
13 14 <21>
USB20_N2
1
<21>
USB20_P2
4
0_0402_5%
2
C350
2
ACES_85201-1205N
R1028
0.1U_0402_16V4Z 1 1
PJDLC05_SOT23-3
0_0402_5%
2
W=60mils
+USB_VCCB
D11 1
L46
@
1
2
4
3
JUSB 2
1 2 3 4
USB20_N2_R USB20_P2_R
3
WCM-2012-900T_0805
VCC DD+ GND
@ GND GND GND GND
5 6 7 8
P-TWO_CU304G-A0G1G-P
4
4
L51
@
R96
<21>
USB20_N1
1
1
2
2
<21>
USB20_P1
4
4
3
3
WCM-2012-900T_0805 R1029
1
2
/
2 0_0402_5%
Compal Secret Data
Security Classification 2008/04/14
Issued Date
0_0402_5%
1
2009/04/14
Deciphered Date
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
SATA HDD/ODD Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
25
of
44
A
B
Place Close to Chip CL2 1
2 0.1U_0402_16V7K PCIE_PTX_IRX_P3
20
<11> PCIE_PTX_C_IRX_N3
CL1 1
2 0.1U_0402_16V7K PCIE_PTX_IRX_N3
21
<11> PCIE_ITX_C_PRX_P3
<16> CLK_PCIE_LAN <16> CLK_PCIE_LAN# <16> CLKREQ_LAN#
1
<12,15,20,27,31,32> PLT_RST# 1
PCIE_ITX_C_PRX_P3
15
PCIE_ITX_C_PRX_N3
16
HSOP HSON
HSIN REFCLK_P REFCLK_M
CLKREQ_LAN#
25
CLKREQB
PLT_RST#
27
PERSTB
46 LAN_WAKE# ISOLATEB
26 28
LAN_X1 LAN_X2
41 42
33 34 35 32
LAN_DO LAN_DI LAN_SK_LAN_LINK# LAN_CS
LED0
38
LAN_ACTIVITY#
MDIP0 MDIN0 MDIP1 MDIN1 NC NC NC NC
2 3 5 6 8 9 11 12
LAN_MDI0+ LAN_MDI0LAN_MDI1+ LAN_MDI1-
RTL8103EL-GR
17 18
RL3 2 2.49K_0402_1%
LED3/EEDO LED2/EEDI/AUX LED1/EESK EECS
HSIP
CLK_PCIE_LAN CLK_PCIE_LAN#
<21> LAN_WAKE#
RSET
@
LANWAKEB ISOLATEB
48
VCTRL12A
LAN_WAKE#
23 24
NC NC
7 14 31 47 22
RL2
2
1 1K_0402_5%
+LAN_VDD12
+3V_LAN
Close to Pin10,13,30,36
1
2
CL3 0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
CL5 0.1U_0402_16V4Z
1
AVDD33 NC NC
CL6 0.1U_0402_16V4Z
1
Close to Pin45
VCTRL12
1
CL7 0.1U_0402_16V4Z
+EVDD12 +LAN_VDD12 +EVDD12
Close to Pin19 2
+LAN_VDD12
29 37
1 1
R97 R98
2 0_0402_5% 2 0_0402_5%
1 40 43
1
R105 2 0_0402_5%
1
2
CL8 1U_0402_6.3V4Z
1
CL9 1U_0402_6.3V4Z
+3V_LAN
+3V_LAN
Close to Pin1,37,29
Reserve bead for EMI 2
RTL8103EL-GR_LQFP48_7X7
+3VS
1
2
CL4
+LAN_VDD12
44 45
VDD33 VDD33
GNDTX
2 3.6K_0402_5%
39
NC VCTRL12D
GND GND GND GND
1
2
19 30 36 13 10
VDDTX DVDD12 DVDD12 DVDD12 DVDD12
CKXTAL1 CKXTAL2
T27 PAD RL1
2
NC
RL4 2 10K_0402_5%
E
4
NC
+3V_LAN 1
D
UL1
<11> PCIE_PTX_C_IRX_P3
<11> PCIE_ITX_C_PRX_N3
C
2
CL10 0.1U_0402_16V4Z
1
2
CL11 0.1U_0402_16V4Z
1
CL12 0.1U_0402_16V4Z
1
1 2
2
RL5
2
1K_0402_1% ISOLATEB
R70 @ 2
1
Close to Pin48
VCTRL12
WOL_EN# <32,34>
YL1
1
0_0402_5% RL6 15K_0402_5%
CL13
Reserve R70 for cost down
27P_0402_50V8J
LAN_X1 1
2
1
LAN_X2
25MHz_20pF_6X25000017 2
2
2
CL16
CL21
LAN_ACTIVITY#
2 2
1
CL17 0.01U_0402_25V7K
1
CL19 0.01U_0402_25V7K LAN_MDI1+ LAN_MDI1-
TD+ TDCT NC NC CT RD+ RD-
TX+ TXCT NC NC CT RX+ RX-
16 15 14 13 12 11 10 9
RJ45_MIDI0+ RJ45_MIDI01
CL18 2 1000P_0402_50V8-J
1
CL20 2 1000P_0402_50V8-J
CL15 0.1U_0402_16V4Z
< LAN Conn > 1
JLAN 12 11
RJ45_MIDI1-
1
RL7 2 75_0402_1%
1
RL8 2 75_0402_1%
7
PR4+
5
RJ45_GND CL22
LF-H1201P-2 LAN_SK_LAN_LINK#2
1
2
1
+3V_LAN
2
68P_0402_50V8J 1 RL11 150_0402_1% RL12 150_0402_1%
Yellow LED+ PR4-
6
RJ45_MIDI1+
3
RJ45_MIDI0-
2
RJ45_MIDI0+
1 10 9
@
Yellow LED-
8
4 RJ45_MIDI1+ RJ45_MIDI1-
1
2
Add CL18, CL20 for customer request
UL2 1 2 3 4 5 6 7 8
RL9 1 150_0402_1% RL10 1 150_0402_1%
2 2
+3V_LAN
3
LAN_MDI0+ LAN_MDI0-
10U_0805_10V4Z
27P_0402_50V8J
68P_0402_50V8J
Place these components colsed to LAN chip
2
CL14
@ 1
3
PR2PR3PR3+ PR2+ PR1SHLD2 PR1+ SHLD1
14 13
Green LEDGreen LED+ TYCO_2068888-1_12P-T
RJ45_GND
1
CL23 2 1000P_1808_3KV7K
LANGND 1
2
1
CL24 0.1U_0402_16V4Z
2
CL25 4.7U_0603_6.3V6K
4
4
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc. RTL8103EL 10 / 100 LAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
26
of
44
A
B
C
D
E
< PCIe Mini Card for WLAN/ WiMAX > +1.5VS 1
1
2
CM20 0.01U_0402_25V7K
+3VS
1
2
1
CM21 0.1U_0402_16V4Z
2
1
CM22 4.7U_0805_10V4Z
2
1
CM17 0.01U_0402_25V7K
+1.5VS JWLAN
CLKREQ_MCARD2#
<16> CLKREQ_MCARD2#
CLK_PCIE_MCARD2# CLK_PCIE_MCARD2
<16> CLK_PCIE_MCARD2# <16> CLK_PCIE_MCARD2
PCIE_PTX_C_IRX_N2 PCIE_PTX_C_IRX_P2
<11> PCIE_PTX_C_IRX_N2 <11> PCIE_PTX_C_IRX_P2
PCIE_ITX_C_PRX_N2 PCIE_ITX_C_PRX_P2
<11> PCIE_ITX_C_PRX_N2 <11> PCIE_ITX_C_PRX_P2
+3VS
2
E51_TXD E51_RXD
RM6 RM7
2 0_0402_5% 2 0_0402_5%
1 1
E51_TXD_R E51_RXD_R
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
53
GND1
0.1U_0402_16V4Z
2
RM8 100K_0402_5%
1
CM19 4.7U_0805_10V4Z
+3VS
@ 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
GND2
54
WL_OFF# PLT_RST#
WL_OFF# <32> PLT_RST# <12,15,20,26,31,32>
SMB_CK_CLK1 SMB_CK_DAT1 USB20_N8 USB20_P8
SMB_CK_CLK1 <21> SMB_CK_DAT1 <21> USB20_N8 <21> USB20_P8 <21> 2
1 RN3
2
<32> E51_TXD <32> E51_RXD
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
2
1
CM18
2 PLT_RST# 100K_0402_5%
1
ACES_88911-5204
< R1 for customer BOM STRUCTURE >
< R3 for mass production BOM STRUCTURE >
< PCB >
3
U3
RS780MN
3
U3 ZZZ
RS780MN RS780MN R1 RS780MNR1@
PCB RS780MN R3 RS780MNR3@
PCB 075 LA-5831P REV1 M/B
U3
RS780MC RS780MC R1 RS780MCR1@ U15
SB700 SB700R1 SB700R1@ 4
4
/
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc. WLAN / CAMERA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
27
of
44
5
4
3
CC1
2
2
1 0.1U_0402_16V4Z
RC1
1
1 0_0402_5%
2
UC1 CC2 +3VS_CR RC2 2 0_0603_5%
1
+3VS
D
@
1
1 3 7 9 11 33
1 0.1U_0402_16V4Z
+3VS_CR 1
+3VALW
2
+VCC_3IN1
2
RC3 2 0_0603_5%
1
CC3 0.1U_0402_16V4Z
2
VREG MS_D4 NC
CC4
XTLI
8 44 45 47 48
3V3_IN RST# MODE_SEL XTLO XTLI
USB20_N4 USB20_P4 CR_LED#
4 5 14
DM DP GPIO0
RST#_R MODE SEL
1U_0402_6.3V4Z
<21> <21>
confirm that whether can be removed
AV_PLL NC NC CARD_3V3 D3V3 D3V3
USB20_N4 USB20_P4
2 RC8
1
100K_0402_5%
2
RST#
RC9 1 0_0402_5%
2
RST#_R
CC8 RREF DGND DGND
6 46
AGND AGND
CC5 1U_0402_6.3V4Z
XD_CLE_SP19 XD_CE#_SP18 XD_ALE_SP17 SD_DAT2/XD_RE#_SP16 SD_DAT3/XD_WE#_SP15 XD_RDY_SP14 SD_DAT4/XD_WP#/MS_D7_SP13 SD_DAT5/XD_D0/MS_D6_SP12 SD_CLK/XD_D1/MS_CLK_SP11 SD_DAT6/XD_D7/MS_D3_SP10 MS_INS#_SP9 SD_DAT7/XD_D2/MS_D2_SP8 SD_DAT0/XD_D6/MS_D0_SP7 SD_DAT1/XD_D3/MS_D1_SP6 XD_D5_SP5 XD_D4/SD_DAT1_SP4 SD_CD#_SP3 SD_WP_SP2 XD_CD#_SP1 EEDI
43 42 41 40 39 38 37 35 34 31 29 28 27 26 25 23 21 20 19 18
D
XTAL_CTR MS_D5
13 24
EEDO EECS EESK SD_CMD
15 16 17 36
For EMI SD_DATA2 SD_DATA3
SD_MS_CLK MS_DATA3_SD_DATA6 MSCD# MS_DATA2_SD_DATA7 SD_MS_DATA0 MS_DATA1 MSBS SD_DATA1 SDCD# SDWP#
1
RC4 2 22_0402_5% SDCLK
1
RC6 2 22_0402_5% MSCLK
1 1
@
RC5 2 10_0402_5%
@
CC6 10P_0402_50V8J
@
RC7 2 10_0402_5%
@
CC7 10P_0402_50V8J
XTAL_CTR
SDCMD
2
RC10 0_0402_5%
RC11
C
RC12 RTS5159-VDD-GR 0_0402_5% 1
6.19K_0402_1% 1
2
CC9 0.1U_0402_16V4Z @ 2
1
2
1
MODE SEL
C
2 12 32
1U_0402_6.3V4Z
1
2
+3VS_CR
1
10 22 30
< Card Reader LED > < 3 in 1 Card Reader > JREAD
1 RC13
22
120_0402_5% DC1 HT-110UYG-CT_YEL/GRN
1
Vf=1.9V(typ),2.4V(max) B
CR_LED# 22 23
Cost-down option
1
XTLI
1
RC15 2 0_0402_5%
R925 33_0402_5% @
XTAL_CTR 2
+3VS_CR
1
2
A
R
C
0
NC
SDWP# SD_DATA1 SD_MS_DATA0 MSBS SDCLK MS_DATA1 SD_MS_DATA0 +VCC_3IN1
MS_DATA2_SD_DATA7 1
MSCD# MS_DATA3_SD_DATA6 SDCMD MSCLK
2
CC10 0.1U_0402_16V4Z
1
2
CC11 1U_0402_6.3V4Z B
SD_DATA3 SD_DATA2 SDCD#
YES
NC
47P
YES
NC
NC
NC
680P
@ C919 22P_0402_50V8J
Description
USB AUTO DE-LINK MS FORMATTER
For EMI 1
<16> CLK_48M_CR
RC14 2 0_0402_5%
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
TAITW_R009-125-LR_RV
CR_LED: Low when card reader is being accessed.
< 48MHz >
@
SD-WP SD-DAT1 SD-DAT0 SD-GND MS-GND MS-BS SD-CLK MS-DAT1 MS-DAT0 SD-VCC MS-DAT2 SD-GND MS-INS MS-DAT3 SD-CMD MS-SCLK MS-VCC SD-DAT3 MS-GND GND1 SD-DAT2 GND2 SD-CD
+3VS
Recommended YES Compatible with RTS5158E
YES
LED ON
10K 180P
LED ON A
10K 680P
YES
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc. RTS5159 Card Reader
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet 1
28
of
44
A
B
C
D
E
+3VS_DVDD
30mil
+AVDD 1
1
1
10U_0805_10V4Z
2
1
CA4 10U_0805_10V4Z
2
1
CA5 0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
Ext. Mic CA14 1
MIC2_L
<30>
MIC2_R
<30> MIC1_C_L <30> MIC1_C_R 2 100P_0402_50V8J
<21> HDA_BITCLK_CODEC <21> HDA_SDOUT_CODEC 2
<21> HDA_SDIN0 <21> HDA_RST#_CODEC <21> HDA_SYNC_CODEC <22>
MUTE#
9
1 DVDD
DVDD_IO
38
1
10U_0805_10V4Z
LOUT1_L
35
AMP_SPK_L
LOUT1_R
36
AMP_SPK_R
MIC2_L
16
MIC2_L
LOUT2_L
39
MIC2_R
17
MIC2_R
LOUT2_R
23
LINE1_L
SPDIFO1
48
24
LINE1_R
SPDIFO2
45
MIC1_L
HPOUT_L
33
HPL
RA5
1
2 63.4_0402_1%
HP_L
<30>
MIC1_R
HPOUT_R
32
HPR RA6
1
2 63.4_0402_1%
HP_R
<30>
MIC1_C_L
21
MIC1_C_R
22
MONO_IN
12
HDA_BITCLK_CODEC
6
HDA_SDOUT_CODEC
5
1 33_0402_5% HDA_SDIN0_R
8
HDA_RST#_CODEC
11
HDA_SYNC_CODEC
10 2
13
SENSE_B <30>
2
CA8
LINE2-R
SENSE_A
MUTE#
0.1U_0402_16V4Z
LINE2-L
3
GPIO63-->SPK_SEL HIGH: HARMAN LOW: NO-BRAND
1
CA7
15
SPK_SEL
SPK_SEL
10U_0805_10V4Z
14
RA7 2
AVDD2
AVDD1
UA2
25
2
<30>
2
CA6
Remove LDO
Int. Mic
0.1U_0402_16V4Z
+3VS
CA2
RA39 1
34 2 0_0402_5%
47
MONO_OUT
BITCLK
DMIC_CLK1/2
46
SDATA_OUT
DMIC_CLK3/4
SDATA_IN
LINE2_VREFO
RESET#
LINE1_VREFO
SYNC
44 2
20 18
10mil 10mil
MIC1_VREFO
28
MIC2_VREFO
19
CPVREF
31
VREF
27
JDREF
40
AC_JDREF
30
CA17 1
GPIO0/DMIC_DATA1/2 GPIO1/DMIC_DATA3/4 SENSE A SENSE B CBN EAPD CBP
+MIC1_VREFO +MIC2_VREFO CA16 1
2 2.2U_0603_6.3V6K
AC_VREF 1 RA10
2
2.2U_0603_6.3V6K
29
1
CA18
CA19
2 10U_0805_10V4Z
2
0.1U_0402_16V4Z
20K_0402_1%
NC 2
43
41
37
BEEP_IN
AMP_SPK_L <30> AMP_SPK_R <30>
1
2
2
40mil
RA3 1 0_0603_5% 1 CA3
2
+5VS
RA1 1 0_0603_5%
2 1
CA1
4 7
For EMI @ HDA_BITCLK_CODEC
@ 1 R313
C618 1 2 100_0402_5%
DGND
2 100P_0402_50V8J
DVSS DVSS
AVSS1 AVSS2
26 42
ALC272-GR_LQFP48
AGND 1 RA12 1 RA13 1 RA14 1 RA15 1 RA19
3
< SENSE_A & SENSE_B, place close to chip > 1
<30>
1
NBA_PLUG
MIC@ 1
Sense Pin
SENSE_A
RA16 2 5.1K_0402_1%
SENSE_B
Add RA19 for EMI
RA17 2 20K_0402_1%
Impedance 39.2K
< MONO_IN SOURCE >
Codec Signals
Function
PORT-A (PIN 39, 41)
20K
PORT-B (PIN 21, 22)
10K
PORT-C (PIN 23, 24)
5.1K
PORT-D (PIN 35, 36)
39.2K
PORT-E (PIN 14, 15)
20K
PORT-F (PIN 16, 17)
10K
PORT-H (PIN 37)
5.1K
PORT-I (PIN 32, 33)
EC Beep <32> EC_BEEP
1
RA8 2 47K_0402_5%
PCI Beep <21> SB_SPKR
1
RA9 2 47K_0402_5%
1
CA15 2 0.1U_0402_16V4Z MONO_IN
Ext. MIC RA11 10K_0402_5%
SPK out
4
SENSE B
1
CA20 0.1U_0402_16V4Z
2
2
SENSE A
RA18 2 20K_0402_1%
3
1
<30> MIC_SENSE
2 0_0603_5% 2 0_0603_5% 2 0_0603_5% 2 0_0603_5% 2 0_0603_5%
4
Int. MIC /
Headphone out
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc. HD Audio ALC272 Codec
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
29
of
44
A
B
C
D
E
< TPA6017 Medium Range Amplifier > +5VS
< Ext. Mic > 1
2
1
CA23 10U_0805_10V4Z
2
1
CA24 0.1U_0402_16V4Z
2
CA25
2
10 dB
CA32 0.033U_0402_16V7K LINE_C_OUTL
5
2
RA23 1 4.7K_0402_5%
2
1
1
16 15 6
+MIC1_VREFO
MIC1_L MIC1_R
1 1K_0402_5% RA22
DA2 2 CH751H-40PT_SOD323-2
1
+MIC1_VREFO 1
2
GAIN1
3
ROUT+
18
SPKR+
14
SPKR-
LOUT+
4
SPKL+
LOUT-
8
SPKL-
RIN-
@
ROUT-
2 1
GAIN0
LIN+
100K_0402_5%
< Int. Mic >
RA29
RA30
100K_0402_5%
100K_0402_5%
+MIC2_VREFO
close to JMIC
LIN-
DA3 RA24 4.7K_0402_5% MIC@
MIC@
2 1
For EMI
3
2
<29> AMP_SPK_L
1 4.7U_0805_10V4Z
1
9
<29> MIC1_C_R
CA22 2
DA1 2 CH751H-40PT_SOD323-2
1
RA21 1 1K_0402_5%
2
CA31 0.033U_0402_16V7K
17
RIN+
1
<29> AMP_SPK_R
2
@ 100K_0402_5%
2
7
CA30 0.033U_0402_16V7K LINE_C_OUTR
1 4.7U_0805_10V4Z
RA28
2
CA29 0.033U_0402_16V7K
<29> MIC1_C_L
CA21 2
+5VS RA27
VDD PVDD1 PVDD2
UA3 1
RA20 1 4.7K_0402_5%
0.1U_0402_16V4Z
MUTE#
19
2
21 20 13 11 1
MIC@ CA26 1 1U_0402_6.3V4Z
AMP_BYPASS
10
BYPASS SHUTDOWN GND5 GND1 GND2 GND3 GND4
<29> MUTE#
PJDLC05_SOT23-3
Keep 10 mil width
12
NC
1
<29>
MIC2_L
2
<29>
MIC2_R
2
MIC@ RA25 1 1K_0402_5%
2
MIC@ LA12 JMIC @ 1 2INT_MIC_L 1 1 NC1 3 SBY100505T-121Y-N 2 2 NC2 4 MIC@ LA11 ACES_85204-0200N 1 2 SBY100505T-121Y-N
INT_MIC
CA33 0.47U_0603_10V7K
1 1U_0402_6.3V4Z CA28 MIC@
TPA6017A2_TSSOP20
1 1K_0402_5% RA26 MIC@
2
CA27 1 2 220P_0402_50V7K MIC@
close to Codec
close to JMIC
GAIN0 GAIN1 Av(db) Rin(ohm) 2
2
0
0
6
90K
0
1
10
70K
1
0 15.6
45K
1
1 21.6
25K
DA9
Left Connector
< Speaker Connector >
@
2 1 3 PJDLC05_SOT23-3 SPK_L1 SPK_L2
LA3 FBMA-L11-160808-800LMT_0603 1 2 1 2
SPKL+ SPKL-
JSPKL
1 2
LA4 FBMA-L11-160808-800LMT_0603
DA10
@
1 3
LA5 FBMA-L11-160808-800LMT_0603 1 2 1 2
PJDLC05_SOT23-3 SPK_R1 SPK_R2
JSPKR
1 2
LA6 FBMA-L11-160808-800LMT_0603
< Volume Control >
3 4
2
Right Connector SPKR+ SPKR-
1 NC1 2 NC2
ACES_85204-0200N @
1 NC1 2 NC2
@ 3 4
ACES_85204-0200N
< HeadPhone JACK > +3VS
JLINE
@
5 1
3
NBA_PLUG
<29> NBA_PLUG
RA32
2
100K_0402_5%
<29>
HP_R
L35 1
<29>
HP_L
L36 1
2 KC FBM-L11-160808-121LMT 0603 2 KC FBM-L11-160808-121LMT 0603
1
2
+3VS
3 6 2 1
HP_L_L
DA8 CA36 0.1U_0402_16V4Z
3
4
HP_R_L
FOX_JA6333L-B3T0-7F
2 1 3
1 10K_0402_5%
5
+3VS
1
P
RA35 2 10K_0402_5%
2
A
3
1
DIP
B
1
0.01U_0402_25V7K
4
SW_XRE094_3P
1
2
1
2
< Ext.MIC/LINE IN JACK >
4
74LVC1G14GW_SOT353-5
UA5
1 2 3 4 5 6 7
RA36 2 10K_0402_5% CA37
+3VS
UA4
Y
3
COM
1
10K_0402_5%
NC
2
CA35 0.1U_0402_16V4Z 2
1
G
A
RA34
2
2
DIP
SW2
5
1
PJDLC05_SOT23-3 RA33
CA38 0.01U_0402_25V7K
CD1# D1 CP1 SD1# Q1 Q1# GND
VCC CD2# D2 CP2 SD2# Q2 Q2#
14 13 12 11 10 09 08
74LCX74MTC_TSSOP14
JEXMIC
<29> MIC_SENSE
1
MIC1_R LA9
4 3 6 2 1
1
2 KC FBM-L11-160808-121LMT 0603
MIC1_L_R
MIC1_L LA10 1
2 KC FBM-L11-160808-121LMT 0603
MIC1_L_L
CA39
0.1U_0402_16V4Z 2 DA7
FOX_JA6333L-B3T0-7F
2 4
1
1
ENCODER_DIR <32> ENCODER_PULSE <32>
3 PJDLC05_SOT23-3
/
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2
CA40 100P_0402_50V8J @
2009-02-12
Deciphered Date
Title
1
2
Date:
B
C
CA41 100P_0402_50V8J @
4
Compal Electronics, Inc.
AMP / Audio Jack / HP / SPEAKER / VR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
@
5 MIC_SENSE
D
Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
30
of
44
A
B
< SPI Flash 8Mb*1 >
C
U46 8
2
1
C786 0.1U_0402_16V4Z
2
C877 @ 10P_0402_50V8J
1
2
C878 @ 10P_0402_50V8J
3 7 <32> SPI_CS# <32> SPI_CLK
1
E
+3VL
20mils 1
D
VCC
4
< MDC 1.5 Conn >
HOLD
SPI_CS# 1
S
SPI_CLK 6
C
5
D
<32> EC_SO_SPI_SI
VSS
W
1
Q
2
+3VALW
EC_SI_SPI_SO <32>
JMDC
@
MX25L8005M2C-15G 1 HDA_SDOUT_MDC 3 5 HDA_SYNC_MDC 7 HDA_SDIN1_MDC 9 HDA_RST#_MDC 11
<21> HDA_SDOUT_MDC MDC@
R495 1
2 33_0402_5%
2 4 6 8 10 12
HDA_BITCLK_MDC
HDA_BITCLK_MDC <21>
1
<21> HDA_SYNC_MDC <21> HDA_SDIN1 <21> HDA_RST#_MDC
GND1 RES0 IAC_SDATA_OUT RES1 GND2 3.3V IAC_SYNC GND3 IAC_SDATA_IN GND4 IAC_RESET# IAC_BITCLK GND GND GND GND GND GND
R496 @ 10_0402_5% 2
13 14 15 16 17 18
ACES_88018-124G
< LPC Debug Port >
2
Connector for MDC Rev1.5
Please place the PAD under DDR DIMM. +3VS
SERIRQ
<20,32> SERIRQ
2
1
<20,32> LPC_AD3 <20,32> LPC_AD1
5
7
4
PLT_RST#
LPC_AD3
8
3
LPC_AD2
LPC_AD1
9
2
LPC_AD0
10
1
R622 2 0_0402_5%
C777 @ 10P_0402_50V8J
@
6
LPC_FRAME#
+3VALW
PLT_RST# <12,15,20,26,27,32> LPC_AD2 <20,32>
1
LPC_AD0 <20,32>
2
MDC@ C778 1000P_0402_50V7K
1
2
1
MDC@ C779 0.1U_0402_16V4Z
2
2
MDC@ C780 4.7U_0805_10V4Z
CLK_PCI_SIO2 <20,24> 2
<20,32> LPC_FRAME#
H1
1
R634 @ 22_0402_5% 1
DEBUG_PAD
2
1
C639 @ 22P_0402_50V8J
For EMI
4
34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1 R502
2 300_0402_5%
+3VS
1 R503
2 300_0402_5%
+3VS
KSO14 KSO6
KSO2 KSO1 KSO0 KSO4 KSO3 KSO5 KSO14 KSO6 KSO7 KSO13 KSO8 KSO9 KSO10 KSO11 KSO12 KSO15 KSI7 KSI2 KSI3 KSI4 KSI0 KSI5 KSI6 KSI1
2 1 CAPS_LED# R509 300_0402_5% CURS_LED# NUM_LED#
KSO7 KSO13 KSO8 KSO9 KSO10 KSO11 KSO12 KSO15 KSI7 KSI2 KSI3 KSI4 KSI0
+3VS CAPS_LED# <32> CURS_LED# <32> NUM_LED# <32>
KSI5 KSI6 KSI1
ACES_88170-3400
CAPS_LED# CURS_LED# NUM_LED#
<33>
TP_SWL
TP_SWL
SW8 SMT1-05_4P
1
3
2
4
<33>
TP_SWR
TP_SWR
1
B
3
2
4
3
1
C889 180P_0402_50V8J @ 2
C890 180P_0402_50V8J @ 2
D86 PJDLC05_SOT23-3 @
For EMI
D85 PJDLC05_SOT23-3 @
For EMI
4
/
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc. SPI / LPC / MDC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
1
6 5
KSO5
JKB @
Right Switch
SW7 SMT1-05_4P
2
KSO3 3
Left switch
3
KSO4
1
KSO0
<32>
KSO[0..15] <32>
6 5
KSI[0..7]
2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J
2
KSI[0..7] KSO[0..15]
1 C725 1 C717 1 C721 1 C609 1 C724 1 C728 1 C730 1 C715 1 C732 1 C733 1 C740 1 C737 1 C729 1 C738 1 C718 1 C736 1 C716 1 C741 1 C726 1 C723 1 C731 1 C739 1 C735 1 C734 1 C722 1 C727 1 C714
3
KSO1
1
KEYBOARD CONN.
KSO2
C
D
Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
31
of
44
B
C
+3VL
D
+3VL_EC L25 1 0_0603_5%
+EC_AVCC
VCC VCC VCC VCC VCC VCC
U33
67
9 22 33 96 111 125
2
<21> GATEA20 <21> KB_RST# <20,31> SERIRQ <20,31> LPC_FRAME# <20,31> LPC_AD3 <20,31> LPC_AD2 <20,31> LPC_AD1 <20,31> LPC_AD0
Reserve for EMI request @
R530 2 33_0402_5%
<20,24> CLK_PCI_EC R533 1
<12,15,20,26,27,31> PLT_RST#
2 47K_0402_5%
<21> EC_SCI# <33> WL_LED# C811
+3VS
2
1
2.2K_0402_5% 2
1 R986
EC_SMB_DA2
2.2K_0402_5% 2
1 R987
EC_SMB_CK2
2.2K_0402_5% 2
1 R988
EC_SMB_DA1
<31>
KSI[0..7]
<31>
KSO[0..15]
KSI[0..7] KSO[0..15]
EC_SMB_CK1
4.7K_0402_5% 2
1 R991
TP_CLK
4.7K_0402_5% 2
1 R992
TP_DATA
+3VALW
100K_0402_5% 1
2 R995
LID_SW#
+3VL
100K_0402_5% 1
2
+5VS
3
1 R989
R996
<36> <36> <7> <7>
<21> <21> <21> <33>
ON/OFFBTN#
47K_0402_5% 1
2
R998
KSO1
47K_0402_5% 1
2
R999
KSO2
1 1 R993
EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2
PM_SLP_S3# PM_SLP_S5# EC_SMI# LID_SW# <33> ESB_CK <33> ESB_DA
1 R994
SUSP#
2
55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82
EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2
77 78 79 80
PM_SLP_S3# PM_SLP_S5# EC_SMI# LID_SW# ESB_CK ESB_DA
6 14 15 16 17 18 19 25 28 29 30 31 32 34 36
CRY1
122 123
KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47
PS2 Interface
DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F
68 70 71 72
DAC_BRIG EN_DFAN1 IREF CHGVADJ
PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F
83 84 85 86 87 88
USB_EN#2 USB_EN#0 ENCODER_DIR ENCODER_PULSE TP_CLK TP_DATA
NC
OSC
NC
OSC
@
SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0
WOL_EN# USB_OC#2 VGATE
SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS#
119 120 126 128
EC_SI_SPI_SO EC_SO_SPI_SI SPI_CLK_R SPI_CS#
CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59
73 74 89 90 91 92 93 95 121 127
EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 GPO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11
100 101 102 103 104 105 106 107 108
PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7
110 112 114 115 116 117 118
SPI Flash ROM
PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A
GPI
XCLK1 XCLK0
V18R
L80
1
2 0_0603_5% 1
+EC_AVCC
2
OVP component ADP_I
<37>
C896 2 0.22U_0603_16V4Z
Reserve pull high for cap. sensor +3VL
USB_EN#2 <25> USB_EN#0 <25> ENCODER_DIR <30> ENCODER_PULSE <30> TP_CLK <33> TP_DATA <33>
WOL_EN# <26,34> USB_OC#2 <21,25> VGATE <42> EC_SI_SPI_SO <31> EC_SO_SPI_SI <31>
@ CAP_INT#
R1025
2 4.7K_0402_5%
1 @
ESB_CK
R1033
1
ESB_DA
R1034
1
2 4.7K_0402_5% 2 4.7K_0402_5%
For EMI 2
R74 1
2
SPI_CLK <31>
SPI_CS# <31>
0_0402_5% 1 C607 10P_0402_50V8J CAP_INT# @ CAP_INT# <33> 2 FSTCHG FSTCHG <37> BATT_FULL_LED# BATT_FULL_LED# <33> CAPS_LED# CAPS_LED# <31> BATT_CHG_LOW_LED# BATT_CHG_LOW_LED# <33> PWR_ON_LED# PWR_ON_LED# <33> SYSON SYSON <34,40> CPU_VCORE_ENABLE CPU_VCORE_ENABLE <42> ACIN_D R541 2 1 10K_0402_5% EC_RSMRST# EC_RSMRST# <21> EC_LID_OUT# EC_LID_OUT# <21> EC_ON EC_ON <33> SB_PWRGD BKOFF#_R WL_OFF# CURS_LED#
SB_PWRGD <21,42> WL_OFF# <27> CURS_LED# <31>
R560 2 150K_0402_5%
1 UMA_ENBKL EC_THERM# SUSP# PBTN_OUT# USB_OC#0
124 C814 2
+3VL
UMA_ENBKL <12> EC_THERM# <22> SUSP# <34,39> PBTN_OUT# <21> USB_OC#0 <21,25>
ACIN_D
1 D33 CH751H-40PT_SOD323-2
2
1 4.7U_0805_10V4Z
2
ACIN
3
<22,33,35>
C326 1 100P_0402_50V8J
KB926QFD3_LQFP128_14X14
ECAGND
CRY2
+3VL_EC
ADP_V <37>
DAC_BRIG <18> EN_DFAN1 <5> IREF <37> CHGVADJ <37>
97 98 99 109
GPIO
R545 20M_0402_5%
4
Power has removed BATT_TEMPA <36> R1024 BATT_OVP <37> 1 2 100K_0402_5% 1
SPI Device Interface
1
32.768KHZ 12.5PF Q13MC14610002 C815 1 2 15P_0402_50V8J
1
C812 2 100P_0402_50V8J ECAGND
1
@
SM Bus
2
3
KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15
C813 2 15P_0402_50V8J
SYSON Y7
10K_0402_5% 2
AD
EC_BEEP <29> ACOFF <37>
BATT_TEMPA BATT_OVP ADP_I_R ADP_V
DA Output
CAP_RST# FAN_SPEED1 VLDT_EN E51_TXD E51_RXD ON/OFFBTN# PWR_SUSP_LED# NUM_LED#
<33> CAP_RST# <5> FAN_SPEED1 <34> VLDT_EN <27> E51_TXD <27> E51_RXD <33> ON/OFFBTN# <33> PWR_SUSP_LED# <31> NUM_LED#
Add for KB926D2 issue. Please refer to KB926D-AN1-100 for detail
10K_0402_5% 2
PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D
ACOFF
63 64 65 66 75 76
BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43
1
2.2K_0402_5% 2
12 13 37 20 38
INVT_PWM_R EC_BEEP
21 23 26 27
PWM Output MISC
0.1U_0402_16V4Z
2
+3VL
CLK_PCI_EC PLT_RST# ECRST# EC_SCI# WL_LED#
INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13
AGND
+3VL
GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC &
69
1
C810 2 15P_0402_50V8J1
1 2 3 4 5 7 8 10
GND GND GND GND GND
@
GATEA20 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0
11 24 35 94 113
1
E
AVCC
A
C816 0.1U_0402_16V4Z
Add R344 and R345 for EC pin damage issue L81
2
1 0_0603_5%
R344 BKOFF#_R
2 33_0402_5%
1
BKOFF# <18>
R345 INVT_PWM_R +3VL_EC
1 4
2
1 C805 0.1U_0402_16V4Z
2
1 C806 0.1U_0402_16V4Z
/
2
1 C807 1000P_0402_50V7K
2
2 33_0402_5%
2
C809 1000P_0402_50V7K
4
Compal Secret Data 2009-02-12
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
INVT_PWM <18>
1 C808 0.1U_0402_16V4Z
Security Classification Issued Date
1
D
ENE KB926 D3 Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
32
of
44
A
B
C
Power Button/ PWR/B
D
CS/B Connector
Touch Pad Connector
@ JPOWER ON/OFFBTN#
2
1 3
R512 100K_0402_5% 51_ON#
@
S
ESB_DA_L
1
ESB_CK_L
1
1
R1015 100_0402_5% 1
DC-IN LED
1
+3VALW
U34 APX9132ATI-TRL_SOT23-3
<22,32,35>
1
D49
2
PWR_SUSP_LED# <32>
< Ultra Bright Yellow Green >
2 1 120_0402_5% 2
BATT_CHG_LOW_LED# <32>
H2
Vf=1.9V(typ),2.4V(max) for amber Vf=2.0V(typ),2.4V(max) for green If=30mA(max)
HT-210UD/UYG_AMB/GRN
H12
1
< Ultra Bright Amber > Vf=1.9V(typ),2.4V(max) for amber Vf=2.0V(typ),2.4V(max) for green If=30mA(max)
2
H6 H_3P0 @
H14 H_3P0 @
H15 H_3P0 @
H37 H_3P0N @
H7 H_3P0 @
H8 H_3P0 @
H9 H_3P0 @
H10 H_3P0 @
H_3P0 @
H11 H_3P0 @
H_5P0 @
3
H38 H_5P0X3P0N @
H_11P0X4P0N @
Vf=1.9V(typ),2.4V(max) C199 1
2 0.22U_0603_16V4Z
@
C200 1
2 0.22U_0603_16V4Z
@
C201 1
2 0.22U_0603_16V4Z
@
C202 1
2 0.22U_0603_16V4Z
@
C203 1
2 0.22U_0603_16V4Z
H32
MINI CARD-1
H34 H_3P8 @
H27
1
MDC
2
SATA_LED# <22>
CPU H_3P8 @
INS87990490H22 H_3P7 @
H19 H_3P8 @
H21 H_4P8X3P8 @
1
@
1
WL_LED# <32>
1
+5VALW
D50 2 2 1 120_0402_5% HT-110UD_1204_AMBER
1
WLAN LED +3VS
1
For EMI
H4 H_3P0 @
H13 H_3P0 @
H16
1 R550
1 C647 10P_0402_50V8J
1
3
H3 H_3P0 @
1
1 R549
H_3P8X4P8 @
H33 H_1P2 @
1
+3VALW
< Ultra Bright Amber >
BATT_FULL_LED# <32>
1
3
C645 0.1U_0402_16V4Z
Screw Hole
HT-210UD/UYG_AMB/GRN D38
LID_SW# <32>
1
BATT CHARGE/FULL LED
1
2 120_0402_5%
PWR_ON_LED# <32>
1
1 R521
2
3
1
+3VALW
< Ultra Bright Yellow Green >
2
3
1
S
POWER ON/SUSPEND LED
2N7002_SOT23-3
VOUT
1
3
VDD
1
1
2
1
2 G
2 2 1 120_0402_5% HT-110UYG-CT_YEL/GRN
C895 100P_0402_25V8K
Q20
D
1 R515
2
1
ACES_85201-06051
C894 100P_0402_25V8K @ 2
2
1
ACIN
Vf=1.9V(typ),2.4V(max)
+3VALW
2
1
@
2
1
6 5
@
Lid SW D54
1
@
1 2 3 4 5 6 GND GND
@ 2
R1016 100_0402_5%
2
2
For EMI
Q19
GND
3
4
@
D87 @ PJDLC05_SOT23-3
R514 10K_0402_5%
SMT1-05-A_4P
@
3
2N7002_SOT23-3
3
2
D
2 G
ESB_CK_L ESB_DA_L
2 FBMA-11-100505-301T_0402 2 FBMA-11-100505-301T_0402 1 2
JCS 1 2 3 4 5 6 7 8
1
EC_ON 2
1
BTM side
1
6 5
<32>
+3VL_CS
1 0_0603_5% 2 0_0402_5% 2 0_0402_5%
1
D60 PJDLC05_SOT23-3 @
4
SW6
@ @ @
ACES_85201-06051
<35>
ON/OFFBTN# <32>
SMT1-05-A_4P
@ @
1 1
1
2
L93 L94
ESB_CK ESB_DA
1
ON/OFFBTN#
3
<32> <32>
CAP_INT# CAP_RST#
1
1
SW5 1
TOP side
<32> <32>
1 2 3 4 5 6 GND GND
1
For Debug
TP_CLK TP_DATA TP_SWL TP_SWR
R1030 2 R1031 1 R1032 1
+3VL
C899 10P_0402_50V8J
ACES_85201-04051
<32> <32> <31> <31>
1 2 3 4 5 6 7 8
C898 10P_0402_50V8J
C713 1U_0402_6.3V4Z
+5VS_TOUCH TP_CLK TP_DATA TP_SWL TP_SWR
1
2
+5VS
2 R111 1 0_0603_5%
C897 10P_0402_50V8J
1
1 2 GND 3 GND 4
5 6
20 mil width
@ JTOUCH 1 2 3 4
2
+3VL
E
H_1P2 @
HDD LED 2 R546 1 10K_0402_5%
6 5
2 2 1 120_0402_5% HT-110UYG-CT_YEL/GRN
3
PCB Fedical Mark PAD 4
4 FD1
FD2
FD3
FD4
Q18B 2N7002DW-T/R7_SOT363-6 @
Vf=1.9V(typ),2.4V(max)
@
@
Compal Secret Data
Security Classification 2008/04/14
Issued Date
@
1
1 R548
1
+3VS
1
4
1 Q18A 2N7002DW-T/R7_SOT363-6
D46
1
+3VS
2009/04/14
Deciphered Date
Title
Compal Electronics, Inc. LED/LID/PB/FB/SCREW HOLE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
33
of
44
A
B
< +5VALW TO +5VS >
C
D
+1.8V +5VALW Q35
Inrush current = 0A
1 2 3 4
S S S G
1
1
C833
8 7 6 5
C835
RUNON 2
SI4800BDY_SO8
1U_0402_6.3V4Z
2
1
4.7U_0805_10V4Z
2
4.7U_0805_10V4Z
Inrush current = 0A
1 2 3
C842
1
2
2
C848 1U_0402_6.3V4Z
1
C841 10U_0805_10V4Z
4.7U_0805_10V4Z
2
1.8VS_ENABLE 1
R809
< +3VALW TO +3VS >
10M_0402_5%
2
0.01U_0402_25V7K
2
+3VS
Q14 8 7 6 5 C840 4.7U_0805_10V4Z
1
SUSP
Q143A 2N7002DW-T/R7_SOT363-6
D D D D
Inrush current = 0A
1 2 3 4
S S S G
1
2
SI4800BDY_SO8
1
C839 1U_0402_6.3V4Z
2
< +1.2VALW TO +1.2V_HT >
C838
+1.2VALW
4.7U_0805_10V4Z
2 RUNON
R152 1 750K_0402_1%
8 7 6 5
+VSB
1
C847
2
4.7U_0805_10V4Z
2
1
R808 10M_0402_5%
2
2
+3VALW +3VALW
2
+ C879 @ 330U_D2E_2.5VM
4.7U_0805_10V4Z
2
2
For +1.2VALW OVP issue Just mount for TPS51117
< +3VALW TO +3V_LAN >
1U_0402_6.3V4Z
C862
R367 @ 1K_0402_5%
S
2N7002_SOT23-3
2
1
C846
R233 330K_0402_5%
1
+VSB
1
SUSP
2 G
1 1
4
Q17
2
0.01U_0402_25V7K
D
Inrush current = 0A
1 2 3
1
R556 @ 10M_0402_5%
3
2
C834
2
1
1
1
2
For power noise issue
+1.2V_HT
Q11 IRF8113PBF_SO8
+3V_LAN
2
6
+3VALW
+VSB
C849
1
2
< close to PQ20, must EMI confirm >
1
R138 750K_0402_1%
2
6
1
1
1
D D D D
Q4 IRF8113PBF_SO8
4
1
C864
+1.8VS
+5VS
8 7 6 5
E
< close to PQ20, must EMI confirm > < +1.8V TO +1.8VS >
C837 0.01U_0402_25V7K
2 1
Vgs=-4.5V, Id=3A
VLDT_EN#
Q12A 2N7002DW-T/R7_SOT363-6
Rds<97m ohm 2
< Inversion of SYSON, SUSP#, VLDT_EN, EC_ON > R17
2
R596
4.7U_0805_10V4Z
1
2
<41>
C680
SYSON#
SYSON#
1U_0402_6.3V4Z Q142B 2N7002DW-7-F_SOT363-6 5
3
SUSP
Q142A 2N7002DW-7-F_SOT363-6 2 SUSP# 4
<32,40> SYSON
2 SUSP
VLDT_EN#
<41>
<32>
1
2
Inrush current = 0A
D
3
C679
6
1 @
R597 100K_0402_5%
100K_0402_5% 2
2
0.01U_0402_25V7K
+5VL 1
1 R595
3
2
+5VL
100K_0402_5%
1
1
C182
PJ29 JUMP_43X79
S
VLDT_EN 2 G
VLDT_EN
<32,39>
Q53 2N7002_SOT23-3
1
2
1
+5VL
2 2
Q38 AO3413_SOT23
1
3
@
G
1
C880 0.1U_0402_16V7K
D
<26,32> WOL_EN#
1 R19 2 47K_0402_5% 1
1
S
100K_0402_5% WOL_EN#
3
+0.9V
+1.5VS
+1.1VS
2
2
2
2
2
2
+3VS
SUSP
2N7002_SOT23-3 2N7002DW-T/R7_SOT363-6
SYSON#
Q144B 2N7002DW-7-F_SOT363-6
5
1
D Q49
2 G S
SUSP
D Q50
2 G
2N7002_SOT23-3
S
SUSP
2N7002_SOT23-3
1
Q143B 5
D
3
SYSON#
3
S
2N7002DW-T/R7_SOT363-6
5
S
Q52
2 G
2N7002_SOT23-3
4
1
4
3
VLDT_EN#
3
Q12B Q48
1
3
D
2 G
4
1
6
SUSP
1
470_0805_5%
1
R294
470_0805_5%
1
R293
470_0805_5%
1
R292
470_0805_5%
3 1
R288
470_0805_5%
3 1
R284
470_0805_5%
1
R280
470_0805_5%
1
R279
470_0805_5%
2N7002DW-7-F_SOT363-6
2
+1.8V
R239
Q144A SUSP
+1.2V_HT 2
+1.8VS
+5VS
2
< Discharge circuit >
4
4
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
DC / DC Circuits Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
34
of
44
A
B
C
D
VIN PL1 SMB3025500YA_2P 1 2
PF1 DC_IN_S2
2
PR1 1M_0402_1% 1 2
VIN
VS
PJP1
1 PR3 84.5K_0402_1%
P
PU1A 3
+ -
1
1
0
2
2
LM358DT_SO8
VIN
2
1
2
PC6 0.1U_0603_25V7K 2 1
10K_0402_1% PD2 GLZ4.3B_LL34-2
2
PR7 10K_0402_1%
2 1
4
1
1
G
PR2 PR5 2 0_0402_5%
1
<22,32,33> ACIN
@ SINGA_2DW -0005-B03
PR4 22K_0402_1% 1 2
2
1
PC4 100P_0402_50V8J
8
2
2
PC3 1000P_0402_50V7K
1
4
PC2 100P_0402_50V8J
1
-
1
PC1 1000P_0402_50V7K
2
3
1
2
-
2
+
10A_125V_451010MRL
1
1
1
+
2
1
2
DC_IN_S1
PR6 20K_0402_1%
DC301001M80
PC5 1000P_0402_50V7K
RTCVREF
PR8 10K_0402_1%
1
1
PD4 RLS4148_LL34-2
PR9 68_1206_5% PQ1 TP0610K-T1-E3_SOT23-3 N1
3
Vin Detector
1
High 18.384 17.901 17.430 Low 17.728 17.257 16.976
VS
RTC Battery
2
2 <33>
1
2 PR13 22K_0402_1%
51_ON#
-
OUT
IN
2
N2
GND
SP093MX0000 PC10
1
2
PC9 10U_0805_10V4Z
@ MAXEL_ML1220T10
G920AT24U_SOT89-3
1
3
2
+RTCBATT
2
PU2
3.3V 1
+CHGRTC
+RTCBATT
1
1 PR14 200_0603_5%
PR16 560_0603_5% 1 2
+
PBJ1
2
RTCVREF
PR15 560_0603_5% 1 2
2
PC8 0.1U_0603_25V7K
2
PC7 0.22U_1206_25V7K
2
PR12 100K_0402_1%
1
1
1
2
PR10 68_1206_5%
2
PR11 200_0603_5% CHGRTCP 1 2
2
2
BATT+
1
1
PD3 RLS4148_LL34-2
1U_0805_25V4Z
3
3
PJ1
2
+3VALW P
2
PJ2
1
1
+3VALW
+1.8VP
@ JUMP_43X118
PJ5 +5VALW P
2
1
+5VALW
(5A,200mils ,Via NO.= 10) OCP(min)=7.9A 2
2
+3VLP
1
+VSB
+5VL
(100mA,40mils ,Via NO.= 2) PJ7 +1.2VALW P
1
2
2
2
1
+3VL
(5A,200mils ,Via NO.=10) OCP(min)=7.78A
PJ9
2
2
PJ10 +NB_CORE
1
1
+VDDNBP
2
@ JUMP_43X39
+0.9VP
2
2
1
+VDDNB
1
(3A,120mils ,Via NO.=6)
PJ12
(0.5A,20mils ,Via NO.=1)
2
@ JUMP_43X118
(7.0A,280mils ,Via NO.=14) OCP(min)=9.32A
+2.5VS
1
+1.2VALW
1
1
@ JUMP_43X118
1
@ JUMP_43X118
PJ11
2
1
1
(100mA,40mils ,Via NO.= 2) +NB_COREP
2
2
@ JUMP_43X39
@ JUMP_43X39
1
(120mA,40mils ,Via NO.= 1) +2.5VSP
2
VL
PJ6
@ JUMP_43X39
4
+1.8V
(8A,320mils ,Via NO.= 16) OCP(min)=8.87A
PJ8 +VSBP
PJ3
1
1
@ JUMP_43X118
1
@ JUMP_43X118
2
2
@ JUMP_43X118 PJ4 2 2 1 1
(5A,200mils ,Via NO.= 10) OCP(min)=7.7A 2
2
PJ13
1
1
+0.9V
+1.5VSP
2
2
4
1
1
+1.5VS
@ JUMP_43X79
@ JUMP_43X79
(2A,80mils ,Via NO.= 4)
(2.0A,80mils ,Via NO.=4) Compal Secret Data
Security Classification Issued Date
2008/04/14
Deciphered Date
2009/04/14
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
Title
Compal Electronics, Inc. DCIN/DECTOR
Size
Document Number
Rev 1.0
LA-5831P Date:
W ednesday, August 12, 2009 D
Sheet
35
of
44
A
B
C
D
PH1 under CPU botten side : CPU thermal protection at 92 degree C Recovery at 56 degree C VMB PF2 15A_65V_451015MRL 1 2
PJP2
VL VL
PL2 SMB3025500YA_2P 1 2
ENTRIP1
<38>
VL
1
PC13 0.1U_0603_25V7K
PR20 47K_0402_1% 1 2
2
8 2
PQ2 SSM3K7002FU_SC70-3
-
1
O
2
4
1
ENTRIP2
2
1
<7,38>
PD5 RLS4148_LL34-2
LM393DG_SO8
D
VL
S
PQ3 SSM3K7002FU_SC70-3
PR27 100K_0402_1% 1
1 2
1
PR29 100K_0402_1% 2
2
2
S
2 G
2
PR28 1K_0402_1%
PC15 1000P_0402_50V7K
1 2
PR25 13.7K_0402_1%
2
+3VLP
1
PC14 0.22U_0805_16V7K
1
PR26 6.49K_0402_1% 2 1
D
2 G
PU3A
+
P
2
2
2
3
TM_REF1
PR24 100_0402_1% 1
PR23 100_0402_1%
PR22 13.7K_0402_1% 1 2
G
PR21 1K_0402_1%
@ OCTEK_BTJ-09HA1G
1
PR19 47K_0402_1%
1
PH1 100K_0402_1%_NCP15WF104F03RC
1
PC12 0.01U_0402_25V7K
2
PC11 1000P_0402_50V7K
1
+3VLP
1
2 PR18 47K_0402_1%
3
1
1
2 PR17 1K_0402_1%
3
2
BATT+
2
1 EC_SMDA EC_SMCA
2
GND GND GND GND
BATT_S1
1
10 11 12 13
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9
1
1
BATT_TEMPA <32>
EC_SMB_DA1 <32> EC_SMB_CK1 <32>
PH2 near main Battery CONN : BAT. thermal protection at 92 degree C Recovery at 56 degree C
VL
VL
1
2
PQ4 TP0610K-T1-E3_SOT23-3
PR30 47K_0402_1%
2
8
O -
4 PC18 0.22U_0805_16V7K
PU3B
3
P
+
7
LM393DG_SO8
2
1
PD6 RLS4148_LL34-2
PR34 16.9K_0402_1% 2
1
D
3
PR37 0_0402_5% 2
S
PQ5 SSM3K7002FU_SC70-3
2 G
2
1
1
PC19 @ .1U_0402_16V7K
1 POK
6
G
1
@
PR36 100K_0402_1%
<38,39>
5 TM_REF1
1
1
1 2
2 2
@
PR33 13.7K_0402_1% 1 2
2
2
PR35 22K_0402_1% 1 2
PC17 0.1U_0603_25V7K
VL
PR31 47K_0402_1% 1 2
100K_0402_1%_NCP15WF104F03RC PC16 0.22U_1206_25V7K
2 1 PR32 100K_0402_1%
3
+VSBP
1
1
PH2 3
B+
4
4
Compal Secret Data
Security Classification Issued Date
2008/04/14
Deciphered Date
2009/04/14
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
Compal Electronics, Inc. BATTERY CONN / OTP Document Number
Rev 1.0
LA-5831P Wednesday, August 12, 2009 D
Sheet
36
of
44
B
1
2
PR40 100K_0402_1% 2 1
2 1
PC24 4.7U_1206_25V6K
1
2
PC23 4.7U_1206_25V6K
2 5 6 7 8
PQ9 1 2 3 4
/BATDRV
S S S G
D D D D
1
8 7 6 5
3 2 1 PL3 10UH_SIL1045RA-100PF_4.5A_30% 1 2
ACSET
1
1
2
RLS4148_LL34-2 PC31 0.1U_0603_25V7K
24
REGN
1
PC36 1U_0603_10V6K
PQ11 AO4466_SO8
2
3
PC34 .1U_0402_16V7K 1 2 1
2
4
PR45 0.02_1206_1% 4 BATT+
2
2
PR48 120K_0402_1%
1
1
PD7 2
2
25
PH
1
ACDRV ACDET
1 1
1 2
PC35 @ 0.01U_0402_25V7K
FDS4435BZ_SO8
PC33 10U_1206_25V6M
6
8 7 6 5
1
ACSET
D D D D
PQ10 AO4466_SO8
4
2
PR47 100K_0402_1% 1 2
S S S G
26
HIDRV
REGN
2
ACN ACP
1 2 3 4
@ FDS4435BZ_SO8
PR43 0_0603_5% 1 2
10U_1206_25V6M PC32
4 5
27
BTST
1
2 2 3
VREF
28
PVCC
PC30 @0.1U_0603_25V7K
ACDET
PR46 54.9K_0402_1%
CHGEN
1
1 PC29 0.1U_0603_25V7K
PC27 0.22U_1206_25V7K 1 2
PU4 1
PL16 HCB2012KF-121T50_0805 CHG_B+ 1 2 PC22 4.7U_1206_25V6K
PR163 4.7_1206_5% 1
4
PC26 .1U_0402_16V7K 1 2
PC141 @0.1U_0402_25V6 2 1
3
PC20 0.01U_0402_25V7K
PQ6
5 6 7 8
1
1
2
2
2 1 2
2 PR44 340K_0402_1%
8 7 6 5
PR42 100K_0402_1%
1
1 1 2
PC28 2.2U_0805_25V6K
2
PR41 3.3_1210_5%
E
PR38 0.015_1206_1% 1 4
CHGEN#
1
PC25 0.01U_0603_50V7K
2 1
PR39 3.3_1210_5%
1 2 3
PR162 1K_0402_1%
2
8 7 6 5
D
B+
PQ8 AO4407A_SO8
PQ7 FDS4435BZ_SO8 1 D S D S 2 D S 3 D G 4 PC148 PC21 1000P_0402_50V7K 0.022U_0402_25V7K 2 1 2 1
VIN
C
2
A
PGND
22
LEARN
21
CELLS
20
PC38 0.1U_0603_25V7K
2
23
PC39 @0.1U_0603_25V7K
1
LODRV
2
2 7 ACOP PC37 0.47U_0603_16V7K
3 2 1
1 PR49 340K_0402_1% 2
OVPSET
2
8
2
OVPSET
9
AGND
10
VREF
ACOFF
<32>
PR50 54.9K_0402_1% CELLS
1
17 1
1
2
VADJ
PC42 0.1U_0603_25V7K
VREF
29
TP
2
ACGOOD PR55 2 1 49.9K_0402_1%
PQ14 SSM3K7002FU_SC70-3 3
15
IADAPT
1
PR56 100K_0402_1%
2
2
2 G
16
SRSET BATDRV
1
14
IREF
PR63 100K_0402_1%
<32>
1
D
/BATDRV
BQ24751ARHDR_QFN28_5X5
S
PR58 340K_0402_1%
PR57 10_0603_5%
REGN
PC44 @0.01U_0402_25V7K
CHGEN# PQ15 SSM3K7002FU_SC70-3 3
CHGVADJ
Pre Cell
PR61 499K_0402_1%
PU1B 5
0V
4.35V
Current
2.968V
3A
1.484V
1.5A
VIN
4V
PR159 309K_0402_1%
CHGVADJ要要要EC DA pin
ADP_V
<32>
2
1
1
PC147 .1U_0402_16V7K
2
2
PR161 47K_0402_1%
@ PC47 0.01U_0402_25V7K
6
1
-
LM358DT_SO8
2
0
Compal Secret Data
Security Classification 2008/04/14
Issued Date
2009/04/14
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
PR160 10K_0402_1% 1 2
4
+
2 1 @ PR66 105K_0402_1%
7
2 1 2 1 @ PR64 @ PR62 499K_0402_1% 340K_0402_1%
1 P
@ PR65 10K_0402_1% 1 2
8
2 BATT_OVP
G
<32>
4
4
PC46 0.01U_0402_25V7K
VS
2
VMB
3.28V
S
<32>
1
2
VADJ
1
<32> CHGVADJ
PR60 210K_0402_1% 1 2
ADP_I
IREF
PR59 @ 0_0402_5%
75W,Iadapter=3.947A,PR38=0.015ohm,PR47=100K,PR48=120K,CP=3.63A
2
1
2
PC45 100P_0402_50V8J
3
D
2 G
<32> FSTCHG 1
2
PC43 .1U_0402_16V7K
1
2 1
1
ACOFF 3
PQ13 SSM3K7002FU_SC70-3
2 G
2
PR54 100K_0402_1%
1
13
1
1 3
S
12
PR52 100K_0402_1%
1
ACSET
18
SRN BAT
VADJ
ACGOOD# D
VDAC
2
1
PR53 200K_0402_1%
11
2
1
1
PC41 0.1U_0603_25V7K
19
SRP
RTCVREF
2
2
VREF VREF
PC40 1U_0603_10V6K
2
PR51 100K_0402_1% 1 2
3
1
VREF PQ12 SI2301BDS-T1-E3_SOT23-3
B
C
D
Compal Electronics, Inc. CHARGER Document Number
Rev 1.0
LA-5831P Wednesday, August 12, 2009
Sheet E
37
of
44
A
B
C
D
PC48 1U_0603_10V6K
2VREF_51125
B++
1
1
2
1
PR67 13K_0402_1% 1 2
PR68 30K_0402_1% 1 2
PR69 20K_0402_1% 1 2
PR70 19.6K_0402_1% 1 2
B++
3
2
D
S
<7,36>
5 6 7 8
1 2
PC52 10U_1206_25V6M
1 2
21
UG_5V
20
LX_5V
19
LG_5V
3 2 1
PR74 PC55 2.2_0603_1% .1U_0402_16V7K BST_5V 1 2 1 2
2
4
<36,39>
22
2VREF_51125
2
1
+
PC143 @ .1U_0402_16V7K
1 2
3 2 1
VL
1
PC57 220U_6.3V_M
2 4 TPS51125RGER_QFN24_4X4
+5VALWP
2
1
PQ19 AO4712_SO8
PC59 PR76 680P_0603_50V7K 4.7_1206_5%
PL5 4.7U_LF919AS-4R7M-P3_5.2A_20% 1 2 5 6 7 8
23
VCLK
2
B++
PQ21 SSM3K7002FU_SC70-3
2 G
S
VL
1 2 G
3
1
D
POK
1 2
1
PR79 @ 0_0402_5%
3
PQ20 SSM3K7002FU_SC70-3
24
PQ16 AO4466_SO8
PC60 4.7U_0805_10V6K
ENTRIP2
18
VREG5 17
13
16
EN0
DRVL1
VIN
DRVL2
PR77 499K_0402_1% 1 2
PC51 2200P_0402_50V7K
ENTRIP1
LL1
2 <36>
1
2
3
DRVH1
LL2
2 1 PC61 0.1U_0603_25V7K
ENTRIP1
ENTRIP1
VFB1
VREF
4 TONSEL
5
6
DRVH2
1
8 7 6 5
B+ 1 2 3
2
12
VBST1
4
PR78 100K_0402_1%
+
11
PGOOD
VBST2
GND
1 2 3 1
LG_3V
10
VREG3
PQ18 AO4712_SO8
PC58 680P_0603_50V7K 2 1
PC56 220U_6.3V_M
PC142 @ .1U_0402_16V7K 2 1
Ipeak = 5A Imax = 3.5A F = 305kHz Total Capacitor = 220 uF ESR = 15m Ohm
PR75 4.7_1206_5% 2 1
PL4 4.7U_LF919AS-4R7M-P3_5.2A_20% 1 2
9
PR72 150K_0402_1% 2
VO1
15
8 PR73 2 1 2 BST_3V 2.2_0603_1% UG_3V PC54 .1U_0402_16V7K LX_3V 1
VO2
SKIPSEL
4
1
14
7
+3VALWP
P PAD
2
25
ENTRIP2
PU5
1
PC53 4.7U_0805_10V6K
8 7 6 5
1 2
PQ17 AO4466_SO8
2
PR71 150K_0402_1% 1 2
VFB2
+3VLP
1 PC50 10U_1206_25V6M
1
1
2
@ JUMP_43X118
2
2
PC49 2200P_0402_50V7K
B+
ENTRIP2
PJ15
Ipeak = 5A Imax = 3.5A F = 245kHz Total Capacitor = 220 uF ESR = 15m Ohm
3
1
1
D
S
PQ22 SSM3K7002FU_SC70-3
2 G
2
PR81 100K_0402_1%
1
2
@ PC62 0.01U_0402_16V7K
1
2 1 PR82 49.9K_0402_1%
VS
3
PR80 100K_0402_1%
4
4
Compal Secret Data
Security Classification Issued Date
2008/04/14
Deciphered Date
2009/04/14
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
Compal Electronics, Inc. 3VALW/5VALW Document Number
Rev 1.0
LA-5831P Wednesday, August 12, 2009 D
Sheet
38
of
44
5
4
3
2
1
D
D
1
2
2
1
1
51124_B+
+NB_COREP
21
UG_NB_COREP
LL1
20
LX_NB_COREP
LG_1.2V
12
DR VL2
DR VL1
19
LG_NB_COREP
1
PGND1
PQ26 AO4712_SO8
TPS51124RGER_QFN24_4x4
2
18
4 1
TRIP1
3 2 1
PR93 13.7K_0402_1% 1 2
2
PR92 16.5K_0402_1% 2
PR94 0_0402_5% 2 1
+5VALW
SUSP# <32,34>
1
PC79 4.7U_0805_10V6K
PC80 .1U_0402_16V7K
+NB_COREP
1 + 2
2
1
PC67 4.7U_1206_25V6K 2 1
Ipeak =7A Imax = 4.9A F = 240kHz Total Capacitor = 550 uF ESR = 7.5m Ohm
B
2
1 2
PC78 1U_0603_10V6K
1
2
PC77 @ .1U_0402_16V7K
2
PR96 22K_0402_5% 1 2
PR95 3.3_0402_5%
2
B
1
1
<36,38> POK
+1.1V
PL7 1.8UH_SIL104R-1R8PF_9.5A_30% 1 2
1
17
V5IN 16
V5FILT 15
TRIP2
PGND2 13
4
14
PQ25 AO4712_SO8
PC66 4.7U_1206_25V6K 2 1
C
2
PC74
DR VH1
PC70 .1U_0402_16V7K
4.7U_0805_6.3V6K 1 2
LL2
PR89 2.2_0603_1% 2 1
5 6 7 8
DR VH2
11
5 6 7 8
1
2 VFB1
4
5
3 GND
TONSEL
VO1
BST_NB_COREP
VBST1
10
4
23 22
VBST2
LX_1.2V
24
PR91 4.7_1206_5%
UG_1.2V
EN1
PC76 680P_0603_50V7K
9
PGOOD1
EN2
1
1 2 3 8 7 6 5
BST_1.2V
PGOOD2
PQ24 AO4466_SO8
1 2 3
PR90 4.7_1206_5% 2 1 PC75 680P_0603_50V7K 2 1
Ipeak =5A Imax = 3.5A F = 300kHz Total Capacitor = 220 uF ESR = 15m Ohm
PC72 4.7U_0805_6.3V6K
2
1
+
2
PC71 220U_6.3V_M
PC144 @ .1U_0402_16V7K 2 1
1
8
P PAD
B+
3 2 1
7 PC69 PR88 .1U_0402_16V7K 2.2_0603_1% 2 1 2 1
PL6 1.8UH_SIL104R-1R8PF_9.5A_30% 1 2
+1.2VALWP
6
1 4
C
VO2
25
VFB2
8 7 6 5
PU6 PQ23 AO4466_SO8
+1.2VALWP
2
PR87 0_0402_5%
2200P_0402_50V7K PC65 2 1
PC64 4.7U_1206_25V6K 2 1
PC63 4.7U_1206_25V6K 2 1
51124_B+
PC137 0.1U_0402_25V6 2 1
PL14 HCB2012KF-121T50_0805 1 2
PC145 @ .1U_0402_16V7K 2 1
2
PC139 @0.1U_0402_25V6 2 1
PR86 33K_0402_1%
PC138 @0.1U_0402_25V6 2 1
2
PR85 75K_0402_1%
2200P_0402_50V7K PC68
1
PR84 75K_0402_1%
PC73 220U_6.3V_M
PR83 44.2K_0402_1% +1.2VALWP
A
A
Compal Secret Data
Security Classification 2008/04/14
Issued Date
2009/04/14
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc. NB_COREP/1.2VALWP Document Number
Rev 1.0
LA-5831P Wednesday, August 12, 2009
Sheet 1
39
of
44
3
2
1
PQ27 AO4466_SO8 PR97 255K_0402_1% 1 2
1
D
DL_1.8VP TPS51117RGYR_QFN14_3.5x3.5
+
1
4
1
2
2
1
PQ28 AO4712_SO8 2
+1.8VP
PC146 @ .1U_0402_16V7K
7
2
C
1
PC89 4.7U_0805_10V6K
9
DRVL
+5VALW
PC85 220U_D2_4VM
PGOOD
PC88 @ 47P_0402_50V8J 1 2
GND
PC86 4.7U_0603_10V6K
8
6
PGND
1
VFB
2 PR102 15.4K_0402_1%
2
V5DRV
10
1
1
11
2
5
LX_1.8VP
12
LL TRIP
V5FILT
0.1U_0603_25V7K
PR100 4.7_1206_5%
14
15 TP
VOUT
4
2
PC87 680P_0603_50V7K
3
DH_1.8VP
13
DRVH
1
5 6 7 8
PR101 100_0603_1% 1 2
TON
PL8 1.8UH_SIL104R-1R8PF_9.5A_30% 1 2
PC84 BST_1.8VP
3 2 1
2
+5VALW
1
PU7
EN_PSV
2
PC83 @.1U_0402_16V7K
B+
3 2 1
PR99 2.2_0603_1% 1 2
VBST
SYSON
PL15 HCB2012KF-121T50_0805 1 2
4
PR98 0_0402_5% 1 2 1
<32,34>
2
2
5 6 7 8
1
D
PC81 4.7U_1206_25V6K
51117_B+
PC140 @0.1U_0402_25V6 2 1
4
PC82 4.7U_1206_25V6K
5
Ipeak = 8A Imax = 5.6A F = 312kHz Total Capacitor = 220 uF ESR = 15m Ohm
C
1
PR103 28.7K_0402_1% 1 2
2
PR104 20.5K_0402_1%
B
B
PU8 APL5508-25DC-TRL_SOT89-3
PJ18 1
1
2
2
2
@ JUMP_43X39
IN
OUT
3
1
2
1 2
PC90 1U_0603_10V6K
+2.5VSP
GND 1
+3VS
PC91 4.7U_0805_6.3V6K
A
A
Compal Secret Data
Security Classification 2008/04/14
Issued Date
2009/04/14
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc. 1.8VP/2.5VS Document Number
Rev 1.0
LA-5831P Wednesday, August 12, 2009
Sheet 1
40
of
44
5
4
3
2
1
+3VS D
1
D
2
1
PJ19 @ JUMP_43X79
VCNTL
6
GND
NC
5
3
VREF
NC
7
VOUT
NC
+5VALW 1
VIN
2 1
2
2
PU9 1
PC93 1U_0603_6.3V6M
2
1
PC92 4.7U_0805_6.3V6K
PR105 1.15K_0402_1% 2
4
TP
8 9
APL5331KAC-TRL_SO8 +1.5VSP
2
PC94 PQ29 .1U_0402_16V7K SSM3K7002FU_SC70-3
1 PC95 10U_0805_6.3V6M
2
S
1
1
1
PR107 0_0402_5% PC96 @ .1U_0402_16V7K
PR106 D 1K_0402_1%
2 G
2
2
1 1
3
SUSP
SUSP
2
<34>
C
C
PJ20 @ JUMP_43X79
2
1
1
+1.8V
VIN
VCNTL
6 5
GND
NC
3
VREF
NC
7
4
VOUT
NC
8
+3VALW
1 2
2
PR108 1K_0402_1%
2
PC97 4.7U_0805_6.3V6K
1
B
2
1
2
PU10 1
TP
B
PC98 1U_0603_6.3V6M
9
+0.9VP
PC99 .1U_0402_16V7K
1
1
PR109 1K_0402_1%
S PQ30 SSM3K7002FU_SC70-3
2
PC101 @ .1U_0402_16V7K
D
PC100 10U_0805_6.3V6M
2
3
2 G
2
1
PR110 0_0402_5% 1 2
2
SYSON#
1
<34>
1
APL5331KAC-TRL_SO8
A
A
Compal Secret Data
Security Classification 2008/04/14
Issued Date
2009/04/14
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Compal Electronics, Inc. 0.9VP/1.5VSP Document Number
Rev 1.0
LA-5831P Wednesday, August 12, 2009
Sheet 1
41
of
44
D
E
PR112 2_0603_5% 1 2
<7>
+CPU_CORE_1
2
1
1
1 2
PC132 0.1U_0402_25V6 2 1
3 2 1 4
1
PHASE1
26
UGATE1
25
BOOT1
3 2 1
2
2
LGATE0
2
27
PC118 1U_0603_16V6K
PC117 2 1 0.1U_0603_16V7K 1
PR136 47K_0402_1%
ISP0
LGATE1
28
PR128 3.65K_0402_1%
PC116 680P_0603_50V7K PQ35 @ TPCA8028-H_SOP-ADVANCE8-5
3 2 1
PQ34 TPCA8028-H_SOP-ADVANCE8-5
29
+CPU_CORE_0
ISN0
+5VS
30
3
1 4
LGATE0
31
4
2
1
32
PR130 4.7_1206_5% 1 2
PHASE0
1
2
UGATE0
33
5
34
2
PC115 0.22U_0603_10V7K
2
PL11 0.36UH_PCMC104T-R36MN1R17_30A_20%
5
BOOT0
PR127 2.2_0603_1% BOOT0 1 2 1
5
49
PQ36 SI7686DP-T1-E3_SO8 UGATE1
4
PC119 10U_1206_25V6M 2 1
CPU_B+
3
PHASE1
PL12 0.36UH_PCMC104T-R36MN1R17_30A_20%
3 2 1
PR139 2.2_0603_1% BOOT1 1 2 1
1
4
2
3
PR146 1
PQ37 TPCA8028-H_SOP-ADVANCE8-5
2 PR141 3.65K_0402_1%
PC122 680P_0603_50V7K PQ38 @ TPCA8028-H_SOP-ADVANCE8-5
1
1 2
4
PC123 2 1
2
4
3 2 1
PR145 0_0402_5% 1 VSEN1
+CPU_CORE_1
1
5
2
PC121 0.22U_0603_10V7K
5
@ 10_0402_5% 1 PR143 2
PR142 @ 10_0402_5% 1 2
1
PJ23
PR144 4.7_1206_5%
2 2
4
TP
ISN1 24 ISN1
ISP1 23 ISP1
VW1 22
21
FB1
COMP1
BOOT1
35
1RTN1 PR140 0_0402_5%
<7> CPU_VDD1_RUN_FB_H
1
PC114 10U_1206_25V6M 2 1
PQ33 SI7686DP-T1-E3_SO8 UGATE0
PC113 10U_1206_25V6M 2 1
5 UGATE1
36
BOOT_NB
2
+CPU_CORE_1
1 2
3 2 1
COMP0
<7> CPU_VDD1_RUN_FB_L
1
1
37
38
PHASE1
VW0
<7>
2
CPU_VDDNB_RUN_FB_L
3 2 1
<7> CPU_VDD0_RUN_FB_L
UGATE_NB
39
FB0
ISP0 ISN0 PR135 0_0402_5% 2 1 VSEN0 0_0402_5% 2 PR138 1 RTN0
<7> CPU_VDD0_RUN_FB_H
PHASE_NB
40
LGATE_NB
42
43
44
45
41
PGND_NB
OCSET_NB
RTN_NB
VSEN_NB
FSET_NB
46
PGND1
PR137 2 1 @ 10_0402_5%
3
FB_NB
LGATE1
VDIFF0
13
+CPU_CORE_0
OCSET
ISP0
12
PVCC
ISL6265HRTZ-T_QFN48_6X6
20
11
RBIAS
VDIFF1
10
LGATE0
19
9
ENABLE
VSEN1
8
PGND0
18
7
SVC
RTN1
6
PHASE0
17
PR132 0_0402_5%
PR134 4.02K_0402_1% 2 1
5
UGATE0
SVD
RTN0
PR133 113K_0402_1% 2 1
1
PWROK
VSEN0
<32> CPU_VCORE_ENABLE
4
BOOT_NB BOOT0
16
1 PR131 0_0402_5%2
3
2
2
2
PHASE0
PGOOD
15
ISL6265_PWROK
CPU_SVD CPU_SVC
OFS/VFIXEN
ISN0
<7> <7>
2
14
<21,32> SB_PWRGD
2 PR129 100K_0402_5% 2 PR158 100K_0402_5%
COMP_NB
47 VCC
VIN
48
1 2
2 1 @ 1
1
PJ22 2
+CPU_CORE_0
UGATE_NB
PR125 @ 10_0402_5%
1
VGATE
2
@ JUMP_43X118
1 PR122 0_0402_5%
PU11
2
@ JUMP_43X118
CPU_B+
2
2
1
1 2 <32> <7,20> H_PWRGD
2
LGATE_NB
2
PR121 @ 105K_0402_1%
PR126 @ 105K_0402_1%
PJ21 PC110 220U_D2_4VM
PHASE_NB
PR124 @ 10K_0402_1%
2
PC111 680P_0603_50V7K
@ JUMP_43X118
2
PR123 105K_0402_1%
AP1 +
PHASE_NB
1
PC112 0.1U_0603_25V7K
1 PR120 0_0402_5%
CPU_VDDNB_RUN_FB_H
PR119 11.3K_0402_1% 2 1
PQ32 AO4712_SO8
2
2 PR117 2_0603_5%
+3VS
1
+5VS
PR114 4.7_1206_5%
2
PC109 0.22U_0603_10V7K 4
LGATE_NB
+VDDNBP
1
PR113 2.2_0603_1% BOOT_NB 1 2 1
PR118 0_0402_5% 2 1
2
PL10 4.7U_LF919AS-4R7M-P3_5.2A_20% 1 2
3 2 1
PHASE_NB
PR115 22K_0402_1% 2 1 PR116 @ 10_0402_5% 1 2 +VDDNBP
CPU_B+
B+
1
PC107 1000P_0402_50V7K 2 1
PC108 0.1U_0603_16V7K
1
PQ31 AO4466_SO8
4
+ 2
PL9 HCB4532KF-800T90_1812 1 2
PC134 @0.1U_0402_25V6 2 1
UGATE_NB
+ 2
1
PC136 0.1U_0402_25V6 2 1
1
PC105 1000P_0402_50V7K
5 6 7 8
+5VS
1
1
5 6 7 8
2
1
PC104 @ 220U_25V_M
1
PR111 44.2K_0402_1%
PL13 HCB2012KF-121T50_0805 1 2
PC103 220U_25V_M
2
PC106 10U_1206_25V6M 2 1
CPU_B+ PC102 33P_0402_50V8J 2 1
PC133 0.1U_0402_25V6
C
PC135 @0.1U_0402_25V6 2 1
B
PC120 10U_1206_25V6M 2 1
A
0.1U_0603_16V7K
@ 10_0402_5% VW0
DIFF_1
VW1
2
2
1
COMP0
PC125 180P_0402_50V8J PR149 1K_0402_5% 2 1
PR150 2
1
PC130 2 1
1
PC126 1000P_0402_50V7K
2
1
COMP1
2
PC128 180P_0402_50V8J
PR151 6.81K_0402_1% 2 1
PR152 1K_0402_5% 2 1
PR153 2
1
1
PC129 1000P_0402_50V7K 4
PR154 6.81K_0402_1% 2 1
PC131 2 1
1 PR155 @ 36.5K_0402_1%
PR156 @ 36.5K_0402_1%
Compal Secret Data
Security Classification 2008/04/14
2009/04/14
Deciphered Date
Title
Compal Electronics, Inc.
2
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
1
PR157 47K_0402_1%
54.9K_0402_1% 1200P_0402_50V7K
1
54.9K_0402_1% 1200P_0402_50V7K
2
4
2
PR148 PC127 255_0402_1% 4700P_0402_25V7K FB_1 2 1 2 1
ISP1
LGATE1 PR147 PC124 255_0402_1% 4700P_0402_25V7K FB_0 2 1 2 1
ISN1
DIFF_0
B
C
D
+CPU_CORE Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
42
of
44
A
B
C
D
E
Version Change List ( P. I. R. List ) for Circuit Item Page# 1
35-43 39-40 38 36 37
PVT Pre-MP Pre-MP Pre-MP Pre-MP
Title Change Change Change Change
PL6,PL7,PL8 PC56 PH1,PH2 PR38,PR45
Date
Request Owner
2009/07/20 2009/07/30 2009/07/30 2009/08/4 2009/08/4
Release POWER POWER POWER POWER
Issue Description
Rev.
Solution Description
1
Change change change change
PL6,PL7,PL8 footprint to common circuit. to common circuit. to common circuit.
2
2
3
3
4
4
Compal Secret Data
Security Classification 2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
List History Rev 1.0
LA-5831P
Wednesday, August 12, 2009
Sheet E
43
of
44
5
4
3
2
1
HW4 Product Improvement Record (P.I.R.) D
NBWAE LA-5831P SCHEMATIC CHANGE LIST REVISION CHANGE: 0.1 TO 1.0 GERBER-OUT DATE: 2009/08/07 NO DATE PAGE MODIFICATION LIST PURPOSE -------------------------------------------------------------------------------------------------------------1 7/21 25 Change JUSBB footprint back to E-T_6905-E12N-00R_12P USB/B pin define reverse 2 7/27 25 Add D11 For ESD 3 7/27 9 Add C120~C123 For EMI 4 7/27 32 Add R344 and R345 For EC pin damage issue 5 7/30 26 Add R97, R98 and R105 Reserve bead for EMI 6 8/6 18 Add C707, C708 and C709 For EMI 7 8/6 30 Add LA11 and LA12 For EMI 8 8/6 32 Add R74 and C607 For EMI 9 8/6 31 Delete R518 and C606 For EMI 10 8/6 7 Add C124 For EMI --------------------------------------------------------------------------------------------------------------
D
C
C
B
B
A
A
2009-02-12
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2009-02-12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
PIR Document Number
Rev 1.0
Wednesday, August 12, 2009
Sheet 1
44
of
44
