Transcript
A
B
C
D
E
1
1
SAPPORO 150A+G 2
LA-2101 REV0.1 Schematic
2
Portability Prescott/Northwood
3
3
RC300ML(RX300ML)+IXP150+ATI M11P/M10C(128MB VRAM) 2003-11-10
4
4
Title
Compal Electronics, Inc. Cover Page
Size B Date: A
B
C
D
Document Number Tuesday, November 18, 2003
Rev 0.1 Sheet E
1
of
52
A
B
C
D
E
DAL01 LA-2101 BLOCK DIAGRAM 4
4
Programming Clock Gen
Northwood-MT Prescott-MT
PAGE 36
(uFCBGA/uFCPGA-478) page 23
Clock Generator ICS951402AGT
PAGE 5
PAGE16
PAGE 4,5,6
LCD Conn 2
LCD Conn 1
Thermal Sensor ADM1032
FANController
PAGE 42
RTC Battery
PAGE 24
CPU VID PAGE 5
page 23
FSB
533MHz
DC/DC Interface PAGE 43
CRT & TV-OUT Conn.
page 23 W/INT VGA
W/EXT VGA CHIP
533MHz(0.8V)
ATI-M11P/M10C
AGP 8X BUS
3
page 17,18,19,20
ATI-RC300ML (ATI-RX300ML)
266/333MHz (2.5V)
Memory Bus
LID/Kill Switch Power Buttom
PAGE 41
SO-DIMM x 2(DDR) BANK 0,1,2,3
PAGE 13,14,15
3
VGA M9 Embeded 868 pin u-BGA
DCIN&DETECTOR
PAGE 44
BATT CONN/OTP
PAGE 45
CHARGER
PAGE 46
3V/5V/12V
PAGE 47
PAGE 7,8,9,10,11,12
VGA DDR x2 CHA
VGA DDR x2 CHB
page 21
Mini PCI
A-Link
266MHz(3.3V)
page 22
480MHz(5V)
USB 2.0 Port *3 0, 2, 4
PAGE 37
PAGE 31
PAGE 28
PAGE 28
PCI BUS 33MHz (3.3V)
ATI-SB150
IEEE1394 TSB43AB21A
Port 1 2
Primary ATA-100 (5V)
LAN RTL8100C
RJ-45
PAGE 32
Slot 0 PAGE 30
PAGE 35
1.5V/VGA_CORE
BGA 457 pin
PAGE 32
DDR_2.5V/1.25V, 1.8VPAGE 48 IDE HDD
Secondary ATA-100 (5V)
CARDBUS
AC-LINK
ENE 712/1410
24.576MHz
PAGE 29
AC97 CODEC ALC 250
PAGE 33
PAGE 50,51,52
Audio Amplifier TPA0232
PAGE 34
Direct Board Connector
LPC BUS 33MHz (3.3V)
SD Conn
2
CPU_CORE
IDE ODD PAGE 35
PAGE 24,25,26,27
PAGE 48
(LS-1911) PAGE 40
MDC Connector
PAGE 30
PAGE 38
CB PWR SW
VR/CIR Board (LS-1913) Connector PAGE 40
ENE CP2211
PAGE 30
Super I/O
Embedded Controller
LPC47N217 REV B
NS PC87591L
PAGE 36
TP Board Connector
PAGE 39
(LS-2101) PAGE 40
1
1
FIR PAGE 37
Parallel PAGE 38
Scan KB PAGE 39
BIOS(1M) & I/O PORT PAGE 40
Title
Compal Electronics, Inc. Block Digram
Size Document Number Custom Date: A
B
C
D
Rev 0.1 Sheet
Tuesday, November 18, 2003 E
2
of
52
A
B
C
D
Voltage Rails STATE
1
2
Power Plane
Description
S1
S3
S5
VIN
Adapter power supply (19V)
ON
ON
ON
B+
AC or battery power rail for power circuit.
ON
ON
ON
+CPU_CORE
Core voltage for CPU
ON
OFF
OFF
+CPUVID
1.2V switched power rail for CPU AGTL Bus
ON
OFF
OFF
+VGA_CORE
1.0V/1.2V switched power rail for VGA chip
ON
OFF
OFF
+1.25VS
1.25V switched power rail
ON
OFF
OFF
+1.5VS
AGP 4X/8X
ON
OFF
OFF
+1.8VS
1.8VS switched power rail
ON
OFF
OFF
+2.5VALW
2.5V always on power rail
ON
ON
ON*
+2.5V
2.5V power rail
ON
ON
OFF
+2.5VS
2.5V switched power rail
ON
OFF
OFF
+3VALW
3.3V always on power rail
ON
ON
ON*
+3V
3.3V power rail
ON
ON
OFF
+3VS
3.3V switched power rail
ON
OFF
OFF ON*
+5VALW
5V always on power rail
ON
ON
+5V
5V power rail
ON
ON
OFF
+5VS
5V switched power rail
ON
OFF
OFF
+12VALW
12V always on power rail
ON
ON
ON*
+RTCVCC
RTC power
ON
ON
ON
SIGNAL
Full ON
E
SLP_S3# SLP_S5#
+VALW
+V
+VS
Clock
HIGH
HIGH
ON
ON
ON
ON
HIGH
HIGH
ON
ON
ON
LOW
S3 (Suspend to RAM)
LOW
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
HIGH
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
ON
OFF
OFF
OFF
S1(Power On Suspend)
1
Board ID Table for AD channel Vcc Ra Board ID
0 1 2 3 4 5 6 7
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
3.3V +/- 5% 100K +/- 5% Rb 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC
V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V
V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V
V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V
2
External PCI Devices Device
IDSEL#
REQ#/GNT#
Interrupts
VGA
AD16
CardBus
AD20
2
PIRQA
PIRQA
LAN
AD19
3
PIRQD
Mini-PCI
AD18
1/4
PIRQC/PIRQD
1394
AD16
0
PIRQA
SD
AD20
2
PIRQB
Board ID 0 1 2 3 4 5 6 7
3
EC SM Bus1 address
4
3
EC SM Bus2 address
Device
Address
Device
Address
Smart Battery
0001 011X b
ADM1032
1001 110X b
EEPROM(24C16/02)
1010 000X b
ICS960011
1101 110X b
(24C04)
PCB Revision 0.1
1011 000Xb
IXP150 SM Bus address Device
Address
Clock Generator (ICS951402AGT)
1101 001Xb
DDR DIMM0
1010 000Xb
DDR DIMM2
1010 001Xb
4
Compal Electronics, Inc. Title
Notes Size B Date:
A
B
C
D
Document Number
Rev 0.1
LA-2101 Tuesday, November 18, 2003
Sheet E
3
of
52
5
4
3
2
1
A10 A12 A14 A16 A18 A20 A8 AA10 AA12 AA14 AA16 AA18 AA8 AB11 AB13 AB15 AB17 AB19 AB7 AB9 AC10 AC12 AC14 AC16 AC18 AC8 AD11 AD13 AD15 AD17 AD19 AD7 AD9 AE10 AE12 AE14 AE16 AE18 AE20 AE6 AE8 AF11 AF13 AF15 AF17 AF19 AF2 AF21 AF5 AF7 AF9 B11 B13 B15 B17 B19 B7 B9 C10 C12 C14 C16 C18 C20 C8 D11 D13 D15 D17 D19 D7 D9 E10
+CPU_CORE
7 H_ADS# +CPU_CORE R67 +CPU_CORE
1 1 R87
2 51_0402_5% H_IERR# 2 51_0402_5%
J1 K5 J4 J3 H3 G1
REQ#0 REQ#1 REQ#2 REQ#3 REQ#4 ADS#
AC1 V5 AA3 AC3
AP#0 AP#1 BINIT# IERR#
H6 D2 G2 G4
BR0# BPRI# BNR# LOCK#
AF22 AF23
BCLK0 BCLK1
7 H_BR0# 7 H_BPRI# 7 H_BNR# 7 H_LOCK# 16 CLK_BCLK 16 CLK_BCLK#
CLK_BCLK CLK_BCLK#
F3 E3 E2
7 H_HIT# 7 H_HITM# 7 H_DEFER#
HOST ADDR
Northwood-MT Prescott-MT
HOST ADDR
CONTROL
CLK
CON TROL
GND
HIT# HITM# DEFER#
B
FOX_PZ47803-274A-42_Prescott
POWER VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_80 VCC_79 VCC_78 VCC_77 VCC_76 VCC_75 VCC_74
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_ADS#
C
POWER
BOOTSELECT
7 H_REQ#[0..4]
H_D#[0..63] D#0 D#1 D#2 D#3 D#4 D#5 D#6 D#7 D#8 D#9 D#10 D#11 D#12 D#13 D#14 D#15 D#16 D#17 D#18 D#19 D#20 D#21 D#22 D#23 D#24 D#25 D#26 D#27 D#28 D#29 D#30 D#31 D#32 D#33 D#34 D#35 D#36 D#37 D#38 D#39 D#40 D#41 D#42 D#43 D#44 D#45 D#46 D#47 D#48 D#49 D#50 D#51 D#52 D#53 D#54 D#55 D#56 D#57 D#58 D#59 D#60 D#61 D#62 D#63
B21 B22 A23 A25 C21 D22 B24 C23 C24 B25 G22 H21 C26 D23 J21 D25 H22 E24 G23 F23 F24 E25 F26 D26 L21 G26 H24 M21 L22 J24 K23 H25 M23 N22 P21 M24 N23 M26 N26 N25 R21 P24 R25 R24 T26 T25 T22 T23 U26 U24 U23 V25 U21 V22 V24 W26 Y26 W25 Y23 Y24 Y21 AA25 AA22 AA24
7
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
D
C
F13 F15 F17 F19 F9 F11 E8 E20 E18 E16 E14 E12
H_REQ#[0..4]
A#3 A#4 A#5 A#6 A#7 A#8 A#9 A#10 A#11 A#12 A#13 A#14 A#15 A#16 A#17 A#18 A#19 A#20 A#21 A#22 A#23 A#24 A#25 A#26 A#27 A#28 A#29 A#30 A#31 A#32 A#33 A#34 A#35
AD1
D
K2 K4 L6 K1 L3 M6 L2 M3 M4 N1 M1 N2 N4 N5 T1 R2 P3 P4 R3 T2 U1 P6 U3 T4 V2 R6 W1 T5 U4 V3 W2 Y1 AB1
H1 VSS_0 H4 VSS_1 H23 VSS_2 H26 VSS_3 A11 VSS_4 A13 VSS_5 A15 VSS_6 A17 VSS_7 A19 VSS_8 A21 VSS_9 A24 VSS_10 A26 VSS_11 A3 VSS_12 A9 VSS_13 AA1 VSS_14 AA11 VSS_15 AA13 VSS_16 AA15 VSS_17 AA17 VSS_18 AA19 VSS_19 AA23 VSS_20 AA26 VSS_21 AA4 VSS_22 AA7 VSS_23 AA9 VSS_24 AB10 VSS_25 AB12 VSS_26 AB14 VSS_27 AB16 VSS_28 AB18 VSS_29 AB20 VSS_30 AB21 VSS_31 AB24 VSS_32 AB3 VSS_33 AB6 VSS_34 AB8 VSS_35 AC11 VSS_36 AC13 VSS_37 AC15 VSS_38 AC17 VSS_39 AC19 VSS_40 AC2 VSS_41 AC22 VSS_42 AC25 VSS_43 AC5 VSS_44 AC7 VSS_45 AC9 VSS_46 AD10 VSS_47 AD12 VSS_48 AD14 VSS_49 AD16 VSS_50 AD18 VSS_51 AD21 VSS_52 AD23 VSS_53 AD4 VSS_54 AD8 VSS_55
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31
VCC_0 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73
JCPU1A 7 H_A#[3..31]
B
+CPU_CORE 2
1 R42 0_0402_5%
Reference Intel document Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0 Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5 Pin number Northwood Pin name B6
AA20
FERR#
Commend
Pull-up 62ohm to +VCC_CORE
Prescott Pin name
TESTHI6
AD2 AD3
NC
VID5
float
Northwood
TESTHI7 VIDPWRGD
A
Pull-up 62ohm to +VCC_CORE Pull-up 62ohm to +VCC_CORE Pull-up 8.2Kohm to +VCCVID Pull-up1Kohm to +3VRUN & connect to PWRIC Connect to +VCCVID
AF3
NC
float
VCCVIDLB VCCIOPLL
Connect to CPU Filter Connect to CPU Filter BOOTSELECT CPU determine OPTIMIZED/ float COMPAT#
AD20
VCCA
AF23
VCCIOPLL
AD1
VSS
Connect to CPU Filter Connect to CPU Filter Connect to GND
AE26
VSS
Connect to GND
Prescott
R_C
FERR#/PBE# Pull-up 62ohm to +VCC_CORE
ITPCLKOUT0 Pull-up56ohm to +VCC_CORE ITPCLKOUT1 Pull-up 56ohm to +VCC_CORE NC float
AB22
Commend
Pop
Pop
Pop
Pop
Pop
Pop
Depop
Pop
Depop
Pop
Depop
Pop
Pop
Depop
H_BOOTSELECT 50
1 2 R45 0_0402_5%
Pop: Northwood Depop: Prescott
A
VCCA
Title
Pop
Depop
Prescott Processor in uFCPGA478 (1/2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
Rev 0.1
LA-2101
Date:
3
2
Saturday, November 22, 2003
Sheet 1
4
of
52
5
4
3
2
1
2
H_SKTOCC#
RP4 8 7 6 5
24 24 24 7
ITP_TMS ITP_TRST# ITP_TCK ITP_TDI
H_INTR H_NMI H_INIT# H_RESET#
Close to the CPU
+CPU_CORE
6 H_THERMTRIP#
R82 R78 R75 R81 R77 R74
1 1 1 1 1 1
2 2 2 2 2 2
51_0402_5% 51_0402_5% 51_0402_5% 51_0402_5% 51_0402_5% 51_0402_5%
D1 E5 W5 AB25
H_THERMDA H_THERMDC
B3 C4
H_THERMTRIP#
A2 AC6 AB5 AC4 Y6 AA5 AB4
ITP_TCK ITP_TDI
D4 C1 D5 F7 E6
+CPU_CORE
ITP_TMS ITP_TRST# L5 1
LQG21F4R7N00_0805 2
C80
LQG21F4R7N00_0805 2
1
2 Trace >= 25mils
+
L6 1
H_VSSA
VCCIOPLL VCCA VCCSENSE VSSSENSE VCCVIDLB VSSA
2
2 1
ADSTB#0 ADSTB#1 DBI#0 DBI#1 DBI#2 DBI#3
DATA MISC
DBR#
MISC GROUND
PROCHOT# MCERR# SLP# NC1 NC2 NC3 NC4 NC5
MISC
F8 G21 G24 G3 G6 J2 J22 J25 J5 K21 K24 K3 K6 L1 L23 L26 L4 M2 M22 M25 M5 N21 N24 N3 N6 P2 P22 P25 P5 R1 R23 R26 R4 T21 T24 T3 T6 U2 U22 U25 U5 V1 V23 V26 V4 W21 W24 W3 W6 Y2 Y22 Y25 Y5
R44 51.1_0603_1%
ADDR
ITP CLK
2 @100K_0402_0.5%
CLK_ITP
R570 1
2 @100K_0402_0.5%
CLK_ITP#
Place decoupling cap 220PF near CPU.
C76 1
2
220P_0402_50V7K
D
Pop: Northwood Depop: Prescott
AA21 AA6 F20 F6 R127 1
AE26 AD24 AA2 AC21 AC20 AC24 AC23 AA20 AB22 U6 W4 Y3 A6 AD25
R_G
0_0402_5% 2
+CPU_CORE
H_TESTHI0 H_TESTHI1
R123 R59
1 1
2 56_0402_5% 2 56_0402_5%
H_TESTHI2_7
R111
1
2 56_0402_5%
H_TESTHI8 H_TESTHI9 H_TESTHI10 H_GHI# H_DPSLPR#
R79 R73 R58 R89 R124
1 1 1 1 1
2 2 2 2 2
E22 K22 R22 W22
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
F21 J23 P23 W23
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
L5 R5
H_ADSTB#0 H_ADSTB#1
E21 G25 P26 V21
56_0402_5% 56_0402_5% 56_0402_5% 300_0402_5% 56_0402_5%
H_DSTBN#[0..3] 7
H_DSTBP#[0..3]
H_DSTBP#[0..3] 7
H_ADSTB#0 7 H_ADSTB#1 7 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
AE25
130_0402_5% 2
C3 V6 AB26
H_PROCHOT#
C
7 7 7 7 R62 1
+CPU_CORE H_PROCHOT# 45 H_SLP# 24
A22 A7 AF25 AF24 AE21
Trace >= 25mils R571 1
CPU_GHI# 25
1
R112 51.1_0603_1%
2.H_VCCIOPLL,HVCCA,HVSSA trace wide 12 mils(min)
ITP_CLK0 ITP_CLK1 COMP0 COMP1
DSTBP#0 DSTBP#1 DSTBP#2 DSTBP#3
ITP
2 0_0402_5%
1
MISC
TCK TDI TDO TMS TRST#
L24 P1
DSTBN#0 DSTBN#1 DSTBN#2 DSTBN#3
DATA
BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5
+CPU_GTLREF
J26 K25 K26 L25
H_DSTBN#[0..3]
Northwood-MT Prescott-MT
VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181
COMP0 COMP1
AF26
MISC
THER MAL THERMTRIP#
CLK_ITP AC26 CLK_ITP# AD26
1.Place cap within 600 mils of the VCCA and VSSA pins.
TESTHI0 TESTHI1 TESTHI2 TESTHI3 TESTHI4 TESTHI5 TESTHI6 TESTHI7 TESTHI8 TESTHI9 TESTHI10 TESTHI11 TESTHI12
ITP
33U_D2_8M_R35
PLL Layout note :
OPTIMIZED/COMPAT#
THERMDA THERMDC
AD22
Pop: Prescott Depop: Northwood
REF
LEGACY
A5 A4 AF3
2 VCCVIDLB @0_0402_5%
1 R70
GTLREF0 GTLREF1 GTLREF2 GTLREF3
LINT0 LINT1 INIT# RESET#
AD20 AE23
H_VCCA 50 VCCSENSE 50 VSSSENSE +CPUVID
DP#0 DP#1 DP#2 DP#3
CON TROL
DBSY# DRDY# BSEL0 BSEL1
1 R80
GROUND
A20M# FERR# IGNNE# SMI# PWRGOOD STPCLK#
H5 H2 AD6 AD5
ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4 ITP_BPM#5
Note: Please change to 10uH, DC current of 100mA parts and close to cap
C
H_INTR H_NMI H_INIT# H_RESET# H_DBSY# H_DRDY#
7 H_DBSY# 7 H_DRDY# 12,16 BSEL0 12,16 BSEL1
1K_8P4R_1206_5%
C6 B6 B2 B5 AB23 Y4
H_GHI#
VCCVID
JTAG PULL DOWN
H_A20M# H_FERR# H_IGNNE# H_SMI# H_PWRGOOD H_STPCLK#
RS#0 RS#1 RS#2 RSP# TRDY#
R126 @0_0402_5%
AF4
24 H_A20M# 24 H_FERR# 24 H_IGNNE# 24 H_SMI# 24 H_PWRGOOD 24 H_STPCLK#
Place near CPU
1 2 3 4
H_TRDY#
7 H_TRDY#
2 H_RESET# 51_0402_5%
1 R120
F1 G5 F4 AB2 J6
VIDPWRGD
H_RS#0 H_RS#1 H_RS#2
AD2
2 H_PWRGOOD 300_0402_5%
VID0 VID1 VID2 VID3 VID4 VID5
2 H_THERMTRIP# 56_0402_5%
1 R119
H_RS#[0..2]
7 H_RS#[0..2]
AE5 AE4 AE3 AE2 AE1 AD3
D
1 R61
VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128
JCPU1B
SKTOCC#
AE11 AE13 AE15 AE17 AE19 AE22 AE24 AE7 AE9 AF1 AF10 AF12 AF14 AF16 AF18 AF20 AF6 AF8 B10 B12 B14 B16 B18 B20 B23 B26 B4 B8 C11 C13 C15 C17 C19 C2 C22 C25 C5 C7 C9 D10 D12 D14 D16 D18 D20 D21 D24 D3 D6 D8 E1 E11 E13 E15 E17 E19 E23 E26 E4 E7 E9 F10 F12 F14 F16 F18 F2 F22 F25 F5
+CPU_CORE
FOX_PZ47803-274A-42_Prescott
2 50 50 50 50 50 50
B
VID PWRGD Circuit
H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5
RE Pop: Prescott Depop: Northwood
+CPUVID
1
C35 0.1U_0402_10V6K
R_E +CPUVID
H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5
B
R76 @680_0603_5% 1 2 H_VID_PWRGD
GTL Reference Voltage Layout note :
Thermal Sensor
+3V
1. Place R_A and R_B near CPU (Within 1.5"). 2. +CPU_GTLREF Trace wide 12mils(min),Space 15mils
VID PULL HIGH
+3VS
+3VS
1
+3VS
8
36,39 EC_SMB_DA2
7
DSCLK SDATA
ALERT# THERM# GND
2
6 U44A 4 H_VID_PWRGD 5
3
O
1 R628 P
2 0_0402_5%
R134
VCORE_ENLL 50
I
24,50 PM_STPCPU#
14
+CPU_GTLREF
SN74LVC125APWLE_TSSOP14 G
2
1 R110 100_0603_1%
R_B
7
H_VID3 H_VID2 H_VID1 H_VID0
5 6 7 8
2 1K_0402_5% 2 1K_0402_5%
2
1
2
4.7K_0402_5%
2
1 Q6 2 3 MMBT3904_SOT23 1 Q5 3 MMBT3904_SOT23
RP3 4 3 2 1 1K_8P4R_1206_5%
A
C69 1U_0603_10V4Z
2
ADM1032ARM_RM8
1 R57 1 R47
2
1 R109 49.9_0603_1%
R_A
VID_PWRGD 50
1
2
VDD1
H_VID4
4.7K_0402_5%
1
36,39 EC_SMB_CK2
D+
H_VID5
R135 H_DPSLPR#
R627 10K_0402_5%
2
1
3
+CPU_CORE
1
0.1U_0402_16V4Z R93 @10K_0402_5%
U4 2
2
C736
0.1U_0402_16V4Z
1
H_THERMDC A
C47
2
C45 2200P_0402_50V7K
2
1
OE#
H_THERMDA
1
1
+3V POWER
Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Prescott Processor in uFCPGA478 (2/2) Document Number
Rev 0.1
LA-2101 Saturday, November 22, 2003 1
Sheet
5
of
52
5
4
3
2
1
Place 11 North of Socket(Stuff 8) +CPU_CORE
1
D
2
1
C549 22U_1206_10V4Z
2
C567 22U_1206_10V4Z
1
2
1
C585 22U_1206_10V4Z
2
1
C606 22U_1206_10V4Z
2
1
C624 22U_1206_10V4Z
2
1
C641 22U_1206_10V4Z
2
1
C18 22U_1206_10V4Z
2
1
C507 22U_1206_10V4Z
2
C518 22U_1206_10V4Z
1
2
1
C525 22U_1206_10V4Z
2
C542 22U_1206_10V4Z
D
22uF depop reference Springdale Customer Schematic R1.2 page82 Place 12 Inside Socket(Stuff all) +CPU_CORE
1
2
1
C595 22U_1206_10V4Z
2
C618 22U_1206_10V4Z
1
2
1
C643 22U_1206_10V4Z
2
1
C655 22U_1206_10V4Z
2
1
C597 22U_1206_10V4Z
2
1
C617 22U_1206_10V4Z
2
C642 22U_1206_10V4Z
1
2
1
C654 22U_1206_10V4Z
2
C57 22U_1206_10V4Z
1
2
C50 22U_1206_10V4Z
+CPU_CORE
C
1
2
1
C56 22U_1206_10V4Z
2
C
C68 22U_1206_10V4Z
Decoupling Reference Document: Springdale Chipset Platform Design guide Rev1.11 (12474)page239
+CPU_CORE
Place 9 South of Socket(Unstuff all) 1
2
1
C17 22U_1206_10V4Z
2
1
C16 22U_1206_10V4Z
2
1
C15 22U_1206_10V4Z
2
1
C14 22U_1206_10V4Z
470uF _ERS10m ohm* 15,
2
1
C22 22U_1206_10V4Z
2
1
C21 22U_1206_10V4Z
2
Decoupling Reference Requirement: 560uF Polymer, ESR:5m ohm(each) * 10 22uF X5R * 32
C20 22U_1206_10V4Z
ESR=0.5m ohm
+CPU_CORE B
B
1
1
+
1
+
C119 470U_D2_2.5VM
2
C100 470U_D2_2.5VM
2
1
+
C96 470U_D2_2.5VM
2
1
+
C79 @470U_D2_2.5VM
2
+
1 C71 470U_D2_2.5VM
2
+
C64 470U_D2_2.5VM +CPU_CORE
2
1
44,45,47 MAINPWON
R485 470_0402_5%
** +
C53 470U_D2_2.5VM
2
C9 470U_D2_2.5VM
2
1
+
C29 470U_D2_2.5VM
2
2
1
+
C43 470U_D2_2.5VM
2
+
C51 470U_D2_2.5VM
2
1
+
1
C491
1 Q39 3 MMBT3904_SOT23
2 1
R60 330_0402_5% 2
H_THERMTRIP#
H_THERMTRIP# 5
*01
2
1
0.1U_0402_16V4Z
1
1 Q30 3 MMBT3904_SOT23
2
+CPU_CORE
+CPU_CORE
1 A
+
1 C62 470U_D2_2.5VM
2
+ 2
1 C37 470U_D2_2.5VM
+
A
C30 @470U_D2_2.5VM
2
Title
CPU Decoupling
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 0.1
LA-2101
Date:
5
4
3
2
Saturday, November 22, 2003
Sheet 1
6
of
52
5
4
3
2
H_A#[3..31]
1
H_A#[3..31] 4
H_REQ#[0..4]
H_REQ#[0..4] 4
H_D#[0..63]
H_D#[0..63] 4
5 H_TRDY# 4 H_HIT# 4 H_HITM#
R613
L
Note: PLACE CLOSE TO RC300M, USE 10/10 WIDTH/SPACE +CPU_CORE 2
PLACE CLOSE TO U27 Ball W28, USE 20/20 WIDTH/SPACE
B
R292
+CPU_CORE
+1.8VS
R308 1
F26 J26 H25
NB_SUS_STAT#
2 24.9_0402_1%COMP_N
A9 AH5 AG5 C7 V28
R309 1 2 49.9_0402_1%COMP_P L13 CPVDD 1 2 HB-1M2012-121JT03_0805 C282 1 2CPVSS 1U_0603_10V4Z NB_GTLREF
W29 H23 J23 W28
PART 1 OF 6
H_TRDY# H_HIT# H_HITM#
DATA GROUP 1
A17 G25 G26 J25
ADDR. GROUP 0
H_RESET# H_RS#2 H_RS#1 H_RS#0
CPU_ADS# CPU_BNR# CPU_BPRI# CPU_DEFER# CPU_DRDY# CPU_DBSY# CPU_BR0# CPU_LOCK# CPU_CPURSET# CPU_RS2# CPU_RS1# CPU_RS0# CPU_TRDY# CPU_HIT# CPU_HITM# CPU_RSET SUS_STAT# SYSRESET# POWERGOOD CPU_COMP_N CPU_COMP_P CPVDD CPVSS CPU_VREF
1
R303 100_0402_1%
1U_0603_10V4Z
1
2
Y29 Y28
C339 220P_0402_50V7K
2
2
C378
MISC.
1
1
49.9_0402_1%
1 2 330_0402_5% 25 NB_SUS_STAT# 17,24 NB_RST# 9,27 NB_PWRGD
L27 K25 H26 J27 L26 G27 F25 K26
B17
THERMALDIODE_N THERMALDIODE_P TESTMODE
1
C363 CLOSE TO Ball W28
CPU_D0# CPU_D1# CPU_D2# CPU_D3# CPU_D4# CPU_D5# CPU_D6# CPU_D7# CPU_D8# CPU_D9# CPU_D10# CPU_D11# CPU_D12# CPU_D13# CPU_D14# CPU_D15# CPU_DBI0# CPU_DSTBN0# CPU_DSTBP0# CPU_D16# CPU_D17# CPU_D18# CPU_D19# CPU_D20# CPU_D21# CPU_D22# CPU_D23# CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_DBI1# CPU_DSTBN1# CPU_DSTBP1#
PENTIUMAGTL+ I/F IV
5 H_RESET# 5 H_RS#2 5 H_RS#1 5 H_RS#0
0.1U_0402_10V6K C724 2 1
H_ADS# H_BNR# H_BPRI# H_DEFER# H_DRDY# H_DBSY# H_BR0# H_LOCK#
CPU_A17# CPU_A18# CPU_A19# CPU_A20# CPU_A21# CPU_A22# CPU_A23# CPU_A24# CPU_A25# CPU_A26# CPU_A27# CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_ADSTB1#
DATA GROUP 2
4 H_ADS# 4 H_BNR# 4 H_BPRI# 4 H_DEFER# 5 H_DRDY# 5 H_DBSY# 4 H_BR0# 4 H_LOCK#
U30 T30 R28 R25 U25 T28 V29 T26 U29 U26 V26 T25 V25 U27 U28 T29
DATA GROUP 3
5 H_ADSTB#1
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_ADSTB#1
CPU_A3# CPU_A4# CPU_A5# CPU_A6# CPU_A7# CPU_A8# CPU_A9# CPU_A10# CPU_A11# CPU_A12# CPU_A13# CPU_A14# CPU_A15# CPU_A16# CPU_REQ0# CPU_REQ1# CPU_REQ2# CPU_REQ3# CPU_REQ4# CPU_ADSTB0#
ADDR. GROUP 1
C
M28 P25 M25 N29 N30 M26 N28 P29 P26 R29 P30 P28 N26 N27 M29 N25 R26 L28 L29 R27
CONTROL
5 H_ADSTB#0
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_ADSTB#0
DATA GROUP 0
U46A D
R232
CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36# CPU_D37# CPU_D38# CPU_D39# CPU_D40# CPU_D41# CPU_D42# CPU_D43# CPU_D44# CPU_D45# CPU_D46# CPU_D47# CPU_DBI2# CPU_DSTBN2# CPU_DSTBP2# CPU_D48# CPU_D49# CPU_D50# CPU_D51# CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59# CPU_D60# CPU_D61# CPU_D62# CPU_D63# CPU_DBI3# CPU_DSTBN3# CPU_DSTBP3#
L30 K29 J29 H28 K28 K30 H29 J28 F28 H30 E30 D29 G28 E29 D30 F29 E28 G30 G29
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DINV#0 H_DSTBN#0 H_DSTBP#0
B26 C30 A27 B29 C28 C29 B28 D28 D26 B27 C26 E25 E26 A26 B25 C25 A28 D27 E27
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DINV#1 H_DSTBN#1 H_DSTBP#1
F24 D24 E23 E24 F23 C24 B24 A24 F21 A23 B23 C22 B22 C21 E21 D22 D23 E22 F22
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DINV#2 H_DSTBN#2 H_DSTBP#2
B21 F20 A21 C20 E20 D20 A20 D19 C18 B20 E18 B19 D18 B18 C17 A18 F19 E19 F18
H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DINV#3 H_DSTBN#3 H_DSTBP#3
D
H_DINV#0 5 H_DSTBN#0 5 H_DSTBP#0 5
C
H_DINV#1 5 H_DSTBN#1 5 H_DSTBP#1 5
H_DINV#2 5 H_DSTBN#2 5 H_DSTBP#2 5
B
H_DINV#3 5 H_DSTBN#3 5 H_DSTBP#3 5
CHS-216IGP9050A21_BGA718 2
4.7K_0402_5%
+CPU_CORE 0.1U_0402_10V6K C303 22U_1206_10V4Z A
1
2
C307
1
C306
1
2 2 0.1U_0402_10V6K
C305
0.1U_0402_10V6K 1
C280
1
C304
0.1U_0402_10V6K 1
C265
2 2 2 0.1U_0402_10V6K 0.1U_0402_10V6K
1
2
C248
1
1
2 2 0.1U_0402_10V6K
C257 0.1U_0402_10V6K A
Compal Electronics, Inc. Title
ATI RC300M-AGTL+ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Document Number
Rev 0.1
LA-2101 Sheet
Saturday, November 22, 2003 1
7
of
52
5
4
3
2
1
U46B
D
13,14 DDR_SBS0 13,14 DDR_SBS1 13,14 DDR_SMA15 DDR_DM0 DDR_DM1 DDR_DM2 DDR_DM3 DDR_DM4 DDR_DM5 DDR_DM6 DDR_DM7 13,14 DDR_SRAS# 13,14 DDR_SCAS# 13,14 DDR_SWE#
C
13 DDR_CLK0 13 DDR_CLK0# 13 DDR_CLK1 13 DDR_CLK1#
AH19 AJ17 AK17 AH16 AK16 AF17 AE18 AF16 AE17 AE16 AJ20 AG15 AF15 AE23 AH20 AE25 AH7 AF10 AJ14 AF21 AH23 AK28 AD29 AB26
DDR_SRAS# DDR_SCAS#
AF24 AF25
DDR_SWE#
AE24
DDR_DQS0 DDR_DQS1 DDR_DQS2 DDR_DQS3 DDR_DQS4 DDR_DQS5 DDR_DQS6 DDR_DQS7
AJ8 AF9 AH13 AE21 AJ23 AJ27 AC28 AA25
DDR_CLK0 DDR_CLK0#
AK10 AH10
DDR_CLK1 DDR_CLK1#
AH18 AJ19 AG30 AG29
14 DDR_CLK3 14 DDR_CLK3# 14 DDR_CLK4 14 DDR_CLK4#
DDR_CLK3 DDR_CLK3#
AK11 AJ11
DDR_CLK4 DDR_CLK4#
AH17 AJ18 AF28 AG28
B
+1.8VS
13,14 13,14 14 14
DDR_SCKE0 DDR_SCKE1 DDR_SCKE2 DDR_SCKE3
13,14 13,14 14 14
DDR_SCS#0 DDR_SCS#1 DDR_SCS#2 DDR_SCS#3
L10 1 2 HB-1M2012-121JT03_0805
DDR_SCKE0 DDR_SCKE1 DDR_SCKE2 DDR_SCKE3
AF13 AE13 AG14 AF14
DDR_SCS#0 DDR_SCS#1 DDR_SCS#2 DDR_SCS#3
AH26 AH27 AF26 AG27
MPVDD
AC18
MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12 MEM_A13 MEM_A14 MEM_A15
PART 2 OF 6
MEM_DM0 MEM_DM1 MEM_DM2 MEM_DM3 MEM_DM4 MEM_DM5 MEM_DM6 MEM_DM7 MEM_RAS# MEM_CAS# MEM_WE# MEM_DQS0 MEM_DQS1 MEM_DQS2 MEM_DQS3 MEM_DQS4 MEM_DQS5 MEM_DQS6 MEM_DQS7
MEM I/F
DDR_SMA0 DDR_SMA1 DDR_SMA2 DDR_SMA3 DDR_SMA4 DDR_SMA5 DDR_SMA6 DDR_SMA7 DDR_SMA8 DDR_SMA9 DDR_SMA10 DDR_SMA11 DDR_SMA12
MEM_CK0 MEM_CK0# MEM_CK1 MEM_CK1# MEM_CK2 MEM_CK2# MEM_CK3 MEM_CK3# MEM_CK4 MEM_CK4# MEM_CK5 MEM_CK5# MEM_CKE0 MEM_CKE1 MEM_CKE2 MEM_CKE3 MEM_CS#0 MEM_CS#1 MEM_CS#2 MEM_CS#3
MEM_CAP1 MEM_CAP2
MPVDD
MEM_COMP
MPVSS
MEM_DDRVREF
DDR_DQ0 DDR_DQ1 DDR_DQ2 DDR_DQ3 DDR_DQ4 DDR_DQ5 DDR_DQ6 DDR_DQ7 DDR_DQ8 DDR_DQ9 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15 DDR_DQ16 DDR_DQ17 DDR_DQ18 DDR_DQ19 DDR_DQ20 DDR_DQ21 DDR_DQ22 DDR_DQ23 DDR_DQ24 DDR_DQ25 DDR_DQ26 DDR_DQ27 DDR_DQ28 DDR_DQ29 DDR_DQ30 DDR_DQ31 DDR_DQ32 DDR_DQ33 DDR_DQ34 DDR_DQ35 DDR_DQ36 DDR_DQ37 DDR_DQ38 DDR_DQ39 DDR_DQ40 DDR_DQ41 DDR_DQ42 DDR_DQ43 DDR_DQ44 DDR_DQ45 DDR_DQ46 DDR_DQ47 DDR_DQ48 DDR_DQ49 DDR_DQ50 DDR_DQ51 DDR_DQ52 DDR_DQ53 DDR_DQ54 DDR_DQ55 DDR_DQ56 DDR_DQ57 DDR_DQ58 DDR_DQ59 DDR_DQ60 DDR_DQ61 DDR_DQ62 DDR_DQ63
AG6 AJ7 AJ9 AJ10 AJ6 AH6 AH8 AH9 AE7 AE8 AE12 AF12 AF7 AF8 AE11 AF11 AJ12 AH12 AH14 AH15 AH11 AJ13 AJ15 AJ16 AF18 AG20 AG21 AF22 AF19 AF20 AE22 AF23 AJ21 AJ22 AJ24 AK25 AH21 AH22 AH24 AJ25 AK26 AK27 AJ28 AH29 AH25 AJ26 AJ29 AH30 AF29 AE29 AB28 AA28 AE28 AD28 AC29 AB29 AC26 AB25 Y26 W26 AE26 AD26 AA26 Y27
MEM_DQ0 MEM_DQ1 MEM_DQ2 MEM_DQ3 MEM_DQ4 MEM_DQ5 MEM_DQ6 MEM_DQ7 MEM_DQ8 MEM_DQ9 MEM_DQ10 MEM_DQ11 MEM_DQ12 MEM_DQ13 MEM_DQ14 MEM_DQ15 MEM_DQ16 MEM_DQ17 MEM_DQ18 MEM_DQ19 MEM_DQ20 MEM_DQ21 MEM_DQ22 MEM_DQ23 MEM_DQ24 MEM_DQ25 MEM_DQ26 MEM_DQ27 MEM_DQ28 MEM_DQ29 MEM_DQ30 MEM_DQ31 MEM_DQ32 MEM_DQ33 MEM_DQ34 MEM_DQ35 MEM_DQ36 MEM_DQ37 MEM_DQ38 MEM_DQ39 MEM_DQ40 MEM_DQ41 MEM_DQ42 MEM_DQ43 MEM_DQ44 MEM_DQ45 MEM_DQ46 MEM_DQ47 MEM_DQ48 MEM_DQ49 MEM_DQ50 MEM_DQ51 MEM_DQ52 MEM_DQ53 MEM_DQ54 MEM_DQ55 MEM_DQ56 MEM_DQ57 MEM_DQ58 MEM_DQ59 MEM_DQ60 MEM_DQ61 MEM_DQ62 MEM_DQ63
D
DDR_DM[0..7] DDR_DQ[0..63] DDR_DQS[0..7] DDR_SMA[0..12]
DDR_DQ[0..63]
13,14
DDR_DQS[0..7]
13,14
DDR_SMA[0..12] 13,14
C
AF6
C164 1
2
0.47U_0603_16V7K
AA29
C379 1
2
0.47U_0603_16V7K
AK19
DDR_DM[0..7] 13,14
MEN_COMP R243 1
B
2 49.9_0402_1%
C229 1
2MPVSS
AD18
AK20
1U_0603_10V4Z CHS-216IGP9050A21_BGA718
+2.5V 1
+2.5V
C748
2
R647 1K_0603_1%
1 2
0.1U_0402_10V6K
1
DDR_VREF C744
2
R636 1K_0603_1%
1 2
0.1U_0402_10V6K
L
A
DDR_VREF trace width of 20mils and space 20mils(min)
A
Compal Electronics, Inc. Title
ATI RC300M-DDR I/F Size
Document Number
Rev 0.1
LA-2101 Date: 5
4
3
2
Sheet
Saturday, November 22, 2003 1
8
of
52
5
4
3
2
1
A_AD[0..31]
12,24 A_AD[0..31]
A_CBE#[0..3]
24 A_CBE#[0..3]
AGPAND LVDS MUXED SIGNALS
U46C
A_PAR A_STROBE# A_ACAT# A_END# 0_0402_5% 2 A_DEVSEL# A_OFF#
AD5 AC6 AC5 AD2 W4 AD3 AD6
R1741 24 A_DEVSEL# 24 A_OFF#
A_SBREQ# A_SBGNT#
24 A_SBREQ# 24 A_SBGNT# +3VS
W5 W6
1 2 R196 8.2K_0402_5%
V5 V6
AGP_GNT# AGP_REQ#
K5 K6
AGP8X_DET#
M5
AGPREF_8X
J6
2 AGP_COMP
J5
17 AGP_GNT# 17 AGP_REQ# ?
ALINK_CBE#0 ALINK_CBE#1 ALINK_CBE#2 ALINK_CBE#3 PCI_PAR/ALINK_NC PCI_FRAME#/ALINK_STROBE# PCI_IRDY#/ALINK_ACAT# PCI_TRDY#/ALINK_END# INTA# ALINK_DEVSEL# PCI_STOP#/ALINK_OFF# ALINK_SBREQ# ALINK_SBGNT# PCI_REQ#0/ALINK_NC PCI_GNT#0/ALINK_NC
AGP2_GNT#/AGP3_GNT AGP2_REQ#/AGP3_REQ
R573
1
2 @0_0402_5%
AGP_SBA3
R591
1
2 @0_0402_5%
ENVDD 17,23
AGP_SBA4
R590
1
2 @0_0402_5%
AGP_STP# 17,25
AGP_SBA5
R572
1
2 @0_0402_5%
AGP_BUSY# 17,25
AGP_SBA1
R593
1
2 @0_0402_5%
AGP_SBA0
R592
2 @0_0402_5%
1
AGP2_IRDY#/AGP3_IRDY/GPIO8/I2C_CLK AGP2_TRDY#/AGP3_TRDY/TMDS_DVI_CLK AGP2_STOP#/AGP3_STOP/GPIO10/DDC_DATA AGP_PAR AGP2_FRAME#/AGP3_FRAME/TMDS_DVI_DATA AGP2_DEVSEL#/AGP3_DEVSEL/GPIO9/I2C_DATA AGP2_PIPE#/AGP3_DBI_HI AGP2_NC/AGP3_DBI_LO AGP2_RBF#/AGP3_RBF AGP2_WBF#/AGP3_WBF
AGP_COMP AGP_ST0 AGP_ST1 AGP_ST2
169_0402_1%
C3 C2 D4 E4 F6 F5 G6 G5
AGP_SBA0 AGP_SBA1 AGP_SBA2 AGP_SBA3 AGP_SBA4 AGP_SBA5 AGP_SBA6 AGP_SBA7
L6 M6 L5
AGP_ST0 AGP_ST1 AGP_ST2
+3VS
NB_EDID_CLK 23
2 @2.2K_0402_5%
+3VS
AGP_SB_STBF 17 AGP_SB_STBS 17 AGP_AD_STBF0 17 AGP_AD_STBS0 17 AGP_AD_STBF1 17 AGP_AD_STBS1 17
AGP_SBA[0..7] AGP_C/BE#[0..3]
C
AGP_AD[0..31] 17 AGP_SBA[0..7] 17 AGP_C/BE#[0..3] 17 AGP_ST[0..2] 17
AGP_IRDY# 17 AGP_TRDY# 17 AGP_STOP# 17 AGP_PAR 17 AGP_FRAME# 17 AGP_DEVSEL# 17 AGP_DBI_HI 17 AGP_DBI_LO 17 AGP_RBF# 17 AGP_WBF# 17 +3VS
R161 @10K_0402_5%
+3VS
R151
R168
B
1 1
@10K_0402_5%
2
ENBKL 17,39 B
@0_0402_5%
D
2 G S
D
3
@2N7002_SOT23 2 G
7,27 NB_PWRGD
1
1
CHS-216IGP9050A21_BGA718
POP For 150G DEPOP For 150A
NB_EDID_CLK
POP For 150A DEPOP For 150G
AGP_ST[0..2] AGP_IRDY# AGP_TRDY# AGP_STOP# AGP_PAR AGP_FRAME# AGP_DEVSEL# AGP_DBI_HI AGP_DBI_LO AGP_RBF# AGP_WBF#
D
NB_EDID_DAT 23
2 @2.2K_0402_5%
1 R574
AGP_C/BE#0 AGP_C/BE#1 AGP_C/BE#2 AGP_C/BE#3
P5 R6 T6 T5 P6 R5 C1 D3 N6 N5
NB_EDID_DAT 1 R575
AGP_AD[0..31]
AGP2_SBA0/AGP3_SBA#0/GPIO0/VDDC_CNTL0 AGP2_SBA1/AGP3_SBA#1/GPIO1/VDDC_CNTL1 AGP2_SBA2/AGP3_SBA#2/GPIO2/LVDS_BLON# AGP2_SBA3/AGP3_SBA#3/GPIO3/LVDS_DIGON AGP2_SBA4/AGP3_SBA#4/GPIO4/STP_AGP# AGP2_SBA5/AGP3_SBA#5/GPIO5/AGP_BUSY# AGP2_SBA6/AGP3_SBA#6/GPIO6/LVDS_SSOUT AGP2_SBA7/AGP3_SBA#7/GPIO7/LVDS_SSIN
AGP_VREF/TMDS_VREF
AGP_SB_STBF AGP_SB_STBS AGP_AD_STBF0 AGP_AD_STBS0 AGP_AD_STBF1 AGP_AD_STBS1
E5 E6 T3 U2 G3 H2
R3 AGP2_CBE#0/AGP3_CBE0/TMD2_D7 M1 AGP2_CBE#1/AGP3_CBE1/TMD2_DE L3 AGP2_CBE#2/AGP3_CBE2 H1 AGP2_CBE#3/AGP3_CBE3/TMD1_D5
AGP8X_DET#
+1.5VS R589 1
AGP2_SBSTB/AGP3_SBSTBF/NC/LVDS_BLON AGP2_SBSTB#/AGP3_SBSTBS/NC/ENA_BL AGP2_ADSTB0/AGP3_ADSTBF0/TMD2_CLK# AGP2_ADSTB0#/AGP3_ADSTBS0/TMD2_CLK AGP2_ADSTB1/AGP3_ADSTBF1/TMD1_CLK# AGP2_ADSTB1#/AGP3_ADSTBS1/TMD1_CLK
ENBKL#
AGP_SBA2
2
12,24 A_PAR 24 A_STROBE# 24 A_ACAT# 24 A_END# 17,24,29,32 PCI_PIRQA#
C
PART 3 OF 6
AGP_AD0 AGP_AD1 AGP_AD2 AGP_AD3 AGP_AD4 AGP_AD5 AGP_AD6 AGP_AD7 AGP_AD8 AGP_AD9 AGP_AD10 AGP_AD11 AGP_AD12 AGP_AD13 AGP_AD14 AGP_AD15 AGP_AD16 AGP_AD17 AGP_AD18 AGP_AD19 AGP_AD20 AGP_AD21 AGP_AD22 AGP_AD23 AGP_AD24 AGP_AD25 AGP_AD26 AGP_AD27 AGP_AD28 AGP_AD29 AGP_AD30 AGP_AD31
Y2 W3 W2 V3 V2 V1 U1 U3 T2 R2 P3 P2 N3 N2 M3 M2 L1 L2 K3 K2 J3 J2 J1 H3 F3 G2 F2 F1 E2 E1 D2 D1
1
AG4 AE2 AC3 AA3
AGP_AD0/TMD2_HSYNC AGP_AD1/TMD2_VSYNC AGP_AD2/TMD2_D1 AGP_AD3/TMD2_D0 AGP_AD4/TMD2_D3 AGP_AD5/TMD2_D2 AGP_AD6/TMD2_D5 AGP_AD7/TMD2_D4 AGP_AD8/TMD2_D6 AGP_AD9/TMD2_D9 AGP_AD10/TMD2_D8 AGP_AD11/TMD2_D11 AGP_AD12/TMD2_D10 AGP_AD13 AGP_AD14 AGP_AD15 AGP_AD16/TMD1_VSYNC AGP_AD17/TMD1_HSYNC AGP_AD18/TMD1_DE AGP_AD19/TMD1_D0 AGP_AD20/TMD1_D1 AGP_AD21/TMD1_D2 AGP_AD22/TMD1_D3 AGP_AD23/TMD1_D4 AGP_AD24/TMD1_D7 AGP_AD25/TMD1_D6 AGP_AD26/TMD1_D9 AGP_AD27/TMD1_D8 AGP_AD28/TMD1_D11 AGP_AD29/TMD1_D10 AGP_AD30/TMDS_HPD AGP_AD31
2
A_CBE#0 A_CBE#1 A_CBE#2 A_CBE#3
D
ALINK_AD0 ALINK_AD1 ALINK_AD2 ALINK_AD3 ALINK_AD4 ALINK_AD5 ALINK_AD6 ALINK_AD7 ALINK_AD8 ALINK_AD9 ALINK_AD10 ALINK_AD11 ALINK_AD12 ALINK_AD13 ALINK_AD14 ALINK_AD15 ALINK_AD16 ALINK_AD17 ALINK_AD18 ALINK_AD19 ALINK_AD20 ALINK_AD21 ALINK_AD22 ALINK_AD23 ALINK_AD24 ALINK_AD25 ALINK_AD26 ALINK_AD27 ALINK_AD28 ALINK_AD29 ALINK_AD30 ALINK_AD31
PCI BUS 1 / AGP Bus (GPIO , TMDS , ZVPort)
AK5 AJ5 AJ4 AH4 AJ3 AJ2 AH2 AH1 AG2 AG1 AG3 AF3 AF1 AF2 AF4 AE3 AE4 AE5 AE6 AC2 AC4 AB3 AB2 AB5 AB6 AA2 AA4 AA5 AA6 Y3 Y5 Y6
PCI Bus 0 / A-Link I/F
A_AD0 A_AD1 A_AD2 A_AD3 A_AD4 A_AD5 A_AD6 A_AD7 A_AD8 A_AD9 A_AD10 A_AD11 A_AD12 A_AD13 A_AD14 A_AD15 A_AD16 A_AD17 A_AD18 A_AD19 A_AD20 A_AD21 A_AD22 A_AD23 A_AD24 A_AD25 A_AD26 A_AD27 A_AD28 A_AD29 A_AD30 A_AD31
Q8 @2N7002_SOT23
Q10
3
S
+1.5VS
1
ENBKL# AGP8X_DET#
+AGP_VREF
2
R188 10K_0402_5%
POP For 150A DEPOP For 150G
POP For 150A DEPOP For 150G
@1K_0402_1% AGPREF_8X
1
1
R588
POP For 150G DEPOP For 150A
2
R153
2
@1K_0402_1%
2
1
C698 0.1U_0402_10V6K
A
A
Compal Electronics, Inc. Title
ATI RC300M-AGP, ALINK BUS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Document Number
Rev 0.1
LA-2101 Sheet
Saturday, November 22, 2003 1
9
of
52
5
4
3
2
1
+3VS +2.5VS 1
L43 1 2 FBM-11-160808-121-T_0603
1
C723
L45 2
0.1U_0402_10V6K
KC FBM-L11-201209-221LMAT_0805 G9 H9
1
A14 B13 B14
0.1U_0402_10V6K
C13 A15 C745 B15
0.1U_0402_10V6K 0.1U_0402_10V6K 2 2 L42 1 2 KC FBM-L11-201209-221LMAT_0805 1 1 1 C729 C727 C726 10U_0805_10V4Z
2 2 2 0.1U_0402_10V6K 23 NB_CRT_R 23 NB_CRT_G 23 NB_CRT_B 23 CRT_HSYNC 23 CRT_VSYNC R274 1
16 REFCLK1_NB
1 R600
PLLVDD_18
H11
PLLVSS_18
G11
F14 F15 E14 C8 D9
CRT_HSYNC CRT_VSYNC
C14
RC300M_X1
A4 B4
47_0402_5% 2
C
1
R594 @10_0402_5%
16 CLK_NB_BCLK 16 CLK_NB_BCLK#
R599 56_0402_5%
1
CLK_AGP_66M
2
+3VS C702
R614 10K_0402_5%
16 CLK_AGP_66M 16 CLK_MEM
CLK_NB_BCLK CLK_NB_BCLK# R605 @10K_0402_5% 1 2 1 2 @10K_0402_5% R607 1 2 @10K_0402_5% R611 1 2 @10K_0402_5% R585 CLK_AGP_66M CLK_MEM
A5 B5 B6 A6 D8 B2 B3 A3
@10K_0402_5% R609 1 2 1
1
CLK_MEM
2
@15P_0402_50V8J
D7 B7
R595 C5 @10_0402_5%
AVDDQ AVSSQ PLLVDD_18 PLLVSS
C703
LPVDD_18 LPVSS
RED GREEN BLUE DACHSYNC DACVSYNC RSET
LVDDR_18 LVDDR_18 LVSSR LVSSR
XTALIN XTALOUT C_R HCLKIN HCLKIN# SYS_FBCLKOUT SYS_FBCLKOUT#
Y_G COMP_B DACSCL
ALINK_CLK DACSDA
E10 D10 B9 C9 D11 E11 B10 C10
TXA0-_NB 23 TXA0+_NB 23 TXA1-_NB 23 TXA1+_NB 23 TXA2-_NB 23 TXA2+_NB 23 TXACLK-_NB 23 TXACLK+_NB 23
A12
+1.8VS_LPVDD
A11
LPVSS
C735
+1.8VS_LVDDR
B12 C12
2 2 0.1U_0402_10V6K
LVSSR
B11 C11
C225 E15
TV_CRMA
C15
TV_LUMA
D15
TV_COMPS
D6
3VDDCCL
C6
3VDDCDA
TV_CRMA 23
KC FBM-L11-201209-221LMAT_0805 0.1U_0402_10V6K 1 2 L44 1 1 C734 C731
1
1
2 10U_0805_10V4Z
KC FBM-L11-201209-221LMAT_0805 0.1U_0402_10V6K 1 2 L12 1 1 C224 C215
2 0.1U_0402_10V6K
2
+1.8VS
+1.8VS
2 10U_0805_10V4Z
TV_LUMA 23 1 R242
2 75_0603_1%
C
3VDDCCL 23 3VDDCDA 23
AGPCLKOUT AGPCLKIN CPUSTOP#
D5 R603
EXT_MEM_CLK SYSCLK USBCLK REF27
1K_0402_5%
+3VS
A8
CLK. GEN.
SYSCLK#
B8
OSC CHS-216IGP9050A21_BGA718
R602
R192 @10K_0402_5%
@10K_0402_5%
@10K_0402_5% 1
@15P_0402_50V8J
TXOUT_L0N TXOUT_L0P TXOUT_L1N TXOUT_L1P TXOUT_L2N TXOUT_L2P TXCLK_LN TXCLK_LP
D
R204
2
2
AVSSDI
0.1U_0402_10V6K
2 715_0402_1% NB_RSET
2
AVDDDI_18
TXB0-_NB 23 TXB0+_NB 23 TXB1-_NB 23 TXB1+_NB 23 TXB2-_NB 23 TXB2+_NB 23 TXBCLK-_NB 23 TXBCLK+_NB 23
2
+1.8VS
AVSSN
D12 E12 F11 F12 D13 D14 E13 F13
2
1
TXOUT_U0N TXOUT_U0P TXOUT_U1N TXOUT_U1P TXOUT_U2N TXOUT_U2P TXCLK_UN TXCLK_UP
1
2 L48 1 2 KC FBM-L11-201209-221LMAT_08051 C746
PART 4 OF 6
AVDD_25
1
+1.8VS
VDDR3 VDDR3
SVID
+1.8VS
2
KC FBM-L11-201209-221LMAT_0805 L11 1 2 1 C261
C741 0.1U_0402_10V6K
CRT
D
LVDS
2
U46D
B
B
A
A
Compal Electronics, Inc. Title
ATI RC300M-AGP, ALINK BUS Size
Document Number
Rev 0.1
LA-2101 Date: 5
4
3
2
Saturday, November 22, 2003 1
Sheet
10
of
52
5
4
+1.5VS
3
2
1
+2.5V U46F U46E
+3VS
AA1 AA7 AA8 AC7 AC8 AD1 AD7 AD8 AK3 W8
B
PART 5 OF 6
VDDL_ALINK VDDL_ALINK VDDL_ALINK VDDL_ALINK VDDL_ALINK VDDL_ALINK VDDL_ALINK VDDL_ALINK VDDL_ALINK VDDL_ALINK
MEM I/F PWR
CORE PWR
VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU
AA23 AA27 AB30 AC10 AC12 AC13 AC15 AC17 AC19 AC21 AC23 AC24 AC25 AC27 AD10 AD12 AD13 AD15 AD17 AD19 AD21 AD23 AD24 AD25 AD27 AE10 AE14 AE15 AE19 AE20 AE30 AE9 AF27 AG11 AG12 AG17 AG18 AG23 AG24 AG26 AG8 AG9 AJ30 AK14 AK23 AK8 V23 W23 W24 W25 Y25
VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM
R608 1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
PART 6 OF 6
GND
0_0603_5% 2 +1.5VS
1
2
R610
R23 R7 R8 T12 T13 T14 T15 T16 T17 T18 T19 T27 T4 U15 U16 U7 U8 V15 V16 V27 V4 V7 V8 W15 W16 W27 Y1 Y23 Y24 Y30 Y4 Y7 Y8 R19 R18 R17 R16 R15 R14 R13 R12 R1 P4 P27 P16 P15 N8 N24 N23 N16 N15 M4 M27 M16 M15 L8 L7 L25 L24 L23 K4 K27 J8
D
C
+1.8VS +3VS
B
0.1U_0402_10V6K
+3VS
0.1U_0402_10V6K
@0_0603_5% C263 10U_0805_10V4Z
+1.8VS
CHS-216IGP9050A21_BGA718
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
CHS-216IGP9050A21_BGA718
POP For 150G DEPOP For 150A
AC22 AC9 H10 H22
VDD_18 VDD_18 VDD_18 VDD_18
A29 AB23 AB24 AB27 AB4 AB8 AC1 AC11 AC14 AC16 AC20 AC30 AD11 AD14 AD16 AD20 AD4 AE27 AF30 AF5 AG10 AG13 AG16 AG19 AG22 AG25 AG7 AH28 AH3 AJ1 AK13 AK2 AK22 AK29 AK4 AK7 B1 B16 B30 C19 C23 C27 C4 D21 D25 E3 E8 E9 F27 F4 F8 G14 G15 G18 G20 H14 H15 H18 H20 H27 H4 H8 J7
+1.5VS
A2 G4 H5 H6 H7 J4 K8 L4 M7 M8 N4 P1 P7 P8 R4 T8 U4 U5 U6 E7 F7 G8
VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP/VDDP33 VDDP_AGP/VDDP33 VDDP_AGP/VDDP33
AGP PWR
C16 D16 D17 E16 E17 F16 F17 G17 G21 G23 G24 H16 H17 H19 H21 H24 K23 K24 M23 P23 P24 T23 T24 U23 U24 W30
POWER
+CPU_CORE
C
CPU I/F PWR
D
VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE
ALINK PWR
F10 F9 G12 H12 H13 M12 M13 M14 M17 M18 M19 N12 N13 N14 N17 N18 N19 P12 P13 P14 P17 P18 P19 U12 U13 U14 U17 U18 U19 V12 V13 V14 V17 V18 V19 W12 W13 W14 W17 W18 W19
1
2
POP For 150A DEPOP For 150G
C288
1
C186
2 0.1U_0402_10V6K
1
2
C184
1
1
2 0.1U_0402_10V6K
2
C289 C130 0.1U_0402_10V6K 10U_0805_10V4Z
1
C178
2
1
C179
1
C170
0.1U_0402_10V6K 1
C172
2 2 2 0.1U_0402_10V6K 0.1U_0402_10V6K
1
2
C171
0.1U_0402_10V6K 1
C140
1
2 2 0.1U_0402_10V6K
C141
0.1U_0402_10V6K 1
1
C150
2 2 0.1U_0402_10V6K
+2.5V +1.5VS 0.1U_0402_10V6K 0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
C137
+
C163
1
1
C156
C142
1
C155
1
C169
1
C151
1
C168
1
C154
1
1
C790
2
2 0.1U_0402_10V6K
2
2 0.1U_0402_10V6K
2
2 0.1U_0402_10V6K
2
2 0.1U_0402_10V6K
2
+
C258
1
C252
1
C241
1
C216
1
0.1U_0402_10V6K
C203
1
C247
1
0.1U_0402_10V6K
C204
1
C180
1
0.1U_0402_10V6K
C352
1
C353
1
C329
0.1U_0402_10V6K 1
C330
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
2
0.1U_0402_10V6K 2 2 2 0.1U_0402_10V6K
C354C317
1
C308
1
C293
1
C322
0.1U_0402_10V6K 1
C309
1
1
C272
C183 100U_D2_6.3VM
47U_B_6.3VM
0.1U_0402_10V6K
1
1
2 0.1U_0402_10V6K
2
2 0.1U_0402_10V6K
2
2 0.1U_0402_10V6K
2
2 0.1U_0402_10V6K
2
2 0.1U_0402_10V6K
2
2 0.1U_0402_10V6K
2
2 0.1U_0402_10V6K
2
2 0.1U_0402_10V6K
2 2 0.1U_0402_10V6K
+1.5VS 0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.01U_0402_16V7Z
C182
1
C181
1
C262
1
1
C249
1
C256
1
C255 C240
1
C239
1
C200
1
C209
1
C202
1
C214
1
C201
1
C213
1
1
C212
C199
1
C211
1
C198
1
C254
1
C238
1
C253
1
C237
1
1
C230
C271
1
+
1
1 C279
C707
2
2 2 2 2 2 2 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2
2 2 0.1U_0402_10V6K
2 2 2 0.1U_0402_10V6K 0.1U_0402_10V6K
2
2 2 0.1U_0402_10V6K
2 2 0.1U_0402_10V6K
2 2 0.1U_0402_10V6K
2 2 2 2 0.1U_0402_10V6K 0.01U_0402_16V7Z
2
A
47U_B_6.3VM
2
A
4.7U_0805_10V4Z 4.7U_0805_10V4Z
Compal Electronics, Inc. Title
ATI RC300M-POWER THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Document Number
Rev 0.1
LA-2101 Sheet
Tuesday, November 18, 2003 1
11
of
52
5
4
3
R142 1
D
A_AD30
R163
R587
2 10K_0402_5% D22 2 1
+3VS
4.7K_0402_5%
BSEL1 5,16
A_AD[31..30] : FSB CLK SPEED
DEFAULT: 01
CH751H-40_SC76 R569 1 2 10K_0402_5% +3VS D59 4.7K_0402_5% 2 1 BSEL0 5,16 CH751H-40_SC76
A_AD29
R147 1
2 10K_0402_5%
R158
@4.7K_0402_5%
A_AD18
R149
@4.7K_0402_5%
R160
4.7K_0402_5%
+3VS
0: DISABLE 1:ENABLE
A_AD17
R563
@4.7K_0402_5%
R580
4.7K_0402_5%
+3VS
R568 1 R584
2 @10K_0402_5%
DEFAULT:0 0: DISABLE 1: ENABLE
A_AD27
R144 1
2 10K_0402_5%
R155
@4.7K_0402_5%
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
00: 1.05V 01: 1.35V 11: 1.75V 10: 1.45V
A_AD28: SPREAD SPECTRUM ENABLE
+3VS
4.7K_0402_5%
D
DEFAULT: 0
DEFAULT:1 0: REDUCEDE SET 1: FULL SET
A_AD28
A_AD18 : ENABLE PHASE CALIBRATION DEFAULT: 0
00: 100 MHZ 01: 133 MHZ 10: 200MHZ 11:166 MHZ
A_AD29: STRAP CONFIGURATION
+3VS
1
A_AD[0..31]
9,24 A_AD[0..31]
A_AD31
2
9,24 A_PAR
A_PAR
R159
@4.7K_0402_5%
R148
4.7K_0402_5%
A_AD27: FrcShortReset#
+3VS
PAR: EXTENDED DEBUG MODE +3VS
DEFAULT : 1 0: DEBUG MODE 1: NORMAL
DEFAULT: 1 0: TEST MODE 1: NORMAL MODE
A_AD26
R143 1
2 10K_0402_5%
R154
@4.7K_0402_5%
A_AD26 : ENABLE IOQ
+3VS
DEFAULT: 1
C
C
0: IOQ=1 1: IOQ=12
A_AD25
R565 1
2 10K_0402_5%
R582
@4.7K_0402_5%
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
+3VS
DEFAULT: 10 00: 1.05V 01: 1.35V 11: 1.75V 10: 1.45V
A_AD24
R566 1
2 10K_0402_5%
AD25=1 DESTOP CPU AD25=0 MOBILE CPU AD17--DON'T CARE
A_AD24 : MOBILE CPU SELECT
+3VS
DEFAULT: 1 0: BANIAS CPU 1: OTHER CPU
A_AD23
R567 1
2 10K_0402_5%
R583
@4.7K_0402_5%
R145 1
2 10K_0402_5%
R156
@4.7K_0402_5%
A_AD23 : CLOCK BYPASS DISABLE
+3VS
DEFAULT: 1 0: TEST MODE 1: NORMAL
B
A_AD22
+3VS
B
A_AD22 : OSC PAD OUTPUT PCICLK
DEFAULT : 1 0: PCICLK OUT 1: OSC CLK OUT
A_AD21
R146 1
2 10K_0402_5%
R157
@4.7K_0402_5%
A_AD21 : AUTO_CAL ENABLE
+3VS
DEFAULT : 1 0: DISABLE 1: ENABLE
A_AD20
R564
@4.7K_0402_5%
R581
4.7K_0402_5%
A_AD20 : INTERNAL CLK GEN ENABLE
+3VS
DEFAULT : 0 0: DISABLE 1: ENABLE
A
A
Compal Electronics, Inc. Title
ATI RC300M-SYSTEM STRAP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Document Number
Rev 0.1
LA-2101 Sheet
Saturday, November 22, 2003 1
12
of
52
B
C
D
E
F
+2.5V
+2.5V
DDR_DQ2 DDR_DQ13 1
DDR_DQ15 DDR_DQS1 DDR_DQ14 DDR_DQ10 8 DDR_CLK0 8 DDR_CLK0#
DDR_DQ17 DDR_DQ21 DDR_DQS2 DDR_DQ23 DDR_DQ18 DDR_DQ29 DDR_DQ[0..63] DDR_DQS[0..7] DDR_DM[0..7] DDR_SMA[0..12]
DDR_DQ[0..63]
8,14
DDR_DQS[0..7]
8,14
DDR_DQ25 DDR_DQS3 DDR_DQ30 DDR_DQ31
DDR_DM[0..7] 8,14 DDR_SMA[0..12] 8,14
2
DDR_CKE1
RP21 8,14 DDR_SCKE1
1 DDR_SMA12 2 DDR_SMA9 3 DDR_SMA7 4
8 7 6 5
DDR_SMAA12 DDR_SMAA9
10_0804_8P4R_5% RP24 DDR_SMA5 1 8 DDR_SMA3 2 7 DDR_SMA1 3 6 DDR_SMA10 4 5
8,14 DDR_SBS0 8,14 DDR_SWE# 8,14 DDR_SCS#0 8,14 DDR_SMA15
10_0804_8P4R_5% RP28 DDR_SBS0 1 8 DDR_SWE# 2 7 3 6 DDR_SMA15 4 5 10_0804_8P4R_5%
DDR_SMAA7 DDR_SMAA5 DDR_SMAA3 DDR_SMAA1 DDR_SMAA10 DDR_BS0 DDR_WE# DDR_CS#0 DDR_SMAA15 DDR_DQ33 DDR_DQ37 DDR_DQS4 DDR_DQ39 DDR_DQ35 DDR_DQ45 DDR_DQ41 DDR_DQS5
3
DDR_DQ43 DDR_DQ47
DDR_DQ49 DDR_DQ53 DDR_DQS6 DDR_DQ55 DDR_DQ51 DDR_DQ56 DDR_DQ63 DDR_DQS7 DDR_DQ62 DDR_DQ58 14,16,25 SMDATA 14,16,25 SMCLK +3VS
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD CB0 CB1 VSS DQS8 CB2 VDD CB3 DU VSS CK2 CK2# VDD CKE1 DU/A13 A12 A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 WE# S0# DU VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDD_SPD VDD_ID
DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD CB4 CB5 VSS DM8 CB6 VDD CB7 DU/RESET# VSS VSS VDD VDD CKE0 DU/BA2 A11 A8 VSS A6 A4 A2 A0 VDD BA1 RAS# CAS# S1# DU VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD CK1# CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
DDR_DQ0 DDR_DQ6
C105 0.1U_0402_10V6K
R133 1K_0603_1%
1 DDRA_VREF
DDR_DM0 DDR_DQ5 DDR_DQ7 DDR_DQ12
1
DDR_DQS0 DDR_DQ3
2 VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS
2 C101 0.1U_0402_10V6K
R132 1K_0603_1%
1
DDR_DQ8 DDR_DM1 DDR_DQ9 DDR_DQ11
1
2
DDR_DQ1 DDR_DQ4
VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 CK0# VSS
H
1
+2.5V JP24 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
G
+2.5V
2
A
L
DDRA_VREF trace width of 20mils and space 20mils(min)
DDR_DQ20 DDR_DQ16
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
DDR_DM2 DDR_DQ22 DDR_DQ19 DDR_DQ24 DDR_DQ28 DDR_DM3 DDR_DQ26 DDR_DQ27
2
RP20 8 7 6 5
DDR_CKE0 DDR_SMAA11 DDR_SMAA8
1 2 3 4
10_0804_8P4R_5% RP25 8 1 7 2 6 3 5 4
DDR_SMAA6 DDR_SMAA4 DDR_SMAA2 DDR_SMAA0 DDR_BS1 DDR_RAS# DDR_CAS# DDR_CS#1
10_0804_8P4R_5% RP29 8 1 7 2 6 3 5 4
DDR_DQ32 DDR_DQ36
DDR_SCKE0 8,14
DDR_SMA11 DDR_SMA8
DDR_SMA6 DDR_SMA4 DDR_SMA2 DDR_SMA0
DDR_SBS1 DDR_SRAS# DDR_SCAS#
DDR_SBS1 8,14 DDR_SRAS# 8,14 DDR_SCAS# 8,14 DDR_SCS#1 8,14
10_0804_8P4R_5%
DDR_DM4 DDR_DQ38 DDR_DQ34 DDR_DQ44 DDR_DQ40 DDR_DM5
3
DDR_DQ42 DDR_DQ46 DDR_CLK1# 8 DDR_CLK1 8 DDR_DQ48 DDR_DQ52 DDR_DM6 DDR_DQ54 DDR_DQ50 DDR_DQ61 DDR_DQ60 DDR_DM7 DDR_DQ57 DDR_DQ59
KLINK_5747-3-111 4
4
Layout note Layout note Place Add/Command resisotrs Close to Pin, max L = 300 mils
Compal Electronics, Inc. Title
DDR-SODIMM SLOT0 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
E
F
Size
Document Number
Rev 0.1
LA-2101 Date:
Saturday, November 22, 2003 G
Sheet
13 H
of
52
DDR_DQ1 DDR_DQ4 DDR_DQS0 DDR_DQ3
8 7 6 5 56_0804_8P4R_5%
8 7 6 5
DDR_DQ0 DDR_DQ6 DDR_DM0 DDR_DQ5
1 2 3 4
DDR_DQ1 DDR_DQ4 DDR_DQS0 DDR_DQ3
56_0804_8P4R_5%
RP8 DDR_DQ2 DDR_DQ13 DDR_DQ15 DDR_DQS1
8 7 6 5 56_0804_8P4R_5%
8 7 6 5
8 7 6 5
DDR_DQ7 DDR_DQ12 DDR_DQ8 DDR_DM1
1 2 3 4
DDR_DQ14 DDR_DQ10 8 DDR_CLK3 8 DDR_CLK3#
56_0804_8P4R_5%
RP10 DDR_DQ14 DDR_DQ10 DDR_DQ17 DDR_DQ21
DDR_DQ15 DDR_DQS1
RP7 1 2 3 4
DDR_DQ17 DDR_DQ21
RP9 1 2 3 4
56_0804_8P4R_5%
8 7 6 5
DDR_DQ9 DDR_DQ11 DDR_DQ20 DDR_DQ16
1 2 3 4
DDR_DQS2 DDR_DQ23 DDR_DQ18 DDR_DQ29
56_0804_8P4R_5% DDR_DQ25 DDR_DQS3
RP12 DDR_DQS2 DDR_DQ23 DDR_DQ18 DDR_DQ29
8 7 6 5
DDR_DQ30 DDR_DQ31
RP11 1 2 3 4
56_0804_8P4R_5%
8 7 6 5
DDR_DM2 DDR_DQ22 DDR_DQ19 DDR_DQ24
1 2 3 4
56_0804_8P4R_5%
2
*27 RP14 DDR_DQ25 DDR_DQS3 DDR_DQ30 DDR_DQ31
8 7 6 5
8 DDR_SCKE3
RP13 1 2 3 4
56_0804_8P4R_5%
8 7 6 5
DDR_SCKE3 1 R267 10_0402_5%
2
DDR_DQ28 DDR_DM3 DDR_DQ26 DDR_DQ27
1 2 3 4
8 7 DDR_SCKE3 6 DDR_SMA12 5
DDR_SMA7 DDR_SMA5 DDR_SMA3 DDR_SMA1
56_0804_8P4R_5%
1 2 3 4
8 DDR_SCS#2
DDR_CKE3 DDR_SMA12 DDR_SMA9
RP18 8,13 DDR_SCKE0 8,13 DDR_SCKE1
DDR_SCS#2 1 R291 10_0402_5%
8,13 DDR_SBS0 8,13 DDR_SWE# 2 8,13 DDR_SMA15
DDR_SMA10 DDR_SBS0 DDR_SWE# DDR_CS#2 DDR_SMA15 DDR_DQ33 DDR_DQ37
33_0804_8P4R_5%
DDR_DQS4 DDR_DQ39 RP23 DDR_SMA9 DDR_SMA7 DDR_SMA5 DDR_SMA3
3
8 7 6 5
8 7 6 5
RP27 8 7 6 5
1 2 3 4
DDR_SCKE2 DDR_SMA11 DDR_SMA8 DDR_SMA6
DDR_DQ41 DDR_DQS5 DDR_DQ43 DDR_DQ47
33_0804_8P4R_5%
33_0804_8P4R_5%
DDR_SMA1 DDR_SMA10 DDR_SBS0 DDR_SWE#
DDR_DQ35 DDR_DQ45
RP22 1 2 3 4
RP26 1 2 3 4
33_0804_8P4R_5%
8 7 6 5
1 2 3 4
DDR_SMA4 DDR_SMA2 DDR_SMA0 DDR_SBS1
33_0804_8P4R_5%
Layout note Place these resistor closely DIMM1, all trace length<=800mil
DDR_DQ49 DDR_DQ53 DDR_DQS6 DDR_DQ55 DDR_DQ51 DDR_DQ56 DDR_DQ63 DDR_DQS7
RP31 8,13 DDR_SCS#1 8,13 DDR_SCS#0
DDR_SCS#2 DDR_SMA15
8 7 6 5
33_0804_8P4R_5%
RP30 1 2 3 4
8 7 6 5
+2.5V
+2.5V
1 2 3 4
DDR_DQ62 DDR_DQ58
DDR_SRAS# DDR_SCAS# DDR_SCS#3
13,16,25 SMDATA 13,16,25 SMCLK +3VS
33_0804_8P4R_5%
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 CK0# VSS DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD CB0 CB1 VSS DQS8 CB2 VDD CB3 DU VSS CK2 CK2# VDD CKE1 DU/A13 A12 A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 WE# S0# DU VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDD_SPD VDD_ID KLINK_5763-3-111
4
1
JP23
DDR_DQ2 DDR_DQ13 1
E
+2.5V
+2.5V
+1.25VS RP5 1 2 3 4
D
VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD CB4 CB5 VSS DM8 CB6 VDD CB7 DU/RESET# VSS VSS VDD VDD CKE0 DU/BA2 A11 A8 VSS A6 A4 A2 A0 VDD BA1 RAS# CAS# S1# DU VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD CK1# CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
2 DDR_DQ0 DDR_DQ6
1
DDR_DM0 DDR_DQ5
DDR_SMA[0..12] R556 C690 0.1U_0402_10V6K 1K_0603_1% DDR_DQS[0..7] DDRB_VREF
2
DDR_DQ7 DDR_DQ12
1
DDR_DQ8 DDR_DM1
DDR_DQ[0..63] DDR_DM[0..7]
DDR_SMA[0..12] 8,13 DDR_DQS[0..7]
8,13
DDR_DQ[0..63]
8,13
DDR_DM[0..7] 8,13
R561 C692 0.1U_0402_10V6K 1K_0603_1%
1
2
RP6
C
2
B
1
A
DDR_DQ9 DDR_DQ11
L
DDRB_VREF trace width of 20mils and space 20mils(min)
DDR_DQ20 DDR_DQ16 DDR_DM2 DDR_DQ22
+1.25VS
DDR_DQ19 DDR_DQ24
RP34 DDR_DQ33 DDR_DQ37 DDR_DQS4 DDR_DQ39
DDR_DQ28 DDR_DM3 DDR_DQ26 DDR_DQ27
8 7 6 5
RP33 1 2 3 4
56_0804_8P4R_5%
8 7 6 5
56_0804_8P4R_5%
RP36 DDR_DQ35 DDR_DQ45 DDR_DQ41 DDR_DQS5
*27 DDR_CKE2 2 R226 10_0402_5% DDR_SMA11 DDR_SMA8
1
8 7 6 5
RP35 1 2 3 4
56_0804_8P4R_5% DDR_SCKE2
8 7 6 5
DDR_SBS1 DDR_SRAS# DDR_SCAS# DDR_CS#3 2 10_0402_5%
DDR_DQ43 DDR_DQ47 DDR_DQ49 DDR_DQ53 DDR_SBS1 8,13 DDR_SRAS# 8,13 DDR_SCAS# 8,13 DDR_SCS#3 1 R288 *27
8 7 6 5
56_0804_8P4R_5%
RP37 1 2 3 4
56_0804_8P4R_5%
8 7 6 5
56_0804_8P4R_5%
RP41 DDR_DQS6 DDR_DQ55 DDR_DQ51 DDR_DQ56
DDR_DQ34 DDR_DQ44
DDR_DQ42 DDR_DQ46 DDR_DQ48 DDR_DQ52
1 2 3 4
DDR_SCS#3 8
DDR_DQ32 DDR_DQ36 DDR_DM4 DDR_DQ38
2
DDR_DQ34 DDR_DQ44 DDR_DQ40 DDR_DM5
1 2 3 4
DDR_SCKE2 8
RP38 DDR_SMA6 DDR_SMA4 DDR_SMA2 DDR_SMA0
DDR_DQ32 DDR_DQ36 DDR_DM4 DDR_DQ38
1 2 3 4
8 7 6 5
RP40 1 2 3 4
56_0804_8P4R_5%
8 7 6 5
DDR_DM6 DDR_DQ54 DDR_DQ50 DDR_DQ61
1 2 3 4
56_0804_8P4R_5%
DDR_DQ40 DDR_DM5
3
DDR_DQ42 DDR_DQ46
RP43 DDR_CLK4# 8 DDR_CLK4 8
DDR_DQ48 DDR_DQ52
DDR_DQ63 DDR_DQS7 DDR_DQ62 DDR_DQ58
8 7 6 5
RP42 1 2 3 4
56_0804_8P4R_5%
8 7 6 5
DDR_DQ60 DDR_DM7 DDR_DQ57 DDR_DQ59
1 2 3 4
56_0804_8P4R_5%
DDR_DM6 DDR_DQ54 DDR_DQ50 DDR_DQ61 DDR_DQ60 DDR_DM7 DDR_DQ57 DDR_DQ59 +3VS
Layout note Place these resistor close by DIMM1, all trace length Max=0.8"
4
DDR TOPOLOGY 1 FOR SMAA[0, 3, 6:12], SBA[1, 0], SRAS#, SCAS#, SWE# Compal Electronics, Inc. Title
DDR-SODIMM SLOT1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A
B
C
D
Document Number
Rev 0.1
LA-2101 Sheet
Saturday, November 22, 2003 E
14
of
52
A
B
C
D
Layout note :
Layout note :
Distribute as close as possible to DDR-SODIMM0.
Distribute as close as possible to DDR-SODIMM1.
+2.5V
+2.5V
1 1 +
1
E
1 C798 220U_D2_4VM
2
1 C124 0.1U_0402_10V6K
2
1 C136 0.1U_0402_10V6K
2
1 C159 0.1U_0402_10V6K
2
1 C185 0.1U_0402_10V6K
2
1 C206 0.1U_0402_10V6K
2
1 C227 0.1U_0402_10V6K
2
1 C358 0.1U_0402_10V6K
2
+ C388 0.1U_0402_10V6K
1 C797 220U_D2_4VM
2
1 C207 0.1U_0402_10V6K
2
1 C242 0.1U_0402_10V6K
2
1 C267 0.1U_0402_10V6K
2
1 C463 0.1U_0402_10V6K
2
1 C812 0.1U_0402_10V6K
2
1 C704 0.1U_0402_10V6K
2
1 C711 0.1U_0402_10V6K
2
C722 0.1U_0402_10V6K 1
2
2
1
2
1 C424 0.1U_0402_10V6K
1
2
1 C128 0.1U_0402_10V6K
2
1 C135 0.1U_0402_10V6K
2
1 C158 0.1U_0402_10V6K
2
1 C196 0.1U_0402_10V6K
2
1 C233 0.1U_0402_10V6K
2
1 C357 0.1U_0402_10V6K
2
1 C398 0.1U_0402_10V6K
2
1 C427 0.1U_0402_10V6K
+
C686 220U_D2_4VM
2
2
1 C730 0.1U_0402_10V6K
2
1 C737 0.1U_0402_10V6K
2
1 C742 0.1U_0402_10V6K
2
1 C770 0.1U_0402_10V6K
2
1 C781 0.1U_0402_10V6K
2
1 C792 0.1U_0402_10V6K
2
1 C795 0.1U_0402_10V6K
2
C807 0.1U_0402_10V6K
Layout note :
1
+
2
1 C725 0.1U_0402_10V6K
C685 220U_D2_4VM
for EMI solution
2
+2.5V 1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
Layout note : Place one cap close to every 2 pull up resistors termination to +1.25VS
2
C92
2
1000P_0402_50V7K
1 C104 0.1U_0402_10V6K
2
1 C110 0.1U_0402_10V6K
2
1 C103 0.1U_0402_10V6K
2
1 C109 0.1U_0402_10V6K
2
1 C116 0.1U_0402_10V6K
C91
1
C90
1
C133
1
C268
1
C390
1
C450
1
C462
1
C461
1 2
+1.25VS
1
1
2
1 C127 0.1U_0402_10V6K
2
1 C115 0.1U_0402_10V6K
2
1 C126 0.1U_0402_10V6K
2
2
2 1000P_0402_50V7K
1 C144 0.1U_0402_10V6K
2
2
2 1000P_0402_50V7K
2
2
2
2
2
1000P_0402_50V7K
C149 0.1U_0402_10V6K
1000P_0402_50V7K
+1.25VS
1
2
1 C143 0.1U_0402_10V6K
2
1 C148 0.1U_0402_10V6K
2
1 C166 0.1U_0402_10V6K
2
1 C176 0.1U_0402_10V6K
2
1 C165 0.1U_0402_10V6K
2
1 C175 0.1U_0402_10V6K
2
1 C188 0.1U_0402_10V6K
2
1 C195 0.1U_0402_10V6K
2
1 C187 0.1U_0402_10V6K
2
C194 0.1U_0402_10V6K
+1.25VS
1
3
2
1 C243 0.1U_0402_10V6K
2
1 C251 0.1U_0402_10V6K
2
1 C284 0.1U_0402_10V6K
2
1 C292 0.1U_0402_10V6K
2
1 C283 0.1U_0402_10V6K
2
C291 0.1U_0402_10V6K 3
+1.25VS
1
2
1 C314 0.1U_0402_10V6K
2
1 C321 0.1U_0402_10V6K
2
1 C313 0.1U_0402_10V6K
2
1 C320 0.1U_0402_10V6K
2
1 C337 0.1U_0402_10V6K
2
1 C347 0.1U_0402_10V6K
2
1 C336 0.1U_0402_10V6K
2
1 C346 0.1U_0402_10V6K
2
1 C364 0.1U_0402_10V6K
2
C371 0.1U_0402_10V6K
+1.25VS
1
2
1 C363 0.1U_0402_10V6K
2
1 C370 0.1U_0402_10V6K
2
1 C387 0.1U_0402_10V6K
2
1 C401 0.1U_0402_10V6K
2
1 C386 0.1U_0402_10V6K
2
1 C400 0.1U_0402_10V6K
2
1 C420 0.1U_0402_10V6K
2
1 C431 0.1U_0402_10V6K
2
1 C419 0.1U_0402_10V6K
2
C430 0.1U_0402_10V6K
+1.25VS
4
1
2
1 C442 0.1U_0402_10V6K
2
1 C446 0.1U_0402_10V6K
2
1 C441 0.1U_0402_10V6K
2
1 C445 0.1U_0402_10V6K
2
4
1 C457 0.1U_0402_10V6K
2
C456 0.1U_0402_10V6K
Compal Electronics, Inc. Title
DDR SODIMM Decoupling THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A
B
C
D
Document Number
Rev 0.1
LA-2101 Sheet
Tuesday, November 18, 2003 E
15
of
52
A
B
C
D
E
F
G
H
+3V_CLK +3VS L14 1
0.1U_0402_10V6K
2
HB-1M2012-121JT03_0805 Width=40C310 mils
1
C290
2 10U_0805_10V4Z
1
1
2
0.1U_0402_10V6K 1
C274
C276
2 0.1U_0402_10V6K
1
C392
2
1
C773
2 0.1U_0402_10V6K
1
2 0.1U_0402_10V6K
1
C410
R363 @10_0402_5% 2
U18
10P_0402_50V8K XTALIN_CLK 2 1
1
1
Y1
6
VDDCPU VDDSD VDDAGP VDD48M VDDPCI VDDPCI VDDREF VDDXTAL
1
36 SYS_XCLK
42 48 30 29 19 13 1 9
+3VS_VDDA
XIN
VDDA
C275
+3VS
1 1
2
2
XTALOUT_CLK 2 14.31818MHZ_20P_6X1430004201 10P_0402_50V8K
7
VSSA XOUT CPUT0
35 34
13,14,25 SMCLK 13,14,25 SMDATA
R228
SCLK SDATA CPUC0
R343 10K_0402_5%
CPUT1
2
10K_0402_5% VTT_PWRGD
2
25,27 VTT_PWRGD R256 1
2 10K_0402_5% PCI33/66#
10 45 12 26 11
VTTPWRGD/PD# CPU_STP# PCI_STOP# 24/48#SEL PCI33/66#SEL CPUC1
R255 1
2
2@10K_0402_5%
29 SD_CLKIN
R254 1
2 33_0402_5%
10 REFCLK1_NB 36 CLK_14M_SIO 25 CLK_SB_14M
R658 1 R663 1 R664 1
2 20_0402_5% 2 33_0402_5% 2 33_0402_5%
1
1
C366
C277
L15 1 2 +3VS CHB2012U121_0805
0.1U_0402_10V6K 1
C391
1
1
2
2
C380
R321 @1M_0402_5%
1 C411
+3VS_VDDA
36
CLK_48M
FS2 FS1 FS0
27 28
4 3 2 38
AGPCLK0 AGPCLK1 FS3/PCICLK_F0 FS4/PCICLK_F1
FS2/REF2 FS1/REF1 FS0/REF0
PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5
IREF
2
CLK_IREF
SDRAMOUT 48MHz_1 48MHz_0
40
39
CLK_CPU_CLK
CLK_CPU_CLK# CLK_NB
44
R265 1
0.1U_0402_10V6K
2 33_0402_5% CLK_BCLK
CLK_BCLK 4
R235 1
2 49.9_0402_1%
R236 1
2 49.9_0402_1%
R266 1
2 33_0402_5% CLK_BCLK#
CLK_BCLK# 4
R263 1
2 33_0402_5%
CLK_NB_BCLK 10
R237 1
2 49.9_0402_1%
R238 1
2 49.9_0402_1%
43
CLK_NB#
R264 1
2 33_0402_5%
CLK_NB_BCLK# 10
47
MEM_66M
R262 1
2 33_0402_5%
CLK_MEM 10
32 31
R239 1 AGP_66M AGP_EXT_66M R240 1
2 33_0402_5% 2 33_0402_5%
CLK_AGP_66M 10 CLK_AGP_EXT_66M 17
14 15
FS3 FS4
2 33_0402_5%
CLK_ALINK_SB 24
R332 1
2
POP For 150G DEPOP For 150A
16 17 20 21 22 23
GNDXTAL GNDREF GNDPCI GNDPCI GND48M GNDAGP GNDSD GNDCPU
R253
0.1U_0402_10V6K 0.1U_0402_10V6K 2 2 2 10U_0805_10V4Z VSSA 37
8 5 18 24 25 33 46 41
1
475_0402_1%
ICS951402AGT_TSSOP48
CLOCK FREQUENCY SELECT TABLE MEM
A-LINK FREQ
With Spread Enabled…
+3V_CLK
0
0
0
100
100
R316
@10K_0402_5% @10K_0402_5% FS1 FS0 FS2 FS3 FS4 PCI33/66#
+3V_CLK
R362 10K_0402_5%
5,12 BSEL0
R317
R327
@10K_0402_5%
10K_0402_5%
R341
R314
R313
R329
R331
R333
R330
10K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
@10K_0402_5%
2
2
2
1 D47 1 D46
5,12 BSEL1
1
1
R342 10K_0402_5%
2
10K_0402_5%
2
R357
1
+3VS
1
1
+3VS
Note: 0 = PULL LOW 1 = PULL HIGH
R315
1
0
33MHZ
Spreaf OFF OR Center spread +/-0.3%
2
0
PCI33/66# = LOW
3
*
1
133
2
133
1
1
2
0
1
0
2
0
66MHZ 1
0
PCI33/66# = HIGH
2
200
1
200
2
0
1
1
2
0
1
0
2
**
0
1
CPU
** 3
2
FS4 FS3 FS2 FS1 FS0
2 CH751H-40_SC76 2 CH751H-40_SC76
4
4
Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
E
F
G
Clock Generator Document Number
Rev 0.1
LA-2101 Saturday, November 22, 2003
Sheet
16 H
of
52
4
3
2
AGP, DAC & LVDS INTERFACE
U3A
AGP8X_DET# HIGH: AGP2.0
AGP_ST0 AGP_ST1 AGP_ST2
AF29 AD27 AE28
AGP_DBI_HI AGP_DBI_LO
9 AGP_DBI_HI 9 AGP_DBI_LO
SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7
+3VS
AB25 AB26
2 R492
1 10K_0402_5%
AC25
2 R494
1 @10K_0402_5%
AE11 AF11
2 715_0402_1%
AK21
R510
DBI_HI DBI_LO AGP8X_DET# DMINUS DPLUS
1
1
2
1
23 CRMA 23 LUMA
R506
CRMA LUMA COMPS
R30 75_0402_1%
THRM
2
AG23 AG24 SSIN
AK25
SSOUT
AJ25
XTALIN
AH28
*27
R13
C_R Y_G COMP_B H2SYNC V2SYNC DDC3CLK DDC3DATA SSIN SSOUT
10K_0402_5% 1
AJ29
XTALIN XTALOUT
DDC2CLK DDC2DATA
25 AGP_SUS_STAT#
1
2 1K_0402_5%
AH27 AG26
R460
2
1 @10K_0402_5%
STRAP_F
R23
2
1 @10K_0402_5%
STRAP_G
R3 R18
2 2
1 10K_0402_5% 1 @10K_0402_5%
STRAP_H
R4 R19
2 2
1 10K_0402_5% 1 @10K_0402_5%
STRAP_J
R6 R21
2 2
1 @10K_0402_5% 1 @10K_0402_5%
STRAP_K
R5 R20
2 2
1 @10K_0402_5% 1 @10K_0402_5%
STRAP_O
R457
2
1 @10K_0402_5%
R43
2
1 @10K_0402_5%
R53
2
1 @10K_0402_5%
STRAP_N
R46
2
1 @10K_0402_5%
STRAP_R
R454 R461
2 2
1 @10K_0402_5% 1 10K_0402_5%
STRAP_S
R16 R17
2 2
1 @10K_0402_5% 1 10K_0402_5%
STRAP_T
R455 R462
2 2
1 @10K_0402_5% 1 @10K_0402_5%
DRAM128M
R468 R471
2 2
1 @10K_0402_5% 1 10K_0402_5%
1
GPIO5 GPIO6
POWER_SEL 49
GPIO0
2
(25 mil)
1K_0402_1%
AF5 R465 STRAP_R STRAP_S
GPIO1
1K_0402_1% 2
GPIO2 GPIO3
+3VS
GPIO9
R478
2
AH6 AJ6 AK6 AH7 AK7 AJ7 AH8 AJ8 AH9 AJ9 AK9 AH10 AE6 AG6 AF6 AE7 AF7 AE8 AG8 AF8 AE9 AF9 AG10 AF10
GPIO11 STRAP_L
R487
2.2K_0402_5%
2.2K_0402_5%
GPIO12 STRAP_M
GPIO13 EDID_DATA 23 EDID_CLK 23
STRAP_T
AJ10 AK10 AJ11 AH11 AE10
DVOMODE 1 R466
AK16 AH16 AH17 AJ16 AH18 AJ17 AK19 AH19 AK18 AJ18 AG16 AF16 AG17 AF17 AF18 AE18 AH20 AG20 AF19 AG19
TXOUT0TXOUT0+ TXOUT1TXOUT1+ TXOUT2TXOUT2+
AE12 AG12
ENVDD ENBKL
2 0_0402_5%
TXOUT0TXOUT0+ TXOUT1TXOUT1+ TXOUT2TXOUT2+
TXCLKTXCLK+ TZOUT0TZOUT0+ TZOUT1TZOUT1+ TZOUT2TZOUT2+
23 23 23 23 23 23
TXCLK- 23 TXCLK+ 23 TZOUT0- 23 TZOUT0+ 23 TZOUT1- 23 TZOUT1+ 23 TZOUT2- 23 TZOUT2+ 23
RSET DDC1DATA DDC1CLK AUXWIN TEST_MCLK/(NC)
TESTEN SUS_STAT#
PLLTEST/(NC) RSTB_MSK/(NC)
R 0
S 0
4Mx32 Samsung
0
1
4Mx32 Hynix
1
0
8Mx32 Samsung
1
1
8Mx32 Hynix
TZCLKTZCLK+
TZCLK- 23 TZCLK+ 23
R54 10K_0402_5%
ENVDD 9,23 ENBKL 9,39
AJ13 AH14 AJ14 AH15 AJ15 AK15 AH13 AK13
C
+3VS
* 3.3V OSC out for W180
X1 4 1 1
VDD OE
FREQOUT 1 R469
3
OUT
XTALIN
2 261_0402_1%
B
R467 150_0402_5%
27MHZ_15P C28 0.1U_0402_10V6K
2
Ra
2
GND
Rb
C530 @15P_0402_50V8J
AE13 AE14 AF12
R463
AK27 AJ27 AJ26 AG25 AH25
R G B DACA_HSYNC DACA_VSYNC
AH26
AGP_RSET
AF25 AF24
DDC_DATA DDC_CLK
AF26
1 R479
R92
36 VGA_XCLK
100K_0402_5%
For VGA DDR R G B HSYNC VSYNC
TEST_YCLK/(NC) R12
AGP_SUS_STAT# R470 1 2 0_0402_5%
STRAP_E
D
R458 POWER_SEL XTALIN_SS
1 TX0M TX0P TX1M TX1P TX2M TX2P TXCM TXCP
HPD1
*27
R14
10K_0402_5% 1
R2SET
2
2
1
100_0402_1%
AJ23 AJ22 AK22 AJ24 AK24
TXOUT_L0N TXOUT_L0P TXOUT_L1N TXOUT_L1P TXOUT_L2N TXOUT_L2P TXOUT_L3N TXOUT_L3P TXCLK_LN TXCLK_LP TXOUT_U0N TXOUT_U0P TXOUT_U1N TXOUT_U1P TXOUT_U2N TXOUT_U2P TXOUT_U3N TXOUT_U3P TXCLK_UN TXCLK_UP DIGON BLON/(BLON#)
R15 (15mil)
324_0402_1% +AGP_VREF
DVOMODE
ST0 ST1 ST2
2
+1.5VS
AD28 AD29 AC28 AC29 AA28 AA29 Y28 Y29
STP_AGP# AGP_BUSY# RBF# AD_STBF_0 AD_STBF_1 AD_STBS_0 AD_STBS_1
AGP_SB_STBF AB29 SB_STBF AGP_SB_STBS AB28 SB_STBS C603 1 2 0.1U_0402_10V6K M26 +AGP_VREF AGPREF M27 AGPTEST
9 AGP_SB_STBF 9 AGP_SB_STBS R508 47_0402_5% 1 2 (15mil)
+1.5VS
AGP_SBA0 AGP_SBA1 AGP_SBA2 AGP_SBA3 AGP_SBA4 AGP_SBA5 AGP_SBA6 AGP_SBA7
WBF#
1 @10K_0402_5%
1
STP_AGP# AH30 AGP_BUSY# AH29 AGP_RBF# AE29 AGP_AD_STBF0 M28 AGP_AD_STBF1 V25 AGP_AD_STBS0 M29 AGP_AD_STBS1 V26
9,25 AGP_STP# 9,25 AGP_BUSY# 9 AGP_RBF# 9 AGP_AD_STBF0 9 AGP_AD_STBF1 9 AGP_AD_STBS0 9 AGP_AD_STBS1
B
AC26
2
2
AGP_WBF#
9 AGP_WBF#
ZV_LCDCNTL0 ZV_LCDCNTL1 ZV_LCDCNTL2 ZV_LCDCNTL3
R459
spread sprum
R 23 G 23 B 23 DACA_HSYNC 23 DACA_VSYNC 23
1
U2
DDC_DATA 23 DDC_CLK 23 2 10K_0402_5%
+3VS
+3VS 2 R105 2 R106
E8
FREQOUT
1
1 7 10K_0402_5% 1 8 10K_0402_5%
X1/CLK
C58
2 2 0.1U_0402_10V6K
CLKOUT
FS1
X2
FS2
AE25 1 R41
+3VS
0.1U_0402_10V6K 1 1 C61
(15mil) 1 2 R472 499_0402_1%
B6
AG29
2 @10_0402_5% FREQOUT
1
L4
1 1
C55
2
2.2U_0603_6.3V4Z C65 FCM2012C-800_0805
2 2 0.1U_0402_10V6K
SS%
5
XTALIN_SS 2 22_0402_5%
1 R486
2 R484
EXT_SSIN 1 @10_0402_5%
EXT_SSIN 36
+3VS
2 4
SS%
2 R84
2
C
1 @10K_0402_5%
STRAP_D
GPIO4
+3VS
6
9 AGP_REQ# 9 AGP_GNT# 9 AGP_PAR 9 AGP_STOP# 9 AGP_DEVSEL# 9 AGP_TRDY# 9 AGP_IRDY# 9 AGP_FRAME# 9,24,29,32 PCI_PIRQA#
PCICLK RST# REQ# GNT# PAR STOP# DEVSEL# TRDY# IRDY# FRAME# INTA#
1 @10K_0402_5%
2
VDD
CLK_AGP_EXT_66M AG30 AG28 AGP_REQ# AF28 AGP_GNT# AD26 AGP_PAR M25 AGP_STOP# N26 AGP_DEVSEL# V29 AGP_TRDY# V28 AGP_IRDY# W29 AGP_FRAME# W28 PCI_PIRQA# AE26
2
2
R22
VGA_Disable
1 @10K_0402_5%
R91 W180-01GT_SO8
2 1K_0402_5%
10K_0402_5%
3
1 R488 10_0402_5%
SSC DAC2
16 CLK_AGP_EXT_66M 7,24 NB_RST#
C/BE#0 C/BE#1 C/BE#2 C/BE#3
ROMCS#
R476
STRAP_B
1
2
N29 U28 P26 U26
VREFG
STRAP_A
GPIO7
2
1
@10P_0402_50V8K @10_0402_5%
AGP_C/BE#0 AGP_C/BE#1 AGP_C/BE#2 AGP_C/BE#3
AG4
+3VS
ID_Disable GPIO8
2
R477
TMDS
C537 1 2
STRAP_G STRAP_H STRAP_J STRAP_K STRAP_D STRAP_E STRAP_F STRAP_B STRAP_A STRAP_O DRAM128M STRAP_L STRAP_M STRAP_N
1
Pull High for AGP 4X
VREFG/(NC)
AJ5 AH5 AJ4 AK4 AH4 AF4 AJ3 AK3 AH3 AJ2 AH2 AH1 AG3 AG1 AG2 AF3 AF2
1
@10K_0402_5% AGP_DBI_HI 1 AGP_DBI_LO 1 @10K_0402_5%
CLK
R496 2 2 R495
+1.5VS
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16
ZV_LCDDATA0 ZV_LCDDATA1 ZV_LCDDATA2 ZV_LCDDATA3 ZV_LCDDATA4 ZV_LCDDATA5 ZV_LCDDATA6 ZV_LCDDATA7 ZV_LCDDATA8 ZV_LCDDATA9 ZV_LCDDATA10 ZV_LCDDATA11 ZV_LCDDATA12 ZV_LCDDATA13 ZV_LCDDATA14 ZV_LCDDATA15 ZV_LCDDATA16 ZV_LCDDATA17 ZV_LCDDATA18 ZV_LCDDATA19 ZV_LCDDATA20 ZV_LCDDATA21 ZV_LCDDATA22 ZV_LCDDATA23
DAC1
9 AGP_ST[0..2]
M10-P/(M9+X) (1/6)
ZV PORT / EXT TMDS / GPIO / ROM
AGP_ST[0..2]
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
PCI/AGP
AGP_C/BE#[0..3]
9 AGP_C/BE#[0..3] D
H29 H28 J29 J28 K29 K28 L29 L28 N28 P29 P28 R29 R28 T29 T28 U29 N25 R26 P25 R27 R25 T25 T26 U25 V27 W26 W25 Y26 Y25 AA26 AA25 AA27
AGP8X
AGP_SBA[0..7]
9 AGP_SBA[0..7]
AGP_AD0 AGP_AD1 AGP_AD2 AGP_AD3 AGP_AD4 AGP_AD5 AGP_AD6 AGP_AD7 AGP_AD8 AGP_AD9 AGP_AD10 AGP_AD11 AGP_AD12 AGP_AD13 AGP_AD14 AGP_AD15 AGP_AD16 AGP_AD17 AGP_AD18 AGP_AD19 AGP_AD20 AGP_AD21 AGP_AD22 AGP_AD23 AGP_AD24 AGP_AD25 AGP_AD26 AGP_AD27 AGP_AD28 AGP_AD29 AGP_AD30 AGP_AD31
LVDS
AGP_AD[0..31]
9 AGP_AD[0..31]
1
GND
5
A
A
1
SA002160E00(0301021300)
Compal Electronics, Inc. Title
ATI M10-P & M9+X (AGP BUS) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Document Number
Rev 0.1
LA-2101 Saturday, November 22, 2003 1
Sheet
17
of
52
5
21 NMDA[0..63]
MEMORY INTERFACE A
21 NMAA[0..13] 21 NDQMA[0..7] 21 NDQSA[0..7]
3
2
NMDA[0..63]
22 NMDB[0..63]
NMAA[0..13]
22 NMAB[0..13]
NDQMA[0..7]
22 NDQMB[0..7]
NDQSA[0..7]
22 NDQSB[0..7]
U3B
C
B
L25 L26 K25 K26 J26 H25 H26 G26 G30 D29 D28 E28 E29 G29 G28 F28 G25 F26 E26 F25 E24 F23 E23 D22 B29 C29 C25 C27 B28 B25 C26 B26 F17 E17 D16 F16 E15 F14 E14 F13 C17 B18 B17 B15 C13 B14 C14 C16 A13 A12 C12 B12 C10 C9 B9 B10 E13 E12 E10 F12 F11 E9 F9 F8
DQA0 DQA1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQA8 DQA9 DQA10 DQA11 DQA12 DQA13 DQA14 DQA15 DQA16 DQA17 DQA18 DQA19 DQA20 DQA21 DQA22 DQA23 DQA24 DQA25 DQA26 DQA27 DQA28 DQA29 DQA30 DQA31 DQA32 DQA33 DQA34 DQA35 DQA36 DQA37 DQA38 DQA39 DQA40 DQA41 DQA42 DQA43 DQA44 DQA45 DQA46 DQA47 DQA48 DQA49 DQA50 DQA51 DQA52 DQA53 DQA54 DQA55 DQA56 DQA57 DQA58 DQA59 DQA60 DQA61 DQA62 DQA63
D
NMAB[0..13] NDQMB[0..7] NDQSB[0..7]
U3C
M10-P/(M9+X) AA0 (2/6) AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12/(AA13) AA13/(AA12) AA14/(NC)
MEMORY INTERFACE A
NMDA0 NMDA1 NMDA2 NMDA3 NMDA4 NMDA5 NMDA6 NMDA7 NMDA8 NMDA9 NMDA10 NMDA11 NMDA12 NMDA13 NMDA14 NMDA15 NMDA16 NMDA17 NMDA18 NMDA19 NMDA20 NMDA21 NMDA22 NMDA23 NMDA24 NMDA25 NMDA26 NMDA27 NMDA28 NMDA29 NMDA30 NMDA31 NMDA32 NMDA33 NMDA34 NMDA35 NMDA36 NMDA37 NMDA38 NMDA39 NMDA40 NMDA41 NMDA42 NMDA43 NMDA44 NMDA45 NMDA46 NMDA47 NMDA48 NMDA49 NMDA50 NMDA51 NMDA52 NMDA53 NMDA54 NMDA55 NMDA56 NMDA57 NMDA58 NMDA59 NMDA60 NMDA61 NMDA62 NMDA63
1
NMDB[0..63]
DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7 QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7
RASA# CASA# WEA# CSA0# CSA1# CKEA CLKA0 CLKA0# CLKA1 CLKA1# DIMA0 DIMA1 MVREFD MVREFS/(NC)
E22 B22 B23 B24 C23 C22 F22 F21 C21 A24 C24 A25 E21 B20 C19
NMAA0 NMAA1 NMAA2 NMAA3 NMAA4 NMAA5 NMAA6 NMAA7 NMAA8 NMAA9 NMAA10 NMAA11 NMAA12 NMAA13
J25 F29 E25 A27 F15 C15 C11 E11
NDQMA0 NDQMA1 NDQMA2 NDQMA3 NDQMA4 NDQMA5 NDQMA6 NDQMA7
J27 F30 F24 B27 E16 B16 B11 F10
NDQSA0 NDQSA1 NDQSA2 NDQSA3 NDQSA4 NDQSA5 NDQSA6 NDQSA7
A19
NMRASA#
E18
NMCASA#
E19
NMWEA#
E20
NMCSA0#
F20
NMCSA1#
B19
NMDB0 NMDB1 NMDB2 NMDB3 NMDB4 NMDB5 NMDB6 NMDB7 NMDB8 NMDB9 NMDB10 NMDB11 NMDB12 NMDB13 NMDB14 NMDB15 NMDB16 NMDB17 NMDB18 NMDB19 NMDB20 NMDB21 NMDB22 NMDB23 NMDB24 NMDB25 NMDB26 NMDB27 NMDB28 NMDB29 NMDB30 NMDB31 NMDB32 NMDB33 NMDB34 NMDB35 NMDB36 NMDB37 NMDB38 NMDB39 NMDB40 NMDB41 NMDB42 NMDB43 NMDB44 NMDB45 NMDB46 NMDB47 NMDB48 NMDB49 NMDB50 NMDB51 NMDB52 NMDB53 NMDB54 NMDB55 NMDB56 NMDB57 NMDB58 NMDB59 NMDB60 NMDB61 NMDB62 NMDB63
NMRASA# 21 NMCASA# 21 NMWEA# 21 NMCSA0# 21 NMCSA1# 21
NMCKEA
NMCKEA 21
B21 C20
NMCLKA0 NMCLKA0#
C18 A18
NMCLKA1 NMCLKA1#
NMCLKA0 21 NMCLKA0# 21 NMCLKA1 21 NMCLKA1# 21
D30 B13 B7
MVREFD
B8
MVREFS
D7 F7 E7 G6 G5 F5 E5 C4 B5 C5 A4 B4 C2 D3 D1 D2 G4 H6 H5 J6 K5 K4 L6 L5 G2 F3 H2 E2 F2 J3 F1 H3 U6 U5 U3 V6 W5 W4 Y6 Y5 U2 V2 V1 V3 W3 Y2 Y3 AA2 AA6 AA5 AB6 AB5 AD6 AD5 AE5 AE4 AB2 AB3 AC2 AC3 AD3 AE1 AE2 AE3
DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 DQB9 DQB10 DQB11 DQB12 DQB13 DQB14 DQB15 DQB16 DQB17 DQB18 DQB19 DQB20 DQB21 DQB22 DQB23 DQB24 DQB25 DQB26 DQB27 DQB28 DQB29 DQB30 DQB31 DQB32 DQB33 DQB34 DQB35 DQB36 DQB37 DQB38 DQB39 DQB40 DQB41 DQB42 DQB43 DQB44 DQB45 DQB46 DQB47 DQB48 DQB49 DQB50 DQB51 DQB52 DQB53 DQB54 DQB55 DQB56 DQB57 DQB58 DQB59 DQB60 DQB61 DQB62 DQB63
M10-P/(M9+X) (3/6)
AB0 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12/(AB13) AB13/(AB12) AB14/(NC)
MEMORY INTERFACE B
D
4
DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7 QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6 QSB7 RASB# CASB# WEB# CSB0# CSB1# CKEB CLKB0 CLKB0# CLKB1 CLKB1#
N5 M1 M3 L3 L2 M2 M5 P6 N3 K2 K3 J2 P5 P3 P2
NMAB0 NMAB1 NMAB2 NMAB3 NMAB4 NMAB5 NMAB6 NMAB7 NMAB8 NMAB9 NMAB10 NMAB11 NMAB12 NMAB13
E6 B2 J5 G3 W6 W2 AC6 AD2
NDQMB0 NDQMB1 NDQMB2 NDQMB3 NDQMB4 NDQMB5 NDQMB6 NDQMB7
F6 B3 K6 G1 V5 W1 AC5 AD1
NDQSB0 NDQSB1 NDQSB2 NDQSB3 NDQSB4 NDQSB5 NDQSB6 NDQSB7
R2
NMRASB#
T5
NMCASB#
T6
NMWEB#
R5
NMCSB0#
R6
NMCSB1#
R3
NMCKEB
N1 N2
NMCLKB0 NMCLKB0#
T2 T3
NMCLKB1 NMCLKB1#
C
NMRASB# 22 NMCASB# 22 NMWEB# 22 NMCSB0# 22 NMCSB1# 22 NMCKEB 22 NMCLKB0 22 NMCLKB0# 22 B
NMCLKB1 22 NMCLKB1# 22 +1.8VS
MEMVMODE0 MEMVMODE1 DIMB0 DIMB1 MEMTEST
C6 C7
R122 1 R540 1
2 4.7K_0402_5% 2 4.7K_0402_5%
R532 1
2 47_0402_1% (15mil)
E3 AA3 C8
SA002160E00(0301021300) SA002160E00(0301021300)
+2.5VS
1
1
+2.5VS
R544 R543 1K_0402_1% 1K_0402_1% (25 mil)
1 C668
1
C669
1
R539
R538 0.1U_0402_16V4Z
2
2
1K_0402_1%
2
1K_0402_1%
Compal Electronics, Inc.
2
0.1U_0402_10V6K
A
1
(25 mil)
MVREFD
2
MVREFS
2
A
Title
ATI M10-P/M9+X DDR-A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Document Number
Rev 0.1
LA-2101 Sheet
Saturday, November 22, 2003 1
18
of
52
5
4
3
2
POWER INTERFACE
POWER Sequence 3.3VS --> 2.5VS --> 1.8VS --> +VGA_Core --> +1.5VS
U3D
C
AC11 AC20 H11 H20 L23 P8 Y23 Y8
+1.5VS
B
+VDD_PNLPLL1.8
+VDD_DAC1.8 +VDD_DAC2.5 +VDD_DAC1.8
AK12 AJ12
AH24 AG21 AH21 AF22
AH22 AJ21 AF23
VDDC15/(VDDC18) VDDC15/(VDDC18) VDDC15/(VDDC18) VDDC15/(VDDC18) VDDC15/(VDDC18) VDDC15/(VDDC18) VDDC15/(VDDC18) VDDC15/(VDDC18)
VSSRH0 VSSRH1
F19 M6
PVDD PVSS
VDDR3 VDDR3 VDDR3 VDDR3 VDDR3 VDDR3 VDDR3 VDDR3
VDDR4 VDDR4 VDDR4 VDDR4 VDDR4
LVDDR_25/(LVDDR_18_25) LVDDR_25/(LVDDR_18_25) LVDDR_18 LVDDR_18 LPVDD
TPVDD TPVSS
AVDD A2VDD A2VDD A2VDDQ
A2VSSN A2VSSN A2VSSQ
AVSSN AVSSQ
A7 A6
+VDD_MEMPLL1.8 C644
AK28 AJ28
+VDD_PLL1.8
AC19 AC21 AC22 AC8 AD19 AD21 AD22 AD7
+3VS
22U_1206_10V4Z
1
2
LVSSR LVSSR LVSSR LVSSR LPVSS
C598
2 0.1U_0402_10V6K
1
2
C519 2.2U_0603_6.3V4Z
2 0.1U_0402_10V6K
VSS1DI VSS2DI
2
C630
1
C607
1
1
2
2
1
C587
2 2 2 0.01U_0402_16V7Z 0.1U_0402_10V6K
1
2
C579
0.01U_0402_16V7Z0.1U_0402_10V6K 1
C571
1
C573
1
C545
2 2 2 0.1U_0402_10V6K 0.1U_0402_10V6K
1
2
0.1U_0402_10V6K
C553
1
C558
1
2 2 0.1U_0402_10V6K
0.1U_0402_10V6K
1
C586
2
+1.5VS
L36 1 2 CHB1608U301_0603
(20 mil)
+2.5VS
1
2
+2.5VS
C592
C626
0.1U_0402_10V6K 4.7U_0805_10V4Z
C
+VDD_PLL1.8 L26
C521 10U_0805_10V4Z
1
C527
2
L23
1 2 CHB1608U301_0603 1
1
2
2
(20 mil)
+1.8VS
C531
C513
0.1U_0402_10V6K
10U_0805_10V4Z
1 2 CHB1608U301_0603
1
1
2
2
+1.8VS
C523 0.1U_0402_10V6K
0.1U_0402_10V6K +VDD_DAC1.8
+VDD_MEMPLL1.8 L27 1 2 CHB1608U301_0603
(20 mil) C522 10U_0805_10V4Z
1
1
2
2
L7 1 2 CHB1608U301_0603
(20 mil)
+1.8VS
C529
C85
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
2
2
+1.8VS
2.2U_0603_6.3V4Z C88
+VDD_PNLIO1.8 (20 mil)
+VDD_PNLIO2.5
+VDD_PNLIO1.8 +VDD_PNLPLL1.8
C520 10U_0805_10V4Z
1
L25 1 2 CHB1608U301
0.1U_0402_10V6K C546
2
1
C543
2
1
2
0.1U_0402_10V6K
C544
B
2 0.1U_0402_10V6K
+VDD_PNLIO2.5
+VDD_DAC1.8 C561 10U_0805_10V4Z
AE23 AE21
1
2
+1.8VS
1
+3VS 0.1U_0402_10V6K C548
1
2
C547
1
L34 1 2 CHB1608U301 L59 1 2 @CHB1608U301
0.1U_0402_10V6K
+2.5VS +3VS
C559 22U_1206_10V4Z
2
0.1U_0402_10V6K
TXVSSR TXVSSR TXVSSR
0.1U_0402_10V6K
C619
C528
(20 mil)
AF20 AF15 AE19 AE16 AJ19
AF13 AF14
1
+2.5VDDRH
(20 mil) VDD1DI VDD2DI
C632
1
+VDD_PNLPLL1.8
AA23 AA24 AB30 AC23 AC27 AE30 AF27 J30 M23 M24 N30 P23 P27 T23 T24 T30 U27 V23 V24 W30 Y27
AE24 AE22
0.01U_0402_16V7Z 0.1U_0402_10V6K
1 C635
L24 1 2 CHB1608U301_0603
(20 mil)
AC10 AC9 AD10 AD9 AG7
AE20 AE17 AF21 AE15 AJ20
C569
1
+VDD_DAC2.5
+1.5VS VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP
D
+1.5VS 0.1U_0402_10V6K
MPVDD MPVSS
TXVDDR TXVDDR AH23 AD24
The differ between +2.5VS and +1.8VS should not be greater than 1.2V
F18 N6
1
VDDRH0 VDDRH1
2
VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1/(CLKAFB) VDDR1/(CLKBFB)
+2.5VDDRH
1U_0603_10V4Z
+2.5VS
M10-P/(M9+X) (4/6)
I/O POWER
D
B1 B30 A15 A21 A28 A3 A9 AA1 AA4 AA7 AA8 AD4 D5 D8 D11 D13 D14 D17 D20 D23 D26 E27 F4 G7 G10 G13 G15 G19 G22 G27 H10 H13 H15 H17 H19 H22 J1 J23 J24 J4 J7 J8 L27 L8 M4 N4 N7 N8 R1 T4 T7 T8 V4 V7 V8 D19 R4
1
1
C554
2
1
C552
2
1
C557
2
0.1U_0402_10V6K
0.01U_0402_16V7Z 1
C556
2
1
2
0.01U_0402_16V7Z
+VDD_PNLIO1.8
AG13 AG14 AH12
SA002160E00(0301021300) A
A
Compal Electronics, Inc. Title
ATI M10-P/M9+X POWER-A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Document Number
Rev 0.1
LA-2101 Sheet
Tuesday, November 18, 2003 1
19
of
52
5
4
3
2
1
U3E
C
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
+VGA_CORE
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
H4 H8 H9 H12 H14 H18 H21 H23 H27 K1 K23 K24 K27 K30 K7 K8 L4 M30 M7 M8 N23 N24 N27 P4 R23 R24 R30 R7 R8 T1 T27 U23 U4 U8 V30 W23 W24 W27 W7 W8 Y4 G9 G12 G16 G18 G21 G24
M12 M13 M14 M17 M18 M19 N12 N13 N14 N17 N18 N19 P12 P13 P14 P17 P18 P19 U12 U13 U14 U17 U18 U19 V12 V13 V14 V17 V18 V19 W12 W13 W14 W17 W18 W19
POWER INTERFACE
AB22 AB9 J10 J12 J14 J15 J16 J17 J19 J21 K22 K9 M22 M9 P22 P9 R22 R9 T22 T9 U22 U9 V22 V9 Y22 Y9
SA002160E00(0301021300)
B
+VGA_CORE 22U_1206_10V4Z
0.1U_0402_10V6K
0.1U_0402_10V6K
0.01U_0402_16V7Z
1 C2
22U_1206_10V4Z 2
2
1 C616
1 C600
2
2
0.1U_0402_10V6K
1 C608
1 C599
2
2
C572
1
C582
2
0.1U_0402_10V6K
1
C555
2
0.01U_0402_16V7Z
VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC
M10-P/(M9+X) (6/6) VDDC M10-P&M9+X VDDC VDDC COMMON VDDC VDDC VDDCI VDDCI VDDCI VDDCI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
M10-P ONLY
VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
M9+X ONLY
D
AD15 AD13 AC17 AC15 AC13 T12 M15 W16 R19
+VGA_CORE_CI
R12 R13 T13 R14 T14 N15 P15 R15 T15 U15 V15 W15 H16 M16 N16 P16 R16 T16 U16 V16 R17 T17 R18 T18 T19
C
AA22 AA9 J11 J13 J18 J20 J22 J9 L22 L9 N22 N9 W22 W9
B
0.01U_0402_16V7Z SA002160E00(0301021300)
1 1 C524
+VGA_CORE
U3F
CORE POWER
D
CORE POWER
M10-P/(M9+X) (5/6) A10 A16 A2 A22 A29 AA30 AB1 AB23 AB24 AB27 AB4 AB7 AB8 AC12 AC14 AC16 AC18 AC4 AD12 AD16 AD18 AD25 AD30 AE27 AG11 AG15 AG18 AG22 AG27 AG5 AG9 AJ1 AJ30 AK2 AK29 C1 C28 C3 C30 D10 D12 D15 D18 D21 D24 D25 D27 D4 D6 D9 E4 F27
1
C570
2
1
+ C560
2
2
0.01U_0402_16V7Z
100U_D2_10M_R45 +VGA_CORE_CI
+2.5VS 0.1U_0402_10V6K 1 C671 22U_1206_10V4Z 2
0.1U_0402_10V6K
0.1U_0402_10V6K
1 C647
1 C634
1 C620
1 C589
1 C565
2
2
2
2
2
0.1U_0402_10V6K
0.01U_0402_16V7Z C633
1
C639
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1 C629
1 C666
1 C594
2
2
2
2
0.01U_0402_16V7Z
0.1U_0402_10V6K
C610
1
2
L38 1 2 CHB1608U301
(20 mil)
0.01U_0402_16V7Z C623 10U_0805_10V4Z
1
1
2
2
480MIL
+VGA_CORE
1 C593 C578 0.1U_0402_10V6K 0.1U_0402_10V6K 2
0.1U_0402_10V6K
As close as ppossible to related pin +2.5VS A
0.1U_0402_10V6K
22U_1206_10V4Z
0.1U_0402_10V6K
0.1U_0402_10V6K
1 C46
1 C636
1 C577
1 C637
1 C660
1 C662
2
2
2
2
2
2
0.1U_0402_10V6K
0.01U_0402_16V7Z C656
1
2
0.1U_0402_10V6K
0.01U_0402_16V7Z
C661
0.1U_0402_10V6K 1 C631
1 C568
1 C645
2
2
2
2
0.1U_0402_10V6K
A
0.01U_0402_16V7Z
1
C640
1
2
Compal Electronics, Inc.
0.1U_0402_10V6K Title
As close as ppossible to related pin
ATI M10-P/M9+X POWER-B THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Document Number
Rev 0.1
LA-2101 Sheet
Tuesday, November 18, 2003 1
20
of
52
5
4
3
2
1
VGA DDR FOR CHANNEL A +2.5VS
+2.5VS 22U_1206_10V4Z
1 C721 22U_1206_10V4Z
0.1U_0402_10V6K
1 C689
2
1 C697
2
0.1U_0402_10V6K
1 C696
2
1 C705
2
1 C712
2
2
0.1U_0402_10V6K 1 C714 2
22U_1206_10V4Z
1 C715
1 C710
2
22U_1206_10V4Z
2
1 C152
1 C683
2
2
0.1U_0402_10V6K 1 C118
1 C117
2
2
0.1U_0402_10V6K 1 C129
1 C134
2
2
0.1U_0402_10V6K 1 C138
1 C139
2
2
1 C131 2
D
D
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
As close as ppossible to related pin
As close as ppossible to related pin
2
1K_0402_1%
B2 H13 H2 B13
VREF_1
N13 M13 L9 M10
1
(25mil)
NDQSA2 NDQSA1 NDQSA0 NDQSA3
1
2
C687 0.1U_0402_10V6K
18 18 18 18
NMRASA# NMCASA# NMWEA# NMCSA0#
18 NMCKEA 18 NMCLKA0
NMRASA# NMCASA# NMWEA# NMCSA0#
M2 L2 L3 N2
NMCKEA
N12
NMCLKA0
M11 M12
B
R562 56.2_0402_1% C701
1
10P_0402_50V8K 2
18 NMCLKA0#
NMCSA1#
E7 E8 E10 K6 K7 K8 K9 L5 L10 E5
VREF MCL RFU1 RFU2 RAS# CAS# WE# CS#
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
CKE CK CK# NC NC NC NC NC NC NC NC NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VDD VDD VDD VDD VDD VDD VDD VDD
F6 F7 F8 F9 G6 G7 G8 G9 H6 H7 H8 H9 J6 J7 J8 J9
18 NMCSA1#
NMCLKA0#
R560 56.2_0402_1%
C4 C11 H4 H11 L12 L13 M3 M4 N3
DQS0 DQS1 DQS2 DQS3
+2.5VS 1
NMDA23 NMDA22 NMDA21 NMDA20 NMDA19 NMDA18 NMDA17 NMDA16 NMDA15 NMDA14 NMDA13 NMDA12 NMDA11 NMDA10 NMDA9 NMDA8 NMDA7 NMDA6 NMDA5 NMDA4 NMDA3 NMDA2 NMDA1 NMDA0 NMDA31 NMDA30 NMDA29 NMDA28 NMDA27 NMDA26 NMDA25 NMDA24
NMAA0 NMAA1 NMAA2 NMAA3 NMAA4 NMAA5 NMAA6 NMAA7 NMAA8 NMAA9 NMAA10 NMAA11 NMAA12 NMAA13
N5 N6 M6 N7 N8 M9 N9 N10 N11 M8 L6 M7 N4 M5
NDQMA6 NDQMA5 NDQMA4 NDQMA7
B3 H12 H3 B12
NDQSA6 NDQSA5 NDQSA4 NDQSA7
B2 H13 H2 B13
VREF_2
N13 M13 L9 M10
NMRASA# NMCASA# NMWEA# NMCSA0#
M2 L2 L3 N2
NMCKEA
N12
R136 1K_0402_1%
(25mil)
R138 1K_0402_1% +2.5VS
1
2
C107 0.1U_0402_10V6K
C3 C5 C7 C8 C10 C12 E3 E12 F4 F11 G4 G11 J4 J11 K4 K11
18 NMCLKA1
NMCLKA1
M11 M12
R140 56.2_0402_1%
C106 10P_0402_50V8K
1
2
D7 D8 E4 E11 L4 L7 L8 L11
18 NMCLKA1#
NMCLKA1#
NMCSA1#
R139 56.2_0402_1%
C4 C11 H4 H11 L12 L13 M3 M4 N3 E7 E8 E10 K6 K7 K8 K9 L5 L10 E5
A0 A1 A2 A3 A4 A5 A6 A7 A8/AP A9 A10 A11 BA0 BA1
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DM0 DM1 DM2 DM3 DQS0 DQS1 DQS2 DQS3 VREF MCL RFU1 RFU2 RAS# CAS# WE# CS#
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
CKE CK CK# NC NC NC NC NC NC NC NC NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VDD VDD VDD VDD VDD VDD VDD VDD
F6 F7 F8 F9 G6 G7 G8 G9 H6 H7 H8 H9 J6 J7 J8 J9
R554
DM0 DM1 DM2 DM3
B7 C6 B6 B5 C2 D3 D2 E2 K13 K12 J13 J12 G13 G12 F13 F12 F3 F2 G3 G2 J3 J2 K2 K3 E13 D13 D12 C13 B10 B9 C9 B8
2
B3 H12 H3 B12
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
1
NDQMA2 NDQMA1 NDQMA0 NDQMA3
A0 A1 A2 A3 A4 A5 A6 A7 A8/AP A9 A10 A11 BA0 BA1
2
1
+2.5VS
N5 N6 M6 N7 N8 M9 N9 N10 N11 M8 L6 M7 N4 M5
VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH
C
NMAA0 NMAA1 NMAA2 NMAA3 NMAA4 NMAA5 NMAA6 NMAA7 NMAA8 NMAA9 NMAA10 NMAA11 NMAA12 NMAA13
B4 B11 D4 D5 D6 D9 D10 D11 E6 E9 F5 F10 G5 G10 H5 H10 J5 J10 K5 K10
U42
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
U8
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
18 NDQSA[0..7]
K4D263238A-GC_FBGA144
NMDA55 NMDA54 NMDA53 NMDA52 NMDA51 NMDA50 NMDA49 NMDA48 NMDA47 NMDA46 NMDA45 NMDA44 NMDA43 NMDA42 NMDA41 NMDA40 NMDA39 NMDA38 NMDA37 NMDA36 NMDA35 NMDA34 NMDA33 NMDA32 NMDA63 NMDA62 NMDA61 NMDA60 NMDA59 NMDA58 NMDA57 NMDA56
B7 C6 B6 B5 C2 D3 D2 E2 K13 K12 J13 J12 G13 G12 F13 F12 F3 F2 G3 G2 J3 J2 K2 K3 E13 D13 D12 C13 B10 B9 C9 B8
C
+2.5VS
C3 C5 C7 C8 C10 C12 E3 E12 F4 F11 G4 G11 J4 J11 K4 K11
B
D7 D8 E4 E11 L4 L7 L8 L11
VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH
NDQSA[0..7]
B4 B11 D4 D5 D6 D9 D10 D11 E6 E9 F5 F10 G5 G10 H5 H10 J5 J10 K5 K10
NDQMA[0..7]
18 NDQMA[0..7]
2
0.1U_0402_10V6K
NMDA[0..63]
18 NMDA[0..63]
1K_0402_1%
0.1U_0402_10V6K
NMAA[0..13]
18 NMAA[0..13]
R555
0.1U_0402_10V6K
K4D263238A-GC_FBGA144
A
A
Compal Electronics, Inc. Title
VGA DDR FOR CHANNEL A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Document Number
Rev 0.1
LA-2101 Sheet
Saturday, November 22, 2003 1
21
of
52
5
4
3
+2.5VS
2
1 C70
2
C73
2
D
1
C67
2
1
1 C658
2
0.1U_0402_10V6K
0.1U_0402_10V6K 1 C63
2
0.01U_0402_16V7Z
1 C60
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K C72
1 22U_1206_10V4Z
2
1 C49
1 C32
2
2
0.01U_0402_16V7Z
0.01U_0402_16V7Z 1 C33 2
0.1U_0402_10V6K 1 C36
1 C40
2
2
1
C39
2
0.1U_0402_10V6K
D
0.01U_0402_16V7Z
As close as ppossible to related pin
NDQSB0 NDQSB3 NDQSB2 NDQSB1
B2 H13 H2 B13
VREF_3
N13 M13 L9 M10
DM0 DM1 DM2 DM3
R118
1
1K_0402_1%
2
(25mil) 1 C74 0.1U_0402_10V6K
1
18 18 18 18
NMRASB# NMCASB# NMWEB# NMCSB0#
18 NMCKEB
NMRASB# NMCASB# NMWEB# NMCSB0# NMCKEB
NMCLKB0
DQS0 DQS1 DQS2 DQS3 VREF MCL RFU1 RFU2
M2 L2 L3 N2
RAS# CAS# WE# CS#
N12
CKE
M11 M12
B
R113
R1141 10P_0402_50V8K
C4 C11 H4 H11 L12 L13 M3 M4 N3
NC NC NC NC NC NC NC NC NC
E7 E8 E10 K6 K7 K8 K9 L5 L10 E5
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VDD VDD VDD VDD VDD VDD VDD VDD
F6 F7 F8 F9 G6 G7 G8 G9 H6 H7 H8 H9 J6 J7 J8 J9
NMCSB1#
C81 56.2_0402_1%
2 NMCLKB0#
56.2_0402_1%
CK CK#
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
B7 C6 B6 B5 C2 D3 D2 E2 K13 K12 J13 J12 G13 G12 F13 F12 F3 F2 G3 G2 J3 J2 K2 K3 E13 D13 D12 C13 B10 B9 C9 B8
NMDB0 NMDB2 NMDB1 NMDB7 NMDB6 NMDB5 NMDB3 NMDB4 NMDB27 NMDB30 NMDB28 NMDB25 NMDB31 NMDB29 NMDB24 NMDB26 NMDB18 NMDB16 NMDB19 NMDB17 NMDB20 NMDB21 NMDB22 NMDB23 NMDB8 NMDB10 NMDB9 NMDB11 NMDB12 NMDB13 NMDB15 NMDB14
+2.5VS
R83 1K_0402_1%
(25mil)
NMAB0 NMAB1 NMAB2 NMAB3 NMAB4 NMAB5 NMAB6 NMAB7 NMAB8 NMAB9 NMAB10 NMAB11 NMAB12 NMAB13
N5 N6 M6 N7 N8 M9 N9 N10 N11 M8 L6 M7 N4 M5
NDQMB5 NDQMB6 NDQMB7 NDQMB4
B3 H12 H3 B12
NDQSB5 NDQSB6 NDQSB7 NDQSB4
B2 H13 H2 B13
VREF_4
N13 M13 L9 M10
1
R90 1K_0402_1% +2.5VS
C3 C5 C7 C8 C10 C12 E3 E12 F4 F11 G4 G11 J4 J11 K4 K11
C44 0.1U_0402_10V6K
2
NMRASB# NMCASB# NMWEB# NMCSB0# NMCKEB
18 NMCLKB1
NMCLKB1
R96 1 10P_0402_50V8K
C4 C11 H4 H11 L12 L13 M3 M4 N3
56.2_0402_1%
C48 56.2_0402_1%
2 18 NMCLKB1#
N12 M11 M12
R97
D7 D8 E4 E11 L4 L7 L8 L11
M2 L2 L3 N2
E7 E8 E10 K6 K7 K8 K9 L5 L10 E5
NMCLKB1#
NMCSB1#
A0 A1 A2 A3 A4 A5 A6 A7 A8/AP A9 A10 A11 BA0 BA1
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DM0 DM1 DM2 DM3 DQS0 DQS1 DQS2 DQS3 VREF MCL RFU1 RFU2 RAS# CAS# WE# CS#
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
CKE CK CK# NC NC NC NC NC NC NC NC NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VDD VDD VDD VDD VDD VDD VDD VDD
F6 F7 F8 F9 G6 G7 G8 G9 H6 H7 H8 H9 J6 J7 J8 J9
B3 H12 H3 B12
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
2
NDQMB0 NDQMB3 NDQMB2 NDQMB1
A0 A1 A2 A3 A4 A5 A6 A7 A8/AP A9 A10 A11 BA0 BA1
1
N5 N6 M6 N7 N8 M9 N9 N10 N11 M8 L6 M7 N4 M5
2
2
+2.5VS
NMAB0 NMAB1 NMAB2 NMAB3 NMAB4 NMAB5 NMAB6 NMAB7 NMAB8 NMAB9 NMAB10 NMAB11 NMAB12 NMAB13
1
C
U35
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
NDQSB[0..7]
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
U39
18 NMCSB1#
2
B4 B11 D4 D5 D6 D9 D10 D11 E6 E9 F5 F10 G5 G10 H5 H10 J5 J10 K5 K10
NDQMB[0..7]
18 NDQSB[0..7]
18 NMCLKB0#
2 0.01U_0402_16V7Z
VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH
18 NMDB[0..63]
18 NMCLKB0
1 C27
NMDB[0..63]
18 NDQMB[0..7]
2
22U_1206_10V4Z 1
NMAB[0..13]
18 NMAB[0..13]
1K_0402_1%
C38
2
0.1U_0402_10V6K
As close as ppossible to related pin
R117
C34
1
B4 B11 D4 D5 D6 D9 D10 D11 E6 E9 F5 F10 G5 G10 H5 H10 J5 J10 K5 K10
1 C66
22U_1206_10V4Z
K4D263238A-GC_FBGA144
B7 C6 B6 B5 C2 D3 D2 E2 K13 K12 J13 J12 G13 G12 F13 F12 F3 F2 G3 G2 J3 J2 K2 K3 E13 D13 D12 C13 B10 B9 C9 B8
NMDB41 NMDB43 NMDB40 NMDB42 NMDB44 NMDB46 NMDB45 NMDB47 NMDB54 NMDB55 NMDB53 NMDB52 NMDB50 NMDB51 NMDB49 NMDB48 NMDB58 NMDB57 NMDB56 NMDB59 NMDB60 NMDB61 NMDB63 NMDB62 NMDB35 NMDB33 NMDB32 NMDB34 NMDB37 NMDB38 NMDB36 NMDB39
C
+2.5VS
C3 C5 C7 C8 C10 C12 E3 E12 F4 F11 G4 G11 J4 J11 K4 K11
B
D7 D8 E4 E11 L4 L7 L8 L11
VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH VSS TH
1 C78
0.01U_0402_16V7Z
1
VGA DDR FOR CHANNEL B
+2.5VS 0.1U_0402_10V6K
22U_1206_10V4Z
2
K4D263238A-GC_FBGA144
A
A
Compal Electronics, Inc. Title
VGA DDR FOR CHANNEL B THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Document Number
Rev 0.1
LA-2101 Sheet
Saturday, November 22, 2003 1
22
of
52
A
B
POP For 150A DEPOP For 150G
1 R121
2 0_0805_5%
2 22P_0402_50V8J
3
+3VS
D50
1
2 0_0402_5%
1 L1
1
2 0_0402_5%
1
R28
17 TXOUT017 TXOUT0+ 17 TXOUT2+ 17 TXOUT217 TXOUT1+ 17 TXOUT117 TXCLK+ 17 TXCLK-
0.1U_0402_16V4Z
JP15
2 CHB1608B121_0603
1 2 3 4
LUMA_1
75_0603_1%
C7
C6
C515
1. 2. 3. 4.
1 2 3 4
Y C Y C
ground ground (luminance+sync) (crominance)
+LCDVDD 17 17 17 17 17 17 17 17
SUYIN_030008FR004T100ZL C516
270P_0402_50V7K 2
330P_0402_50V7K 2
2
330P_0402_50V7K
270P_0402_50V7K
2
2
75_0603_1%
CRMA_1
1 2 C514 22P_0402_50V8J
1
POP For 150G R24 DEPOP For 150A
1
R25
L2
2
1
1
R29
@DAN217_SOT23
2 CHB1608B121_0603
1
17 CRMA
1
17 LUMA
EDID_CLK EDID_DATA
17 EDID_CLK 17 EDID_DATA
2
C517 1
2
2
C93
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
+LCDVDD
TZCLKTZCLK+ TZOUT0TZOUT0+ TZOUT2TZOUT2+ TZOUT1TZOUT1+
JP1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
1 R507
C621
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
+LCDVDD
2 @0_0805_5% 1
R26
@4.7U_0805_10V4Z 2
+NB_EDID
JP2 D51 @DAN217_SOT23
R10 1
C596 1 +3VS
NB_EDID_CLK NB_EDID_DAT
9 NB_EDID_CLK 9 NB_EDID_DAT
@0.1U_0402_16V4Z 2
2 @0_0402_5%
Width: 40mils
+VGA_EDID
1
1
+3VS
1
R11 1
10 TV_CRMA 75_0603_1% 2
2 @0_0402_5%
E
LVDS Conn.
3
75_0603_1% 2 1
1 R27
D
TV-OUT Conn.
1
10 TV_LUMA
C
10 TXB2+_NB 10 TXB2-_NB 10 TXBCLK-_NB 10 TXBCLK+_NB 10 TXB0-_NB 10 TXB0+_NB 10 TXB1+_NB 10 TXB1-_NB +LCDVDD 10 TXA2-_NB 10 TXA2+_NB 10 TXACLK+_NB 10 TXACLK-_NB 10 TXA0+_NB 10 TXA0-_NB 10 TXA1-_NB 10 TXA1+_NB
ACES_87213-2200
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
1
@ACES_87213-2200
POP For 150G DEPOP For 150A
POP For 150A DEPOP For 150G
EDID_CLK
C87 1
EDID_DATA
C82 1
47P_0402_50V8J 2 NB_EDID_CLK
C605 @47P_0402_50V8J 1 2
NB_EDID_DAT
C612 @47P_0402_50V8J 1 2
47P_0402_50V8J 2
JP3 1 2 3 4 5 6 7
2
39 DAC_BRIG L40 CHB2012U170_0805 IB+ 1 2 1 2 L41 CHB2012U170_0805
B+
1 R172
39 INVT_PWM
DISPOFF#
2 0_0402_5%
1 2 3 4 5 6 7
2
+3VS
+12VALW
3
1
1
2 2
22K
1000P_0402_50V7K 200K_0402_5%
C581 0.1U_0402_16V4Z
2
Q41 DTC124EK_SOT23 ENVDD 2
9,17 ENVDD
R1045, R1047, R1049, R1060, R1061 POP For 150A DEPOP For 150G
3 1 2
CRT Conn. JP14 SUYIN_7849S-15G2T-HC
1
2 0_0402_5%
1
2 @0_0402_5%
R52
1
R456 1K_0402_5%
+CRT_VCC
0.1U_0402_16V4Z 2
C3
2
1 A
C4
C512 C508
2
2
DDC_CLK_1
2
2
2
10 CRT_HSYNC
10 CRT_VSYNC
R71
1 R72
2 @0_0402_5%
POP For 150G DEPOP For 150A
1
1
1 1
3
1
2 0_0402_5%
DDC_DATA 17
1
2 0_0402_5%
DDC_CLK 17
1
2 @0_0402_5%
3VDDCDA 10
1
2 @0_0402_5%
3VDDCCL 10
R56
Q1 2N7002_SOT23
1
R50
4.7K_0402_5% 4.7K_0402_5%
2 G
220P_0402_50V7K 1
R48
100K_0402_5%
1
3 R55
220P_0402_50V7K
@68P_0402_50V8K
4
2
@68P_0402_50V8K
2
R49
S
DACA_VSYNC_2 1
2
DACA_HSYNC_2
CHB1608B121_0603 2
+3VS
220P_0402_50V7K
R66
4 DACA_VSYNC_1 Y U32 SN74AHCT1G125GW_SOT353-5 R65
3
17 DACA_VSYNC
CHB1608B121_0603 2
L28 1
R34 4.7K_0402_5%
Q38 2N7002_SOT23 DDC_DATA_1
L3 1
5 1
1 C526
P OE#
4
3
Y
G
A
C505
R464 4.7K_0402_5%
+3VS
D
18P_0402_50V8K
5 1 2
U1 SN74AHCT1G125GW_SOT353-5
P OE#
2 0_0402_5%
G
1 R51
1
2
DACA_HSYNC_1
17 DACA_HSYNC
C509
15P_0402_50V8J 15P_0402_50V8J 15P_0402_50V8J 2
2
2 75_0603_1% 75_0603_1% +CRT_VCC 1 2 C19 0.1U_0402_16V4Z
4
C510
18P_0402_50V8K
2
2
2
2
18P_0402_50V8K 75_0603_1%
CRT_VCC C511
+3VS
2 G
C535
+CRT_VCC
S
C534
+CRT_VCC
D
1
C533
CRT_B 1
R33 R474 R473 1
1
1
R475
CRT_G
2
2 0_0402_5%
1
1
R32 17 B
CRT_R
1 2 FCM2012C-800_0805 L30 1 2 FCM2012C-800_0805 L29 1 2 FCM2012C-800_0805
2
2 0_0402_5%
1
2 0_0402_5%
1
1
1 R31
17 G
1
17 R
6 11 1 7 12 2 8 13 3 9 14 4 10 15 5
2
L31
1
2
3
2
3
2
0.1U_0402_16V4Z
2
CH491D_SOT23 FUSE_1A C506
2 @0_0402_5% 2
1 R37
R40 1
Q40 DTC124EK_SOT23
+CRT_VCC
1
D5 2
+R_CRT_VCC F1 1 1
1
+5VS
+3VS
10 NB_CRT_B 75_0603_1% 2
D4 DAN217_SOT23
1
2 @0_0402_5%
R36
R39 1
D3 DAN217_SOT23
1
1
75_0603_1% 2
POP For 150A DEPOP For 150G
R1051, R1052, R1053, R1056, R1058 POP For 150G DEPOP For 150A
Compal Electronics, Inc. Title
CRT,TV-OUT & LVDS Connector THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
4.7U_0805_10V4Z
22K
3
D2 DAN217_SOT23
10 NB_CRT_G
2
2 @0_0402_5%
R35
R38 1
3
75_0603_1% 2
2 0_0402_5%
22K
R497 10K_0402_5%
1
1
10 NB_CRT_R 3
1 R498
C550
2
2 220P_0402_50V7K
2
1
S
1 2 R514 47K_0402_5%
22K
3
1
@TC7SH08FU_SSOP5
3
1
SI2302DS-T1_SOT23 +LCDVDD
2 G Q2 2N7002_SOT23
100K_0402_5%
10U_1210_35V4Z
C145
S C52
D
2
1
1
R104
4.7U_0805_10V4Z
1
4 ENVDD
3
CH751H-40_SC76
R509 10K_0402_5%
220_0402_5%
1
24,28,29,31,32,36,39 PCIRST#
R558 C682
C31
Q3
2 G
2
U34
D
12
DISPOFF#
1
2
1
R88
1
100K_0402_5%
1 @0.1U_0402_16V4Z
2
D28 1
39 BKOFF#
2 C566
5
R171 10K_0402_5%
R103
+5V
1
2
Use for B+ discharge
2
+LCDVDD
+3VS B+
1
+3VS
1
2
ACES_85204-0700
B
C
D
Document Number
Rev 0.1
LA-2101 Saturday, November 22, 2003 E
Sheet
23
of
52
5
4
3
2
1
+3VS
Layout note:
A_AD[0..31]
9,12 A_AD[0..31]
PCI_SERR# PCI_PERR# PCI_TRDY# PCI_IRDY#
Trace length of PCI_CLK_R + PCI_CLK_FB should be less than 200 mils.
A_CBE#[0..3]
9 A_CBE#[0..3]
RP58 4 3 2 1
5 6 7 8
U47A
22
H_CPUFERR#
1 R244
2
@10_0402_5% 1
2
C259 @15P_0402_50V8J
+3VS 1 8.2K_0402_5% A_SERR#
R323
10K_0402_5%
4.7K_0402_5%
9 A_STROBE# 9 A_DEVSEL# 9 A_ACAT# 9 A_END# 9,12 A_PAR 9 A_OFF#
2
R304
2
PM_STPCPU#
1
1
+3VS
PCI_STP# C
9 A_SBREQ# 9 A_SBGNT#
+CPU_CORE
5,50 PM_STPCPU#
1 R688 20M_0603_5%
200_0402_5% 200_0402_5% 200_0402_5% 200_0402_5% 200_0402_5% 200_0402_5% 200_0402_5% 200_0402_5%
9,17,29,32 29 31 28,31
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#
C20 P20 B23 P21
A_INTA# INTB# INTC# INTD#
+3VS RTCX1
AC12
RTCX2
AC11
X1
2
2
CPURSTIN#
5 H_PWRGOOD 5 H_INTR 5 H_NMI 5 H_INIT# 5 H_SMI# 5 H_SLP# 5 H_IGNNE# 5 H_A20M#
R689 2
1 C814
X2
4.7K_0402_5% 1 20M_0603_5%
12P_0402_50V8K
4
1 IN
OUT
Y3
NC
NC
2 2 2 2 2 2 2 2
PCIRST# AD0/ROMA18 AD1/ROMA17 AD2/ROMA16 AD3/ROMA15 AD4/ROMA14 AD5/ROMA13 AD6/ROMA12 AD7/ROMA11 AD8/ROMA9 AD9/ROMA8 AD10/ROMA7 AD11/ROMA6 AD12/ROMA5 AD13/ROMA4 AD14/ROMA3 AD15/ROMA2 AD16/ROMD0 AD17/ROMD1 AD18/ROMD2 AD19/ROMD3 AD20/ROMD4 AD21/ROMD5 AD22/ROMD6 AD23/ROMD7 AD24/RTC_AD7 AD25/RTC_AD6 AD26/RTC_AD5 AD27/RTC_AD4 AD28/RTC_AD3 AD29/RTC_AD2 AD30/RTC_AD1 AD31/RTC_AD0 CBE#0/ROMA10 CBE#1/ROMA1 CBE#2/ROMWE# CBE#3/RTC_RD# FRAME# DEVSEL#/ROMA0 IRDY# TRDY#/ROMOE# PAR STOP# PERR# SERR# REQ#0 REQ#1 REQ#2 REQ#3/PDMAREQ0# REQ#4/PLLBP33/PDMAREQ1# GNT#0 GNT#1 GNT#2 GNT#3/PDMAGNT0# GNT#4/PLLBP50/PDMAGNT1# CLKRUN#
CPU_STP#/DPSLP# PCI_STP#
R225
RTCX1
2
1 C813
1 1 1 1 1 1 1 1
N20 R23
2
3
12P_0402_50V8K
RTCX2
R617 R618 R200 R202 R616 R203 R615 R201
1
H_INIT# H_A20M# H_SLP# H_INTR H_NMI H_SMI# H_STPCLK# H_IGNNE#
PM_STPCPU# PCI_STP#
2
H_A20M# H_CPUFERR#
5 H_STPCLK# R275 R250 R258 R231
1
50 PM_DPRSLPVR 32.768KHZ_12.5P_1TJS125DJ2A073
2 2 2 2
GPIO0
0_0402_5% 10K_0402_5%SB_APIC_D0 10K_0402_5%SB_APIC_D1 1K_0402_1%
GPIO1/ROMCS#
CPURSTIN# CPU_PWRGD INTR/LINT0 NMI/LINT1 INIT SMI# SLP# IGNNE# A20M# FERR# STPCLK# SSMUXSEL/GPIO0 DPRSLPVR APIC_D0 APIC_D1 APIC_CLK
LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ#0 LDRQ#1 SERIRQ
2
RTC
100K_0402_5% R259 B
1 1 1 1
B18 E4 B17 B16 C17 C16 F19 D17 D18 E19 E16 E17 E18 C19 C18 B19
PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 PCICLK7 PCICLK_FB
LPC
+3VS
A_AD0 A_AD1 A_AD2 A_AD3 A_AD4 A_AD5 A_AD6 A_AD7 A_AD8 A_AD9 A_AD10 A_AD11 A_AD12 A_AD13 A_AD14 A_AD15 A_AD16 A_AD17 A_AD18 A_AD19 A_AD20 A_AD21 A_AD22 A_AD23 A_AD24 A_AD25 A_AD26 A_AD27 A_AD28 A_AD29 A_AD30 A_AD31 A_CBE#0 A_CBE#1 A_CBE#2 A_CBE#3 A_STROBE# A_DEVSEL# A_ACAT# A_END# A_PAR A_OFF# A_SERR# A_SBREQ# A_SBGNT#
XTAL
R310 2
H22 P23 L23 N23 N22 M23 M22 K22 M21 M20 L21 K21 L20 N21 K23 K20 F23 G21 F20 H21 F22 F21 G20 E21 E20 D23 D22 E22 D20 C23 D21 C22 L22 J23 G22 E23 H20 J21 G23 H23 J20 J22 P22 B21 B20
CPU
3
5 H_FERR#
CLK_ALINK_SB
2
1
MMBT3904_SOT23 1
A_AD0 A_AD1 A_AD2 A_AD3 A_AD4 A_AD5 A_AD6 A_AD7 A_AD8 A_AD9 A_AD10 A_AD11 A_AD12 A_AD13 A_AD14 A_AD15 A_AD16 A_AD17 A_AD18 A_AD19 A_AD20 A_AD21 A_AD22 A_AD23 A_AD24 A_AD25 A_AD26 A_AD27 A_AD28 A_AD29 A_AD30 A_AD31 A_CBE#0 A_CBE#1 A_CBE#2 A_CBE#3 A_STROBE# A_DEVSEL# A_ACAT# A_END# A_PAR A_OFF# A_SERR# A_SBREQ# A_SBGNT#
Part 1 of 3
PCICLKF A_RST#
PCI CLKS
R210 330_0402_5%
470_0402_5%
Q15
SB200 SB
NBRST#
PCI INTERFACE
2 8.2K_0402_5%
PULL DOWN FOR S3
1
2
R3111
B22 R22
A-LINK INTERFACE
+3VS R197
R199 56_0402_1% D
CLK_ALINK_SB
16 CLK_ALINK_SB
+CPU_CORE 1
+CPU_CORE
USBOC5#/GPM1 RTC_ALE/USBOC4#/GPIO3 RTC_WR#/RTC_CLKOUT RTC_CS#/USBOC3#/GPIO2 VBAT RTC_GND
R623 R622 R620 R621 R624 R625
33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5%
B15 D16 A14 A15 A16 A17 D15 A18 A19
PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1
C15 B1 C1 A1 D2 B2 C2 A2 D3 C3 A3 D4 B4 C4 A4 D5 B5 C8 D8 B8 A8 C9 D9 B9 A9 C10 B10 D11 A10 C11 B11 D12 A11 B3 C5 A7 D10 B7 A6 C7 D7 A5 B6 C6 D6 B12 C12 D13 A12 C13 A13 B13 C14 D14 B14 A20
SB_PCI_RST# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_C/BE#0 PCI_C/BE#1 PCI_C/BE#2 PCI_C/BE#3 PCI_FRAME# PCI_DEVSEL# PCI_IRDY# PCI_TRDY# PCI_PAR PCI_STOP# PCI_PERR# PCI_SERR# PCI_REQ#0 PCI_REQ#1 PCI_REQ#2 PCI_REQ#3 PCI_REQ#4 PCI_GNT#0 PCI_GNT#1 PCI_GNT#2 PCI_GNT#3 PCI_GNT#4 PM_CLKRUN#
AB5
GPIO1
Y14 AA14 AB14 AA13 AB13 AC14 Y13
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# LPC_DRQ0# LPC_DRQ1#
LPC_AD0 36,39 LPC_AD1 36,39 LPC_AD2 36,39 LPC_AD3 36,39 LPC_FRAME# 36,39
AC13
SIRQ
SERIRQ 29,36,39
AA2 AB7 AB8 AC8 AC10 AB11
OVCUR#5 OVCUR#4
1 1 1 1 1 1
2 2 2 2 2 2
PCI_CLK_R R222 1 PCI_CLK_FB
2 33_0402_5% C2361 PCI_AD[0..31]
8.2K _8P4R_0804_5%
CLK_PCI_MINI 31 CLK_PCI_CB 29 CLK_PCI_LPC 39 CLK_PCI_1394 32 CLK_PCI_LAN 28 CLK_PCI_SIO 36
RP57 PCI_FRAME# PCI_DEVSEL# PCI_STOP# PCI_PAR
4 3 2 1
5 6 7 8
8.2K _8P4R_0804_5%
2 22P_0402_50V8J
PCI_PIRQA#
PCI_AD[0..31] 27,28,29,31,32
PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_REQ#0 PCI_REQ#3 PCI_GNT#0 PCI_GNT#1
1 R249 2 8.2K_0402_5% 1 R325 2 8.2K_0402_5% 1 R221 2 8.2K_0402_5% 1 R324 2 8.2K_0402_5% RP17 4 5 3 6 2 7 1 8
D
8.2K _8P4R_0804_5% RP16 PCI_GNT#2 PCI_GNT#3 PCI_REQ#2 PCI_REQ#1
4 3 2 1
5 6 7 8
8.2K _8P4R_0804_5%
PCI_C/BE#[0..3]
PCI_REQ#4
R246 1 2 8.2K_0402_5%
PCI_GNT#4
R234 1 2 8.2K_0402_5%
PCI_C/BE#[0..3] 28,29,31,32
RP47 LPC_AD0 LPC_AD1 LPC_AD3 LPC_AD2
PCI_FRAME# 28,29,31,32 PCI_DEVSEL# 28,29,31,32 PCI_IRDY# 28,29,31,32 PCI_TRDY# 28,29,31,32 PCI_PAR 28,29,31,32 PCI_STOP# 28,29,31,32 PCI_PERR# 28,29,31,32 PCI_SERR# 28,29,31,32 PCI_REQ#0 32 PCI_REQ#1 31 PCI_REQ#2 29 PCI_REQ#3 28
4 3 2 1
5 6 7 8
C
15K_0804_8P4R_5% RP48 SIRQ LPC_DRQ0# LPC_FRAME# LPC_DRQ1#
8 10K_0804_8P4R_5% 7 6 5
1 2 3 4
PM_CLKRUN# R213 2
PCI_GNT#0 32 PCI_GNT#1 31 PCI_GNT#2 29 PCI_GNT#3 28
1 4.7K_0402_5%
R276 GPIO0
10K_0402_5% 2
1
PM_CLKRUN# 28,29,31,32,36,39
R374
1 10K_0402_5% +3V
2
+3V
OVCUR#5
R367 1
2 10K_0402_5%
OVCUR#3
R377 2
1 10K_0402_5%
LPC_DRQ1# 36
USB_OC4# 37
OVCUR#3 +SB_VBAT
B
South bridge SB200 +3VALW
RTC Battery
+
BATT1
+RTCBATT
C469
O
2
3
I
U24B O
R417
PCIRST#
PCIRST# 23,28,29,31,32,36,39
1 4
NB_RST#
2
NB_RST# 7,17
H_A20M#
2 C13
3
7
7
2 C11
H_INIT# TC7SH08FU_SSOP5
H_INTR
2 C10
10K_0402_5%
R431 1
220_0402_5% 2
R247
1
@0_0402_5%
Place Caps Close to CPU Socket
SB_PCI_RST# 35
C484 0.1U_0402_16V4Z
2
JOPEN1
2
1 @220P_0402_50V7K 1 @220P_0402_50V7K 1 @220P_0402_50V7K 1 @220P_0402_50V7K
NBRST# CHGRTC
2
W=20mils
2 C12
SN74LVC14APWLE_TSSOP14
2
3 220_0402_5% 2
1
1U_0603_10V4Z
4
H_NMI
C488 1
0.1U_0402_16V4Z
U15
SN74LVC14APWLE_TSSOP14
BAS40-04_SOT23 +RTCVCC
+SB_VBAT
5
U24A
G
I
1K_0402_5% 2
14
14 1
G
SB_PCI_RST#
1
RTCBATT
D49
R432 1
C285
R268
P
Place J1 close to DDR-SODIMM
0.1U_0402_16V4Z
1 +RTCBATT
2
P
-
1
+3VALW
No short
A
A
Title
Compal Electronics, Inc. SB200M(1/4)- PCI/CPU/LPC
Size
Document Number
Rev 0.1
LA-2101 Date: 5
4
3
2
Saturday, November 22, 2003 1
Sheet
24
of
52
5
4
3
2
1
U47B
L4 L3 M4 M3
USB20P4-
1
37 USBP4-
USB20P3+
R272
K2 K1 L2 L1
USB20P3-
2
@10_0402_5% 1
C278 @15P_0402_50V8J
2
USB20P2+
37 USBP2+
H2 H1 J2 J1
USB20P2-
37 USBP2-
USB20P1+
G3 J3 H3 K3
USB20P1-
1
CLK_SB_14M R224
USB20P0+
37 USBP0+
@10_0402_5%
F1 F2 G1 G2
USB20P0-
2
37 USBP0-
1
C235
R5 W1 V4 V2
@15P_0402_50V8J
2
T1 USB20P2+
1 R285 2 15K_0402_5% 1 R287 2 15K_0402_5% 1 R300 2 15K_0402_5% 1 R293 2 15K_0402_5%
C
T3 U2 T5 W4
USB20P2USB20P4USB20P4+
T2 U1 T4
USB20P3+ 8 USB20P37 6 5 15K_0804_8P4R_5% USB20P1+ 1 R282 2 15K_0402_5% USB20P11 R284 2 15K_0402_5% USB20P0+ 1 R281 2 15K_0402_5% USB20P01 R283 2 15K_0402_5%
27 MII_TXEN
W2 W3 U5 Y7
+3V
R358 2
1 10K_0402_5%
R319 2 27 SB_EEDO 27 SB_EECLK
1 10K_0402_5%
39 EC_RSMRST# 2 100K_0402_5%
R375 1
+3V
MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0
27 27 27 27
RP32 1 2 3 4
USB20P5+ USB20P5-
U4 V1 U3 V3
16 CLK_SB_14M
P2 R3 R2 R4
EC_RSMRST#
AB9
CLK_SB_14M
A23 W6
10K_0402_5%
+3V
R373 1
OVCUR#1
2
B
R370 2 40 EC_FLASH# 37 USB_OC2# 27 SUSCLK
R365 2
34 SPKR
1 10K_0402_5%
1 10K_0402_5% FLASH# OVCUR#2
AB2 AA3 W11 AB1 Y4 AA1
OVCUR#1 SPKR
USB_HSDP4+ USB_FLDP4+ USB_HSDM4USB_FLDM4USB_HSDP3+ USB_FLDP3+ USB_HSDM3USB_FLDM3USB_HSDP2+ USB_FLDP2+ USB_HSDM2USB_FLDM2USB_HSDP1+ USB_FLDP1+ USB_HSDM1USB_FLDM1-
AGP_STP#
2
1 CH751H-40_SC76
AGP_STP#_R AGP_BUSY#_R GHI#
AC1 AC6 AC2 AC3 AC4 AC5
GPOC0#/SCL0 GPOC1#/SDA0 GPOC2#/SCL1 GPOC3#/SDA1 RTC_IRQ#/PWR_STRP PIDE_IORDY PIDE_IRQ PIDE_A0 PIDE_A1 PIDE_A2 PIDE_DACK# PIDE_DRQ PIDE_IOR# PIDE_IOW# PIDE_CS1# PIDE_CS3#
MCOL MCRS MDCK MDIO RX_CLK RXD3 RXD2 RXD1 RXD0 RX_DV RX_ERR TX_CLK TXD3 TXD2 TXD1 TXD0
EE_CS EE_DI EE_DO EE_CK RSMRST# OSC_IN SIO_CLK
PIDE_D0 PIDE_D1 PIDE_D2 PIDE_D3 PIDE_D4 PIDE_D5 PIDE_D6 PIDE_D7 PIDE_D8 PIDE_D9 PIDE_D10 PIDE_D11 PIDE_D12 PIDE_D13 PIDE_D14 PIDE_D15 SIDE_IORDY SIDE_IRQ SIDE_A0 SIDE_A1 SIDE_A2 SIDE_DACK# SIDE_DRQ SIDE_IOR# SIDE_IOW# SIDE_CS1# SIDE_CS3#
TX_EN PHY_PD PHY_RST# CLK_25M
BLINK/GPM0 FANOUT1/USBOC2#/GPM2 32KHZ_IN/GPM3 USBOC1#/GPM4 SPEAKER/GPM5 FANOUT0/GPM6 GPIO_X0/AGP_STP# GPIO_X1/AGP_BUSY# GPIO_X2/GHI# GPIO_X3/VGATE GPIO_X4 GPIO_X5
2
35 PIDERST# 35 SIDERST#
GA20_IN/GEVNT0# KB_RST#/GEVNT1# SMB_ALERT#/GEVNT2# LPC_PME#/GEVNT3# LPC_SMI#/GEVNT4# GEVENT5#/ETH_VALERT# GEVENT6#/ETH_FALERT# GEVENT7#/ETH_CALERT#
USB_HSDP0+ USB_FLDP0+ USB_HSDM0USB_FLDM0-
D48 9,17 AGP_STP#
ACPI / WAKE UP EVENTS
USB20P4+
37 USBP4+ IAC_BITCLK
USB_HSDP5+ USB_FLDP5+ USB_HSDM5USB_FLDM5-
USB INTERFACE
M2 M1 N2 N1
USB20P5-
PME#/EXT_EVNT0# RI#/EXT_EVNT1# SLP_S3# SLP_S5# PWR_BTN# PWR_GOOD PCI_REQACT# SUS_STAT# TEST1 TEST0
PRIMARY ATA 66/100
D
ETHERNET MII
USB20P5+
TALERT#/ETH_TALERT#
Part 2 of 3
EEPROM
OVCUR#0
37 USB_OC0#
SB200 SB USBCLK/CLK48 USB_RCOMP USB_VREFOUT USB_ATEST1 USB_ATEST0 USBOC0#/GPM7
CLK / RST
2
P3 R1 P1 N4 N3 P4
GPIO_XTRA GPIO SECONDARY ATA 66/100 AC97
R322 1 12.4K_0603_1%
OSCLIN USB_RCOMP
R376
SIDE_D0 SIDE_D1 SIDE_D2 SIDE_D3 SIDE_D4 SIDE_D5 SIDE_D6 SIDE_D7 SIDE_D8 SIDE_D9 SIDE_D10 SIDE_D11 SIDE_D12 SIDE_D13 SIDE_D14 SIDE_D15 AC_BITCLK AC_SDOUT AC_SDIN0 AC_SDIN1 AC_SDIN2 AC_SYNC AC_RST# SPDIF_OUT
AB4
SB_EC_THERM#
AC9 AC7 AA11 AB10 AA10 Y11 C21 Y10 AA5 AA6
SB_PM_BATLOW# RI# PM_SLP_S3# PM_SLP_S5# PBTN_OUT# SB_PWRGD PCI_ACT_REQ# SUS_STAT# SB_TEST1 SB_TEST0
Y5 AA4 AB3 Y6 W5 Y8 AA7 AB6
SB_GA20 SB_KBRST# SB_AC_IN SB_EC_SWI# LPC_SMI# SB_EC_SMI# SB_SCI# SB_LID_OUT#
AA12 W12 Y12 AB12 AA8
SMB_CK_CLK2 SMB_CK_DAT2 SMB_CK_CLK2_SB SMB_CK_DAT2_SB PWR_STRP
AB17 AC16 AB15 AB16 AC15 Y16 AA17 AA16 AC17 Y15 AA15
IDE_PDIORDY INT_IRQ14 IDE_PDA0 IDE_PDA1 IDE_PDA2 IDE_PDDACK# IDE_PDDREQ IDE_PDIOR# IDE_PDIOW# IDE_PDCS1# IDE_PDCS3#
AC18 AA18 AC19 AA19 AC20 AA20 AC21 AB21 AA21 Y20 AB20 Y19 AB19 Y18 AB18 Y17
IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15
AA23 AA22 AC23 Y21 AB23 Y22 W21 Y23 W20 AC22 AB22
IDE_SDIORDY INT_IRQ15 IDE_SDA0 IDE_SDA1 IDE_SDA2 IDE_SDDACK# IDE_SDDREQ IDE_SDIOR# IDE_SDIOW# IDE_SDCS1# IDE_SDCS3#
W23 V21 V23 U21 U23 T21 T23 R21 R20 T22 T20 U22 U20 V22 V20 W22
IDE_SDD0 IDE_SDD1 IDE_SDD2 IDE_SDD3 IDE_SDD4 IDE_SDD5 IDE_SDD6 IDE_SDD7 IDE_SDD8 IDE_SDD9 IDE_SDD10 IDE_SDD11 IDE_SDD12 IDE_SDD13 IDE_SDD14 IDE_SDD15
E1 E2 Y1 Y2 Y3 E3 V5 E5
IAC_BITCLK
PM_SLP_S3# 39 PM_SLP_S5# 39 PBTN_OUT# 39 SB_PWRGD 27
SB_EC_THERM# D43
2
1CH751H-40_SC76
EC_THRM#
EC_THRM# 39
SB_EC_SWI#
D44
2
1CH751H-40_SC76
EC_SWI#
EC_SWI# 39
SB_GA20
D41
2
1CH751H-40_SC76
GATEA20
GATEA20 39
SB_KBRST#
D40
2
1CH751H-40_SC76
KBRST#
KBRST# 39
SB_AC_IN
D39
2
1CH751H-40_SC76
ACIN
ACIN 39,40,44
SB_EC_SMI#
D42
2
1CH751H-40_SC76
EC_SMI#
EC_SMI# 39
SB_SCI#
D37
2
1CH751H-40_SC76
EC_SCI#
EC_SCI# 39
SB_LID_OUT#
D33
2
1CH751H-40_SC76
EC_LID_OUT#
EC_LID_OUT# 39
D
SMCLK 13,14,16 SMDATA 13,14,16 PWR_STRP 27 IDE_PDIORDY 35 INT_IRQ14 35 IDE_PDA0 35 IDE_PDA1 35 IDE_PDA2 35 IDE_PDDACK# 35 IDE_PDDREQ 35 IDE_PDIOR# 35 IDE_PDIOW# 35 IDE_PDCS1# 35 IDE_PDCS3# 35
+3VALW 8 7 6 5 10K_0804_8P4R_5%
PM_SLP_S3# PBTN_OUT# PM_SLP_S5#
1 2 3 4 RP49
SB_PM_BATLOW# SB_EC_SMI# SB_SCI# SB_EC_SWI#
1 2 3 4 RP61
8 7 6 5 10K_0804_8P4R_5%
1 2 3 4 RP60 1 R379 1 R372 1 R230 4 3 2 1 RP50
8 7 6 5 10K_0804_8P4R_5%
+3V
IDE_PDD[0..15] 35 SB_LID_OUT# AGP_BUSY#_R SB_KBRST# SB_EC_THERM#
*
RI# SB_AC_IN PCI_ACT_REQ# SB_GA20 LPC_SMI# GHI# AGP_STP#_R
IDE_SDIORDY 35 INT_IRQ15 35 IDE_SDA0 35 IDE_SDA1 35 IDE_SDA2 35 IDE_SDDACK# 35 IDE_SDDREQ 35 IDE_SDIOR# 35 IDE_SDIOW# 35 IDE_SDCS1# 35 IDE_SDCS3# 35
SMB_CK_DAT2 SMB_CK_CLK2_SB SMB_CK_CLK2 SMB_CK_DAT2_SB
1 2 3 4 RP39
8 7 6 5 2.2K_0804_8P4R_5% +3V
IAC_RST#
2 8.2K_0402_5%
1 R347
+3VS
IDE_SDD[0..15] 35 AGP_STP# 8.2K_0402_5% 1 AGP_BUSY# 8.2K_0402_5% 1
SB_TEST1 SB_TEST0 ICH_AC_BITCLK IAC_SDATAI2 IAC_SDATAI1 IAC_SDATAI0 ICH_AC_BITCLK IAC_SDATAO IAC_SDATAI0 IAC_SDATAI1 IAC_SDATAI2 IAC_SYNC 2 22_0402_5% IAC_RST# SPDIF_OUT
1 R277 2 22_0402_5%
1 R270
C
2 2 10K_0402_5% 2 10K_0402_5% 10K_0402_5% 5 6 7 8 10K_0804_8P4R_5% +3VS
2R385 2R206
8.2K_0402_5% 1 8.2K_0402_5% 1 8.2K_0402_5% 1 8.2K_0402_5% 1 8.2K_0402_5% 1 8.2K_0402_5% 1
2R387 2R386 2R245 2R382 2R388 2R383
B
ICH_AC_BITCLK 33,38 ICH_AC_SDOUT 27,33,38 ICH_AC_SDIN0 33 ICH_AC_SDIN1 38 ICH_AC_SYNC 27,33,38 ICH_AC_RST# 33,38 SPDIF_OUT 27
33_0402_5% 1
South bridge SB200 +3V
VTT_PWRGD 16,27
2
2
2
2 R207 1
4.7K_0402_5% R186
4.7K_0402_5% R185
10K_0402_5% R175
SUS_STAT#
2 1K_0402_5%
Q14
MMBT3904_SOT23 1
3
Q13 AGP_SUS_STAT# 17
*27
R183 4.7K_0402_5%
4.7K_0402_5% R184 1
AGP_BUSY# 9,17
21
AGP_BUSY#
2
3
+3VS
C439 48MHZ_4P_FN4800002 0.1U_0402_10V6K
2N7002_SOT23
1
21
2
AGP_BUSY#_R
S
GND
*
OSCLIN
D
OE
1 2 R337 0_0402_5%
1
1
3
+2.5V
SUS_STAT#
3
MMBT3904_SOT23 1
NB_SUS_STAT# 7 2
2
OUT
+2.5V
G
2 1
VDD
2
Q17 X3 4
+3VS 1
1
+2.5V +2.5V
R371 10K_0402_5%
*27
R182 10K_0402_5%
+3V A
A
1
1
** R390
22
470_0402_5%
Q24 GHI#
3
MMBT3904_SOT23 1
CPU_GHI# 5 Title
Compal Electronics, Inc. SB200M(2/4) - IDE/USB/MII
Size
Document Number
Rev 0.1
LA-2101 Date: 5
4
3
2
Saturday, November 22, 2003 1
Sheet
25
of
52
4
3
2
+3VS
+3VS
22U_1206_10V4Z 0.1U_0402_10V6K C315 D
22U_1206_10V4Z
1
C412
2
1
1 C287
1 C286
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
1 C300
1 C299
2 2 2 2 0.1U_0402_10V6K 0.1U_0402_10V6K
1 C298
1 C297
1 C296
1 C295
1 C311
1 C361
1 C405
1 C416
1 C372
1 C432
1
2 2 2 2 2 2 2 2 2 2 2 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2
+3VS
1 C340
1 C341
0.1U_0402_10V6K
1 C383
1 C331
1 C393
1 C394
1
0.1U_0402_10V6K
ATI request
C327
1
C318
1
C302
1
C360
1
1
2
2
C404
C333 0.1U_0402_10V6K
2
C417
0.1U_0402_10V6K
1 C332
0.01U_0402_16V7Z 22U_1206_10V4Z
E11 E12 E15 E7 E8 F11 F12 F15 F16 F17 F7 F8 G18 G19 H18 H19 M18 M19 N18 N19 T18 T19 U18 U19 V17 V18 W17 W18
0.01U_0402_16V7Z 0.1U_0402_10V6K
1
U47C
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
+2.5VS
C355
1
2
2
2
0.01U_0402_16V7Z
2 2 2 2 2 2 2 2 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
0.01U_0402_16V7Z
0.01U_0402_16V7Z
+2.5VS +2.5VS
ATI request
+2.5V
J10 J11 J13 J14 K15 K9 L15 L9 N15 N9 P15 P9 R10 R11 R13 R14
0.01U_0402_16V7Z 0.1U_0402_10V6K C408 22U_1206_10V4Z C
1
2
1 C381
1 C397
0.1U_0402_10V6K 1 C425
1
2 2 2 0.1U_0402_10V6K
2
C434
C334
0.1U_0402_10V6K
0.01U_0402_16V7Z
1
C395
2
1
2
C409 22U_1206_10V4Z
1 C426
2
2
1 C433
1 C428
1
+2.5V
2 2 0.1U_0402_10V6K
2
C435 0.1U_0402_10V6K
C406 0.1U_0402_10V6K
0.01U_0402_16V7Z
1
C344
C382
C373
1
1
1
2
C384 0.01U_0402_16V7Z
C414 0.1U_0402_10V6K
1
2
C328
1
1
2
2
+2.5V
P6 R6 V13 W13 V12 L6 H6 J6
C348 0.1U_0402_10V6K
2
0.1U_0402_10V6K
2
C374
2
1U_0603_10V4Z
P5
+3V_AVDDC
T6 U6 V9 V10 V11 W9 W10
+3V
+3V_AVDDC
C359 2
2
0.1U_0402_10V6K
2
FBM-10-201209-260-T_0805
2
2
ATI request
R312 1
1
C319 0.1U_0402_10V6K
+3V_AVDDC
+3V
1
1
ATI request CLOSE TO L6,H6,J6
+3V
0.1U_0402_10V6K 0.1U_0402_10V6K 1
1
0.01U_0402_16V7Z
ATI request +3V
C396
10U_0805_10V4Z
1000P_0402_50V7K
1
2
F4 J4 K5 F3 K4 L5
+3V_AVDDUSB
+5VS 1
B
R271
+3V
C226
1
CH751H-40_SC76 1
1 C351
1 C343
1 C326
1 C312
1 C301
1
2
2 2 2 2 2 0.1U_0402_10V6K 0.1U_0402_10V6K
2
1
1
C342 C223
22U_1206_10V4Z
2
+3V_AVDDUSB
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
1K_0402_5% D32
2
+
0.1U_0402_10V6K 47U_B_6.3VM
2
ATI request
+3VALW
D19
+2.5VS
+5VS_VREF
2
R299 1 2 FBM-10-201209-260-T_0805
+3VS
ATI request
C210 1U_0603_10V4Z
+3V_AVDDUSB
D1 A21
+2.5V_AVDDCK +2.5VALW
Y9
+3VALW
AA9
C436 0.1U_0402_10V6K
1
2
1
2
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
SB200 SB Part 3 of 3
VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE
POWER
5
STB_2.5V STB_2.5V STB_2.5V STB_2.5V STB_2.5V VDD_USB VDD_USB VDD_USB AVDDC STB_3.3V STB_3.3V STB_3.3V STB_3.3V STB_3.3V STB_3.3V STB_3.3V AVDDTX0 AVDDTX1 AVDDTX2 AVDDRX0 AVDDRX1 AVDDRX2
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_USB VSS_USB AVSSC
VREF_CPU
S5_2.5V
AVSSRX2 AVSSRX1 AVSSRX0 AVSSTX2 AVSSTX1 AVSSTX0
S5_3.3V
AVSSCK
5V_VREF AVDD_CK
E10 E13 E14 E6 E9 F10 F13 F14 F18 F6 F9 G6 J12 J15 J18 J19 J9 K10 K11 K12 K13 K14 K18 K19 L10 L11 L12 L13 L14 L18 L19 M10 M11 M12 M13 M14 M15 M6 M9 N10 N11 N12 N13 N14 N6 P10 P11 P12 P13 P14 P18 P19 R12 R15 R18 R19 R9 V14 V15 V16 V19 V6 V7 V8 W14 W15 W16 W19 W7 W8 H5 G5
D
C
B
N5 M5 J5 G4 K6 H4 F5 A22
South bridge SB200 C447 0.1U_0402_10V6K
+2.5V_AVDDCK +2.5V_AVDDCK
A
1
R215 1 2 FBM-10-201209-260-T_0805 1
C222
C231
1
C193
4.7U_0805_10V4Z 22U_1206_10V4Z
2
2
0.1U_0402_10V6K
C460
1
C245
2
2
C197
1
1
2
2
1U_0603_10V4Z
+2.5VS
0.01U_0402_16V7Z
1000P_0402_50V7K A
Title
Compal Electronics, Inc. SB200M(3/4) - PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5
4
3
2
Document Number
Rev 0.1
LA-2101 Sheet
Tuesday, November 18, 2003 1
26
of
52
+3V
+3VALW
+3V
1
+3V
1
+3V
1
1
+3V
1
+3VS
1
+3VS
1
1
+3VS
1
+3V
2
1
+3V
1
+3VALW
R364
10K_0402_5%
10K_0402_5%
D
2
R384
10K_0402_5% 2
R353
10K_0402_5% 2
R356
10K_0402_5% 2
R340
10K_0402_5% 2
R361
@10K_0402_5% 2
R269
@10K_0402_5% 2
R280
@10K_0402_5% 2
R251
@10K_0402_5% 2
R338
@10K_0402_5% 2
R339
10K_0402_5% 2
R369
2
+3VS
D
3
1
4
1
5
1
25 PWR_STRP 25 SB_EEDO 25 SB_EECLK 25,33,38 ICH_AC_SYNC 25,33,38 ICH_AC_SDOUT @10K_0402_5% 25 SPDIF_OUT
2
R261
1
1
1
1
1
1
1
1
2
R381
R354
@10K_0402_5%
@10K_0402_5%
@10K_0402_5%
PWR_STRP
IGN DEBUG EEDO
EECK
AC_SYNC
AC_SDOUT
SPDIF_OUT
SPEEDSTEP CPU_STP#
FREQLTCH TX_EN
ETHERNET TXD[3:0]
32KHZ_S5
C
STRAP HIGH
MANUAL PWR ON
USE DEBUG STRAPS
ROM ON PCI BUS
INIT ACTIVE HIGH
33MHz NB BUS
SIO 24MHz
ENABLE SPEED STEP
IGNORE DEBUG STRAPS
ROM ON LPC BUS
INIT ACTIVE LOW (PIII)
HI SPEED A-LINK
SIO 48MHz
DISABLE SPEED STEP
STRAP LOW
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
1
+3VALW C476
32KHZ INPUT TO SB200 (EXT RTC)
+3VALW
+3VALW
+3VALW
0.1U_0402_16V4Z
8
O
0.47U_0603_16V7K 11
U24D
2
14 O
10
13
I
B
O
U24E
12
R393 1
2 47_0603_5%
U24F
R392 SN74LVC14APWLE_TSSOP14 @10K_0402_5%
2 SN74LVC14APWLE_TSSOP14
SN74LVC14APWLE_TSSOP14
2
SN74LVC14APWLE_TSSOP14
SB_PWRGD 25
2
@1M_0402_5%
I
7
7
C466
1
P
R396 1 2 330K_0402_5%
P
14
I
1
9
G
6
U24C
7
O
7
3
1
C475 0.1U_0402_10V6K
TC7SH08FU_SSOP5
R422
I
G
5 1
G
P 1 2 330K_0402_5%
P
R415 4
2
50 VCORE_PWRGD
14
14
U26
1
G
2
1K_0402_5%
5
10K_0402_5% B
DEFAULT
R421
2
R420
PROCESSOR FREQ MULTIPLIER
ENABLE CPU FREQSETTING
+3VALW
1
+3VS
DEFAULT
C
32KHZ OUTPUT FROM SB200 (INT RTC)
DISABLE CPU FREQ SETTING
DEFAULT
AUTO PWR ON
2
R349
@10K_0402_5%
2
R348
@10K_0402_5%
2
R355
@10K_0402_5%
2
R360
10K_0402_5%
2
R273
10K_0402_5%
2
R279
10K_0402_5%
2
R233
10K_0402_5%
2
R318
10K_0402_5% 2
R328
@10K_0402_5%
1
REQUIRED SYSTEM STRAPS
1
1 R366
2
2
10K_0402_5%
2
1 R252
1
25 MII_TXEN 25 MII_TXD3 25 MII_TXD2 25 MII_TXD1 25 MII_TXD0 25 SUSCLK
24,28,29,31,32 PCI_AD26
+3VS
*
1 R416
VTT_PWRGD 16,25
@0_0402_5%
R391
NB_PWRGD 7,9 1
1
2
1K_0402_5%
D Q25 2N7002_SOT23
2 G
R395 47K_0402_5% 2
3
S
A
A
Title
Compal Electronics, Inc. SB200M(4/4) - STRAPS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5
4
3
2
Document Number
Rev 0.1
LA-2101 Sheet
Saturday, November 22, 2003 1
27
of
52
5
4
3
2
1
LAN Realtek RT8101L
0.1U_0402_16V4Z Place closed to RTL8101L pin58
IDSEL
24,29,31,32 PCI_PAR 24,29,31,32 PCI_FRAME# 24,29,31,32 PCI_IRDY# 24,29,31,32 PCI_TRDY# 24,29,31,32 PCI_DEVSEL# 24,29,31,32 PCI_STOP#
24 18 19 20 21 23
PAR FRAME# IRDY# TRDY# DEVSEL# STOP#
24,29,31,32 PCI_PERR# 24,29,31,32 PCI_SERR#
25 26
PERR# SERR#
24 PCI_REQ#3 24 PCI_GNT#3
83 82
REQ# GNT#
80 79 57
INTA# INTB# PME#
81 97 50
RST# PCICLK CLKRUN#
6 22 37 49 90 95
VDD VDD VDD VDD VDD VDD
0.1U_0402_16V4Z TRACE=20mil
AVDD
70
+3V_LAN_VDD2
TRACE=20mil
AVDD
75
+3V_LAN_VDD3
TRACE=20mil
EEDO EEDI EESK EECS
52 53 54 55
LAN_EEDO LAN_EEDI LAN_EECLK LAN_EECS
LED0 LED1 LED2
78 77 76
ACTIVITY# LINK10_100#
TXD+ TXD-
72 71
LAN_TD+ LAN_TD-
RXIN+ RXIN-
68 67
LAN_RD+ LAN_RD-
X1
61
LAN_X1
X2
60
LWAKE
64
ISOLATE#
74
RTSET
65
RTT3
63
VCTRL
56
Power
+3V_LAN_VDD1
+2.5V_LAN
1
1 2 L35 LQG21N4R7K10_0805
+3V
D
TRACE=30mil
AT93C46-10SI-2.7_SO8
Layout Note TS6121 pls close to U36 conn.
C551 0.1U_0402_16V4Z LAN_TD+ LAN_TD-
LAN_RD+ LAN_RD-
16 14 15
7 6 8
CT RD+ RD-
CT RX+ RX-
10 11 9
RJ45_RX+ RJ45_RX-
TS6121C_16P
1
R69 75_0402_5%
R68 75_0402_5%
C609
B
C580
C41
C
2
0.1U_0402_16V4Z
Q42 @2SB1197K_SOT2 3
E
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
47K
1
2
2
2
+3V
RJ45_TX+ RJ45_TX-
1
R85 49.9_0402_1%
2 10K
Closed to RTL8101L
C
Closed to Bothhand TS6121 RJ45_PR
reserve transistor for ver.C
100 99
+2.5V_LAN C42 @22U_1206_10V4Z
DGND1 DGND2 DGND3 DGND4 DGND5 AGND1 AGND2 AGND3
2 16 31 44 88 62 66 73
Y2 25MHZ_20PF_6X25000017 LAN_X1 LAN_X2 C583 27P_0402_50V8J
C588 27P_0402_50V8J 3
+3V
Q44 DTA114YKA_SOT23 1 1 2 R526 300_0402_5%
C
51 69
JP17 12
Amber LED+
11
Amber LED-
8
RTL8101L_LQFP100 2
B
TX+ TXCT
2
2
2 15K_0402_5% 2 5.6K_0603_1%
R86 49.9_0402_1%
1
1 R101 1 R102
+3VS
2
2 1K_0402_5%
3
1 R100
TD+ TDCT
1
R500 49.9_0402_1%
LAN_X2
1
R501 49.9_0402_1%
1 3 2
1
1
1
+3V
2
2
1 2 R502 5.6K_0402_5%
1 3 4 5 7
ROMCS/OEB NC
Power
+3V
10K
GPIO0 GPIO1
5 6 7 8 1
GND NC NC VCC
1
AC_RST# AC_SYNC AC_DOUT AC_DIN AC_BCK
DO DI SK CS
1
PCI I/F LAN I/F
U37 4 3 2 1
E
+3V
59
47K
CLK_PCI_LAN
AVDD
B
29,31,32,39 LAN_PME# 23,24,29,31,32,36,39 PCIRST# 24 CLK_PCI_LAN 24,29,31,32,36,39 PM_CLKRUN#
+2.5V_LAN
2
24,31 PCI_PIRQD#
58
1
2 LAN_IDSEL 100_0402_5%
C584
2
PCI_AD19 1 R545
C574
2
98
PCI_C/BE#0 PCI_C/BE#1 PCI_C/BE#2 PCI_C/BE#3
C575
RTL8101L has internal +2.5V generator at pin58
AVDD25
1
IDSEL:PCI_AD17
PCI_C/BE#0 PCI_C/BE#1 PCI_C/BE#2 PCI_C/BE#3
2
TRACE=20mil
2
C
24,29,31,32 24,29,31,32 24,29,31,32 24,29,31,32
0.1U_0402_16V4Z
2
C/BE#0 C/BE#1 C/BE#2 C/BE#3
D
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C590
1
22U_1206_10V4Z 1 C576
2
C622
2
38 27 17 84
PCI_AD[0..31]
PCI_AD[0..31]
VDD25 VDD25
48 94
2
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
AC-Link
24,27,29,31,32
47 46 45 43 42 41 40 39 36 35 34 33 32 30 29 28 15 14 13 12 11 10 9 8 96 93 92 91 89 87 86 85
2
C657
U40 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
1
0_0805_5%
1
R499
1
+2.5V_DLAN
1
TRACE=20mil +2.5V_LAN
7
PR4+
6
PR2-
5
PR3-
4
PR3+
RJ45_RX+
3
PR2+
RJ45_TX-
2
PR1-
RJ45_TX+
1
PR1+
ACTIVITY#
1
15
SHLD2
14
SHLD1
10
Green LED-
9
13
Green LED+
B
TYCO_1566203-1
1
C
16
SHLD3
1
B
CLK_PCI_LAN
Q43 DTA114YKA_SOT23 1 1 2 R516 300_0402_5%
10K
+3V
3
47K
E
RJ45_RX-
SHLD4 PR4-
R63 75_0402_5% 2
LINK10_100#
2
R64 75_0402_5%
2
R537 @10_0402_5%
12
RJ45_PR
2
@0.1U_0402_16V4Z LANGND 1
1000P_1206_2KV7K
C667 @10P_0402_50V8K
C564
Termination plane should be coupled to chassis ground
2
A
C5 1
C8 4.7U_0805_10V4Z
2
A
+3V
C652
C673
C672
C653
C613
C663
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Title
LAN REALTEK RTL8101L THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
Compal Electronics, Inc.
3
2
Document Number
Rev 0.1
LA-2101 Saturday, November 22, 2003
Sheet 1
28
of
52
5
4
3
2
1
+3VS 0.1U_0402_16V4Z
+S1_VCC 1
0.1U_0402_16V4Z 1
C684
1
C700 2
2
1 C699
2
C718
1 C694
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z +3VS
1
30 VPPD0 30 VPPD1 30 VCCD0# 30 VCCD1#
C717
IDSEL:PCI_AD20
24,28,31,32 24,28,31,32 24,28,31,32 24,28,31,32
23,24,28,31,32,36,39 PCIRST# 24,28,31,32 PCI_FRAME# 24,28,31,32 PCI_IRDY# 24,28,31,32 PCI_TRDY# 24,28,31,32 PCI_DEVSEL# 24,28,31,32 PCI_STOP# 24,28,31,32 PCI_PERR# 24,28,31,32 PCI_SERR# 24,28,31,32 PCI_PAR 24 PCI_REQ#2 24 PCI_GNT#2 24 CLK_PCI_CB
2
+3VS
1
R606 10K_0402_5%
E1 J3 N1 N5
PCI_C/BE#3 PCI_C/BE#2 PCI_C/BE#1 PCI_C/BE#0 PCIRST#
CLK_PCI_PCM
L8 L11
28,31,32,39 PCM_PME# PCI_AD20
B
1 R125 R579 2 R152 2 R601 2 R164 2 R596 2 R167 2 R169 2
PCI_PIRQA#
9,17,24,32 PCI_PIRQA#
PCI_PIRQB#
24 PCI_PIRQB# 24,36,39 SERIRQ
41 SDLED# 24,28,31,32,36,39 PM_CLKRUN#
G4 J4 K1 K3 L1 L2 L3 M1 M2 A1 B1 H1
PCM_ID 2 F4 100_0402_5% 1 0_0402_5% K8 1 @10K_0402_5% N9 1 0_0402_5% K9 1 0_0402_5% N10 1 @10K_0402_5%L10 1 0_0402_5% N11 1 0_0402_5% M11 PCIRST#
M10
B4 C8 D12 H11 L9 L6 N4 K2 G1 F3
A7 G13
CCBE3#/REG# CCBE2#/A12 CCBE1#/A8 CCBE0#/CE1# CRST#/RESET CFRAME#/A23 CIRDY#/A15 CTRDY#/A22 CDEVSEL#/A21 CSTOP#/A20 CPERR#/A14 CSERR#/WAIT# CPAR/A13 CREQ#/INPACK# CGNT#/WE# CCLK/A16
PCIRST# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# PAR PCIREQ# PCIGNT# PCICLK RIOUT#_PME# SUSPEND#
CSTSCHG/BVD1_STSHG# CCLKRUN#/WP_IOIS16#
IDSEL
CBLOCK#/A19
MFUNC0 MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6
CINT#/READY_IREQ# SPKROUT CAUDIO/BVD2_SPKR# CCD2#/CD2# CCD1#/CD1# CVS2/VS2# CVS1/VS1#
GRST#
E8 H7
MFUNC7
RSVD4 RSVD3 RSVD2 RSVD1
SD
VCC_SD GND_SD SDCD# MSINS#
MSDATA3 MSDATA2 MSDATA1 MSDATA0
J9 E7 G5
MSCLK SDCLK
30 MMC_DET#
1 0_0402_5%
MSPWREN# SDPWREN33#
2
1 1U_0603_10V4Z
SDCMD SDWP SDCLKI MSBS
R187 2 C708
R577
1 0_0402_5% 1
2
F9 G8 H9 G9
J8 G7
E5 F8 H5 H8
E9 F6
A
16 SD_CLKIN
0.1U_0402_16V4Z
C5 D5
S1_BVD1 S1_WP
D11
S1_A19
D6
S1_RDY#
M9 B5
PCM_SPK# S1_BVD2
A4 L12 D9 C6
S1_CD2# S1_CD1# S1_VS2 S1_VS1
1
S1_RST
SDDAT0 SDDAT1 SDDAT2 SDDAT3
D3 H2 L4 M8 K11 F12 C10 B6 J13 E10 A2
Reserved layout for debug used. R190 47K_0402_5%
S1_IOWR# 30 S1_IORD# 30
2
B9 B11 A12 A13 B13 C12 C13 A5 D13 B8 C11 B12
R208 47K_0402_5%
S1_OE# 30 S1_CE2# 30
R189 R586 47K_0402_5% 47K_0402_5%
Reserved layout for debug used. R598 @47K_0402_5%
S1_REG# 30 S1_CE1# 30 S1_A23
S1_A15 S1_A22 S1_A21 S1_A20 S1_A14 S1_WAIT# S1_A13 S1_INPACK# S1_WE# A16_CLK
C
+S1_VCC
1
S1_REG# S1_A12 S1_A8 S1_CE1#
S1_D[0..15] 30
+S1_VCC
S1_RST 30
S1_WAIT# 30 S1_INPACK# 30 S1_WE# 30
2 R604
S1_A16
1 10_0402_5% 1 C713
S1_BVD1 30 S1_WP 30
2 @10P_0402_50V8K
S1_RDY# 30 B
PCM_SPK# 34 S1_BVD2 30 S1_CD2# 30 S1_CD1# 30 S1_VS2 30 S1_VS1 30
2
C157 10P_0402_50V8K
Close to CB712 CD1# and CD2# S1_D14 S1_A18 S1_D2
H6 J7 J6 J5 E6 F7 F5 G6
SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3
30 30 30 30 A
CB712_ LFBGA_169P
30 SD_CLK 30 SD_CMD 30 SD_WP 30 SD_PWREN# R576 @10K_0402_5%
Title
PCMCIA Controller ENE CB1410 & CB712
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
C709 2
S1_A[0..25] 30
S1_D[0..15]
1
B7 A11 E11 H13
S1_A[0..25]
2
S1_D10 S1_D9 S1_D1 S1_D8 S1_D0 S1_A0 S1_A1 S1_A2 S1_A3 S1_A4 S1_A5 S1_A6 S1_A25 S1_A7 S1_A24 S1_A17 S1_IOWR# S1_A9 S1_IORD# S1_A11 S1_OE# S1_CE2# S1_A10 S1_D15 S1_D7 S1_D13 S1_D6 S1_D12 S1_D5 S1_D11 S1_D4 S1_D3
2 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 CRSV1/D14 CRSV2/A18 CRSV3/D2
+SD3_VCC
2
0.1U_0402_16V4Z
C108 10P_0402_50V8K
30 SD_OC#
C706
2
VCC10 VCC9 VCC8 VCC7 VCC6 VCC5 VCC4 VCC3 VCC2 VCC1
VCCA2 VCCA1
M13 N13
M12 N12 VPPD1 VPPD0
CBE3# CBE2# CBE1# CBE0#
C691
D
1
2
C95 @18P_0402_50V8K
1
1
2
B2 C3 B3 A3 C4 A6 D7 C7 A8 D8 A9 C9 A10 B10 D10 E12 F10 E13 F13 F11 G10 G11 G12 H12 H10 J11 J12 K13 J10 K10 K12 L13
1
1
CAD31/D10 CAD30/D9 CAD29/D1 CAD28/D8 CAD27/D0 CAD26/A0 CAD25/A1 CAD24/A2 CAD23/A3 CAD22/A4 CAD21/A5 CAD20/A6 CAD19/A25 CAD18/A7 CAD17/A24 CAD16/A17 CAD15/IOWR# CAD14/A9 CAD13/IORD# CAD12/A11 CAD11/OE# CAD10/CE2# CAD9/A10 CAD8/D15 CAD7/D7 CAD6/D13 CAD5/D6 CAD4/D12 CAD3/D5 CAD2/D11 CAD1/D4 CAD0/D3
2
2
C
C716 2
1
R129 @10_0402_5%
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
1
1
CLK_PCI_PCM
C2 C1 D4 D2 D1 E4 E3 E2 F2 F1 G2 G3 H3 H4 J1 J2 N2 M3 N3 K4 M4 K5 L5 M5 K6 M6 N6 M7 N7 L7 K7 N8
1
0.1U_0402_16V4Z
2
PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0
CARDBUS
PCI_AD[0..31]
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
VCCD1# VCCD0# 24,27,28,31,32 PCI_AD[0..31]
C695 2
+3VS
D
U7
1 C688
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
4
3
2
Rev 0.1
LA-2101
Saturday, November 22, 2003
Sheet 1
29
of
52
CARDBUS SOCKET
SD SOCKET
S1_A[0..25]
29 S1_A[0..25]
S1_D[0..15]
29 S1_D[0..15]
+SD3_VCC JP26
29 S1_WE# 29 S1_RDY# +S1_VCC +S1_VPP
S1_A16 S1_A15 S1_A12 S1_A7 S1_A6 S1_A5 S1_A4 S1_A3 S1_A2 S1_A1 S1_A0 S1_D0 S1_D1 S1_D2 S1_WP
29 S1_WP
S1_A22 S1_A23 S1_A24 S1_A25 S1_VS2 S1_RST S1_WAIT# S1_INPACK# S1_REG# S1_BVD2 S1_BVD1 S1_D8 S1_D9 S1_D10 S1_CD2#
1
1
R653
Close to chip +S1_VCC +S1_VPP
1 R578
29 SD_CLK
S1_VS2 29 S1_RST 29 S1_WAIT# 29 S1_INPACK# 29 S1_REG# 29 S1_BVD2 29 S1_BVD1 29
2 JP4
29 SD_WP
11
29 SD_DAT1 29 SD_DAT0
29 SD_CMD 29 SD_DAT3
8 7 6 5 4 3 2 1
29 SD_DAT2
9
2 22_0402_5% C776
@10P_0402_50V8K
R674 43K_0402_5% 2
R669 43K_0402_5%
2 43K_0402_5%
2 43K_0402_5%
S1_CE2# 29 S1_VS1 29 S1_IORD# 29 S1_IOWR# 29
2 43K_0402_5%
1
R676 R673 R649 R644
1
1
1
S1_CD1# 29
2 43K_0402_5%
S1_CD1# S1_D11 S1_D12 S1_D13 S1_D14 S1_D15 S1_CE2# S1_VS1 S1_IORD# S1_IOWR# S1_A17 S1_A18 S1_A19 S1_A20 S1_A21
1
+3VS
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84
2 43K_0402_5%
29 S1_OE#
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 GND GND GND GND GND GND GND GND
1
29 S1_CE1#
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 GND GND GND GND GND GND GND GND
2
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83
S1_D3 S1_D4 S1_D5 S1_D6 S1_D7 S1_CE1# S1_A10 S1_OE# S1_A11 S1_A9 S1_A8 S1_A13 S1_A14 S1_WE# S1_RDY#
Wr_Pt
Wr_Pt_Vss VSS
10 12
DAT1 DAT0 Vss2 SDCLK Vdd Vss1 CMD DAT3 DAT2
MMC_DET#
13
SD_SOCKET
Close to SD socket
29 MMC_DET#
S1_CD2# 29
FOXCONN_1CA415M1-TA_68P +3VS
+SD3_VCC
2
2 R193 10K_0402_5%
1 1
29 SD_PWREN#
PCMCIA Power Controller
2
C173 0.1U_0402_16V4Z U10 1 2 3 4
GND IN IN EN#
1 OUT OUT OUT OC#
8 7 6 5
C772 0.1U_0402_16V4Z
C760 4.7U_0805_10V4Z
Close to SD socket +3VS 2
TPS2041ADR_SO8 R166
9 0.1U_0402_16V4Z
C161
10K_0402_5%
+S1_VCC
U9 VCC VCC VCC
12V
13 12 11
1 2 C121 0.1U_0402_16V4Z
40mil
0.1U_0402_16V4Z
C162
4.7U_0805_10V4Z
C132
VPP 5 6
VCCD0 VCCD1 VPPD0 VPPD1
SHDN
OC
1 2 15 14
VCCD0# 29 VCCD1# 29 VPPD0 29 VPPD1 29
8
CP-2211_SSOP16
1
7
R150 10K_0402_5%
3.3V 3.3V
GND
3 4
16
C167 2
C160
4.7U_0805_10V4Z
20mil
5V 5V
+3VS 0.1U_0402_16V4Z
10
SD_OC# 29
C120 0.1U_0402_16V4Z 1 2 C273 10U_1206_16V4Z 1 2 C122 0.01U_0402_16V7Z 1 2 C260 1U_0603_10V4Z
+S1_VPP +5VS
1
+5VS
Title
Compal Electronics, Inc. PCMCIA/SD SOCKET
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D CustomLA-2101 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Saturday, November 22, 2003
Rev 0.1 Sheet
30
of
52
+3V C422
0.1U_0402_16V4Z
5
PCI_AD[0..31]
39 WL_OFF#
1
39,41 KILL_SW#
2
PCI_AD[0..31]
24,27,28,29,32
U20
4
3
MINI_PCI SOCKET TC7SH08FU_SSOP5 JP27
2
1
KEYLINK_5305-4-211
RING
LAN RESERVED
W=30mils W=40mils PCIRST#
+3VS_MINIPCI +3V
L17
PCIRST# 23,24,28,29,32,36,39 W=40mils
1
PCI_GNT#1 24
2
+3VS
0_0603_5%
WLANPME# 28,29,32,39 PCI_AD30 PCI_AD28 PCI_AD26 PCI_AD24 MINI_IDSEL 1 R260 PCI_AD22 PCI_AD20 PCI_AD18 PCI_AD16
2 PCI_AD18 100_0402_5%
IDSEL : PCI_AD18
PCI_PAR 24,28,29,32
PCI_FRAME# 24,28,29,32 PCI_TRDY# 24,28,29,32 PCI_STOP# 24,28,29,32 C146 0.1U_0402_16V4Z 1
1000P_0402_50V7K
2
C114
1
C402 0.1U_0402_16V4Z
1
PCI_AD15 PCI_AD13 PCI_AD11
+5VS_MINIPCI 2
PCI_DEVSEL# 24,28,29,32
2
C418 10U_1206_16V4Z
PCI_AD9 PCI_C/BE#0 24,28,29,32
W=20mils
2
2
0.1U_0402_16V4Z
C217 0.1U_0402_16V4Z
1
C324 0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
C349
1
0.1U_0402_16V4Z
C234
2
+3VS_MINIPCI C174
1
PCI_AD6 PCI_AD4 PCI_AD2 PCI_AD0
2
C356 10U_1206_16V4Z
+3V
C112 0.1U_0402_16V4Z 1
0603 +5VS_MINIPCI
+5VS_MINIPCI PCI_PIRQC# 24
2
4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124
1
2
2
2 KEY 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124
2
1 KEY 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123
1
2
1
3 LAN RESERVED 5 7 9 D45 11 1 2 13 +3VS_MINIPCI 15 CH751H-40_SC76 17 L16 24,28 PCI_PIRQD# W=40mils 1 2 19 +3VS 21 0_0603_5% 23 CLK_PCI_MINI 25 24 CLK_PCI_MINI 27 29 24 PCI_REQ#1 31 PCI_AD31 33 PCI_AD29 35 37 PCI_AD27 39 PCI_AD25 41 43 45 24,28,29,32 PCI_C/BE#3 PCI_AD23 47 49 PCI_AD21 51 PCI_AD19 53 55 PCI_AD17 57 59 24,28,29,32 PCI_C/BE#2 61 24,28,29,32 PCI_IRDY# 63 65 24,28,29,32,36,39 PM_CLKRUN# 67 24,28,29,32 PCI_SERR# 69 71 24,28,29,32 PCI_PERR# 73 24,28,29,32 PCI_C/BE#1 PCI_AD14 75 77 PCI_AD12 79 PCI_AD10 81 83 PCI_AD8 85 CLK_PCI_MINI PCI_AD7 87 89 PCI_AD5 91 R306 93 @33_0402_5% PCI_AD3 95 W=30mils 97 +5VS_MINIPCI PCI_AD1 99 101 103 105 C368 107 @10P_0402_50V8K 109 111 113 115 117 119 121 1 2 W=30mils 123 +5VS L9 0_0603_5%
1
1
2
TIP
Compal Electronics, Inc. Title
MINI_PCI THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D CustomLA-2101 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Saturday, November 22, 2003
Rev 0.1 Sheet
31
of
52
A
B
C
D
E
+3VS +3VS 1 R504 1 R505 1 R503 1 R550 2 R553
2 4.7K_0402_5% 2 10K_0402_5% 2 4.7K_0402_5% 2 4.7K_0402_5% 1 4.7K_0402_5%
DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD PLLVDD AVDD AVDD AVDD AVDD AVDD
15 27 39 51 59 72 88 100 7 1 2 107 108 120
CPS
106
NC/(TPBIAS1) NC/(TPA1+) NC/(TPA1-) NC/(TPB1+) NC/(TPB1-)
125 124 123 122 121
+3VS
PCI_AD16
2 1394_IDSEL 100_0402_5%
1 R527
24,28,29,31 PCI_C/BE#3 24,28,29,31 PCI_C/BE#2 24,28,29,31 PCI_C/BE#1 24,28,29,31 PCI_C/BE#0 24 CLK_PCI_1394 24 PCI_GNT#0 24 PCI_REQ#0 24,28,29,31 PCI_FRAME# 24,28,29,31 PCI_IRDY# 24,28,29,31 PCI_TRDY# 24,28,29,31 PCI_DEVSEL# 24,28,29,31 PCI_STOP# 24,28,29,31 PCI_PERR# 9,17,24,29 PCI_PIRQA# 28,29,31,39 1394_PME# 24,28,29,31 PCI_SERR# 24,28,29,31 PCI_PAR 24,28,29,31,36,39 PM_CLKRUN# 23,24,28,29,31,36,39 PCIRST#
PCIRST#
C638
C651
C75
C77
C677
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3VS
1
86 96 10 11 CYCLEOUT/CARDBUS CNA TEST17 TEST16
CYCLEIN
PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_C/BE3 PCI_C/BE2 PCI_C/BE1 PCI_C/BE0 PCI_CLK PCI_GNT PCI_REQ PCI_IDSEL PCI_FRAME PCI_IRDY PCI_TRDY PCI_DEVSEL PCI_STOP PCI_PERR PCI_INTA/CINT PCI_PME/CSTSCHG PCI_SERR PCI_PAR PCI_CLKRUN PCI_RST
TSB43AB21A /(TSB43AB22)
PCI BUS INTERFACE
84 82 81 80 79 77 76 74 71 70 69 67 66 65 63 61 46 45 43 42 41 40 38 37 32 31 29 28 26 25 24 22 34 47 60 73 16 18 19 36 49 50 52 53 54 56 13 21 57 58 12 85
C628
0.1U_0402_16V4Z
BIAS CURRENT
R0
118
+3VS
C674 0.01U_0402_16V7Z
1 R515
2 1K_0402_5%
R116
6.34K_0603_1%
C86
C84
C54
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
C102 4.7U_0805_10V4Z
Place very close to U36.5 1394_XTLIN
C681 R1
119
X0
6
X1
5
FILTER0
3
C83
FILTER1
4
0.1U_0402_16V4Z
EEPROM 2 WIRE BUS SDA
92
SCL
91
1 R99 1 R98
PC0 PC1 PC2
99 98 97
OSCILLATOR
2
C59
1000P_0402_50V7K
L8 BLM21A601SPT_0805 1 2 +3VS
1394_PLLVDD 1
C676
1 R551
2 @10_0402_5%
1394_XCLK 36 2
22P_0402_50V8J
2
IDSEL:PCI_AD16
PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_C/BE#3 PCI_C/BE#2 PCI_C/BE#1 PCI_C/BE#0 CLK_PCI_1394 PCI_GNT#0 PCI_REQ#0 1394_IDSEL PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_DEVSEL# PCI_STOP# PCI_PERR# PCI_PIRQA# 1394_PME# PCI_SERR# PCI_PAR
VDDP VDDP VDDP VDDP VDDP
U41
C602
0.1U_0402_16V4Z
X4 24.576MHz_16P_3XG-24576-43E 1 1
2
20 35 48 62 78
PCI_AD[0..31]
24,27,28,29,31 PCI_AD[0..31]
87
1
C601
FILTER
POWER CLASS
PHY PORT 1
TPBIAS0 TPA0+ TPA0TPB0 + TPB0 -
1394_XTLIN
C680
22P_0402_50V8J
2 220_0402_5% 2 220_0402_5%
1 R542 56.2_0603_1%
116 115 114 113 112
R533 56.2_0603_1%
2
C670 0.33U_0603_16V4Z
TPBIAS0 TPA0+ TPA0TPB0+ TPB0-
JP21 4 3 2 1
4 3 2 1 FOX_UV31413-T1
89 90
GPIO3 GPIO2
8 9 109 110 111 117 126 127 128 17 23 30 33 44 55 64 68 75 83 93 103
R95 220_0402_5%
TEST9 TEST8
94 95
TEST3 TEST2 TEST1 TEST0
101 102 104 105
R528 56.2_0603_1%
R523 56.2_0603_1%
C627
R518 5.11K_0603_1%
3
1
TSB43AB21A_PQFP128
2 220P_0402_50V7K
1
1
2
R94 220_0402_5% C675 @10P_0402_50V8K
G_RST
2
R552 @10_0402_5%
2
1
CLK_PCI_1394
14
PLLGND1 REG_EN AGND AGND AGND AGND AGND AGND AGND DGND DGND REG18 DGND DGND DGND DGND DGND DGND DGND REG18 DGND
3
C678 0.1U_0402_16V4Z
C591 0.1U_0402_16V4Z
4
4
Compal Electronics, Inc. Title PROPRIETARY NOTE
A
B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C
D
1394 Interface Size Document Number CustomLA-2101 Date:
Rev 0.1
Saturday, November 22, 2003
Sheet E
32
of
52
4
3
2
DIRECT PLAY PATH
R696 1M_0402_5%
AMP_LEFT 34
3
AMP_LEFT
R295 10K_0402_5% 1 2
U25B 74HCT4066
2 Q21 1
+5VALW P
1
1
2
R642
R257 1K_0402_5%
AMP_RIGHT 34
U25D 74HCT4066
+5VLDO 2N7002_SOT23 Q18
35,39 CD_PLAY
S
D
3
2N7002_SOT23 Q50 CD_PLAY 2 G
1
R692 0_0402_5% 1 2
EC_IDERST_1
D
2 G
2
2
EC_IDERST
1
(4.5V)
C264
2
3.9K_0603_1%
3
S L18 2
19
CD_GND
21
MIC1
22
MIC2
13
PHONE
12
25,38 ICH_AC_RST#
2 1 11 R655 22_0402_5% 1 R302 2 10 22_0402_5% 1 R296 2 5 22_0402_5% 45 46
C794 0.1U_0402_10V6K
25,27,38 ICH_AC_SYNC 25,27,38 ICH_AC_SDOUT
XTL_OUT
3
AFILT1
29
22P_0402_50V8J
C768
Audio Signal Bias Circuit
SPDIFO DVSS1 DVSS2
34 LINE_IN_L
DCVOL
32
34 LINE_IN_R
NC VREFOUT2 VAUX SCK SDA
31 33 34 43 44
NC AVSS1 AVSS2
40 26 42
1 R359
2 0_0402_5%
+AUD_VREF
35 INT_CD_L 1 R368
2 @0_0402_5% 1 R336
1 2
@0_0603_5% AGND
2
C454
1
Place very close to U44.2 AGND
AC97_XTLIN
1 R297
1
2
C801
1
2
C811
C800
2 @10_0402_5%
1
2
C810
C294 @0.1U_0402_16V4Z
2 7
1
8 2N7002_SOT23 Q54 EC_IDERST 2 G
VOUT
5
DELAY
SENSE
6
ERROR ON/OFF#
CNOISE
1
GND
3
@SI9182DH-AD_MSOP8 35,39,40,43 SUSP#
1 C763 2
1
C756
2
1
C749
2
SUSP#
+VDDA R654 @69.8K_0603_1%
C759 @0.1U_0402_16V4Z 2
DGND To AGND Bypass
1 C448 1 C440 1 C806 1 C796
2 LINEIN_L 1U_0603_10V4Z 2 LINEIN_R 1U_0603_10V4Z CD_L 2 1U_0603_10V4Z CD_R 2 1U_0603_10V4Z
+VDDA
2 1 R335 20K_0402_1%
DGND
+AUD_VREF
C444
1
C455
2
+5VALWP TO +5VLDO
R320
R334 6.8K_0402_5%
0_0402_5%
C362 @4.7U_0805_10V4Z
AGND
Analog Reference V
CD_GNA
+5VLDO
L49 1 2 CHB2012U170_0805
+5VAMP A
L46 1 2 CHB2012U170_0805
R651 @24K _0402_1% 1
Compal Electronics, Inc. Title
AC97 Codec
S 3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
2
CD_AGND To CD_GNA Bypass
2
C281 @4.7U_0805_10V4Z
VIN
1 6.8K_0402_5% 1 6.8K_0402_5% 1 6.8K_0402_5% 1 6.8K_0402_5% 1 20K_0402_1% 1 20K_0402_1% 1 6.8K_0402_5% 1 6.8K_0402_5%
2
2
4
35 INT_CD_R
2 R408 2 R407 2 R414 2 R413 2 R686 2 R684 2 R685 2 R687
35 CD_AGND
U17
R671 10K_0402_5%
C762
AC97_XCLK 36
Adjustable Output
+5VALW P
A
1
B
27
2
SDATA_OUT
4 7
C220
2
22P_0402_50V8J
28
+5VALW P
1
C437 1000P_0402_50V7K
2
VREF
ALC250_LQFP48
D
1
VREFOUT
DGND
EC_IDERST_1
X5 24.576MHz_16P_3XG-24576-43E1 1 2 1 C438 1000P_0402_50V7K C767
30
SYNC
48
2
1
25
AFILT2
RESET#
SPDIFI/EAPD
2
C221
R298
PC_BEEP
NC XTLSEL
2
1
@1M_0402_5%
2 R326 @0_0402_5%
ICH_AC_SDIN0
2
1 C266
AC97_XTLIN
+AVDD_AC97
47
34 EAPD
2
2
1
2
34 MONO_IN
8
XTL_IN
1
1
SDATA_IN
2
1 C246
@22U_1206_10V4Z
CD_R
25,38
C205
0.1U_0402_16V4Z
20
ICH_AC_BITCLK
1
22U_1206_10V4Z
CD_R
2 22_0402_5% 1 2 R294 @10K_0402_5% 2 22_0402_5%
1 C190
@0.1U_0402_10V6K
CD_L
1 R657 1 R656
C177
0.1U_0402_10V6K
18
6
1
1
CD_L
BIT_CLK
1 2 C350 @15P_0402_50V8J
@1U_0603_10V4Z
LINE_IN_R
+5VALW P
(4.5V)
1U_0603_10V4Z
41
24
LINEIN_R
+5VLDO
+5VALWP DECOUPLING
AC97_R @4.7U_0805_10V4Z
HP_OUT_R
AC97_L
4.7U_0805_10V4Z
LINE_IN_L
+5VAMP DECOUPLING
@1000P_0402_50V7K 2 1U_0603_10V4Z 2 1U_0603_10V4Z
22U_1206_10V4Z
39
23
LINEIN_L
1 2 C_MD_SPK C785 1U_0603_10V4Z
9 37
HP_OUT_L
1 C452 1 C809
@1000P_0402_50V7K
2
1 2 0_0402_5%
38 MD_SPK
1
MONO_OUT/VREFOUT3
JD1
R672 B
DVDD1
JD2
17
C
1U_0603_10V4Z
R670 1 2 @10K_0402_5%
LINER
16
CD_GNA 1 2 C399 1U_0603_10V4Z C_MIC 1 2 C413 1U_0603_10V4Z
@0.01U_0402_25V4Z C784
36
AUX_R
4.99K_0603_1%
0.1U_0402_16V4Z
1 2 R350 0_0402_5%
34 MIC
LINE_OUT_R
AUX_L
D62 @RB751V_SOD323 1 2
34,40 NBA_PLUG
LINE_OUT_L
LINEL
15
2 @1U_0603_10V4Z
2
1U_0603_10V4Z
1 C775
C443 35
14
R641
C377 10U_1206_16V4Z
1
*
C802
DVDD2
38
U49
25
2
AVDD2
C429 10U_1206_16V4Z
AVDD1
0.1U_0402_16V4Z
3
D61
2
0.1U_0402_16V4Z
1
C423
R
A
1
C769
@CHB2012U170_0805 C
2
1 +3VS
0.01U_0402_16V7Z
+VDDA
K
+AVDD_AC97
CHB2012U170_0805 L50 1 2
1U_0603_10V4Z
1
+5VAMP
1
2
AC97 Codec
R646
LM431SC_SOT23
1U_0603_10V4Z
35,39 EC_IDERST
SI4800DY_SO8 U14
1
R693 1M_0402_5%
AMP_RIGHT
1
R694 1M_0402_5%
9
4 3 2 1
+5VAMP
U25C 74HCT4066
1
2
2
14 8 7 6
R697 1M_0402_5%
5
1M_0402_5%
AMP_RIGHT
3
1
AC97_R
1 1
+5VAMP
14 4 7
2
10K_0402_5% R698 2
D
2
+5VALW P
AOS 3401_SOT23
5 6 7 8
D
C823 1U_0603_10V4Z INT_CD_R 1 2
C325 1
+5VALW P +12VALW
2
2
*
D D D D
R695 1M_0402_5%
10
G S S S
U25A 74HCT4066
*
14 11 7
1
1U_0603_10V4Z
R423 1M_0402_5%
2
+5VAMP
+5VALW P
1U_0603_10V4Z
13
1
1M_0402_5%
AMP_LEFT
2
12
14 1 7
AC97_L
1
1
R424 2
+5VAMP
+5VALW P
C824 1U_0603_10V4Z INT_CD_L 1 2
1U_0603_10V4Z
POWER ON PATH
+5VALW P
1
+5VALWP TO +5VLDO
@1U_0805_25V4Z
5
4
3
2
Size Document Number CustomLA-2101 Date:
Rev 0.1
Saturday, November 22, 2003
Sheet 1
33
of
52
A
B
C
D
Left Speaker Connector
+5VAMP
1
1
R307 0_0402_5% 2 1 2 G
+5VAMP
17 HP_L
2
C481
1
1
C836
C829 0.047U_0402_16V4Z
0.1U_0402_16V4Z 2
R426 1.5K_0603_5%
1
1
D63
2
1
C828
2
C827
1
2
LINE IN JACK
JP29 5 4 L52 LINE_IN_R-1 1 2 FBM-11-160808-700T_0603 LINE_IN_L-1 1 2 L51 FBM-11-160808-700T_0603 C821
33 LINE_IN_R 33 LINE_IN_L
2
1
R702 1.5K_0603_5% 2
1 2 ACES_85204-0200
@V-PORT-0603-220 M-V05_0603 2
@V-PORT-0603-220 M-V05_0603
1 12 13 24
HP_R
2
2
1
D64
JP11
INTSPK_L2 INTSPK_R2
TPA0232
1
AMP_LEFT C825 1 0.47U_0603_16V7K AMP_RIGHT C835 1 0.47U_0603_16V7K
FBM-11-160808-121-T_0603 1 2 1 2 FBM-11-160808-121-T_0603
L54
3
1
1
2 C833 1U_0603_10V4Z 2 C838 1U_0603_10V4Z
L55 INTSPK_R1 INTSPK_R2
0.47U_0603_16V7K
2
1
NBA_PLUG C485 0.1U_0402_16V4Z
0.47U_0603_16V7K
33 AMP_RIGHT
INTSPK_L1 INTSPK_R1 2
22 15 14 11 9 16 10 8
PVDD SHUTDOWN# PVDD SE/BTL# VDD PC-BEEP BYPASS PC-ENABLE LOUTVOLUME ROUTLOUT+ LIN ROUT+ RIN LLINEIN RLINEIN GND LHPIN GND RHPIN GND GND CLK
2 3 4 21 5 23 6 20
1
2 NBA_PLUG VOL_AMP AMP_LEFT C826 1 0.47U_0603_16V7K AMP_RIGHT C837 1 0.47U_0603_16V7K
4
Right Speaker Connector R449 10K_0402_5%
0.47U_0603_16V7K
7 18 19
33 AMP_LEFT
1 2 ACES_85204-0200
S
R433 100K_0402_5%
U31
40 VOL_AMP
L57
JP12
2
2
0.1U_0402_16V4Z
FBM-11-160808-121-T_0603 1 2 1 2 FBM-11-160808-121-T_0603
3
C831 4.7U_0805_10V4Z
INTSPK_L1 INTSPK_L2
EAPD 33
2
1
L58
D C830
4
D67 @V-PORT-0603-220 M-V05_0603
Q34 2N7002_SOT23 2
2
SHUTDOWN# W=40Mil
D68 @V-PORT-0603-220 M-V05_0603
1
R701 100K_0402_5% +5VAMP
1
1
Audio Amplifier
E
C822
3
2
330P_0402_50V7K
FOXCONN JA6033L-5S1-TR
2
330P_0402_50V7K
fo=1/(2*3.14*R*C)=225Hz R=1.5K / C=0.47U
3 6 2 1
HEADPHONE OUT JACK EC Beep
System Beep To AC97' Codec
JP31 5
39 BEEP#
1
+3V POWER
1
C847 150U_D2_6.3VM
2 R629 560_0402_5%
3 6 2 1
C502 330P_0402_50V7K
C503 FOXCONN JA6033L-5S1-TR 330P_0402_50V7K 2
1
4
R352 10K_0402_5%
MICROPHONE IN JACK
2
2
2INTSPK_L1-2
+AVDD_AC97
C733 1U_0603_10V4Z
+3V POWER C728 0.22U_0603_16V4Z
1
2
P I
C189 0.1U_0402_16V4Z U45A SN74LVC14APWLE_TSSOP14 2 1 2 O
7
SN74LVC125APWLE_TSSOP14
14
2 8
O
R619 8.2K_0402_5% 1 2 1
INTSPK_L1
2
NBA_PLUG R450 33,40 NBA_PLUG 47_0402_5% L22 2 INTSPK_R1-3 1 2 INTSPK_R1-4 FBM-11-160808-700T_0603 1 2 INTSPK_L1-3 1 2 INTSPK_L1-4 R451 L21 47_0402_5% FBM-11-160808-700T_0603 1
1
I
1
G
9
U44C
OE#
10
R639 100K_0402_5%
C501 150U_D2_6.3VM 1 2INTSPK_R1-2
1
1
INTSPK_R1
+
+3V
+
+3V
1
2
2
1
R345 10K_0402_5% 2
C407 10U_1206_16V4Z
2
+5VAMP 1 1
29 PCM_SPK#
1 Q23 3 MMBT3904_SOT23
2
C732 2
1
2
R706 @18K_0603_1% 1 2
MONO_IN 33
1U_0603_10V4Z
+5VAMP
R346 2.4K_0402_5%
1 Q56 3 @2SC2411K-CQ_SOT23
2
1 2 R703 @18K_0603_1% R711 @100K_0402_5%
C843 @1U_0603_10V4Z
1 R710
2 0_0402_5%
+AUD_VREF
1
PCI Beep
+3V
1
2
1
1U_0603_10V4Z
2 R626 560_0402_5%
MONO_IN
1
CardBus Beep
C385 2
R707 @2.2K_0402_5%
14 O +3V POWER 1U_0603_10V4Z
1
L53
2 R635 560_0402_5%
U45B SN74LVC14APWLE_TSSOP14
33 MIC
1
2
MIC-1
FBM-11-160808-700T_0603
C840
1
3 6 2 1
D31 220P_0402_50V7K
R633 10K_0402_5%
FOXCONN JA6033L-5S1-TR
2
CH751H-40_SC76
1
2
2
1
MIC
2
2 C740 2
1
7
1
1
P I
JP30
5 4
4
G
25 SPKR
3
R708 2.2K_0402_5%
Compal Electronics, Inc. Title
PROPRIETARY NOTE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
AMP & Audio Jack Size Document Number CustomLA-2101 Date:
Rev 0.1
Saturday, November 22, 2003
Sheet E
34
of
52
25 IDE_PDIOR# 25 IDE_PDCS3# 25 IDE_PDCS1# 25 IDE_PDDACK#
HDD CONNECTOR
+5VS C500 0.1U_0402_16V4Z U29B
IDE_PDD[0..15]
PIDE_RST# PD_D7 PD_D6 PD_D5 PD_D4 PD_D3 PD_D2 PD_D1 PD_D0
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43
PD_PDDREQ PD_PDIOW# PD_PDIOR# PD_PDIORDY PD_PDDACK# PD_IRQ14 PD_PDA1 PD_PDA0 PD_PDCS1# 39 PHDD_LED# +5VS
1 R444
+5VS
2 100K_0402_5%
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44
PD_D8 PD_D9 PD_D10 PD_D11 PD_D12 PD_D13 PD_D14 PD_D15
PCSEL 1 R446
25 INT_IRQ14
1 R437
1
I0 I1
U29A 4
33,39 EC_IDERST 3
O
2
25 PIDERST#
5
74HCT08PW_TSSOP14
I0 O
6 PIDE_RST#
I1
74HCT08PW_TSSOP14
R448
2 470_0402_5%
@0_0402_5%
** 1029: Change U4D to U76D
PD_PDA2 PD_PDCS3#
*
PCMRST# 39 U29C
+5VS
SB_PCI_RST#
ALLTOP_C17826-14401 INT_IRQ14
SB_PCI_RST#
24 SB_PCI_RST#
P
JP10
G
14
25 IDE_PDD[0..15]
9
I0 O
10
25 SIDERST#
I1
** 1028: Remove R825
1 2 R445 8.2K_0402_5%
8
12
I
U28D O
11
SIDE_RST#
*27
74HCT08PW_TSSOP14
2 PD_IRQ14 33_0402_5%
13
25 IDE_PDDREQ 25 IDE_PDA2 25 IDE_PDA1 25 IDE_PDA0
PD_D8 PD_D7 PD_D6 PD_D5 33_0804_8P4R_5% PD_D10 8 PD_D4 7 PD_D9 6 PD_D12 5 33_0804_8P4R_5% PD_D2 8 PD_D3 7 PD_D11 6 PD_D0 5 33_0804_8P4R_5% PD_D14 8 PD_D1 7 PD_PDIOW# 6 PD_D13 5 33_0804_8P4R_5% PD_PDDREQ 8 PD_PDA2 7 PD_PDA1 6 PD_PDA0 5 33_0804_8P4R_5% PD_PDIOR# 2 33_0402_5% PD_D15 8 PD_PDCS3# 7 PD_PDCS1# 6 PD_PDDACK# 5 33_0804_8P4R_5% 8 7 6 5
OE#
25 IDE_PDIOW#
1 2 3 4 RP67 IDE_PDD10 1 IDE_PDD4 2 IDE_PDD9 3 IDE_PDD12 4 RP66 IDE_PDD2 1 IDE_PDD3 2 IDE_PDD11 3 IDE_PDD0 4 RP65 IDE_PDD14 1 IDE_PDD1 2 IDE_PDIOW# 3 IDE_PDD13 4 RP64 IDE_PDDREQ 1 IDE_PDA2 2 IDE_PDA1 3 IDE_PDA0 4 RP63 IDE_PDIOR# 1 R690 IDE_PDD15 1 IDE_PDCS3# 2 IDE_PDCS1# 3 IDE_PDDACK# 4 RP62
7
IDE_PDD8 IDE_PDD7 IDE_PDD6 IDE_PDD5
SN74LVC125APWLE_TSSOP14
R434
R427 10K_0402_5%
10K_0402_5% +5VCD
IDE_SDD[0..15]
Short when not support SWDJ JP28
25 IDE_SDIOR#
25 INT_IRQ15
INT_IRQ15
1 R406
8 7 6 5 8 7 6 5 2 8 7 6 5
39 SHDD_LED# 1 2 SHDD_LED# R409 100K_0402_5%
+5VCD
+5VCD
U27 8 7 6 5
2
C480 10U_1206_16V4Z
C479 0.1U_0402_16V4Z
SI4835DY_SO8 1 R442
+5VALWP
2 240K_0402_5% C490
+5VCD
@10K_0402_5% R398
1
R443
2
10K_0402_5%
1U_0805_16V7K +5VCD 1 2 C477 0.1U_0402_10V6K
+5VCD
SUSP#
33,39,40,43 SUSP#
2
22K
22K
22K Q33 @DTC124EK_SOT23
ALLTOP_C12424-25001
R410
1
1 2 3
+5VALWP
1
@10K_0402_5%
SD_SDDACK# R397 100K_0402_5% 1 2 SD_SDA2 SW_IDE_SDCS3#
+5VCD
1
SD_SDIOW# SD_SDIORDY SD_IRQ15 SD_SDA1 SD_SDA0 SW_IDE_SDCS1# SHDD_LED#
SD_D8 SD_D9 SD_D10 SD_D11 SD_D12 SD_D13 SD_D14 SD_D15 SD_SDDREQ SD_SDIOR#
PJP15 PAD-OPEN 4x4m 1 2
4
R400
+5VS
2
CD_PLAY
CD_PLAY 33,39
22K
3
25 IDE_SDA2
8 7 6 5
Net width should be 60mil wide INT_CD_R 33
Q35 DTC124EK_SOT23
470_0402_5%
+5VS
2 SD_IRQ15 33_0402_5%
Placea caps. near HDD CONN.
G_PCI_RST#
1 2 R412 8.2K_0402_5%
+5VCD
*
+3VALW
1
C494
0.1U_0402_16V4Z C489 14 SD_SDCS1#
+3VALW
2 7
10K_0402_5% R436
P I
OE#
1
1000P_0402_50V7K
3
+5VCD
4
2N7002_SOT23 Q32 SD_SDCS3#
5
3
S
0.1U_0402_16V4Z
+5VALWP
1
2
C473 4.7U_0805_10V4Z
1
2
C471 C474 1U_0805_16V7K
2
C472 4.7U_0805_10V4Z
1
2 C482 10U_1206_16V4Z
1
C486 1U_0805_16V7K
0.1U_0402_16V4Z
I
OE#
1
G_PCI_RST#
D
2 G
C493 C495 1U_0805_16V7K
W=80mils
C470 1000P_0402_50V7K
SB_PCI_RST#
2
+5VCD
GSN74LVC125APWLE_TSSOP14
** 1029: Change U4D to U76D
G_PCI_RST#
2
1 C496 10U_1206_16V4Z
10K_0402_5% R435 SW_IDE_SDCS1#
U28A O
2
1 C497 10U_1206_16V4Z
1
25 IDE_SDA1 25 IDE_SDDREQ
8 7 6 5
SD_D7 SD_D8 SD_D5 SD_D10 33_0804_8P4R_5% SD_D9 SD_D12 SD_D3 SD_D14 33_0804_8P4R_5% SD_SDCS1# SD_SDCS3# SD_SDA0 SD_SDDACK# 33_0804_8P4R_5% SD_SDIOW# SD_D1 SD_SDA1 SD_SDDREQ 33_0804_8P4R_5% SD_SDA2 SD_D15 SD_D13 SD_SDIOR# 33_0804_8P4R_5% SD_D11 33_0402_5% SD_D0 SD_D2 SD_D4 SD_D6 33_0804_8P4R_5%
INT_CD_R
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
2
25 IDE_SDIOW#
8 7 6 5
2
25 IDE_SDCS1# 25 IDE_SDCS3# 25 IDE_SDA0 25 IDE_SDDACK#
1 2 3 4 RP46 IDE_SDD9 1 IDE_SDD12 2 IDE_SDD3 3 IDE_SDD14 4 RP45 IDE_SDCS1# 1 IDE_SDCS3# 2 IDE_SDA0 3 IDE_SDDACK# 4 RP44 IDE_SDIOW# 1 IDE_SDD1 2 IDE_SDA1 3 IDE_SDDREQ 4 RP54 IDE_SDA2 1 IDE_SDD15 2 IDE_SDD13 3 IDE_SDIOR# 4 RP53 IDE_SDD11 1 R394 IDE_SDD0 1 IDE_SDD2 2 IDE_SDD4 3 IDE_SDD6 4 RP52
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
1
IDE_SDD7 IDE_SDD8 IDE_SDD5 IDE_SDD10
INT_CD_L CD_AGND SIDE_RST# SD_D7 SD_D6 SD_D5 SD_D4 SD_D3 SD_D2 SD_D1 SD_D0
33 INT_CD_L 33 CD_AGND
3
25 IDE_SDD[0..15]
10K_0402_5% R430 SW_IDE_SDCS3#
U28B O
6
Place component's closely MODULE CONNECTOR.
SN74LVC125APWLE_TSSOP14
+3VS 2
2
+3VS
2
33_0402_5%
1 R440 1 R439
R405 4.7K_0402_5%
PD_PDIORDY
PD_D7 2 10K_0402_1% PD_PDDREQ 2 5.6K_0402_5%
25 IDE_SDIORDY
1 R404
2
1
25 IDE_PDIORDY
1 R438
1
R447 4.7K_0402_5%
SD_SDIORDY
33_0402_5%
1 R411
2 10K_0402_1%
SD_D7
1 R399
2 5.6K_0402_5%
SD_SDDREQ
Compal Electronics, Inc. Title
IDE/ FDD MODULE CONN. Size C
Document Number
Date:
Saturday, November 22, 2003
Rev 0.1
LA-2101 Sheet
35
of
52
A
B
C
D
E
SUPER I/O SMsC FDC47N217 * LPC_AD[0..3]
1 1K_0402_5% 1 10K_0402_5% 1 10K_0402_5% 1 10K_0402_5%
SIO_GPIO11 SIO_SMI# SIO_IRQ SIO_GPIO23
VTR VCC VCC VCC VCC
7 11 26 45 54
SERIAL I/F
LPD0 LPD1 LPD2 LPD3 LPD4 LPD5 LPD6 LPD7 LPTSLCT LPTPE LPTBUSY LPTACK# LPTERR# LPTAFD# LPTSTB#
CLOCK
23 24 25 27 28 29 30 31 32 33 34 35 36 40
GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 GPIO10 GPIO11/SYSOPT GPIO12/IO_SMI# GPIO13/IRQIN1 GPIO14/IRQIN2 GPIO23
8 22 43 52
VSS VSS VSS VSS
POWER
LPC47N217_STQFP64
LPD[0..7]
LPD[0..7]
1
C192
2
R178 10K_0402_5%
38
@96212-1011S
CLK_PCI_SIO LPTSLCT 38 LPTPE 38 LPTBUSY 38 LPTACK# 38 LPTERR# 38 LPTAFD# 38 LPTSTB# 38
C153 0.1U_0402_16V4Z
C191 0.1U_0402_16V4Z
CLK_14M_SIO R214 @33_0402_5%
R241 @10_0402_5%
1 C208 @22P_0402_25V8K
+3VS
4.7U_0805_10V4Z
C250 0.1U_0402_16V4Z
C270 @15P_0402_50V8J
2
2
10P_0402_50V8K PTALIN 2 1
C786 1
IRRX
INIT# 38 SLCTIN# 38
2
R181 2 R180 2 2 R179 2 R177
41 42 44 46 47 48 49 50 51 53 55 56 57 58 59 60 61
1 2 3 4 5 6 7 8 9 10
11
2 10K_0402_5%
CLK14
INIT# SLCTIN# PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 SLCT PE BUSY ACK# ERROR# ALF# STROBE#
IRRX 37 IRTXOUT 37 IRMODE 37
2
1 R194
9
IRRX IRTXOUT IRMODE
1 2 3 4 5 6 7 8 9 10
RXD1 TXD1 DSR#1 RTS#1 CTS#1 DTR#1 RI#1 DCD#1
2
+3VS
2
2
CLK_14M_SIO 4.7K_8P4R_1206_5% PID0 PID1 PID2 PID3 FIR_EN# BTDET#
37 38 39
JP18
1
+3VS
R198 1 10K_0402_5%
4 3 2 1
IRRX2 IRTX2 IRMODE/IRRX3
FIR
1 2 3 4
1
+3VS 37 FIR_EN#
RP15 5 6 7 8
CLKRUN# PCI_CLK SER_IRQ IO_PME#
8 7 6 5
2
+3VS
19 20 21 6
1
+5V
4.7K_8P4R_1206_5%
1
16 CLK_14M_SIO
PCI_RESET# LPCPD#
PM_CLKRUN# CLK_PCI_SIO SERIRQ SIO_PME#
+3VS RP19 DSR#1 CTS#1 RI#1 DCD#1
2
1 10K_0402_5%
SIO_PD#
17 18
2 1K_0402_5%
1
R229 2
+3VS
LFRAME# LDRQ#
1 R212
2
24,29,39 SERIRQ
15 16
62 63 64 1 2 3 4 5
1
PCIRST# 2 10K_0402_5%
24,28,29,31,32,39 PM_CLKRUN# 24 CLK_PCI_SIO
LPC_FRAME# LPC_DRQ#1
RXD1 TXD1 DSR#1 RTS#1 CTS#1 DTR#1 RI#1 DCD#1
RXD1 TXD1 DSR1# RTS1# CTS1# DTR1# RI1# DCD1#
2
23,24,28,29,31,32,39 1 +3VS R218
LAD0 LAD1 LAD2 LAD3
PARALLEL I/F
24,39 LPC_FRAME# 24 LPC_DRQ1#
10 12 13 14
LPC I/F
U12 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
GPIO
24,39 LPC_AD[0..3] 1
3
2
X1
24.576MHz
10
3
X2
VDD GND
9 11
7
REF1
8 5
VDD GND
CLK1 CLK2
16 18
VDD VDD GND
15 19 17
2
14.31818MHZ_20P 1 C787 16 SYS_XCLK
2 R660
PTALOUT 10P_0402_50V8K
1 10_0402_5%
+3V_CLK 17 EXT_SSIN
2
2 R661
+3V_CLK
2 1 0.1U_0402_16V4Z C751 @1K_0402_5% 2 1 R665 1K_0402_5% 2 R659 1 PCLK_SSOUT PCLK_SSIN 1 10_0402_5% 5,39 EC_SMB_CK2 5,39 EC_SMB_DA2
3
U48
X6
6 4 13
INPUT_SEL/REF0 CLKIN CLK0
CLK3
21
2
1 C757 0.1U_0402_16V4Z
2
C782 0.1U_0402_16V4Z
27 26
SCLK SDATA
VDD GND
20 22
28 14 1 12
AVDD VDD GND GND
CLK4
24
VDD GND
25 23
@ICS960011
1 C754
1
AC97_XCLK 33
+3V_CLK 2 0.1U_0402_16V4Z
2
+3V_CLK
C753 0.1U_0402_16V4Z VGA_PCLK
*27
1
2
2
R650 2 R643
+3V_CLK
1
R666 10_0402_5% 2 1
1 PCLK_SSOUT 10_0402_5% 1 10_0402_5%
VGA_XCLK 17
+3V_CLK
C788 0.1U_0402_16V4Z 2 1 1394_XCLK 32 R648 10_0402_5% 1
2
+3V_CLK
C752 0.1U_0402_16V4Z
4
4
Compal Electronics, Inc. Title
SUPER I/O PROPRIETARY NOTE
A
B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C
D
Size Custom
Document Number
Date:
Saturday, November 22, 2003
Rev 0.1
LA-2101 Sheet E
36
of
52
1
+USB_AS
+3V
+
C539
2
+USB_BS
150U_D2_6.3VM
C536
R491
100K_0402_5%
100K_0402_5%
0.1U_0402_16V4Z D9
USB_OC4# 24
USBP2-
25 USBP2-
USBP2+
25 USBP2+
0.1U_0402_16V4Z
1
2
C562
C563
2
3
1
USB2USB2+ 4 @JTS0402-03_4P
Keep 20 mils minimum spacing
0.1U_0402_16V4Z 2
2
0.1U_0402_16V4Z
25 USBP425 USBP4+
@V-PORT-0603-220 M-V05_0603 JP16
2
@V-PORT-0603-220 M-V05_0603 2
L32 USB_OC4#
1 2 3 4 5 6 7 8
L33
USBP4-
2
3
USB4-
USBP4+
1
4
USB4+
SUYIN_2553A-08G1T-D_8P @JTS0402-03_4P D6
1
TPS2042ADR_SO8
USB_OC2# 25
1
OC1# OUT1 OUT2 OC2#
USB CONNECTOR USB_OC2#
1 2 R489 47_0402_5% 1 2 R493 47_0402_5%
2
C538 @150U_D2_6.3VM
C540
GND IN EN1# EN2#
8 7 6 5
1
1
1 +
2
U33 1 2 3 4
D8
2
+5V
1
R490
1
1
1
+USB_AS
2
@V-PORT-0603-220 M-V05_0603 2
@V-PORT-0603-220 M-V05_0603
D7
1
+USB_BS
+3V
+
C541
2
+USB_CS
150U_D2_6.3VM
C532
1
0.1U_0402_16V4Z +5V U53
0.1U_0402_16V4Z
TPS2041ADR_SO8
USB_OC0#
USB_OC0# 25
C839
1
2
+USB_CS 1 2 R705 47_0402_5%
0.1U_0402_16V4Z
+
C846
C845 0.1U_0402_16V4Z
2
C504 @150U_D2_6.3VM
C842
100K_0402_5%
8 7 6 5
2
+
R704 OUT OUT OUT OC#
1
1
1
GND IN IN EN#
2
1 2 3 4
150U_D2_6.3VM 2
USB CONNECTOR
L56 25 USBP025 USBP0+
JP32
USBP0-
2
3
USB0-
USBP0+
1
4
USB0+
1 2 3 4
@JTS0402-03_4P
C487
@V-PORT-0603-220 M-V05_0603
22U_1206_10V4Z
D66
@V-PORT-0603-220 M-V05_0603 2
C483
6
2
1
2
2
+3VS
D65
1 2 R428 3.3_1206_5%
5
TYCO_3-1470859-1 1
1 2 R699 @3.3_1206_5%
FIR Module 1
+IR_ANODE
1
+3VS
VBUS S_GND DD+ GND S_GND
R700 4.7U_0805_10V4Z 2
1
36 IRRX
+IR_VCC C834 220P_0402_50V7K 2
2
IRRX
1
1
USB4-
U52 47_1206_5% 2 4 6 8
IRED_C RXD VCC GND
IRED_A TXD SD/MODE MODE
1 3 5 7
+IR_ANODE IRTXOUT IRMODE
IRTXOUT 36 IRMODE 36
C24
USB2C26
USB0USBP0-
C844
@0.1U_0402_16V4Z
USBP0+
@0.1U_0402_16V4Z
2
1
2
USBP2USB4+
USB2+
USB0+
1
2
1
2
1
2
C841
USBP4+
1
2
36 FIR_EN#
1 R205
2 0_0402_5%
@0.1U_0402_16V4Z
USB40_0402_5%
R483 @0.1U_0402_16V4Z
USB2+ 0_0402_5%
R482 C25
USB20_0402_5%
R481 USBP4-
C23
USB0+ 0_0402_5%
R480 USBP2+
USB00_0402_5%
R709
TFDU6102-TR3_8P
C832 0.1U_0402_16V4Z +IR_GND
1 R712
@0.1U_0402_16V4Z
USB4+ 0_0402_5%
@0.1U_0402_16V4Z
The component's most place cloely IRDA MODULE.
FIR_EN# LOW FIR Poped HIGH FIR Un-Poped
Compal Electronics, Inc. Title
USB Conn. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D CustomLA-2101 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Saturday, November 22, 2003
Rev 0.1 Sheet
37
of
52
FD5 FIDUCAL
FD6 FIDUCAL
FD4 FIDUCAL
FD1 FIDUCAL
FD3 FIDUCAL
FD2 FIDUCAL
MDC CONN.
2 CHB1608B121_0603
2 R517
1 10K_0402_5%
2 0_0402_5%
1 R531
2 22_0402_5%
ICH_AC_SDIN1
1
1
1
1
1
1
1
1
1
CF22 SMD40M80
CF9 SMD40M80
25
ICH_AC_BITCLK
25,33 1
2 22_0402_5%
2 220P_0402_50V7K
C665
CF7 SMD40M80
CF8 SMD40M80
CF20 SMD40M80
CF23 SMD40M80
@15P_0402_50V8J
1 CF16 SMD40M80
CF15 SMD40M80
1
CF19 SMD40M80
CF12 SMD40M80
CF17 SMD40M80
1
CF10 SMD40M80
1
CF11 SMD40M80
1
CF13 SMD40M80
CF21 SMD40M80
1
CF5 SMD40M80
1
CF4 SMD40M80
1
CF2 SMD40M80
1
1
C604 1U_0805_16V7K
2
1
1 C649 1U_0805_16V7K
1
2
C614 25,27,33
1
2
+3VS
+5VS_MDC
1 C625 1U_0805_16V7K
+5VS
ICH_AC_SYNC 1 R525
2 +3VS_MDC
CF24 SMD40M80
1
1 R521 2 22_0402_5% 1 R524
1
1
CF6 SMD40M80
1
AMP 3-1565120-0 30P H:9MM
+3V_MDC
CF3 SMD40M80
1
25,33 ICH_AC_RST#
1 L37
CF14 SMD40M80
1
25,27,33 ICH_AC_SDOUT
+5VS_MDC
CF1 SMD40M80
1
+3V_MDC 0_0402_5% 2 +3VS_MDC L39 CHB1608B121_0603 1 R541 2 22_0402_5% 1 R546 2 22_0402_5%
R519 1
CF18 SMD40M80
MD_SPK 33
1
+3VS
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
1
+3V
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
1
JP20
PARALLEL PORT +5V_PRN RP55
R1 33_0402_5% 1 2
LPTSTB#
C1
36 LPTAFD# 36 LPTERR#
1 R7
FD0 LPTERR# FD1 LPTINIT# FD2 LPTSLCTIN# FD3 FD4 FD5 FD6 FD7
36 LPTACK# 36 LPTBUSY 36 LPTPE 36 LPTSLCT
LPTACK# LPTBUSY LPTPE LPTSLCT
1
LPD7 LPD6 LPD5 LPD4
1 2 3 4
8 7 6 5
FD7 FD6 FD5 FD4
+5V_PRN
2 FD4 FD5 FD6 FD7
RP1 2.7K_10P8R_1206_5%
LPTACK# LPTBUSY LPTPE LPTSLCT
FD3 FD2 FD1 FD0
1 2 3 4
8 7 6 5
@220P_1206_8P4C_50V8K CP1 1 8 2 7 3 6 4 5
LPTSLCT LPTPE LPTBUSY LPTACK#
@220P_1206_8P4C_50V8K CP3 1 8 2 7 3 6 4 5
FD1 LPTERR# FD0 AFD#/3M# RP2 2.7K_10P8R_1206_5% FD4 FD5 FD6 FD7
+5V_PRN JP13 SUYIN_7843S-25G2T-01
CP2 FD3 LPTSLCTIN# FD2 LPTINIT#
RP56 68_8P4R_1206_5%
+5V_PRN
220P_0402_50V7K 1 2 14 33_0402_5% 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13
FD0 FD1 FD2 FD3
68_8P4R_1206_5%
R2 2.2K_0402_5%
AFD#/3M#
8 7 6 5
10 9 8 7 6
RB420D_SOT23
LPD[0..7] 36 LPTSTB#
1
@220P_1206_8P4C_50V8K CP4 1 8 2 7 3 6 4 5
1 2 3 4 5
2
1
LPTSLCTIN# 2 33_0402_5%
+5VS
1 2 3 4
10 9 8 7 6
36 LPD[0..7]
1 R9
LPD0 LPD1 LPD2 LPD3
D1
1 2 3 4 5
36 SLCTIN#
LPTINIT# 2 33_0402_5%
2
36 INIT#
1 R8
+5V_PRN
@220P_1206_8P4C_50V8K
LPTSLCTIN# LPTINIT# LPTERR# AFD#/3M#
Compal Electronics, Inc. Title
PARALLEL/MDC PORT THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Document Number
Rev 0.1
LA-2101 Saturday, November 22, 2003
Sheet
38
of
52
5
4
3
2
+3VALW
+RTCVCC
+51VDD +3VALW
+3VALW
1
1
1 D
C369
2
24,29,36 SERIRQ
L19 FBM-L11-160808-800LMT_0603
C453
24,36 24,36 24,36 24,36 24,36
0.1U_0402_16V4Z 2
2
0.1U_0402_16V4Z
ECAGND
LPC_FRAME# LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
24 CLK_PCI_LPC
2 R220
1
+3VALW
R630 @33_0402_5%
2 @1K_0402_5%
1 R631
2 1K_0402_5%
1 R632
C738 @22P_0402_25V8K VGA_SELECT
1 R678
2 @1K_0402_5%
1 R677
5 6
25 GATEA20 25 KBRST# 40 KSI0 40 KSI1 40 KSI2 40 KSI3 41 TV_OUT_EN#
SIO_SELECT
(Pin 114)
HIGH: With SIO(Default) C
Low: Without SIO
2
+3VALW
28,29,31,32 WLANPME#
28,29,31,32 1394_PME#
KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7
KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15
49 50 51 52 53 56 57 58 59 60 61 64 65 66 67 68
KBSOUT0 KBSOUT1 KBSOUT2 KBSOUT3 KBSOUT4 KBSOUT5 KBSOUT6 KBSOUT7 KBSOUT8 KBSOUT9 KBSOUT10 KBSOUT11 KBSOUT12 KBSOUT13 KBSOUT14 KBSOUT15
PORTB
161
153 154 162 163 164 165
EC_URXD EC_UTXD EC_USCLK EC_SMB_CK1 EC_SMB_DA1
IOPC0 IOPC1/SCL2 IOPC2/SDA2 IOPC3/TA1 IOPC4/TB1/EXWINT22 IOPC5/TA2 IOPC6/TB2/EXWINT23 IOPC7/CLKOUT
168 169 170 171 172 175 176 1
PBTN_OUT# EC_SMB_CK2 EC_SMB_DA2 FAN_SPEED1 EC_PME# EC_THRM# FAN_SPEED2 ACIN CD_PLAY PM_SLP_S3#
26 29 30
PORTE
IOPE4/SWIN IOPE5/EXWINT40 IOPE6/LPCPD/EXWIN45 IOPE7/CLKRUN/EXWINT46
2 44 24 25
PSCLK1/IOPF0 PSDAT1/IOPF1 PSCLK2/IOPF2 PSDAT2/IOPF3 PSCLK3/IOPF4 PSDAT3/IOPF5 PSCLK4/IOPF6 PSDAT4/IOPF7
PS2 interface
CRY1
158
32KX1/32KCLKIN
CRY2
160
32KX2
PORTH
8 7 6 5
MODE# FRD# SELIO# FSEL#
KBA0 KBA1 KBA2 KBA3 KBA4 KBA5 KBA6 KBA7
IOPI0/D0 IOPI1/D1 IOPI2/D2 IOPI3/D3 IOPI4/D4 IOPI5/D5 IOPI6/D6 IOPI7/D7
138 139 140 141 144 145 146 147
ADB0 ADB1 ADB2 ADB3 ADB4 ADB5 ADB6 ADB7
IOPJ0/RD IOPJ1/WR0
150 151
FRD# FWR#
SELIO#
152
SELIO#
IOPD4 IOPD5 IOPD6 IOPD7
41 42 54 55
NUM_LED# CAPS_LED# PADS_LED#
IOPK0/A8 IOPK1/A9 IOPK2/A10 IOPK3/A11 IOPK4/A12 IOPK5/A13_BE0 IOPK6/A14_BE1 IOPK7/A15_CBRD
143 142 135 134 130 129 121 120
KBA8 KBA9 KBA10 KBA11 KBA12 KBA13 KBA14 KBA15
IOPL0/A16 IOPL1/A17 IOPL2/A18 IOPL3/A19 IOPL4/WR1#
113 112 104 103 48
KBA16 KBA17 KBA18 KBA19 FSTCHG
10K_0804_8P4R_5% PORTJ-1 +5VALW RP59
R675 100K_0402_5%
120K_0402_5%
40 FSEL#
ENBKL BKOFF# FSEL#
R286 1
173 174 47
SEL0# SEL1# CLK
2 ENBKL
C335 120K_0402_5%
2
10P_0402_50V8K
X2
PORTK PORTM
PORTL
C218 1 ECAGND PROPRIETARY NOTE
32.768KHZ_12.5P_1TJS125DJ2A073 5
IOPM0/D8 IOPM1/D9 IOPM2/D10 IOPM3/D11 IOPM4/D12 IOPM5/D13 IOPM6/D14 IOPM7/D15
R216 1
1
4 NC
1 IN
OUT
NC
3
10P_0402_50V8K 2
2
C345 0.1U_0402_16V4Z
1
Rb
0_0402_5%
R668
2
C791
1
1
1
AD_BID0
2
A
2 CRY2 2
2
CRY1 1 R289 20M_0603_5%
148 149 155 156 3 4 27 28
PORTD-2 PORTJ-2
4
2 100K_0402_5% 1 2 C415 0.22U_0603_16V4Z
ALI/MH# 45 EMAIL# 41 MODE# 40 INTERNET# 41
1 L20
ADP_I 45,46
DAC_BRIG 23 EN_DFAN2 42 IREF 46 EN_DFAN1 42
1 2 3 4 5 6 7 8 9 10
KEYBOARD CONN.
INVT_PWM 23 BEEP# 34 PWR_SUSP_LED# ACOFF 46 KILL_SW# 31,41 EC_ON 41 EC_LID_OUT# 25
(ACES_85201-2405_24P) 40,41
JP9
+3VALW
EC_TINIT# EC_TCK EC_TDO EC_TDI EC_TMS EC_URXD EC_UTXD EC_USCLK
EC_SMB_CK1 40,45 EC_SMB_DA1 40,45 PCIRST# 23,24,28,29,31,32,36 PBTN_OUT# 25 EC_SMB_CK2 5,36 EC_SMB_DA2 5,36 FAN_SPEED1 42 EC_THRM# 25 FAN_SPEED2 42 ACIN 25,40,44 CD_PLAY 33,35 PM_SLP_S3# 25 ON/OFF 41 PM_SLP_S5# 25
PM_CLKRUN# 24,28,29,31,32,36
** 1028
NUM_LED# PADS_LED# CAPS_LED#
KSO15 NUM_LED# KSO14 PADS_LED# KSO10 CAPS_LED# KSO11 1 2 300_0402_5% +3VS KSO15 R403 KSO14 KSO8 KSO10 KSO9 KSO11 KSO13 KSO8 KSI7 KSO9 KSO13 KSI7 KSO3 KSO3 KSO7 KSO7 KSO12 KSO12 KSI4 KSI4 KSI6 KSI6 KSI5 KSO6 KSI5 KSO5 KSO6 KSI3 KSO5 KSI0 KSO0 KSI3 KSO1 KSI0 KSI1 KSI2 KSO0 KSO1 KSO2 KSO4 1 2 +3VSKSI1 R402 300_0402_5% KSI2 KSO2 KSO4 1 2 +3VS 300_0402_5% R401
34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
D
CP9 1 2 3 4
100P_1206_8P4C_50V8 8 7 6 5
CP10 1 2 3 4
100P_1206_8P4C_50V8 8 7 6 5
CP11 1 2 3 4
100P_1206_8P4C_50V8 8 7 6 5
CP8 1 2 3 4
100P_1206_8P4C_50V8 8 7 C 6 5
CP5 1 2 3 4
100P_1206_8P4C_50V8 8 7 6 5
CP6 1 2 3 4
100P_1206_8P4C_50V8 8 7 6 5
CP7 1 2 3 4
100P_1206_8P4C_50V8 8 7 6 5
6278-34P-KBCON
(Need to check layout library with KB spec) I/O Address B
BADDR1(KBA3) BADDR0(KBA2) FRD# 40 FWR# 40
*
SELIO# 40
Data
0
2E
2F
0
1
4E
4F
1
0
1
PHDD_LED# 35
Index
0
(HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1
1
Reserved
ENV0 (KBA0) IRE * OBD DEV PROG
0 0 1 1
ENV1 (KBA1)
TRIS (KBA4)
0 1 0 1
0 0 0 0
SHBM(KBA5)=1: Enable shared memory with host BIOS TRIS(KBA4)=1: While in IRE and OBD, float all the signals for clip-on ISE use +3VALW +5VS TP_CLK
1 R667 TP_DATA 1 R662
FSTCHG 46
2 4.7K_0402_5% 2 4.7K_0402_5%
KBA1 KBA2 KBA3 KBA5
1 R683 1 R682 1 R681 1 R680
2 1K_0402_5% 2 @1K_0402_5% 2 1K_0402_5% 2 1K_0402_5%
PC87591L-VPCN01 A2_LQFP176 @1U_0603_10V4Z 2
Compal Electronics, Inc.
2 FBM-L11-160808-800LMT_060 3
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3
1 2 3 4 5 6 7 8 9 10
@96212-1011S
NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10
+3VALW
SYSON SUSP# VR_ON
IOPJ2/BST0 IOPJ3/BST1 IOPJ4/BST2 IOPJ5/PFS IOPJ6/PLI IOPJ7/BRKL_RSTO
AGND
42,43 SYSON 33,35,40,43 SUSP# 50 VR_ON 35 PCMRST# 25 EC_RSMRST# 35 SHDD_LED# 9,17 ENBKL 23 BKOFF#
Analog Board ID definition, Please see page 3.
62 63 69 70 75 76
11 12 20 21 85 86 91 92 97 98
10K_0804_8P4R_5%
Ra
EC_SMI#
25 EC_SMI# 42 S4_SATA 31 WL_OFF# 25 EC_SWI# 42 S4_LATCH
96
EC_SMB_DA2 EC_SMB_CK2 EC_SMB_DA1 EC_SMB_CK1
GND1 GND2 GND3 GND4 GND5 GND6 GND7
1 2 3 4
17 35 46 122 159 167 137
8 7 6 5
1 R351
1 R219 2 10K_0402_5%
124 125 126 127 128 131 132 133
PORTI
BATT_TEMPA 45 BATT_OVP 46
PM_SLP_S5#
IOPH0/A0/ENV0 IOPH1/A1/ENV1 IOPH2/A2/BADDR0 IOPH3/A3/BADDR1 IOPH4/A4/TRIS IOPH5/A5/SHBM IOPH6/A6 IOPH7/A7
RP51 1 2 3 4
DAC_BRIG EN_DFAN2# IREF EN_DFAN1#
IOPB0/URXD IOPB1/UTXD IOPB2/USCLK IOPB3/SCL1 IOPB4/SDA1 IOPB7/RING/PFAIL/RESET2
+3VALW B
99 100 101 102
IOPD0/RI1/EXWINT20 IOPD1/RI2/EXWINT21 IOPD2/EXWINT24/RESET2
110 111 114 115 116 117 118 119
TP_CLK TP_DATA LID_SW# HDD_LED#
BATT_OVP AD_BID0 ALI/MH# EMAIL# MODE# INTERNET#
PORTD-1
JTAG debug port
BATT_TEMP
81 82 83 84 87 88 89 90 93 94
INVT_PWM BEEP# PWR_SUSP_LED# ACOFF KILL_SW# EC_ON EC_LID_OUT# VGA_SELECT
PORTC
TINT# TCK TDO TDI TMS
SIO_SELECT
33,35 EC_IDERST 40 TP_CLK 40 TP_DATA 41 LID_SW# 41 HDD_LED#
BATT_TEMP
Key matrix scan
JP25
1U_0603_10V4Z
32 33 36 37 38 39 40 43
IOPA0/PWM0 IOPA1/PWM1 IOPA2/PWM2 IOPA3/PWM3 IOPA4/PWM4 IOPA5/PWM5 IOPA6/PWM6 IOPA7/PWM7
PWM or PORTA
105 106 107 108 109
EC_PME# 40,41 KSO17
1 C403
DA0 DA1 DA2 DA3
DA output
GA20/IOPB5 KBRST/IOPB6
71 72 73 74 77 78 79 80
EC_TINIT# EC_TCK EC_TDO EC_TDI EC_TMS
28,29,31,32 PCM_PME#
28,29,31,32 LAN_PME#
AD Input
IOPD3/ECSCI#
KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7
1
R645 10K_0402_5%
ECAGND 2 0.01U_0402_16V7Z
31
AD0 AD1 AD2 AD3 IOPE0AD4 IOPE1/AD5 IOPE2/AD6 IOPE3/AD7 DP/AD8 DN/AD9
Host interface
2
Low for M11P 2 1K_0402_5%
EC_SCI#
SERIRQ LDRQ# LFRAME# LAD0 LAD1 LAD2 LAD3 LCLK RESET1# SMI# PWUREQ#
2
1
High for M10C +3VALW
7 8 R634 @0_0402_5% 9 LPC_AD0 15 LPC_AD1 14 LPC_AD2 13 LPC_AD3 10 18 1 EC_RST# 19 4.7K_0402_5% 22 23
25 EC_SCI#
2 +3VALW
0.1U_0402_16V4Z U13
For EC Tools
KBA[0..19] ADB[0..7]
40 KBA[0..19] 40 ADB[0..7]
C365
VBAT
+51AVCC
1 95
1000P_0402_50V7K
R301 0_0603_5% 2 1
C228
VDD
+RTCVCC
1
1
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
2
2
C799 1000P_0402_50V7K
+51AVCC
AVCC
0_0402_5%
34 45 123 136 157 166
R217
VCC1 VCC2 VCC3 VCC4 VCC5 VCC6
+3VS
16
C743
1
C758
2
C765
2
C793
1
0.1U_0402_16V4Z
1
1
1
0.1U_0402_16V4Z C739
1
2
EC PC87591 Size Document Number Custom
Rev 0.1
LA-2101
Date:
Saturday, November 22, 2003
Sheet 1
39
of
52
A
+5VALW P
B
3
11 1
CLK OE
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
7
CDON_LED# MP3_LED# EMAIL_LED# PWR_LED#
2 5 6 9 12 15 16 19
PWR_LED# 41 WL_BT_LED# 41
BATT_LOW_LED # BATT_CHGI_LED#
ODD_LED# 41
SN74HCT374PW_TSSOP20
10
2
O
U19A SN74LVC32APWLE_TSSOP14
AA
1
14 39 SELIO#
A
P
1
SELIO#
1D 2D 3D 4D 5D 6D 7D 8D
G
KBA2
3 4 7 8 13 14 17 18
VCC
2 R344 100K_0402_5%
ADB0 ADB1 ADB2 ADB3 ADB4 ADB5 ADB6 ADB7
GND
U22
+3VALW
+3VALW
20
1 2 C458 0.1U_0402_16V4Z
TP_CLK
C451 1
+5VALW
2
1U_0603_10V4Z
2 220P_0402_50V7K 2 220P_0402_50V7K
VR/B FFC Connector Pin 1 Definition Swap with VR/B
FWR# 39
1
AT24C16AN-10SI-2.7_SO8
R195
1
2
1 C817 2
1
2
ACES_85201-1005 C815
C808
1
2
C816
1
2
1
2
2
2
220P_0402_50V7K
2
220P_0402_50V7K
2
+5VALWP 2 CDON_LED# MP3_LED# 1 1 C761 C755 1 2 +3VALW L47 1 FCM2012C-800_0805 1 C750 2 2 C747
C818
220P_0402_50V7K
C819
KSI2 39 KSI0 39
@120P_0402_50V8K
1 2 3 4
2
A0 A1 A2 GND
@120P_0402_50V8K
39,45 EC_SMB_CK1 39,45 EC_SMB_DA1
VCC WP SCL SDA
51ON# 41,44
EC_REVBTN# EC_PLAYBTN#
@120P_0402_50V8K
U11 8 7 6 5
2 4 6 8 10
@120P_0402_50V8K
100K_0402_5%
1 3 5 7 9
KSO17 EC_FRDBTN# EC_STOPBTN#
51ON#
@120P_0402_50V8K
39,41 KSO17 39 KSI3 39 KSI1
R191
@120P_0402_50V8K
1
C219 2 0.1U_0402_16V4Z
1
MODE#
220P_0402_50V7K
JP7 39 MODE#
220P_0402_50V7K
1
+5VALW +5VALW
1 1 1 1 1 C771 C774 C777 C766 C764
Direct CD button board
C803
220P_0402_50V7K
@120P_0402_50V8K 2
PWR_LED# PWR_SUSP_LED# ACIN BATT_LOW_LE D# BATT_CHGI_LED# EMAIL_LED#
39,41 PWR_SUSP_LED# 25,39,44 ACIN
7
Q22 2N7002_SOT23
TP_CLK TP_DATA
39 TP_CLK 39 TP_DATA
EC_FLASH# 25
S
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
+5VS
220P_0402_50V7K
3
D 5
2
B
1
JP5
SW Board Connector
SW/B and TP/B FFC Connector Pin 1 Definition Same As SW/B and TP/B
220P_0402_50V7K
SUSP# 33,35,39,43
2 G
1
R290 100K_0402_5%
14 P
A
4
G
6
U19B SN74LVC32APWLE_TSSOP14
1 C789
TP_DATA 1 C783
+3VALW
+3VALW
FWE#
1 2 R380 820K_0402_5%
ACES_85201-2005
2
220P_0402_50V7K
2 +5VS
2 C421 0.1U_0402_16V4Z
VR/CIR Board Connector
1
JP6
2
100K_0402_5%
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
* 33,34 NBA_PLUG
1 3 5 7 9
2 4 6 8 10
+5VALW P VOL_AMP
ACES_85201-1005
1MB Flash ROM
1
2
VOL_AMP 34 +5VAMP
C804
2
C316 0.1U_0402_16V4Z
1U_0603_10V4Z
1
KBA[0..19] ADB[0..7]
39 KBA[0..19] 39 ADB[0..7]
+3VALW U51 KBA0 KBA1 KBA2 KBA3 KBA4 KBA5 KBA6 KBA7 KBA8 KBA9 KBA10 KBA11 KBA12 KBA13 KBA14 KBA15 KBA16 KBA17 KBA18 KBA19
21 20 19 18 17 16 15 14 8 7 36 6 5 4 3 2 1 40 13 37
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
FSEL# FRD# FWE#
22 24 9
CE# OE# WE#
VCC0 VCC1
31 30
D0 D1 D2 D3 D4 D5 D6 D7
25 26 27 28 32 33 34 35
RP# NC READY/BUSY# NC0 NC1
10 11 12 29 38
GND0 GND1
23 39
SST39VF080-70_TSOP40
1 ADB0 ADB1 ADB2 ADB3 ADB4 ADB5 ADB6 ADB7
1 2 R691 @100K_0402_5%
2
1MB BIOS Connector
C820 0.1U_0402_16V4Z
JP8 KBA16 KBA15 KBA14 KBA13 KBA12 KBA11 KBA9 KBA8 FWE#
+3VALW KBA18 KBA7 KBA6 KBA5 KBA4 KBA3 KBA2 KBA1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
KBA17
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
KBA19 KBA10 ADB7 ADB6 ADB5 ADB4 1 ADB3 ADB2 ADB1 ADB0 FRD# FSEL# KBA0
2
+3VALW C465 @0.1U_0402_16V4Z
FRD# 39 FSEL# 39
@SUYIN-80065A-040G2T
Compal Electronics, Inc. Title
BIOS & EXT. I/O PORT THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D CustomLA-2101 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Saturday, November 22, 2003
Rev 0.1 Sheet
40
of
52
5
4
LID Switch
3
2
+3VALW
ODD LED
HDD LED
1
1
+5VALW P
R107
+5VALW P
2
D11
LID_SW#
39 LID_SW#
1
100K_0402_5% R170
R209 300_0402_5%
2 1 300_0402_5% SW1 D25 @V-PORT-0603-220 M-V05_0603
D
2
D10
22
CHN202U_SC70
*
1
1
3
42 S4_LID_SW# D
D29
FR2283_2P HT-191NB_BLUE_0603 1 D23
Power Button
*27
1
1
1
2
2
HT-191NB_BLUE_0603
HDD_LED#
39 HDD_LED#
ODD_LED#
40 ODD_LED#
ON/OFFBTN# 42
2
+3VALW
Wireless LED
+5VALW P
PSOT24C_SOT23
1 51ON#
2
0.01U_0402_16V7Z 300_0402_5%
51ON# 40,44
HCH SMT1-05
R227 300_0402_5% +3VALW
2
C
2
CHN202U_SC70
1
2
4
C269
ON/OFF 39
2 1
1
D38 D53
2
C659
DS-1200-02
2
1000P_0402_50V7K
RLZ20A
D34 HT-191NB_BLUE_0603
1
EC_ON
1 R529
2 2
22K B
33K_0603_1%
E
1
3
2
Q47 22K DTC124EK_SOT23 D 2N7002_SOT23 Q46
2
1
1
R549 100K_0402_5% KILL_SW# 31,39
2 1 SN74LVC125APWLE_TSSOP14
O
1
I
OE#
29 SDLED#
11
U44D
1 R211 2 +5VS 10K_0402_5%
@V-PORT-0603-220 M-V05_0603
SW6
D35
D56 1
WL_BT_LED#
40 WL_BT_LED# 39 EC_ON
D36
3
2
@V-PORT-0603-220 M-V05_0603 2
C
12
13
1
R547 4.7K_0402_5%
@V-PORT-0603-220 M-V05_0603
2 1
2
1
HT-191UD_AMBER_0603 +3VALW
3
1
R278 1
D58
3
3 C
Kill SWITCH
+5VS
R548 100K_0402_5%
SW 2
2
SD LED
2
D54
1
3
2
@V-PORT-0603-220 M-V05_0603
2
@V-PORT-0603-220 M-V05_0603
1
D30
2 G 3
S
Internet Button
Console/E-MAIL Button
B
1
B
POWER LED
TV OUT Button
+3VALW
51ON#
R173 2
1 100K_0402_5%
EMAIL#
R115 2
1 100K_0402_5%
INTERNET#
R108 +5VALW P
4
HCH SMT1-05
D24 1N4148_SOT23
KSI4
TV_OUT_EN# 39
D27
D15 SW4
1
3
2
4
D18 1
2
INTERNET# 39
1
3
2
4
@V-PORT-0603-220 M-V05_0603
D26 1
2
EMAIL# 39
1N4148_SOT23
2
2
@V-PORT-0603-220 M-V05_0603
3
HCH SMT1-05 3
D16
2
1
1
HCH SMT1-05 D13
2
1
1N4148_SOT23
2
1
SW 3 HT-191NB_BLUE_0603 HT-191UD_AMBER_0603
1
22
22
300_0402_5%
1
3
2
1
2
1
D12 1N4148_SOT23
300_0402_5% D14
KSO17
2
1
1
39,40 KSO17
D
NDS352P_SOT23 R522
1 2
G
2
R520
SW5
0_0603_5%
3
Q4
S
+5VALWP
D21 D17
PSOT24C_SOT23
PSOT24C_SOT23 A
PWR_SUSP_LED#
39,40 PWR_SUSP_LED#
PWR_LED#
A
PWR_LED# 40
@V-PORT-0603-220 M-V05_0603
Compal Electronics, Inc. Title
Switchs & Connectors THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D CustomLA-2101 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev 0.1
Saturday, November 22, 2003
Sheet 1
41
of
52
A
B
C
D
FAN CONN. 1
Battery mode Hibernation
C650 0.1U_0402_16V4Z 1 2
+5VALW
U38A LM358AMX
2
2 B
2
Q45
C664
R557
R559
R131
100K_0402_5%
680K_0402_5%
D20
C125 1
0.1U_0402_10V6K 2
ON/OFFBTN# 41
ACES_85205-0300
5
1
P
D
4
FAN CONN. 2 C646 0.1U_0402_16V4Z
+
6
-
EN_FAN2
1 2 R128 100_0402_5%
U38B LM358AMX
2
2 B
FMMT619_SOT23D57 2
Q7
C97
1
0.1U_0402_16V4Z
FAN2 1
D19
39 S4_LATCH RTCVREF
1 R165 10K_0402_5%
C89
1N4148_SOT23 2
2 8.2K_0402_5%
1000P_0402_50V7K
U43
1
C94 1000P_0402_50V7K
2 10K_0402_5% 2 1 R137 0_0603_5%
2
39 S4_SATA
1 2 R612 10K_0402_5%
CD1# D1 CP1 SD1# Q1 Q1# GND
VCC CD2# D2 CP2 SD2# Q2 Q2#
14 13 12 11 10 09 08
RTCVREF 0.1U_0402_10V6K 1 2 C693 2
74LCX74MTC_TSS OP14 Q12
D60 2
D_SET_S4
1 CH751H-40_SC76
1 39 FAN_SPEED2
1 R130
+3VALW
1 2 3 ACES_85205-0300
2
+3VS
@1U_0805_16V7K
2 1U_0805_16V7K
1 2 3 4 5 6 7
2 C720
S
JP22
2
1 R535
C679 10U_1206_16V4Z
CH355_SC76
E
1
4
R534 10K_0402_5%
C 7
1 C719
D
2 G 2N7002_SOT23
D
1
S
2
C147 @220P_0402_50V7K
3
5
1
1
1
EN_DFAN2
1 2 R597 10K_0402_5%
R176 1 2 10K_0402_5%
2
2
1 RTCVREF
+5VALW
1
Q49 2N7002_SOT23 S
2 G Q11 2N7002_SOT23
3
39 EN_DFAN2
*
39,43 SYSON
8 2
3
2 1 R530 0_0603_5%
39 FAN_SPEED1
+12VALW
2
S 1000P_0402_50V7K
D
2 G
Q48 2N7002_SOT23
2 G
41 S4_LID_SW#
1 2 R162 10K_0402_5% NC7SZ14M5X_SOT23-5
Y
1
2 10K_0402_5%
U6
A
3
C611
2 1 R511
2
3
1 +3VS
1N4148_SOT23 2 1U_0805_16V7K
1 C111
G
2
1000P_0402_50V7K
1 2 3
3
1
JP19 C615
1N4148_SOT23
2 8.2K_0402_5%
100K_0402_5%
2
FAN1
0.1U_0402_16V4Z
2
1
D52 1 R513
1
CH355_SC76
E
1
1 2 R536 100_0402_5%
RTCVREF
1
EN_FAN1
1
4
R512 10K_0402_5%
1
RTCVREF
1
-
C648 10U_1206_16V4Z
1
2
FMMT619_SOT23D55
1
1
C
2
+
1
1
3
2
2
EN_DFAN1
3
39 EN_DFAN1
RTCVREF
1
8 1
2
+12VALW
E
3
3
4
4
Compal Electronics, Inc. Title
Power OK/Reset/RTC battery/Lid Switch/Int. KB THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
Document Number
Rev 0.1
LA-2101 Saturday, November 22, 2003
Sheet E
42
of
52
2
S
D
1
C338 10U_1206_16V4Z
1
D
C323 0.1U_0402_16V4Z
S 3
2
2
1
SI4800DY_SO8 1
2 SUSP 2 G Q19 2N7002_SOT23
S S S G
1 2 3 4
2
4.7U_1206_16V4Z
2
3
1
SYSON# C492
D
0.1U_0402_16V4Z 3
S
+5VALW P
R640 10K_0402_5%
+12VALW
C478 4.7U_1206_16V4Z 2
1
+5VALWP
R441 6.8K_0402_5% 1 2
SI4800DY_SO8
3
C499 1U_0805_16V7K
2
95.3K_0603_1% 1 2 +12VALW
D D D D
SUSP 2 G Q31 2N7002_SOT23
SYSON
39,42 SYSON
R419 10K_0402_5% SUSP
1
U30 8 7 6 5
2
R248
C244 1U_0805_16V7K
S
1
2
1
C232 10U_1206_16V4Z
S
Q36 @2N7002 2 SUSP G
D 2 SUSP G Q28 2N7002_SOT23
D Q51 2N7002_SOT23
2 G
33,35,39,40 SUSP#
2
D Q29 2N7002_SOT23
2 G
S R637
S R418
3
2
1 2 3 4
S S S G
1
C498
2
2
D D D D
1
+5VALWP
1
U16 8 7 6 5
1
R453 @470_0402_5%
D 2 SUSP G Q27 2N7002_SOT23
3
+5VS S
1
+3VALW
1
1 R425 470_0805_5%
1
R429 470_0805_5%
+5VALW TO +5VS
+3VS
1
+VGA_CORE
+5VS
1
+3VALW TO +3VS
1
1 +3VS
2 SYSON# G Q55 2N7002_SOT23
0.1U_0402_16V4Z 3
1
2 SUSP G Q37 2N7002_SOT23
S
+12VALW
D
C805
S
1
S
S
D 2 SUSP G Q16 2N7002_SOT23
1
10K_0402_5% 1
10K_0402_5%
3
0.1U_0402_16V4Z
1
R679 47K_0402_5% 1 2
2 SYSON# G Q9 2N7002_SOT23
D 2 SYSON# G Q53 2N7002_SOT23
2
1
+12VALW
D
C123
3
2
C113 10U_1206_16V4Z
2
S
R452 470_0805_5%
1
2
C780 4.7U_1206_16V4Z
D 2 SYSON# G Q52 2N7002_SOT23
1
SI4800DY_SO8 1
D
C778 1U_0805_16V7K
2
R141 95.3K_0603_1% 1 2
2
1
S S S G
2
4.7U_1206_16V4Z
1
D D D D
1 2 3 4
1
C779
1
8 7 6 5
1
1
SI4800DY_SO8
1
R223 470_0805_5%
1
U5
3
C99 1U_0805_16V7K
2
R652 470_0805_5%
1
R638 470_0805_5%
1 2 3 4
S S S G
2
C98 10U_1206_16V4Z
2
+3VALW
D D D D
+1.8VS
1
+5V U50
8 7 6 5
1
3
+5VALW P 1
+2.5VS
2
2
+5V
2
+3V
+5VALW TO +5V +3V
E
2
+3VALW TO +3V
D
3
C
3
B
2
A
+2.5VALW TO +2.5V +2.5VALW +2.5V
SI4800DY_SO8
4.7U_0805_10V4Z
2
2 1
H26 H_S315D142
1
C468
H23 H_S315D142
H12 H_S315D142
H30 H_S315D142
H27 H_S315D142
H15 H_S315D142
H8 H_S315D142
H28 H_S315D142
H4 H_C276D181
H21 H_C276D181
11
1 2 3 4
S S S G
1
D D D D
11
U23 8 7 6 5
C467 1U_0805_16V7K
1
1
1
1
1
1
H13 H_C276D142
H10 H_SMDC138
H11 H_C142D142N
H6 H_C236D236N
PJP13
2
2 H2 H_C55D55N
H19 H_C55D55N
H17 H_SMDC157
H18 H_SMDC157
1
1
1
H1 H_C276D181
1
1
H3 H_C276D181
1
1
1
1
H29 H7 H_O268X228D205X165 H_S315D142
11
H24 H_C228D165
1
1
H22 H_C197D98
PAD-OPEN 2x2m
11
H20 H_C197D98
+2.5VS
1
PAD-OPEN 2x2m
+2.5VALW TO +2.5VS +2.5VALW
H16 H_TC197S276D110
2 SYSON# G Q26 2N7002_SOT23 1
S
H9 H_C276D142
3
1
0.1U_0402_16V4Z 3
1
H25 H_S276D110
PJP12 H5 H_C276D181
D
C464
H14 H_C276D181
+12VALW
3
2
1
R389 100K_0402_5% 1 2
2
4.7U_0805_10V4Z
1
C459
U21
2
1U_0603_10V4Z
C376
2
1
2
C375 4.7U_0805_10V4Z
11
1
C389
1
1
SI4800DY_SO8 C449
1
1 2 3 4
S S S G
1
1
D D D D
1
8 7 6 5
PJP14
PJP16
PJP17
2 4.7U_0805_10V4Z
C367
2
2
PAD-OPEN 2x2m
D
4
0.1U_0402_16V4Z S 3
1
PAD-OPEN 2x2m PAD-OPEN 2x2m +12VALW
1
2
R305 100K_0402_5% 1 2
2
4.7U_0805_10V4Z
SUSP 2 G Q20 2N7002_SOT23
4
Compal Electronics, Inc. Title
POWER CONTROL CKT THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND PROPRIETARY NOTE TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Size Document Number CustomLA-2101 Date:
Rev 0.1
Saturday, November 22, 2003
Sheet E
43
of
52
A
B
C
D
VS PR1 1M_0402_1% 1 2
VIN
2
PR6 20K_0402_1%
+
2
-
2
1
PR7 10K_0402_5%
PD2 RLZ4.3B_LL34 2
PR8 10K_0402_5% 2 1
2
PACIN 46,47
1
1
PC6 0.1U_0402_16V4Z
ACIN 25,39,40
PACIN
1
O
2
2
PU1A LM393M_SO8
8 1
PC5 1000P_0402_50V7K
3
G
2 22K_0402_5%
PR4 1K_0402_5% 1 2
P
2
1 PR5
2
PC2 100P_0402_50V8J
2
2
2
PD1 EC10QS04_SOD106
2
SINGA_2DC-S113L200
PC4 100P_0402_50V8J 1
1
1
1
PC3 1000P_0402_50V7K
1
1
PC1 1000P_0402_50V7K 1
2
2
PR2 5.6K_0402_5%
VS
PR3 84.5K_0402_1%
C8B BPH 853025_2P
2
PL1 1
4
G G G G
1
6 5 4 3
PF1 12A_65VDC_451012 1 2
1
1
1
PCN1
1
VIN
Vin Detector
RTCVREF
3.3V
High 18.764 17.901 17.063 Low 17.745 16.903 16.038
2
VIN
PD3 1N4148_SOD80
1
PD5
2
PR10 33_1206_5%
PQ1 TP0610T_SOT23
VIN
2
N3
1
2
B+
1N4148_SOD80 PR12 1K_1206_5% 1 2
D
S
N1
1
1
3
1
2
1
G
PC8 0.1U_0603_25V7K PR16 1M_0402_1% 2 1
6.0V
PR17 499K_0402_1%
2 PR21 10K_0402_5%
1
PR20 499K_0402_1%
PC9 1000P_0402_50V7K
PR22 215K_0402_1%
2
PC11 0.1U_0402_16V4Z
2
6 2
PC10 1000P_0402_50V7K PD9 @ RLZ6.2C_LL34
1
3
2
2
2
1
PD8 RLZ16B_LL34
2
PC13 10U_0805_10V4Z
3
PC12 1U_0805_25V4Z
5
-
2
1
GND
+
O
1
8
RB715F_SOT323
1
N2
2
2
IN
7
1
OUT
1
3
1
1
3
P
46 ACON
4
2
1
CHGRTC
3.3V
6,45,47 MAINPWON
2
PR19 200_0402_5% 1 2
PD7 PR18 200_0402_5%
PU2 S-812C33AUA-C2N-T2_SOT89
PU1B LM393M_SO8
G
RTCVREF
1
PR15 10K_0402_5% 1 2
1
VL
1
2
2
PC7 0.22U_1206_25V7K
2
PR13 100K_0402_5% PR14 22K_0402_5% 1 2
40,41 51ON#
PR11 1K_1206_5% 1 2
2
PD6 RLZ3.6B_LL34 CHGRTCP 2 1
VS
2
BATT+
PR9 1K_1206_5% 1 2
1
PD4 RB751V_SOD323 2 1
RTCVREF
3.3V
1
2
2
+1.8VS
JUMP_43X79 PJP3 1
+2.5VALW
2
2
(12A,480mils ,Via NO.=24)
JUMP_43X118
(1.5A,60mils ,Via NO.= 3)
PJP4 +1.25VSP
1
1
2
2
+1.25VS
(3A,120mils ,Via NO.= 6)
1
2
2
+CPUVID
(150mA,40mils ,Via NO.= 2)
+5VALWP
1
+1.5VSP
1
1
2
+1.5VS
1
2
+5VALW
+5VALWP
1
2
2
+3VALW 4
(6A,240mils ,Via NO.= 12)
PJP9 1
2
JUMP_43X118
(5A,200mils ,Via NO.= 10)
JUMP_43X118
+12VALWP
2
PJP7 1
+3VALWP 2
1
(6A,240mils ,Via NO.= 12)
JUMP_43X39 PJP8 4
PQ3 DTC115EKA_SC59
JUMP_43X118
PJP6 1
PACIN
S
PJP5
JUMP_43X79
+VCCVIDP
Precharge detector 15.34 15.90 16.48 13.13 13.71 14.20
2 G
3
1
+2.5VALWP
D PQ2 2N7002_SOT23
PJP11 1
+1.8VSP
PR23 47K_0402_5% 2 1
1
*
2
2
1
1
JUMP_43X118
3
PJP1 1
PJP10 2
2
+12VALW
(120mA,20mils ,Via NO.= 1)
1
+VGA_COREP
JUMP_43X39
1
2
2
+VGA_CORE
JUMP_43X118
(6A,240mils ,Via NO.= 12)
A
B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS, Date: INC. C
Compal Electronics, Inc. DCIN / DETECTOR Document Number
Rev 0.1
LA-2101 Saturday, November 22, 2003 D
Sheet
44
of
52
A
B
C
VMB
1 2
3
PC16 0.01U_0402_25V7Z
1
VL
VS
VL
2
PC15 1000P_0402_50V7K
2
1 PH1 10KB_0603_1%_TH11-3H103FT
PC14 0.1U_0603_25V7K
PR25 47K_0402_1% PR27 47K_0402_1% 1 2
2
2
2
2
MAINPWON 6,44,47
PQ4 DTC115EKA_SC59
+3VALWP
-
2
1
PR33 100K_0402_1% 2 1 VL
1
2
PU3A LM393M_SO8 3
2
2
2
PC18 1000P_0402_50V7K
PD12 @ BAS40-04_SOT23
1
O
4
1
1
PC17 0.22U_0805_16V7K_V2
3
PD11 1SS355_SOD323 2 1 2
P
2
PR32 3.32K_0402_1%
PR36 1K_0402_5%
1
+
1
PR34 25.5K_0402_1% 1 2
3
G
PR30 1 2 16.9K_0402_1% TM_REF1
ALI/MH# 39
8
2
PD10 @ BAS40-04_SOT23
1
1
PR31 1K_0402_5%
1
PR29 100_0402_5%
2
BATT+
+3VALWP
PH1 under CPU botten side : CPU thermal protection at 84 degree C Recovery at 44 degree C
1
PR28 100_0402_5%
SUYIN_200275MR009G116ZL_RV
PR26 47K_0402_5% 1 2
1
GND GND
1 PR24 1K_0402_5%
2
PL2 C8B BPH 853025_2P 1 2
1
10 11
ALI/NIMH# AB/I TS_A EC_SMDA EC_SMCA 1
1
BATT+ BATT+ ID B/I TS SMD SMC GNDGND-
PF2 15A_65VDC_451015 1 2
1 2 3 4 5 6 7 8 9
1
PCN2
D
2
2
PR35 100K_0402_1%
2
BATT_TEMPA 39 EC_SMB_DA1 39,40
1
1
EC_SMB_CK1 39,40
PD13 @ BAS40-04_SOT23
PH2 near main Battery CONN : BAT. thermal protection at 78 degree C Recovery at 44 degree C
3
2
2
3
PD14 @ BAS40-04_SOT23
+5VALWP
249K_0402_1%
200K_0402_1%
VL
VS
PR39 5 6
+
O -
7
PD15 1SS355_SOD323 2 1
PU3B LM393M_SO8
O
D PQ24 2N7002_SOT23
2 G
PU10A LM393M_SO8
S
PC19 0.22U_0805_16V7K_V2 2
1
4
1
1
PC90 1000P_0402_50V7K
PC91 10P_0402_50V8J
1
-
1
+
2
1
1
2
2
8 3
PR41 3.48K_0402_1%
PC20 1000P_0402_50V7K
2
2
2
2
PR40 100K_0402_1% 2 1 VL
PR42 100K_0402_1%
2
PR112 100K_0402_1%
H_PROCHOT# 5
3
2 249K_0402_1%
1
1 PR111
PR109 365K_0402_1%
PC89 0.1U_0603_25V7K
2 14.7K_0402_1% TM_REF2
3
4
1
1
1
P
39,46 ADP_I VL
G
PR110 64.9K_0402_1% 1 2
PR37 47K_0402_1% PR38 47K_0402_1% 1 2
1
PR111
PR108 1M_0402_1% 1 2
8
88.7K_0402_1%
P
64.9K_0402_1%
G
PR110
PH2 10KB_0603_1%_TH11-3H103FT
1
205K_0402_1%
2
365K_0402_1%
1
PR109
VL
2
3
90W 2
VL
120W
5
+
P
6
-
G
8
4
4
PU10B O
7
Compal Electronics, Inc.
LM393M_SO8 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY Title OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D DEPARTMENT EXCEPT AS Size AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS, Date: INC.
A
B
C
BATTERY CONN / OTP /Throttling Document Number
Rev 0.1
LA-2101 Saturday, November 22, 2003 D
Sheet
45
of
52
A
B
B++
B+
PQ5 SI7447DP_SO8
PL3 C8B BPH 853025_2P 1 2
1 2 3
1
PC23 4.7U_1206_25V6K
1
4 PR46 10K_0402_5% 1 2
2 PQ10 2N7002_SOT23
+INE2
CS
22
4
-INE2 VCC(o)
21
5
FB2
20
3 2 1
3
CS
PC24 0.022U_0402_16V7K 1 2
N18
PQ8 SI4835DY_SO8
4
2
ACOFF 39
7 8 9 10
VREF
VH
18
-INE1
RT
17
+INE1
-INE3
16
FB3
15
OUTC1
PC25 0.1U_0603_25V7K
PC28 0.1U_0603_25V7K 19 1 2
VCC
FB1
2
LXCHRG PC31 0.1U_0603_25V7K 1 2
2
PR56 68K_0402_5% 1 2
CC=0.5~2.7A CV=16.8V(12 CELLS LI-ION) PL4 22UH_SPC-1205P-220A_2.8A_20% 1 2
PR60 PC32 47K_0402_5% 1500P_0402_50V7K 1 2 1 2
PR58 0.02_2512_1% 1 2
BATT+
1
1
PR59 10K_0402_5% 2 1
6
OUT
1
11
OUTD
CTL
14
12
-INC1 +INC1
13
ACON
PC34 4.7U_1206_25V6K 2
2 PQ11 DTC115EKA_SC59
3
2
MB3887_SSOP24
1
PC36 4.7U_1206_25V6K
PD17 EC31QS04
2
PC33 0.1U_0402_16V4Z
1
1
PR61 100K_0402_1%
PR62 47K_0402_5%
PC35 4.7U_1206_25V6K
1
2
PC30 1000P_0402_50V7K
CS
2
PQ9 DTC115EKA_SC59
2
PC27 4700P_0402_25V7K PR55 1K_0402_5% 1 2 1 2
PR57 205K_0402_1% 1 2
1
23
1
2 1 PC29 0.1U_0402_16V4Z
+3VALWP
2
PR54 10K_0402_5% 2 1 2
1
2
2
IREF=1.31*Icharge IREF=0.73~3.3V 39 IREF
OUTC2 GND
3
PR52 33.2K_0402_1%
PR53 10K_0402_1%
PC26 0.1U_0402_16V4Z
2
2
PR49 0_0402_5%
5 6 7 8
1
3
1
S
ACON
44 ACON
24
1
2 G
1 PR50 100K_0402_5%
-INC2 +INC2
1
2 PR51 3K_0402_5%
2 D
1
1
2
39,45 ADP_I
2
PU4 PR48 150K_0402_1%
1 1
VIN
1
1 PD16 1SS355_SOD323 ACOFF# 1 2
PACIN
PR47 47K_0402_5% 1 2
2
2
PR45 200K_0402_1% ACOFF#
44,47 PACIN
5
PC162 2200P_0402_50V7K 2
PC22 4.7U_1206_25V6K 2
PC21 4.7U_1206_25V6K
1
PR43 0.01_2512_1%(2W) 2 1
1
PQ7 SI4825DY_SO8 D 8 S D 7 S D 6 S D 5 G
1
1 2 3 4
PR44 10K_0402_5%
Iadp=0~4.2A
D
2
1 1
Iadp=0~5.8A
90W P3
1
8 7 6 5
VIN
PQ6 SI4825DY_SO8 D S 1 D S 2 D S 3 D G 4
120W
2
P2
C
PQ12 DTC115EKA_SC59
2
PR63 95.3K_0603_0.1% 2 1
PR64 143K_0603_0.1% 2 1
4.2V
3
39 FSTCHG
3
3
PR184 95.3K_0603_0.1% 2 1
1
VMB
PR65 340K_0402_1%
OVP voltage : LI
PR43
PR52
120W
0.01_2512_1%
33.2K_0402_1%
SI7447DP_SO8
PQ5
90W
0.015_2512_1%
29.4K_0402_1%
SI4825DY_SO8
2
4S3P : 17.4V--> BATT_OVP= 1.935V 1
(BAT_OVP=0.1111 *VMB)
PR66 499K_0402_1%
+5VALWP
P
+
3
G
1
-
2
0
1
4
39 BATT_OVP
2
8
PU5A LM358A_SO8
4
1
PC38 0.01U_0402_25V7Z
Compal Electronics, Inc.
2
2
PR68 105K_0603_0.5%
2
PR67 2.2K_0402_5%
1 2
PC37 @ 0.1U_0402_16V4Z
1
4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY Title OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D DEPARTMENT EXCEPT AS Size AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS, Date: INC. A
B
C
CHARGER Document Number
Rev 0.1
LA-2101 Saturday, November 22, 2003 D
Sheet
46
of
52
5
4
3
2
1
PC39 4.7U_1206_25V6K 1 2 2
1
N4
RUN/ON3
1
5 6 7 8
2
G S S S 4 3 2 1 5 6 7 8 D D D D
1
21
2
CSH5
G S S S PLX5
2
2.5VREF PC55 4.7U_1206_16V4Z
+5VALW P
PC59 100P_0402_50V8J
PC57 1 150U_D2E_6.3VM_R18 +
2
8
PR78 10.5K_0402_1%
+ PD22 EP10QY03 2 PC58 @ 150U_D2E_6.3VM_R18
PR81 10K_0402_1% VL 2
2
1
1
2
2
2
2
1
POK 48 PR82 47K_0402_1% 2 1
PR75 0.012_2512_1%
2
PR74 2M_0402_5%
MAX1902EAI_SSOP2 8
PR80 47K_0402_5%
C
1
PDL5
1
2
PC51 47P_0402_50V8J
1
TIME/ON5
1
7 28
PQ49 SI4810DY_SO8
4 5 18 16 17 19 20 14 13 12 15 9 6 11
1
CSH3 CSL3 FB3 SKIP# SHDN#
PC56 680P_0402_50V7K
VS PR79 10K_0402_1%
1
D D D D
1
2
2 1 2 3 10 23
VL
LX3 DL3
V+
DH3
26 24
12OUT VDD BST5 DH5 LX5 DL5 PGND CSH5 CSL5 FB5 SEQ REF SYNC RST#
1
1
PC54 100P_0402_50V8J
2
2 PC53 @ 150U_D2E_6.3VM_R18
1 2 PR76 10K_0402_5%
44,46 PACIN
2
PR77 3.57K_0402_1% PD21 EP10QY03
1
+
2
2
1
1
PC52 1 150U_D2E_6.3VM_R18 +
CSH3
27
2 PDH51 PR71 0_0402_5%
2
2
+3VALW P
PR73 1M_0402_1% 1
PR72 0.012_2512_1%
BST3
GND
2
1
PU6 25
22
2
1
4 3 2 1
2
2
1 1 1
1
PQ14 SI4800DY-T1_SO8
2
PDH3
PC49 4.7U_1206_16V4Z
PDH5
C
PC163 2200P_0402_50V7K
PC46 @ 4.7U_1206_25V6K
2
1 PC45 4.7U_1206_25V6K
PC47 4.7U_1206_16V4Z PC48 0.1U_0603_25V7K
PC50 47P_0402_50V8J
PL6 10UH_SPC-1205P-100_4.5A_20%
2
1
VL +12VALW P
PDL3
PT1 310uH_SDT-1205P-100-118_5A_20%
B+++
PD20 1SS355_SOD323
PLX3
D
2
1
1
PDH31
1 FLYBACK PR69 22_1206_5% 4
2
PC44 0.1U_0603_25V7K 1 2
PD19 DAP202U_SOT323
1
8 7 6 5
PR70 0_0402_5% 1 2
2
3
VS PQ13 SI4814DY_SO8 1 D1 G1 2 D1 S1/D2 3 G2 S1/D2 4 S2 S1/D2
PD18 EC11FS2_SOD106
1
PC43 4.7U_1206_25V6K
2
1
SNB
2
PC42 @ 4.7U_1206_25V6K
BST51
PC40 470P_0805_100V7K
1
B+++ PL5 HCB4532K-800T90_1812 1 2
2
B+
1
D
PC41 0.1U_0603_25V7K BST31 1 2
PC60 0.047U_0603_50V4Z
B
+5V Ipeak = 6.66A ~ 10A
MAINPWON 6,44,45 PC61 0.047U_0603_50V4Z
2
2
1
1
+3.3V Ipeak = 6.66A ~ 10A B
A
A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Compal Electronics, Inc. Title
5V/3.3V/12V Size
Document Number
Rev 0.1
LA-2101 Date:
Saturday, November 22, 2003
Sheet 1
47
of
52
A
B
C
D
2
PC164 2200P_0402_50V7K
PR86 10_0402_5%
DDR Termination Voltage 1
1
2
1
1
1
8 7 6 5
2 1
S S S G
TON2
SC1486
9
VCCA1
VCCA2
11
3
VDDP1
VDDP2
17
7
BST1
BST2
21
2
TON1
25
PC71 1000P_0402_50V7K
1
2
2
PC70 1000P_0402_50V7K
23
1
1
1 2 3 4
PC72 0.1U_0603_25V7K
6
DH2
20
LX1
LX2
19
2
DL1
ILIM2
18
4
ILIM1
DL2
16
FBK2
12
DH1
2
PQ17 SI4814DY_SO8 1 D1 G1 8 2 D1 S1/D2 7 3 G2 S1/D2 6 4 S2 S1/D2 5
1
PC73 0.1U_0603_25V7K
2
4
PR89 0_0402_5% 1 2
PR91 10.7K_0402_1% 1 2
26
FBK1
REFOUT
10
47 POK
0_0402_5% PR189
22
EN/PSV1
PGOOD2
13
27
PGOOD1
REFIN
8
PGND1
PGND2
15
AGND1
AGND2
14
PD31 EP10QY03
PR96 10_0402_5%
2
PR94 10K_0402_1%
2
2
PR95 0_0402_5% 1 2
+1.25VSP
+
2
VOUT1
+1.25V
2
21
2
24 PC152 47P_0402_50V8J
1
2
PR93 42.2K_0402_1%
PC74 220U_D2_4VM
1
1
PR92 15K_0402_1% 1 2
PL9 3UH_SPC-07040-3R0_5A_30% 1 2 1
1
1 2 3
1
5
PR90 100K_0402_5%
1
1
2
PD26 EC31QS04
2
PR88 0_0402_5% 1 2
2
2
2
PR188 0_0402_5%
2
PD25 EP10QY03
PC67 1U_0805_10V7K
8 7 6 5 PQ16 FDS6672A_SO8
1
1
PC151 + 220U_D2_4VM
2
PC69 1U_0603_10V6K 2 1
2
D D D D
PC68 1U_0603_10V6K 1 2 PU7
PR87 100K_0402_5%
PL8 2.2UH_SPC-1205P-2R2B_13A_30% 1 2 1
1
PD24 RB751V_SOD323
PC66 1U_0805_10V7K
+2.5VALWP
PC150 1 220U_D2_4VM +
+2.5V/+1.25V
2
2
1 2
PR85 10_0402_5%
2
PC65 4.7U_1206_25V6K
PD23 RB751V_SOD323
2
1
1
+5VALWP
1
PQ15 IRF7821_S08
B+
1 PR84 750K_0402_5% 2
PR83 1M_0402_1% 1
1
PC64 4.7U_1206_25V6K
2
1
2
PC62 4.7U_1206_25V6K
2
1
PC63 4.7U_1206_25V6K
2
PL7 HCB4532K-800T90_1812 1 2
PC153 1U_0603_10V6K
1
1 28
+5VALWP
+3VS
SC1486ITSTR_TSSOP28 3
+1.8VSP
1
2 2 G 3
2 1
PC157 4.7U_1206_16V4Z
PR196 60.4_0402_1%
2
1
PC159 100P_0402_50V8J
2
1
1
2
PR194 137_0402_1%
PC155 0.1U_0402_16V4Z
2
1 1 2
S PQ48 2N7002_SOT23
PR192 10K_0402_1%
D
S PQ50 2N7002_SOT23
ADJUST
PC158 4.7U_1206_16V4Z
2 G
1
PU18 APL1085UC-TR_TO252 VIN VOUT 2
D
1
3
PR190 10K_0402_1%
1
PR191 0_1206_5% 1 2
2
+3VS
+2.5VALWP
3
PR177 10K_0402_1%
1 1
PC154 0.1U_0402_16V4Z
1
PR97 10K_0402_1%
2
2
2
1
3
4
4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS, Date: INC. A
B
C
Compal Electronics, Inc. DDR_2.5V/1.25V/1.8V Document Number
Rev 0.1
LA-2101 Saturday, November 22, 2003 D
Sheet
48
of
52
A
B
C
D
2
+5VALW
10
11
DH
8
1 2 3 4
+5VALW 9
1
LX 2
2
8 7 6 5
PR99 8.06K_0402_1%
+1.5VSP 1
1
+
6
+
2 1
1 PC80 10P_0402_50V8J
+1.5V
PL10 2.2UH_PLFC1235P-2R2A_6A_30% 1 2
PGND
7
FB
3
PR101 9.09K_0402_1%
PC79 2 220U_D2_4VM
PC78 2 @ 220U_D2_4VM
2
4
3
GND
2
2
PC81 390P_0402_50V7K
S
2
COMP
1 S
PQ54 2N7002_SOT23
2 G PC160 0.1U_0402_16V4Z
PQ53 2N7002_SOT23
2 G
D1 G1 D1 S1/D2 G2 S1/D2 S2 S1/D2
PQ19 SI4814DY_SO8 DL
21
D
PR100 220K_0402_1%
D
3
2
1
2
PR199 10K_0402_1%
1
1
PR198 10K_0402_1%
2
PC77 0.1U_0402_16V4Z
HSD
1
+3VS
BST
2
1
1
PC76 22U_1210_6.3V6M
PC75 22U_1210_6.3V6M
2
5
PD27 EP10QY03
IN
PU8
1
2
1
1
1
PR98 0_1206_5%
2
1
MAX1954EUB_10UMAX
2
+5VALW
10
11
DH
8
LX
9
DL
6
PGND
7
FB
3
HSD
+5VALW
+1.2V/1.0V 1 2 3 4
1
3
+VGA_COREP
3
1 +
PR103 4.53K_0402_1%
PC85 2 @ 220U_D2_4VM
1 + 2
PC86 220U_D2_4VM
2
2
1
1 PC88 390P_0402_50V7K
PL11 8 D1 G1 2.2UH_SPC-1205P-2R2B_13A_30% D1 S1/D2 7 1 2 G2 S1/D2 6 S2 S1/D2 5 PQ21 SI4814DY_SO8
COMP
PC87 15P_0402_50V8J
21
S PQ55 2N7002_SOT23
4
GND
1
3
S
PR104 180K_0402_1% PQ22 2N7002_SOT23
2 G 3
D
2 G
D
2
2 1
2 2
1
1 PR201 20K_0402_1%
MAX1954EUB_10UMAX
1
PC161 0.1U_0402_16V4Z
2
PR200 10K_0402_1%
1
PC84 0.1U_0402_16V4Z
1
+3VS
BST
2
1
PC83 22U_1210_6.3V6M 2
PC82 22U_1210_6.3V6M
2
5
PD28 EP10QY03
IN
PU9
1
2
1
PR102 0_1206_5%
PR105 9.09K_0402_1%
1
2
+5VALW
1
D
1 1
S PQ56 2N7002_SOT23
2 G
PR106 9.09K_0402_1%
PQ23 2N7002_SOT23 2
17 POWER_SEL 4
D
2 G 3
1
2
PR202 10K_0402_5%
4
3
S
2
PR203 100K_0402_5% THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS, Date: INC. A
B
C
Compal Electronics, Inc. 1.5V/VGA_CORE Document Number
Rev 0.1
LA-2101 Saturday, November 22, 2003 D
Sheet
49
of
52
A
B
C
+5VS
D
+5VALWP
2
1
2
1
7
VID4 VID3 VID2 VID1 VID0 VID12.5
PGOOD
39
VCORE_PWRGD 27
5 VCORE_ENLL
34
ENLL
33
PC100 0.047U_0603_16V7K 2 1
1 2
PR130 69.8K_0402_1%
PWM1
25
PWM1 51
ISEN1+ ISEN1-
24 23
ISEN1+ 51 ISEN1- 51
DRSEN
PWM2
26
PWM2 51
35
DSEN#
ISEN2+ ISEN2-
27 28
ISEN2+ 51 ISEN2- 51
10
PWM3 52
OCSET
11
9
1
Frequency Select 1
PU5B 5
+ 0
13
NC
14
GND
VDIFF VSEN VRTN
16 17 18
GND
OFS
38
VR-TT#
40
NTC
2
4 H_BOOTSELECT
IN
4
PG
3
EN
OUT
5
GND
2
+VCCVIDP
2
MIC5258_SOT23-5
2
1
1 C1
PR143 16.2K_0402_1% 2 1 3
+CPU_CORE
2
1
PR152 @ 0_0402_5%
2 1 PR150 @ 0_0402_5%
Remote Sensing
VCCSENSE 5
Place near +VCC_CORE output capacitor VSSSENSE 5
2
3 PQ31 MMBT3904_SOT23
PC109 4.7U_1206_16V4Z 2
PR154 0_0402_5% 2 1
PQ30 2N7002_SOT23 S
E PR155 100K_0402_5%
1
5 VID_PWRGD
1
1
2
PU13
PR151 0_0402_5% 2 1
D
2 G PR153 22K_0402_5% 2 1 2 B
1
PR149 0_0402_5% 2 1
PR147 5.1K_0402_1%
1 2 G
PQ27 2N7002_SOT23
PC107 1U_0603_10V6K 2
2
1
1
S PQ28 TP0610T_SOT23
3
1.2VDD PC108 4.7U_1206_16V4Z
39 VR_ON
3
S 1
+3VALWP
PQ29 2N7002_SOT23
D
2 G
1
Panasonic ERTJ0EV334J (0402) Locate this NTC resistor on PCB between phase 2 and 3 for thermal compensation.
Place close to IC PC106 0.1U_0402_16V4Z 2
2
1
2
+3VALWP
PR142 1M_0402_1%
1
2
1
1
1 2
ISL6247_MLFP40 PR141 32.4K_0402_1%
PR139 2.26K_0402_1% 1 2
+5VS
8
1
1
1
PC105 12 @ 220P_0402_50V9J PR138 @ 330K_0402_5% 19
PR140 @ 10K_0402_5%
D PR146 0_0402_5% 2 1
PC104 PR137 @ 1000P_0402_50V7K @ 0_0402_5% 2 1 2 1
2
@ 0_0402_5% 2
2
2
PR134 1
PR144 45.3K_0402_1%
1 PC103 22P_0402_50V8J
2 PR135 @ 0_0402_5% 2 1
3
2
FB
G
POP
DRSV
D
UNPOP
15
S
PR127
COMP
ISEN4+ 52 ISEN4- 52
27K_0402_5%
17.4K_0402_1%
FS
37
PWM4 52
PC101 PR132 2200P_0402_50V7K 20K_0402_1% 2 1 1 2
PR148
300_0402_1%
20K_0402_1%
DSV
340K_0402_1%
360_0402_1%
PR131
30 29
+5VS
PR127 @ 0_0402_5%
PR145
PR129
ISEN4+ ISEN4-
ISEN3+ 52 ISEN3- 52
1
2
6
PR136 10K_0402_1%
3
31
2
2
1
LM358A_SO8
90W(3-phase)
PWM4
SOFT
36 PR133 100K_0402_1%
21 22
2
7
20
1
PR131 20K_0402_1% 2
PC102 100P_0402_50V8J
PWM3 ISEN3+ ISEN3-
3
1 2
PR129 360_0402_1%
120W(4-phase)
RAMPS
1 2 3 4 5 6
2
PR123 10K_0402_5% 2 1
VCC
H_VID4 H_VID3 H_VID2 H_VID1 H_VID0 H_VID5
1 PR124 2 0_0402_5%
1
PU12 32
1 PR125 2 0_0402_5%
5,24 PM_STPCPU#
PR122 80.6K_0402_1%
1
1 PC99 1U_0603_10V6K 2 1
24 PM_DPRSLPVR
Battery Feed Forward
2
PR185 0_0603_5%
5 5 5 5 5 5
B+
PR126 @ 0_0603_5%
PR156 100K_0402_5%
1
4
A
4
1. When mode control signal is high/ low, the VR will operate to Northwood/ Prescott load line (Northwood="0",Prescott="1") 2. VID5(12.5) should be pulled high, when the VR operates to Nothwood load line.
B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS, Date: INC. C
Compal Electronics, Inc. CPU_CORE_Controller Document Number
Rev 0.1
LA-2101 Saturday, November 22, 2003 D
Sheet
50
of
52
A
B
C
D
1
1
PC141 470P_0402_50V7K
PC142 0.1U_0603_25V7K
1
+
PC149 220U_25V_M
2
+5VP1
1
B+ 1
2
2
PC111 4.7U_1206_25V6K
PC113 4.7U_1206_25V6K
2
PC112 4.7U_1206_25V6K
2
PQ32 SI7392DP_SO8
PL13 1 2 C8B BPH 853025_2P 1
2
PR157 3_0402_5%
1
5
2
2 PR187 @ 0_0603_5%
1
2 1
PR186 0_0603_5%
PC110 0.22U_0805_16V7K_V2 2 1
1
CPU_B+ +5VS +5VALWP
4
1
PU14
1
1 N5
7
EN
PHASE
8
PHASE1
GND LGATE
5
BOOT
Panasonic ETQ-P4LR56WFC
CPU_DRIVE_EN
5 6 7 8 D D D D
PQ35 SI4362DY_SO8 2
PR161 32.4K_0402_1% 1
2
PC119 0.01U_0402_25V7Z 1
4 3 2 1
4 3 2 1
G S S S
5 6 7 8 PQ34 SI4362DY_SO8
D D D D
PC117 1U_0805_25V4Z 1
1
PC116 0.1U_0402_16V4Z
G S S S
ISL6207CB-T_SO8 1
PL14 0.56UH_ETQP4LR56WFC_21A_20% 1 2
3 2 1
PWM UGATE
4
2
PR159 499K_0402_1%
2 PR158 0_0402_5%
VCC
3
PR160 1_0402_5% 2 1
2
2
2
PWM1 50
6
N6 PH3 820_0402_5% 2 1
50 ISEN150 ISEN1+ CPU_B+
PC120 0.22U_0805_16V7K_V2 1 2
1
1
1
2
2
Local Transistor Swtich Decoupling
PWM UGATE
1 N7
7
EN
PHASE
8
4
GND LGATE
5
PHASE2
D D D D
5 6 7 8 ISL6207CB-T_SO8
Panasonic ETQ-P4LR56WFC PL15 0.56UH_ETQP4LR56WFC_21A_20% 1 2
+CPU_CORE
PQ38 SI4362DY_SO8
1
3
PR165 1_0402_5% 2 1
5 6 7 8
VCC
BOOT
2
3 2 1
6
D D D D
2
PC144 0.1U_0603_25V7K
PQ39 SI4362DY_SO8
PD30 EC31QS04
PR166 32.4K_0402_1% 2 1
PC126 0.01U_0402_25V7Z 2 1
2
G S S S 4 3 2 1
4 3 2 1
G S S S
1
1
PC125 1U_0805_25V4Z
PC122 4.7U_1206_25V6K 2
2
1 2 PR164 499K_0402_1%
PC143 470P_0402_50V7K
4 PU15
PWM2 50
PC123 4.7U_1206_25V6K
PC121 4.7U_1206_25V6K 2
PQ36 SI7392DP_SO8
PR163 3_0402_5%
1
1
5
2
2
2
3
3
N8 PH4 820_0402_5% 2 1
50 ISEN250 ISEN2+
Local Transistor Swtich Decoupling
4
4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS, Date: INC. A
B
C
Compal Electronics, Inc. CPU_CORE_Power stage 1 Document Number
Rev 0.1
LA-2101 Saturday, November 22, 2003 D
Sheet
51
of
52
A
B
C
PC145 470P_0402_50V7K
1
PC130 4.7U_1206_25V6K
1
PC129 4.7U_1206_25V6K
1
PC128 4.7U_1206_25V6K
1
1
5
2
PC127 0.22U_0805_16V7K_V2 1 2 +5VP1
D
CPU_B+
1
PC146 0.1U_0603_25V7K
2
2
2
2
2
PR168 3_0402_5% PQ40 SI7392DP_SO8
4 PU16
7
EN
PHASE
8
PHASE3
4
GND LGATE
5
Panasonic ETQ-P4LR56WFC
D D D D
ISL6207CB-T_SO8
1
PL16 0.56UH_ETQP4LR56WFC_21A_20% 1 2
G S S S
5 6 7 8
2
D D D D
BOOT
G S S S
VCC
5 6 7 8
PR170 1_0402_5% 2 1
3
PQ42 SI4362DY_SO8
1
PC131 1U_0805_25V4Z
1
PR169 499K_0402_1%
2
2
PWM3 50
3 2 1
PWM UGATE
1 N9
6
1
PQ43 SI4362DY_SO8 PR171 32.4K_0402_1% 1
PC133 0.01U_0402_25V7Z 2 1
4 3 2 1
4 3 2 1
2
N10 PH5 820_0402_5% 2 1
50 ISEN350 ISEN3+
1
EN
PHASE
8
PHASE4
GND LGATE
5
BOOT
2
4
1
1 2
Panasonic ETQ-P4LR56WFC
PL17 0.56UH_ETQP4LR56WFC_21A_20% 1 2
+CPU_CORE
PQ46 SI4362DY_SO8
PQ47 SI4362DY_SO8 G S S S 4 3 2 1
4 3 2 1
G S S S
1
ISL6207CB-T_SO8
D D D D
2
2
Local Transistor Swtich Decoupling
5 6 7 8
PWM UGATE
VCC
D D D D
7
1 N11
PR175 1_0402_5% 2 1
5 6 7 8
2
3
PC138 1U_0805_25V4Z
1
2
PC148 0.1U_0603_25V7K
PC137 4.7U_1206_25V6K
3 2 1
6
PR174 499K_0402_1%
PC147 470P_0402_50V7K
4 PU17
PWM4 50
PC135 4.7U_1206_25V6K
2
PQ44 SI7392DP_SO8 2
PR173 3_0402_5%
PC136 4.7U_1206_25V6K
2
1
5
2 2
1
CPU_B+
PC134 0.22U_0805_16V7K_V2 1 2
1
CPU_DRIVE_EN
2
PR176 32.4K_0402_1% 1
PC140 0.01U_0402_25V7Z 2 1
N12 PH6 820_0402_5% 2 1
3
50 ISEN450 ISEN4+
3
PC134,PC135,PC136,PC137,PC138,PC140, PC147,PC148,PR173,PR174,PR175,PR176, PQ44,PQ46,PQ47,PU17,PL17,PH6 120W(4-phase)
POP
90W(3-phase)
UNPOP
4
4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS, Date: INC. A
B
C
Compal Electronics, Inc. CPU_CORE_Power stage 2 Document Number
Rev 0.1
LA-2101 Saturday, November 22, 2003 D
Sheet
52
of
52
