Ts-7500 Schematic

Transcript

3.3V U2 FB8 USB_HOST0_DP USB_HOST0_DM USB_HOST1_DP USB_HOST1_DM R38 11 12 19 18 16 VDD_33 USB0_DP VDD_33 USB0_DM VDD_33 USB1_DP VCCA_U2O_33 USB1_DM DEV_AN_33 VDD_AN_POW_33 HOST_USB_RES VDD_HOST_AN33 510 VDD_AN_ETH33 VDD_AN_ETH33 USB_DEV_DP USB_DEV_DM R45 127 126 125 DEV_USB_DP VDD_RAM_25 DEV_USB_DM VDD_RAM_25 HOST_PLL_18 DEV_USB_RES SYS_PLL_18 12.0K CPU_UART_RXD 107 108 VDD_CORE_18 UART_TXD0 VDD_CORE_18 UART_RXD0 Re s . PU VDD_CORE_18 VDD_CORE_18 GPIO_A28 GPIO_A29 SPI_CLK SPI_MOSI SPI_MISO 118 119 117 116 115 SPI_CS0# GPIO_A28 SPI_CS1# GPIO_A29 SPI_CLK GPIO_A27 VDD_CORE_18 VDD_CORE_18 RX+ SPI_MOSI RX- SPI_MISO SDA 103 128 C77 C78 .1 uF .1 uF 123 33 13 FB7 23 3.3V 29 64 2.5V 75 C75 C76 .1 uF .1 uF 15 PHY_GND 38 7 6 20 32 47 10/ 100 Et he rne t 82 98 109 121 27 J5 28 4 GPIO_A26 TX+ SCL 3.3V 39 1.8V VDD_CORE_18 CPU_UART_TXD 2 TXREF_RES 5 RX+ RX- 25 C104 SCL/ GPIO_A14 SDA/ GPIO_A13 R14 100 24 22 R32 6 RX_CT ALIGN 11.5K 10 nF ALIGN INT28 GPIO_A0 GPIO_A1 5 111 112 JTAG_CLK RAM_D0 RAM_D1 INT29/ GPIO_A0 RAM_D2 INT30/ GPIO_A1 RAM_D4 UART0/ GPIO_A2 RAM_D5 GPIO_A3 GPIO_A15 GPIO_A16 GPIO_A17 114 8 9 10 RAM_D6 I2SDR/ GPIO_A3 RAM_D7 GPIO_A22 GPIO_A23 JTAG_DOUT 44 45 74 DATA_00 73 DATA_01 72 DATA_02 71 DATA_03 70 DATA_04 69 DATA_05 68 DATA_06 67 DATA_07 C105 3 POE_RX 10 nF 1 R13 100 2 Re s e t La t ch 35 36 RAM_D8 I2SWS/ GPIO_A16 RAM_D9 I2SCK/ GPIO_A17 RAM_D10 RAM_D12 LED0/ GPIO_A22 RAM_D13 LED1/ GPIO_A23 RAM_D14 LED2/ GPIO_A24 RAM_D15 RAM_ADD0 V25_CONTROL RAM_ADD1 RAM_ADD2 V18_CONTROL RAM_ADD3 34 1.2V 66 RAM_ADD4 V125_CONTROL RAM_ADD5 REF_IN_1.25V RAM_ADD6 R17 RAM_ADD7 3.3V 3.3V POR 226 1% U3 3 U5 R39 2 WD_RESET# UN-RESET VCC 510 RESET# C72 3 32KHZ 1 1 6 D VCC CLK Q CLR# GND 5 CPU_CLKOUT 4 LOW_VOLT# ST1001S-2.9V 120 106 63 DATA_08 62 DATA_09 61 DATA_10 60 DATA_11 59 DATA_12 CPU_TCK 74LVC1G175 JTAG_TMS OD Out put JTAG_DIN 104 101 105 100 R76 RAM_ADD8 CLK_32768KHZ RAM_ADD9 RAM_ADD10 CLK_OUT RAM_ADD11 RAM_ADD12 58 DATA_13 57 DATA_14 56 DATA_15 11 12 ETH_LEFT_LED# 3.3V 99 RAM_WR# JTAG_TCK RAM_RAS# JTAG_TMS RAM_CAS# JTAG_DIN RAM_CS# JTAG_DO RAM_CKE RAM_CLK 42 R27 XTAL_25_OUT RAM_BA0 30 C103 122 Y2 6 1 ADD_01 92 ADD_03 ADD_04 90 ADD_05 89 ADD_06 88 ADD_07 87 ADD_08 86 ADD_09 85 ADD_10 84 ADD_11 83 ADD_12 Gre e n SHD 15 16 RLED+ Ye llow RLED- R19 RJ_POE_4602 ETH_RIGHT_LED# ADD_02 91 POE_78 226 1% EC-MJKF4602-PA08 FRAME Le ft LED (Gre e n) Link / Act ivit y FB3 RAM_BA1 NC RAM_DM1 VFS_PGM RAM_QS0 STAR_8132 4 10 nF 80 RAM_WR# 78 RAM_RAS# 79 50 51 RAM_CAS# RAM_CS# RAM_CKE 52 53 RAM_CLK# RAM_CLK 77 RAM_BA0 76 RAM_BA1 XTAL_25_IN RAM_DM0 680K U9 94 93 POE_45 10 JTAG_RST# RAM_CLK# 41 FPGA_25MHZ ADD_00 LLED- SHD 13 9 LLED+ 226 1% DATA_[00: 15] POE_TX ADD_[00: 12] CPU_RESET# 680K 95 SYS_RESET# 1.0K R26 TXPOE_78 R20 POE_RX 8 2 GND .1 uF 31 POE_TX 7 TX+ POE_45 14 CONTROL_25 TX_CT I2SSD/ GPIO_A15 RAM_D11 43 18 PHY_GND INT28/ USB_INT RAM_D3 113 17 RAM_QS1 TEST_MODE_EN 55 54 49 48 RAM_DM0 RAM_DM1 RAM_QS0 RAM_QS1 XTAL-HC49 PHY_GND GND_HOST_AN GND_HOST_AN GND GND GND GND GND GND GND GND 3 14 17 37 40 46 65 81 96 GND FB9 97 SN74LVC2G04DCKR GND 15 pF 102 15 pF EN_SD_POWER 110 C38 GND_DEV_AN DUAL04 C37 GND_USBD_AN 3 1 SD_POWER# 25MHz 124 4 2 GND_AN_ETH GND GND_AN_ETH VCC 26 5 21 3.3V Te chnologic Sys t e ms Da t e Tit le : TS-7500 CPU, Et he rne t , POR Re v: De s igne r RLM Ma y 30, 2009 She e t 1 of 4 XP2-5 ha s : 5K LUTS 2 PLLs 9 blocks of 1Kx18 Block RAM 44-Pin DIO He a de r 12 18x18 Mult iplie rs 100 I/ O wit h 144 pin pa cka ge FPGA wit h 5000 LUTs "ins t a nt ON" = a bout 1.5 mS input PLL clock = 10 MHz min (Bot t om) HD2 DIO_[05: 40] POE_TX POE_78 DIO_40 DIO_38 DIO_36 DIO_34 DIO_32 DIO_30 DIO_28 DIO_26 DIO_24 DIO_22 DIO_20 SDA 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 DIO_14 DIO_12 3.3V DIO_08 DIO_06 JTAG_DIN JTAG_TMS 14 12 10 8 6 4 2 POE_4 POE_3 POE_2 POE_1 DIO_40 DIO_39 DIO_38 DIO_37 DIO_36 DIO_35 DIO_34 DIO_33 DIO_32 DIO_31 DIO_30 DIO_29 DIO_28 DIO_27 DIO_26 DIO_25 DIO_24 DIO_23 DIO_22 DIO_21 DIO_20 DIO_19 DIO_18 DIO_17 GND 5V SPI_CLK/ DIO MOSI/ DIO MISO/ DIO CS# / DIO 3.3V REBOOT# / DIO CON_RXD MODE1/ TXD DIO_6 MODE2/ DIO JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO 43 CPU_UART_TXD POE_45 41 37 CPU_UART_RXD POE_RX 13 39 DIO_39 28 37 SPI_CLK DIO_37 15 35 DIO_35 SPI_MOSI DIO_33 SPI_MISO IO IO_CLK OUT_CSSPIN IO_CLK IP IO_CLK CLK+ IO IO 31 30 DIO_31 29 46 DIO_29 27 GPIO_A0 DIO_27 25 GPIO_A1 39 137 IO_CLK IO CLK- IO IO IO IO IO IO_CLK DIO_23 21 SDA I2C SCL DIO_21 19 17 DIO_19 GPIO_A3 SCL GPIO_A15 GPIO_A16 15 5V 13 1 2 32 GPIO_A17 27 11 SPI_CS0# DIO_11 9 SPI_CS1# DIO_09 7 GPIO_A28 GPIO_A29 38 40 3 JTAG_CLK 1 JTAG_DOUT 78 17 141 DIO_05 INT28 LED0 IO IO IO IO IO 90 125 R21 56 GPIO_A22 MODE1 a nd MODE2 s t a t e s 7 9 JTAG_DIN 57 TS-7500 1 Boot s from 1 SPI Fla s h R22 142 GPIO_A23 LED1 IO IO IO_CLK IO IO IO IO IO IO IO IO IO_CLK ha ve 4.7K re s is t or pull-ups on TS-7500 1 0 SD ca rd 94 LED0 s hows bot h 50 Off-boa rd Fla s h 0 IO_CLK DIO_08 91 DIO_09 93 DIO_11 99 DIO_12 3.3V 58 112 65 Re s e rve d DIO_14 104 DIO_19 143 DIO_20 100 VCCO_0 IO VCCO_0 IO VCCO_1 IO IO DIO_13 133 95 105 76 VCCO_2 IO_CCLK VCCO_2 IO IO VCCO_3 IO DIO_21 101 DIO_22 103 DIO_23 107 42 49 DIO_24 109 IO VCCO_4 DIO_26 108 VCCO_5 IO VCCO_5 IO_CLK IO_CLK DIO_25 110 IN_CFG1 33 DIO_27 4 113 DIO_28 14 114 DIO_29 IO IO IO_CLK IO IO IO_CLK IO IO IO IO_CLK IO IO 115 DIO_30 116 DIO_31 119 DIO_32 120 DIO_33 62 DIO_34 121 DIO_35 77 DIO_36 89 VCCO_6 IO_INIT# 0 0 a ls o boot s from VCCO_7 IO IO 23 60 85 117 IO VCC_AUX1 IO VCC_AUX2 IO VCC_AUX3 IO_CLK but ca n be s wit che d t o off-boa rd Fla s h, but ma y CPU_CLKOUT 71 IN_CSSPIS IO 83 DIO_37 IO IO IO be cha nge d in t he fut ure FPGA_25MHZ 144 IO IO 70 IO VCC_JTAG IO DIO_38 69 DIO_39 134 DIO_40 67 SPI bus de fa ult t o DIO IO But ca n be s wit che d 26 FPGA_CONFIG# 25 CFG0 IO TOE IO IO IO 130 1.2V 54 24 59 92 RTC_SDA 127 84 RTC_SCL 138 118 IO VCC_INT1 VCC_INT2 IO VCC_INT3 IO_DONE VCC_INT4 RTC_INT1 48 102 EN_SD_POWER 45 19 18 35 22 21 20 SD_D0 SD_D1 SD_D2 SD_D3 SD_CMD SD_CLK 124 52 31 6 44 FLASH_CLK FLASH_MOSI FLASH_MISO SER_FLASH_CS# SER_FLASH_WP# 55 61 123 53 66 43 IO 132 73 ETH_LEFT_LED# ETH_RIGHT_LED# 5 36 10 8 47 3.3V 131 LED1 3 LATTICE_XP2_144 Gre e n GND15 GND14 2 139 GND13 135 126 GND11 GND10 GND9 GND12 111 106 97 86 GND7 GND6 GND8 75 68 64 GND5 JTAG_TMS 51 79 WD_RESET# 16 JTAG_CLK GND4 JTAG_TMS 81 UN-RESET 1 JTAG_DIN GND3 JTAG_CLK 80 129 U8 JTAG_DOUT 41 JTAG_DIN 82 GND2 JTAG_DOUT 29 VCC_PLL_1 IO GND1 t o SPI funct ion 3 t o Re s e t funct ion 34 But ca n be s wit che d 12 de fa ult s t o DIO IO RN2-B 4.7K 98 VCC_PLL_0 IO Re boot # pin (DIO_09) 3 122 VCC_AUX4 IO 140 11 32KHZ VCCO_7 IO a ft e r powe r up (or re s e t ) 2 4 Cons ole a lwa ys is e na ble d DIO a ft e r done boot ing 136 IO IO_CLK Act ivit y a nd Link 0 74 IN_PROGRAM# 226 1% 72 1 DIO_07 IO IO_CLK MODE1 a nd MODE2 0 88 RN2-A 4.7K 63 IO JTAG_TMS Mode 2 1 DIO_06 IO IO DIO_07 5 IO IO IO DIO_13 HD_JTAG44_7500 Mode 1 96 DIO_25 23 226 1% CPU_RESET# is de a s s e rt e d 1.8V ma x. DIO_05 128 33 a re la t che d whe n 87 Re d 4 DUAL_RTA_LED R23 226 1% R18 226 1% Pa ge 37 of Da t a She e t (Hot Socke t ing) Powe r Supplie s ca n be s e que nce d in a ny orde r but mus t be monot onic Pull-up a nd pull-down re s is t ors a re 6 t o 30K ohms Te chnologic Sys t e ms Da t e Ma y 30, 2009 All I/ O line s a re t ri-s t a t e d during powe r cycling Tit le : Re v: TS-7500 FPGA, DIO He a de r, JTAG De s igne r RLM She e t 2 of 4 64 Mbyt e DDR1 SDRAM Micro SD Ca rd Socke t 3.3V 2.5V 2 R77 C120 Q1 1.2V 1 SD_POWER# 1.0K 3 49 19 50 14 53 ADD_[00: 12] CN7 SD_D0 DATA_0 DATA_1 1 SD_D2 DATA_2 GND 2 SD_D3 FRM1 COMMAND FRM2 5 SD_CLK 6 DATA_3 3 SD_CMD CLK FRM3 FRM4 29 30 31 32 35 36 37 38 39 40 28 41 42 17 ADD_00 ADD_01 ADD_02 ADD_03 ADD_04 ADD_05 ADD_06 ADD_07 ADD_08 ADD_09 ADD_10 ADD_11 ADD_12 .1 uF 8 SD_D1 VDD 4 9 10 11 RAM_BA0 12 RAM_BA1 CONN_MICRO_SD RAM_DM0 2.5V RAM_DM1 R51 2.00K RAM_RAS# RAM_CAS# RAM_WR# 26 27 20 47 23 22 21 NC NC VCCIO VCCIO VCCIO VCCIO VCCIO A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 NC/ A13 4MB Se ria l 46 RAM_CLK# 45 R15 100 RAM_CS# FLASH_MISO FLASH_MOSI FLASH_CLK 2 5 6 CS# VCC HOLD# DOUT WP# DIN GND CLK C65 .1 uF C66 .1 uF 1.2V LDQS UDQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 BA0 BA1 R12 100 R11 100 16 RAM_QS0 51 DATA_[00: 15] RAM_QS1 2 4 5 7 8 10 11 13 DATA_07 DATA_06 DATA_05 DATA_04 DATA_03 DATA_02 DATA_01 DATA_00 54 56 57 59 60 62 63 65 DATA_08 DATA_09 DATA_10 DATA_11 DATA_12 DATA_13 DATA_14 DATA_15 LDM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UDM RAS# CAS# WE# GNDIO GNDIO GNDIO GNDIO GNDIO CKE CLK# CLK 6 12 52 58 64 34 GND 48 GND 66 GND CS# DDR1_RAM DDR RAM Not e s U13 1 C64 .1 uF RAM_CLK Fla s h SER_FLASH_CS# 24 3 9 55 61 15 25 NC 43 NC RAM_CKE 44 C63 .1 uF 1 VCCINT 18 VCCINT 33 VCCINT VREF DNU DNU C67 7 C62 .1 uF 10 nF U10 C82 .1 uF C61 .1 uF 8 3.3V The DDR clock diffe re nt ia l pa ir is t he mos t crit ica l t ra ce on t he e nt ire boa rd 7 3 SER_FLASH_WP# 3.3V 1 The da t a line s in e a ch byt e la ne ca n be s wa ppe d on t he RAM chip for opt ima l la yout 4 2 DIO_05 4.7K Exa mple : D0 a nd D5 ca n be s wa ppe d, but not D7 a nd D8 FLASH_SERIAL RN1-A 3 RN1-B 4 DIO_07 6 DIO_08 4.7K The t ra ce le ngt h of e a ch da t a line (in a s ingle byt e la ne ) a nd t he re s pe ct ive 5 QS a nd DM s igna ls mus t be ma t che d t o wit hin 2.5 mm RN1-C 4.7K 7 Addre s s a nd Comma nd s igna ls ca n be groupe d t oge t he r, but mus t be is ola t e d RN1-D 8 JTAG_TMS 4.7K from da t a a nd M_DSQ a nd M_DM s igna ls (by a t le a s t .5 mm) 1 RN3-A 2 CPU_TCK 4.7K Or run t he m on diffe re nt la ye r 3 RN3-B SPI_MOSI 4 JTAG_DIN 5 4.7K RTC 3.3V 7 3 RN5-D 2.2K 8 5 RN5-B 2.2K 4 7 5 RTC_SDA 7 RTC_INT1 SCL VCC 8 1 OUT 3 XIN 5 XOUT GND 4 CPU_CLKOUT RN4-A 2 SDA RN4-B UN-RESET 4 SCL 7 RN4-C 6 RN2-D 4.7K JTAG_CLK 8 2.2K K1 7 RN4-D 8 FPGA_CONFIG# 2.2K 3 XTAL_SMT_8X3 8 C83 M41T00S 2 RN3-D 2.2K 4 12 pF 6 I2C bus 3 .1 uF 2 RN2-C 4.7K EN_SD_POWER 2.2K Y1 1 3.3V SDA BAT 1 6 4.7K U12 6 RN3-C 4.7K RN5-C 2.2K 6 RTC_SCL 5 R75 1.00K Te chnologic Sys t e ms Da t e Ma y 30, 2009 1 RN5-A 2.2K Tit le : TS-7500 RAM, SD Ca rd, RTC, Fla s h 2 Re v: De s igne r RLM She e t 3 of 4 USB De vice Port 3.3V Re gula t or 3.3V J2 FB4 3.3V U6 3 5V VIN 4 3.3V 2 3.3V GND C99 C13 1 C70 10 uF .1 uF C100 C71 .1 uF C101 10 nF LM1117MP-3 470 uF Single USB 5V C102 10 nF C56 C57 C58 C59 .1 uF .1 uF .1 uF .1 uF C114 10 nF C116 C119 1 10 nF 10 nF 2 USB_DEV_DM 10 nF 3 USB_DEV_DP 10V 4 FB5 5V D- 5 FRAME D+ 6 FRAME GND CONN_USB_SINGLE 3.3V FRAME C84 C85 C86 C87 C88 .1 uF .1 uF .1 uF .1 uF .1 uF C112 10 nF C113 C79 C121 10 nF .1 uF 10 nF 1.2V Re gula t or 3.3V USB Hos t Port s R50 2.00K FB2 PF1 R99 5V 1.8V LOW_VOLT# 1 ohm PTC_750 J6 1 2 3 4 5V R47 18.7K D USB_HOST0_DM Q4 3 1 750 uS t ime cons t a nt - U7 + 2 USB_HOST0_DP FDN335N 5 G 4 LMV321_DCK USB_HOST1_DP C68 1.2V R44 12.0K FB1 Q3 C15 C74 C51 C117 10 uF .1 uF .1 uF 10 nF 1 11 FRAME 12 FRAME 1.2V CONN_USB_DUAL .1 uF 2 9 FRAME 10 FRAME 5 6 7 8 USB_HOST1_DM S Dua l USB C73 C106 .1 uF 10 nF C107 10 nF FRAME C108 10 nF 3 2.5V Re gula t or 1.8V Re gula t or R98 3.3V 1 ohm 2 R10 5 5V C90 4 VIN SW EN PGND 1 10 uF C92 10 uF 2 R9 15K C80 C81 .1 uF .1 uF C109 C110 C111 10 nF 10 nF 10 nF C53 C54 C55 .1 uF .1 uF .1 uF Es t . 100 mA loa d 3 1.8V C91 FB 100 Es t . 450 mA loa d 1.84V nomina l 3 PIN 10 uF 6 CONTROL_25 L2 COIL3.3UH U11 FB6 Q2 1 2.5V C115 10 nF C14 C69 C52 10 uF .1 uF .1 uF C118 10 nF C60 .1 uF AGND FAN2002 7 DFN pa cka ge R33 11.5K FAN2002 1.3 MHz fre q. 50 uA quie s ce nt Vout = 800mV * [1+ Rt op/ Rbot ] Te chnologic Sys t e ms Da t e Ma y 30, 2009 > 90% e ff. a t 100-400 mA loa d 1000 mA ma x loa d Tit le : Re v: TS-7500 Powe r Supplie s , USB Port s De s igne r RLM She e t 4 of 4