Transcript
USB De vice Port a nd SiLa b uC SiLa b 4.7V 24 mA ma x loa d
D8 1
FB17
USB De vice Micro Port
BOOST_5.1V
3
SiLa bs
U8
220 ohm C192 .1 uF
5.25V Ma x 4
USB_SILAB_P
USB
5
USB_SILAB_M
USB_DP
PWR_IN
2
C77 10 uF
USB_DEV_5V 1 ohm
4.7V
7
64K
USB_DM
R73
SILAB_3.3V 3
Fla s h
4
USB_5V_DET
RN21-C 47K
1.5K
6
P0.0
Progra m
DEBUG_CLK/ RESET# P0.2
10
SILAB_DATA
DEBUG_DATA
A/ D
P0.3 TXD0_P0.4
A/ D
R123
18
VIN
RXD0_P0.5
P2.0
237K
P0.6
2
6
EN_PWR_RAILS#
3
1 32 31 30 29 28
EN_SILAB_GRN_LED
4 5
CPU_RESET#
P1.1 P1.2 R20
17
BOOST_5.1V
P1.3
P2.1
26 25
23
R118 20.5K
A/ D
R84
P1.5
TXD
AUX_3.3V 9.1K
RXD 16
P1.6
15
P1.7
14 13
Sca le = 50%
6
1
I2C_DAT
2
I2C
3 AN_SCAP_1
Ana log
4 TVS_USB2_NUP4114_SC88
SILAB_PWM
PWM 1
20
RN16-A
8
CONSOLE_RXD SILAB_3.3V
19
P2.2
SiL_3.3V
P2.3
6 C78 10 uF
C191 .1 uF
P2.4 P2.5
4.7V
I2C_CLK
22 21
5
P0.7_VREF
2
RN21-B
7
SILAB_CLK
47K
27
R57 RAM_1.8V
FRM
7
EN_TOP_OFF
20.5K R117 20.5K
GND
FRM
CONSOLE_TXD
REG_3.3V
R116
SENSE
EN_CHRG#
1.5K
AN_CHRG
8
D+
CONN_USB_MICRO-B_RA
AN_REG_5V P1.4
CPU_CORE
FRM
9
TVS2
EN_2.5V_REF
AN_SCAP_2
A/ D
CPU_1.8V
FRM
D-
CPU_PSWITCH
24
25.5K
R85 9.1K
5V
6 P1.0
Sca le = 50%
2
USB_SILAB_M
R27 28K
Sca le = 10.6%
Sca le = 44.6%
1
USB_SILAB_P P0.1
9
SILAB_CLK
Micro B
RN11-C 10K
USB_VBUS
A/ D
P2
5
3
USB_5V_DET 8
RN16-D
12 11
EN_SILAB_GRN_LED EN_2.5V_REF
P2.6 PAD
33
P2.7 GND
3
2 C193 .1 uF
U31
475
C72 10 uF
2
LED1
SiLa b 2500 mV SILAB_C8051F381_QFN32
REF_AN431A_SOT23
1
1
SiLa b LED
Gre e n
R88 CPU_3.3V 9.1K
Sca le = 50%
R80 270
3 R86 9.1K
A/ D full s ca le = 2.50V SiLa b mus t us e Int e rna l A/ D Re fe re nce whe n EN_2.5V_REF off
Pus h Swit ch
D10 1
AUX_3.3V
3 SW1
SiLa b pin 20 mus t be t ri-s t a t e d
a nd de a s s e rt ing CPU_RESET#
SILAB_3.3V
2
a nyt ime MX286 is powe re d off Aft e r MX286 powe re d up, wa it 200 ms be fore driving pin 20
2 1 2 3 4
RN16-B 1.5K 7
SW_PUSH_RT_TH
PUSH_SW#
Pin 20 mus t be re a d be fore de a s s e rt ing CPU_RESET# It s s t a t e is t he "CHARGE OFF" Jumpe r s t a t us
DIODE_BAT54-CC_SOT23
SILAB_DATA
3
RN5-C 10K
Te chnologic Sys t e ms
Da t e
Oct . 22, 2015
6
Tit le :
TS-7553-V2 SiLa b Microcont rolle r
Re v:
A
De s igne r
She e t
3 of 17
Re la y D9 K2
1 1
CN8
NO COM NC
SW_5V
3
3
SW_5V
2
2
ZigBe e Ra dio
5 DIODE_BAT54-CC_SOT23
3
2 4 1
Socke t
RELAY_SPDT_5V_5A_TH
6
3
D
D Q3-A
G 2
EN_RELAY
CN4 FB21 3
XBEE_TXD
Q3-B
G 5
S 1
XBEE_RXD
S 4
DIN
2
VCC
3
CPU_RESET#
RN14-C 1.5K
RN15-C
6
AUX_3.3V 220 ohm
DOUT DIO0
3
1
5
RESET#
DIO1
1.5K DIO2
20
DIO_0
19
DIO_1
18
DIO_2
6 DIO3 12
DIO_8
CTS# DIO4
9
DIO_7
DTR# DIO5
16
DIO_6
RTS# / DIO6 DIO12 PWM/ RSS/ DIO10
13
ON/ SLP#
14
DIO11
17
DIO_3
11
DIO_4
15
DIO_5
4 6 7
VREF
8
DNC
Edge Conn.
GND
10
XBEE_SOCKET_TH
CN99
Edge Conn. A1 AUX_3.3V RXD2_SPI_CLK SPI_OFF_BD_SEL# TXD2_SPI_MOSI
B1 A2 B2 A3 B3
RXD3_SPI_MISO
A4 B4
GND
P3
XBEE_TXD
3
XBEE_RXD
2
D_IN
VCC
D_OUT
DNC
1 8
SPI_PWR 5 SPI_CLK
RESET#
BOOT_SELECT
DTR# 6
SPI_MOSI 7
SPI_DATA3
4 SPI_MISO
9
DIO_7
DIO_10 DIO_11 DIO_12
GND
10
SPI_DATA2 SOCKET_10X1_2MM_TH
SPI_OFF_BD_CS# 7553_FLASH_CS#
A5 B5 A6 B6 A7
SILAB_DATA
B7 A8
SILAB_CLK
B8 A9 B9
CONSOLE_TXD CONSOLE_RXD AUX_3.3V
A10 B10 A11 B11
SPI_CPU_CS# SPI_FLASH_CS# JTAG_TCK OPTION JTAG_TMS UC_DATA JTAG_TDI UC_CLK JTAG_TDO RESET# CONSOLE_TXD CONSOLE_RXD JTAG_PWR GND
CON22_EDGE_PCIE
Te chnologic Sys t e ms Tit le :
TS-7553-V2 Mis c
Re v:
A
De s igne r
Da t e
Oct . 22, 2015
She e t
4 of 17
MX286 ARM9 CPU LCD
UARTs , ADC
U4-D
U4-A
LCD_D23 AUART0_TX AUART0_RX
H5 G5
LCD_D22 UART0_TXD
LCD_D21
UART0_RXD
LCD_D20 LCD_D19
AUART0_RTS/ DEBUG_TXD AUART0_CTS/ DEBUG_RXD
AUART1_TX AUART1_RX
J7
LCD_D18
UART0_RTS
LCD_D17
J6
UART0_CTS
K4 L4
LCD_D16
UART1_TXD
LCD_D15 LCD_D14
UART1_RXD
LCD_D13 LCD_D12 K5 J5 F6
NC on MX283
F5 H6 H7 L6
a nd 286
K6 M5 L5
LCD_D11
AUART1_CTS AUART1_RTS
ADC0
AUART2_RX
ADC1
AUART2_TX ADC2
AUART2_CTS AUART2_RTS
ADC3
AUART3_CTS
ADC4
AUART3_RTS ADC5
AUART3_RX AUART3_TX
ADC6 ADC0_HS
C15
LCD_D10 LCD_D09
C9
LCD_D08
C8 D9
LCD_D07 D13
LCD_D06 LCD_D05
D15
NC on MX283
C14 B14
LCD_D04 N1 N5 M1 L1
a nd 286
MX286_CPU_IND
GPMI_WRN/ SSP1_SCK GPMI_RDY1/ SSP1_CMD GPMI_D00/ SSP1_D0
SPI
GPMI_D01/ SSP1_D1 GPMI_D02/ SSP1_D2
SCK = CLK
GPMI_D03/ SSP1_D3
SSP0_DATA1 SSP0_DATA2 SSP0_DATA3
D0 = MISO
SSP3_SCK
D3 = CS#
A6
SSP3_MOSI
SD0_CLK
A4
SD0_CMD
B6
SD0_D0
C6
SD0_D1
D6
SD0_D2
A5
SD0_D3
SSP3_CS1# SSP3_CS2#
MX286 a dds
SSP0_DATA6/ SSP2_CMD SSP0_DATA4/ SSP2_D0
SD2
SSP2_SS1/ SSP2_D1 SSP2_SS2/ SSP2_D2 SSP0_DATA5/ SSP2_D3
B4
LCD_SPI_CLK
D5
LCD_SPI_MOSI
B5
LCD_CMD#
D3
LCD_RESET#
D4
EN_LCD_BK_LT
C5
LCD_CS#
SPI Boot
SSP2_MOSI/ UART2_TXD SSP2_MISO/ UART3_RXD SSP2_SS0/ UART3_TXD
C1
NC on MX283 a nd 286
E1 D1 B1 B2 C2 A2 D2
SSP1_CMD
SSP0_DETECT
A3 C3 B3 C4
D10
SPDIF
D7
SSP1_SCK SAIF0_MCLK/ PWM3
SSP3_MOSI SSP3_SS0
TXD_CAN0
M8
RXD_CAN0
L8
TXD_CAN1
M7 M9
GPMI_D07
CAN_TX0
GPMI_D05
CAN_RX0
I2C0_SCL
CAN_TX1
I2C0_SDA
CAN_RX1
PWM1/ DEBUG_TXD PWM2/ USB0_ID
RXD2_SPI_CLK TXD2_SPI_MOSI RXD3_SPI_MISO TXD3_SPI_CS#
PWM3
U3.D3 a nd U3.D4 a re e xt ra
SAIF0_LRCLK/ PWM4 SAIF1_SDATA0/ PWM7 SAIF0_SDATA0/ UART4_TXD/ PWM6
LCD_D01
LCD_VSYNC
LCD_D00
LCD_CS/ ENABLE LCD_RD_E/ VSYNCH LCD_WR_RWN/ HSYNCH LCD_RESET/ VSYNCH LCD_RS/ DOTCLK
4
T4 U4 R3 T3
U3 U2
5
PUSH_SW#
47K
DIO_2 DIO_3 DIO_4 DIO_5
ACCEL_INT ACCEL_INT2
T2 T1
JP_SD_BOOT#
R2
JP_UBOOT#
R1
EN_ETH_3.3V# DC_DIO_6
P3 P2
DC_DIO_5 DC_DIO_4
LCD_D[00: 23]
P1 N2 M3
LCD_D06 LCD_D05
M2
LCD_D04
L3
LCD_D03
L2 K3
LCD_D02 LCD_D01
K2
LCD_D00
P5
EN_HOST_USB_5V
P4 K1
EN_232_TRANS
M6
EN_CAN#
M4 RN6-A
1
AUX_3.3V
10K
MX286_CPU_IND
P8
RN23-D
EMMC_CLK
N8
EMMC_CMD
U8
EMMC_D0
T8
EMMC_D1
R8
EMMC_D2
U7
EMMC_D3
LCD_RS bia s e d high
e MMC Int e rfa ce
LCD_RS low = us e OTP
PWM4
Pa ge 1313 of Da t a s he e t
RESET#
JTAG_TRST
ETH_RESET#
G7 G6 E8 E7
NC on MX283 DIO_9 DIO_10 DIO_11
R6
SPI_OFF_BD_SEL#
L9
DIO_6
N7
DIO_7
N9
DIO_8
P6
SPI_OFF_BD_SEL# s hould be t ri-s t a t e
DIO_0
P7
unt il done Boot ing.
DIO_1 3
N6
OTG_HOST_MODE#
U6
RN23-C
6
Drive it low
t o re a d/ writ e e xt e rna l SPI Fla s h
AUX_3.3V
47K
EN_RELAY
T7
EN_SPI_BOOT_FLASH
T6
RED_LED#
R7
GREEN_LED#
C7
I2C_CLK
D8
I2C_DAT
K7
Whe n done Boot ing from SPI Fla s h, Drive EN_SPI_BOOT_FLASH t o logic ze ro The n UARTs ca n be us e d ins t e a d of SPI
CONSOLE_RXD
L7
CONSOLE_TXD
K8
AUTO_485_CLK
E9
EN_SD_3.3V#
E10
2 da t a line s for SPI x4 re a d
JTAG_RTCK
SSP1_DATA0
SSP3_SCK
GPMI_D04
PWM0/ DEBUG_RXD
SSP1_DATA3
SSP3_MISO
GPMI_D06
RXD_CAN1
12 MHz de fa ult boot clock SSP2_SCK/ UART2_RXD
GPMI_RDY0/ USB0_ID
4 CAN s igna ls a nd ba ll D7
SSP0_DATA7/ SSP2_SCK
LCD_HSYNC
POWER_FAIL
R4
CMD = MOSI
SSP3_CS0#
SSP0_DATA0
LCD_D02
UART1_CTS
U5
8
U4-F
SD0
LCD_ENABLE
UART1_RTS
T5
U4-C
SSP3_MISO
SSP0_SCK
LCD_D03
NAND, PWM JTAG, I2C
Audio SD Ca rd SPI Boot SSP0_CMD
LCD_DOTCLK
R5
Pa ge 1311 - Winbond SPI x2 a nd x4 s upport e d
PWM out put s ca n be 24 MHz
D14 E14
1
RN7-A
8
divide d by 16-bit int e ge r
CPU_3.3V
10K JTAG_TCK
EVK s che ma t ic re fe re nce s a 8Mbit Winbond chip
JTAG_TDI JTAG_TDO JTAG_TMS
E11
Allows clock 12MHz a nd lowe r
E12 E13 D12
Te chnologic Sys t e ms
Da t e
Oct . 22, 2015
XBEE_TXD MX286_CPU_IND
SAIF0_BITCLK/ UART4_RXD/ PWM5
F7
TS-7553-V2
Tit le :
XBEE_RXD
MX286_CPU_IND
All JTAG ha ve 47K int e rna l PU e xce pt RTCK
Re v:
A
MX286 CPU
De s igne r
She e t
5
of
17
FB7 SW_5V 220 ohm U4-G
C152 .1 uF
CPU_1.8V VDD5V C149 .1 uF
C150 .1 uF
C151 .1 uF
F9 G9 G8 F8
N17
VDDIO18_2 VDD4P2_DCDC
VDDIO18_1
C139 .1 uF
C140 .1 uF
C141 .1 uF
C142 .1 uF
C143 .1 uF
C144 .1 uF
C145 .1 uF
C146 .1 uF
C147 .1 uF
C148 .1 uF
E16 J10 J9 N3 J8 H8 G3 E6
G12 C132 .1 uF
C133 .1 uF
C134 .1 uF
C135 .1 uF
C136 .1 uF
C137 .1 uF
C138 .1 uF
K12 G11 G10 F11 F10
VDDIO33_8
VSSA2_A
VDDIO33_7
VSSA1
VDDIO33_6
VSSD6
VDDIO33_5
VSSD5
VDDIO33_4
VSSD4
VDDIO33_3
VSSD3
VDDIO33_2
VSSD2
VDDIO33_1
VSSD1
VDDIO33_0
VSSD0 VSSIO_EMI9
VDDD7
VSSIO_EMI8
VDDD6
VSSIO_EMI7
VDDD4
VSSIO_EMI6
VDDD3
VSSIO_EMI5
VDDD2
VSSIO_EMI4
VDDD1
VSSIO_EMI3
VDDD0
VSSIO_EMI2 VSSIO_EMI1 G13
CPU_1.8V
G17 C161 .1 uF
C186 .1 uF
C125 .1 uF
C128 .1 uF
C129 .1 uF
C130 .1 uF
C131 .1 uF
G15 L13 N15 N13 M12 M11
CPU_3.3V
R13 P11 M10
CPU_3.3V
C56 22uF
C61 10 uF
C114 .1 uF
C157 .1 uF
C115 .1 uF
C117 .1 uF
C118 .1 uF
C119 .1 uF
C123 .1 uF
VSSIO_EMI0
VDDIO_EMI10
VSSIO_EMIQ2
VDDIO_EMI9
VSSIO_EMIQ1
VDDIO_EMI8
VSSIO_EMIQ0
VDDIO_EMI7
VSSIO18_2
VDDIO_EMI6
VSSIO18_1
VDDIO_EMI5
VSSIO18_0
VDDIO_EMI4
VSSIO33_8
VDDIO_EMI3
VSSIO33_7
VDDIO_EMI2
VSSIO33_6
VDDIO_EMI1
VSSIO33_5
VDDIO_EMI0
VSSIO33_4 J13 K15 R15
VSSIO33_3
VDDIO_EMIQ2
VSSIO33_2
VDDIO_EMIQ1
VSSIO33_1
VDDIO_EMIQ0
VSSIO33_0 C13
VDD_4P2 C55 22uF
C63 10 uF
C153 .1 uF
D16
VDDIO33_EMI
VSSIO_EMI10 F12
CPU_CORE
A13
VDDIO18_0
VSS_USB A7
E17
VDDIO18_3
VDD1P5 CPU_3.3V
C68 10 uF
A9 B11
R39 0.10 ohms
B13 C16 L11 L10 U1
C154 .1 uF
J12 H12
VDD4P2 is a n out put --
A1 F14
only fe e ds t wo 1.2K re s is t ors
F16 H14 L12 M16
Re g VDD1P5 goe s t o not hing
P16 P14 T14 U17 R12 R10 J15 M14 H16 H10 H9 H11 B7 E15 K11 K10 N4 K9 J11 H3 E5
VDDA1
MX286_CPU_IND
CPU_1.8V U4-H
CPU_1.8V B17
DCDC_VDDIO
DCDC_LN
C17
3.3V
C156 .1 uF
L5
DCDC_VDDA
15 uH
1.8V
C62 10 uF
C57 22uF
B16
CORE A16
DCDC_LP DCDC_VDDD
D17
CPU_CORE
1.2V C155 .1 uF
10K PU A14
C58 22uF
C185 .1 uF
t o 3.3V CPU_RESET#
C65 10 uF
RESETN
BATTERY
A15 D6
A17 C10 B9
CPU_3.3V
CPU_PSWITCH
6
RN22-C
3
A11
DCDC_GND
DCDC_BATT
C54 22uF
2
DEBUG_JTAG 1 = ETM
USB0DM
0 = Bounda ry
USB0DP
USB1DM PSWITCH
USB1DP
A10 B10
B8 A8
RN15-B
7
1.5K
USB_OTG_M USB_OTG_P
USB
R40 0.10 ohms
USB_HOST_M
1
USB_HOST_P RN15-A 1.5K
1 RN22-B 47K
7
VDD_4P2
TESTMODE
47K 2
B15
RN22-A 47K
XTALO
8
B12
8 C12
1V
Y1 XTAL_VDD
C165 .1 uF
XTALI XTALO_RTC XTALI_RTC MX286_CPU_IND
PSWITCH ca n be drive n t o 3.3V if a s e rie s 10K re s is us e d
A12 C11 D11
24 MHz C41
C42
15 pF
15 pF
Te chnologic Sys t e ms
Da t e
Oct . 22, 2015
Tit le :
TS-7553-V2 MX286 CPU Powe r
Re v:
A
De s igne r
She e t
6
of 17
DDR2 SDRAM
(128 or 256 MByt e ) RAM_D[00: 15]
MX286 RAM_A[00: 15]
RAM_D13
H17
RAM_D12
H13
RAM_D11
J14
RAM_D10
G14
RAM_D09
H15 G16
RAM_D08
EMI_A11 EMI_A10
EMI_D13
EMI_A09 EMI_D12
EMI_A08 EMI_A07
EMI_D11
EMI_A06
EMI_D10
EMI_A05 EMI_D09
EMI_A04 EMI_A03
EMI_D08
EMI_A02 EMI_A01 RAM_D07
M17
RAM_D06
L14
RAM_D05
P17
RAM_D04
P13
RAM_D03
N14
RAM_D02
P15
RAM_D01
M13
RAM_D00
N16
EMI_A00
EMI_D07
U11
RAM_A12
T10
RAM_A11
U13
RAM_A10
P10
RAM_A09
U9
RAM_A08
N11
RAM_A07
R9
RAM_A06
R11
RAM_A05
U10
RAM_A04
T11
RAM_A03
U14
RAM_A02
U12
RAM_A01
U15
RAM_A00
RAM_A00 RAM_A01 RAM_A02 RAM_A03 RAM_A04 RAM_A05 RAM_A06 RAM_A07 RAM_A08 RAM_A09 RAM_A10 RAM_A11 RAM_A12
EMI_D06
RAM_A13 EMI_BA2
EMI_D05
EMI_BA1
EMI_D04
EMI_BA0
N12
RAM_BA2
T12
RAM_BA1
T16
RAM_BA0
RAM_A14
EMI_D03 EMI_D02
EMI_CASN
EMI_D01
EMI_RASN
EMI_D00
EMI_WEN
U16
RAM_CAS#
RAM_BA0
R16
RAM_RAS#
RAM_BA1
F15
RAM_DQM1
M15
RAM_DQM0
K17 K16
RAM_DQS0_M
L16
RAM_CLK_M
L17
RAM_CLK_P
EMI_DQM1 RAM_CKE EMI_DQM0
EMI_CLKN EMI_CLK
RAM_DQS0_P
RAM_CKE
RAM_CS# RAM_DQM0
EMI_DQS0 RAM_DQM1 EMI_DQS0N RAM_RAS# EMI_CE0N
J16
RAM_DQS1_M
EMI_DQS1 EMI_CE1N
P9
EMI_DQS1N
RAM_1.8V
RAM_CS#
RAM_CAS# RAM_WE#
NC R53 7.87K
R17
RAM_ODT
NC
T17
RAM_ODT
K2 CKE L8 CS# F3 LDM B3 UDM K7 RAS# L7 CAS# K3 WE#
RAM_D02 RAM_D01 RAM_D05 RAM_D04 RAM_D03 RAM_D06 RAM_D13 RAM_D08 RAM_D12 RAM_D11 RAM_D10 RAM_D09 RAM_D14 RAM_D15
RAM_DQS0_P RAM_DQS0_M
VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9
128M x 16 256 MB
RAM_DQS1_P RAM_DQS1_M
A9 C1 C3 C7 C9 E9 G1 G3 G7 G9
RAM_1.8V
NC0 A2 NC1 E2
J2 VREF
EMI_ODT1
C158 .1 uF
R54 7.87K
R51 7.87K EMI_VREF1 EMI_VREF0
L15
RAM_D07 RAM_D00
UDQS B7 UDQS# A8
K9 ODT
EMI_ODT0
CPU_1.8V
K14
F1 G2 H7 G8 H1 H9 H3 F9 D1 C2 D7 D3 C8 D9 B9 B1
LDQS F7 LDQS# E8
OR
A3 E3 J3 N1 P9
J17
RAM_DQS1_P
P12
128 MB
J8 CK K8 CK#
RAM_CLK_M
DQ6 DQ1 DQ2 DQ0 DQ4 DQ5 DQ3 DQ7 DQ12 DQ9 DQ10 DQ11 DQ8 DQ13 DQ15 DQ14
64M x 16
L2 BA0 L3 BA1 L1 BA2
RAM_WE#
T13
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
R3 A14 R7 A15
RAM_BA2
T15
RAM_CLK_P EMI_CKE
M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 R8
VDDL J1
EMI_A12
EMI_D14
VDD4 R1
EMI_D15
VDD3 M9
F13
U35
VDD2 J9
RAM_D14
RAM_A13
J7 VSSDL A7 VSSQ0 B2 VSSQ1 B8 VSSQ2 D2 VSSQ3 D8 VSSQ4 E7 VSSQ5 F2 VSSQ6 F8 VSSQ7 H2 VSSQ8 H8 VSSQ9
F17
RAM_A14
T9
VSS0 VSS1 VSS2 VSS3 VSS4
RAM_D15
EMI_A13
N10
VDD1 E1
EMI_A14
VDD0 A1
RAM_1.8V
U4-B
DDR2_INDTEMP_128MB_X16
K13 R14
EMI_DDR_OPEN EMI_DDR_OPEN_FB
C160 .1 uF
R52 7.87K
MX286_CPU_IND
RAM_1.8V
C104 .1 uF
C103 .1 uF
C106 .1 uF
C177 .1 uF
C178 .1 uF
C176 .1 uF
C175 .1 uF
C174 .1 uF
C173 .1 uF
C172 .1 uF
C171 .1 uF
C170 .1 uF
Le ngt h of t his t ra ce is e qua l t o [CLK + Da t a ] le ngt hs Da t a = Ave ra ge le ngt h of a ll da t a t ra ce s
Te chnologic Sys t e ms
Oct . 22, 2015
TS-7553-V2 DDR2 RAM
Tit le : Re v:
Da t e
A
De s igne r
She e t
7
of 17
5.0V Powe r Supply
(2.5A) FB6 BOOST_5.1V
5V-13V
U37 L8 C44
18V ma x 2
Powe r In
VIN
FB16
CN5
VIN
SW PAD_SW
PF1
PGOOD EN
0.8V
FB
220 ohm 1500 mA
1 2
PAD_GND
C40 C45
5 10 uF
.1 uF
CON_PWR_BARREL
REG_5V 4.7 uH
9
3.1A
FB15
220 ohm
TVS1
5.0V nomina l
7
.1 uF
6
+ -
220 ohm
REG_5V
COMP
PGND AGND
25V
12V
C79
R68 76.8K
8
C99 220uF 6.3V
10 uF 6.3V
4
R21 25.5K
10 AN_REG_5V 1 R93 14K
3
R119 20.5K
REG_AOZ1022_DFN8
R89 9.1K
R59 475 C48 CN6 + -
Sca le = 44.6%
2.2 nF
FB12
1
.063 hole
2 220 ohm
CONN_PWR_2POS_5MM
GND
Et he rne t a nd SD USB a nd MX286
Swit che d Powe r
Swit che d Powe r
BOOST_5.1V AUX_3.3V
C169 U23 .1 uF BOOST_5.1V
6
VDD
DRAIN_1
4
U19 C168
U22 EN_ETH_3.3V#
.1 uF
2
EN_HOST_USB_5V
RN24-B
7
6
3
VDD
EN_FET1
DRAIN_1
SOURCE_1
BOOST_5.1V
8
2
EN_FET2
8
3
EN_FET1
SOURCE_1
5
SW_ETH_3.3V
47K 2
5
HOST_USB_5V
EN_SD_3.3V#
GND
VCC
3
5 4
AUX_3.3V 2
RN23-B
7
2
EN_FET2
DRAIN_2
1
47K NC7WZ14P6X_SC70
1
RN23-A
4
47K RN24-A
1
6
1
DRAIN_2
7
GND
SOURCE_2
8
SW_SD_3.3V
1 SLG_DUAL_FET_SW_SMT8
47K 7 6
GND
SOURCE_2
8
SW_5V
SLG_DUAL_FET_SW_SMT8
D
5V
2 EN_PWR_RAILS#
Ris e t ime of bot h out put s
Q1-A
G S 1
me a s ure d a t ~ 1V/ ms Ris e t ime of bot h out put s me a s ure d a t ~ 1V/ ms
Te chnologic Sys t e ms Tit le :
Da t e
Oct . 22, 2015
TS-7553-V2 5V a nd Swit che d Powe r
Re v: A
De s igne r
She e t
8
of 17
Boot St ra p Bia s Re s .
Aux. 3.3V Re g AUX 3.3V U6
FB10 3
SW_5V
L2
VIN
SW
3.31V t yp
4
AUX_3.3V 2.2uH
220 ohm C64 10 uF 600 mV
FB GND
2
EN
GND
1.5V = H 0.4V = L
D2
3
PAD
R33 41.2K
6
C31 100 pF
C53 22uF
LCD_D[00: 23]
1 5 7
2 R87 9.1K
2
3
Boot Source
RC = 4 x e -6
CPU_3.3V
7
LCD_D04
3.3V
6
LCD_D05
ETM off
5
LCD_D06
TEST off
8
LCD_D01
7
LCD_D03
10K
REG_1A_RT8016_DFN6
1
RN6-B
LCD_3
2
RN6-C 10K
4
LCD_0
RN6-D
DIODE_BAV99-2_SOT23 RN7-B 10K 7 6 10K RN7-C
10K
0 0 1 0
SPI
1 0 0 1
SD0 Ca rd
1 0 1 0
e MMC
0 0 0 0
USB
0 1 0 0
NAND
1
AUX_3.3V
RN8-A 10K
3
2
RN8-B 10K
4
RN8-D
Se le ct SPI Boot 5
LCD_D02
6
LCD_D00
10K
3
RN8-C 10K
RAM 1.8V Re g
Jumpe rs
RAM 1.8V U5
FB19 3
SW_5V
VIN
L1 SW
1.81V t yp
4
220 ohm
RAM_1.8V
AUX_3.3V
2.2uH C67 10 uF
600 mV
FB GND
2
EN
1.5V = H 0.4V = L
GND PAD
6
R32 41.2K
2 C66 10 uF
3 RN20-B 47K
4 RN20-C 47K
RN20-D 47K HD3
1 7
6
5
5 485_TERM_1
7 R115 20.5K
REG_1A_RT8016_DFN6
C30 100 pF
CAN_TERM_1 JP_UBOOT# JP_SD_BOOT#
RC = 4 x e -6
CONSOLE_RXD
4
RN7-D
1
2
3
4
5
6
7
8
9
10
485_TERM_2 CAN_TERM_2
HD_2X5_JMP_2.54MM 5
10K
Bot t om Jumpe r = "No CHRG"
Te chnologic Sys t e ms Tit le :
Da t e
Oct . 22, 2015
TS-7553-V2 AUX Powe r, Boot St ra p
Re v: A
De s igne r
She e t
9 of 17
10/ 100 Et he rne t Ma gJa ck
FB9
220 ohm T1
FB8 SW_ETH_3.3V
ETH_TX_P
220 ohm
Mode input la t che d on ris ing e dge of Re s e t
ETH_TX_M C162 .1 uF
The s e ca n be s e t via MDC or via Re s e t
C163 .1 uF
R72
4 5
6
SW_ETH_3.3V
RX+ RX-
RX_CT ALIGN
1 ohm C70 10 uF
4
C120 .1 uF
ALIGN
C121 .1 uF
17 18
RN14-D 1.5K U4-E
U11
5
3
TX_CT POE_RX
ENET0_MDIO ENET0_MDC
12
H4
13
G4
MDIO
VDD_1A
MDC
VDD_2A
19
ETH_RX_P
1
J3 J4
NC on MX283
J1 J2 G1 G2 E3 F3
ENET0_RXD0 ENET0_CRS ENET0_RXD1
ENET0_COL
ENET0_RX_EN
ENET0_RXD2
H1
8
H2
7
E4
11
ETH_RX_M
C71 10 uF
C110
1 2
POE_78
ENET0_TX_CLK
ENET0_TXD1
ENET0_RX_CLK ENET0_TX_EN
17 18
F2
16
F4
VDD_IO
9
SW_ETH_3.3V
11
ETH_ACT_LED R44
TXD0
E2
14
POE_TX
9 10
POE_45 POE_78
TXD1
VDD_CR
LLED+ LLED-
Gre e n SHD
1.2V Core
6
140
13 14
TXEN
C159 .1 uF ENET_CLK
POE_RX
RXD1/ MODE_1 CRS_DV/ MODE_2
ENET0_TXD2 F1
TX-
RXD0/ MODE_0
12 ENET0_TXD0
8
TX+ POE_45
ENET0_RXD3 ENET0_TXD3
POE_TX
7
C69 10 uF
SHD
15 16
RLED+ RLED-
Ye llow
R45
C111 .1 uF
SW_ETH_3.3V R95 51
INT# / REF_CLK_OUT
140
R98 51
MAGJACK_POE_10_100
ETH_100MBIT_LED# MX286_CPU_IND
15
ETH_RESET#
RESET# RXP
ETH_RX_P
23
ETH_RX_M 10
RXN
22
RXER/ PHYAD0
2 TXP
RN9-B 10K
TXN
21
R96 51
20
C116 .1 uF
R97 51
7 4
TX a nd RX pa irs s wa ppe d
VDD_2A XTAL2
ETH_TX_P LED1/ REGOFF
50 MHz
5
XTAL1/ CLKIN
Act / Link
3
ETH_TX_M
VDD_2A LED2/ INTSEL
2
100M ETH_ACT_LED
24
VSS
25
ETH_100MBIT_LED#
RBIAS
3 R92 14K
LAN8720AI_QFN24
RN9-C 10K
4
RN9-D
5
SW_ETH_3.3V
10K
6
PHY a ddre s s a nd mode s la t che d
LED high volt a ge
on ris ing e dge of Re s e t #
is VDD_2A = 3.3V
LED a ct ive s t a t e is a lwa ys t he oppos it e a s t he s t ra p s t a t e MDIO bus ca n not be us e d unt il 100 uS a ft e r Re s e t # is de a s s e rt e d
MDCLK ma x is 2.5 MHz
Aut o MDIX is s upport e d a nd Te chnologic Sys t e ms
Pola rit y Corre ct ion s upport e d
Tit le :
Da t e
Oct . 22, 2015
TS-7553-V2 Et he rne t Port
Re v: A
De s igne r
She e t
10 of 17
Fla s h Me mory Micro SD Ca rd Socke t RN5-A
1
SW_SD_3.3V
8
e MMC 4GB
SD0_CMD
4
3
2
1
10K RN10-D 10K
C122 5
CN3
7 8
SD0_D1
1
SD0_D2
2
SD0_D3
3
SD0_CMD
DATA_0
VDD
5
7
RN10-A 10K
U21
AUX_3.3V
8 A3
VCC
DATA_0
VCC
4
A4
EMMC_D1
DATA_1
A5
EMMC_D2
B2
EMMC_D3
DATA_2
DATA_1
VCC VCC
E6 F5
C194 .1 uF
C105 .1 uF
C195 .1 uF
C196 .1 uF
C108 .1 uF
J10 K9
DATA_2 DATA_3
2 GND
6
B3 RN5-B 10K
DATA_3 FRM1 COMMAND FRM2
SD0_CLK
6
RN10-B 10K
EMMC_D0
.1 uF SD0_D0
RN10-C 10K
FRM3
CLK
FRM4
9
EMMC_CMD
7
B4
DATA_4 VCCQ
DATA_5
EMMC_CLK B5
10 B6
11 12
AUX_3.3V
4
RN11-D
VCCQ DATA_6
VCCQ VCCQ
DATA_7
VCCQ
C6 M4 N4 P3 P5
5 M5
10K CONN_MICRO_SD
M6 K5
COMMAND CLK GND
RESET#
GND GND A6
GND
TOSH_GND
GND GND J5 C2
GND TOSH_GND
GND GND
C4 E7 G5 H10 K8 N2 N5 P4 P6
VDD_I
EMMC_MICRON_4GB_BG153_ITEMP C88 1 uF
C112 .1 uF
2 Mbyt e SPI Boot Fla s h U14 6
RXD2_SPI_CLK
5
TXD2_SPI_MOSI
2
RXD3_SPI_MISO
3
TXD3_SPI_CS# AUX_3.3V
7 1
1
2 RN17-A 1.5K
8
4 RN17-B 1.5K
7
3 RN17-D 1.5K
5
9 RN17-C 1.5K
6
10
U24-C
CLK
VCC
8
DIN_DQ0
AUX_3.3V C190 .1 uF
DOUT_DQ1 WP# _DQ2 HOLD# _DQ3 GND
4
CS#
8 FLASH_IS25LQ016B_2MB_SOIC8
74HC00_SOIC14
R60 649
UART2_TXD UART3_RXD UART3_TXD
7553_FLASH_CS# 12
UART2_RXD
13
U24-D
11
SPI_OFF_BD_CS#
74HC00_SOIC14 EN_SPI_BOOT_FLASH
Te chnologic Sys t e ms Tit le :
Da t e
Oct . 22, 2015
TS-7553-V2 Fla s h Me mory
Re v: A
De s igne r
She e t
11 of 17
RTC a nd USB Port s Ext e rna l USB Hos t Port
ST Micro RTC AUX_3.3V
P5 1
2
AUX_3.3V RN14-A 1.5K
RN14-B 1.5K 8
7
6
I2C_CLK
5
I2C_DAT
7
220 ohm 1
SCL
8
VCC
2
USB_HOST_M
SDA D7
OUT
3
USB_HOST_P
3
BAT 1
HOST_USB_5V
C180 .1 uF
U27
Single Ve rt ica l USB
FB18
4
XIN
FRAME1
D-
FRAME2
D+
FRAME3
GND
FRAME4
5 6 7 8
CONN_USB_A_RA_VERT_SINGLE
TVS3
R94
5V
Y3 2 1
XOUT
4
GND
51
4
1 M41T00S_RTC_SOIC8
12 pF 2
1
2
FB14
C181 .1 uF
3
220 ohm
6 K1 2
5
4.7V
XTAL_32KHZ_SMT 3
4
3
4 TVS_USB2_NUP4114_SC88
R63 649
AUX_3.3V
2
RN11-B
7
10K R76 OTG_HOST_MODE# 1 ohm
Re d Gre e n LEDs
Ext e rna l USB De vice Port
DEV_5V
FB22 USB_DEV_5V
P1 220 ohm
Single USB
AUX_3.3V R70 1
3
Top
LED5
1
USB_OTG_M
2
1 ohm Bot
3
R71 Gre e n 2
Re d 4
4
USB_OTG_P
5V DFRAME
5
D+ FRAME
GND
6
1 ohm
LED_RTA_RED-GREEN_TH
CONN_USB_B_RA_BLACK R74
FB20
USB_SILAB_M R42 140
1 ohm
220 ohm
R75 USB_SILAB_P R43 140
1 ohm
GREEN_LED# RED_LED#
Eit he r R70 a nd R71 pop Or e ls e R74 t hru R76
Te chnologic Sys t e ms
Da t e
Oct . 22, 2015
Tit le :
TS-7553-V2 RTC a nd USB Port s
Re v:
A
De s igne r
She e t
12 of 17
RS-232 a nd CAN Tra ns ce ive rs COM He a de r
RS-232 Tra ns ce ive r
HD2 C187 485+
SW_5V
485U10
C126 .1 uF
CAN1_H C183 .1 uF
11 12
Vcc C1+ V+
3.3V < -- 5V
C182 .1 uF
C1-
15
C2+
7
UART0_RTS
U32 UART1_TXD
19 2
UART0_RXD UART0_CTS
3
UART1_RXD
4
UART1_CTS
5
RXD_CAN0
6
RXD_CAN1
7
UART2_RXD
8 9
UART3_RXD
DIR VCC
20
B1 B2
A2
B3
A3 A4
B4
A5
B5
UART1_RTS
AUX_3.3V
V-
2
17
8
A6
B6
A7
B7 B8
A8
GND
RX+ _CANH_(DTR) RX-_CANL_(RI)
TXD
NC
10
RTS RXD
GND
5
CTS
6 20 21
2
T1
3
T2
28
T4
J1
DB-9M
9
R1
5
1
485+
4
R2
16
6
48526
15 RXD_CAN0_5V
13
RXD_CAN1_5V
12
RXD_485_5V
27
R3
22
4
CAN0_H
9
CAN0_L
23
R4
19
3
18
R5
7
RXD_DC_5V SW_5V
10
24
EN_RX
SD#
25
EN_232_TRANS
2
GND
74LVC245_TSSOP20
R110
8
10 SP213_SOIC28
UART0_TXD
R105
5
2.0K
CONSOLE_RXD
Cons ole or 2nd COM
DB-9M
1
T3
17
11
TX-_(DSR)
C2-
8
18
14
9
3
OE A1
4
TX+ _(DCD)
HD_COM_2X5_2.54MM
Le ve l s hift e r 1
C184 .1 uF
13
6
7
14
16
CAN1_L
1
TX+ _(DCD) TX-_(DSR) RX+ _(DTR) RX-_(RI)
TXD RTS RXD FRAME1
10
CTS GND
FRAME2
11
CONN_DB9M_RA_TH
2.0K R69 CONSOLE_TXD 1 ohm
CAN_0 Tra nce ive r 2nd Tra nce ive r (Opt iona l)
SW_5V R17 CAN_TERM_1 C164 .1 uF
U25 EN_CAN# SW_5V TXD_CAN0
EN_CAN# TXD_CAN1 RXD_CAN1_5V
8 1 4 5
EN#
VCC
TXD
CANH
RXD
CANL
VREF
GND
R14
60.4
60.4
RXD_CAN0_5V
C166 .1 uF
U26
R13
8 1 4 5
3
EN#
VCC
TXD
CANH
RXD
CANL
VREF
GND
60.4 R18
3
CAN_TERM_2 60.4
7
CAN0_H
6
CAN0_L
2 2 RN13-B 1.5K
TJA1040_SOIC8
7
CAN1_H
6
CAN1_L
1
7
1
2
RN13-A 1.5K
TVS5
8
24V
2 3
4 RN13-C 1.5K
TJA1040_SOIC8 6
1
2
RN13-D 1.5K
3 TVS6
5
NUP2105L_SOT23
C127 .1 uF
24V
3
NUP2105L_SOT23
C124 .1 uF
Te chnologic Sys t e ms Tit le :
Da t e
Oct . 22, 2015
TS-7553-V2 RS-232 Port s
Re v: A
De s igne r
She e t
13 of 17
RS-485 a nd Aut o circuit
Aut o 485 TX Ena ble U17
RS-485 Drive r 4
VCC 3
RN5-D
5
SW_5V
4
10K
5 C167 .1 uF
R62 649
U15 4
UART2_TXD
TXD
VCC
6
Clock = 1.25 t o 1.30 t ime s t he Ba ud Ra t e
1 3
RXD
X+
TXEN
X-
R64 2
485_TX_EN
RXEN#
GND
6
485+
10 AUX_3.3V
7 R15 60.4
5
9
1 485_TERM_1
3
2
C189 .1 uF
6
GND
VCC
5
AUX_3.3V
485_TERM_2
D
7
U18
R61 649
SP485EEN_SOIC8
3
AUX_3.3V
Q1
D2
Q2
D3
Q3
12 11
CLK
15
CLEAR# C32 100 pF
EN_CTT EN_CTP
GND
8
LOAD#
74HC161_TSSOP16
U16 3
4
C188 .1 uF
D
VCC
5 1
Q2-B
1
R16 60.4
5 EN_SPI_BOOT_FLASH
D1
13
CARRY
649
G
14
Q0
D0
2
AUTO_485_CLK
8
1 RXD_485_5V
16
AUX_3.3V
S 4
NC7WZ14P6X_SC70
6
CLK CLR#
Q GND
4
3
2
U24-A
2
74HC00_SOIC14
NC7SZ175P6_SC70
485-
4 5
UART2_TXD
U24-B
6
485_TX_EN
74HC00_SOIC14
Aut o RS-485 Ena ble Count e r a s s e rt s TX_EN for 14.5 clocks a ft e r Cle a r re move d As s uming t he clock is 1.28 t ime s t he Ba ud ra t e , t his is 11.3 da t a bit s Wors t ca s e (bit 7 = 0 of la s t da t a byt e in pa cke t ), TX_EN a s s e rt e d a bout 11 bit t ime s pa s t e nd of pa cke t Quicke s t Turn off of TX_EN occurs whe n la s t pa cke t byt e is FF
DIO
The n TX_EN t urns off a bout 2 bit t ime s a ft e r e nd of pa cke t
Ma x Ba ud Ra t e s upport e d is 1042 Kba ud HD5 DIO_0 DIO_1 DIO_2 DIO_3 DIO_4
1
2
3
4
5
6
7
8
9
10
AUX_3.3V
Clock for t his ba ud ra t e is 1.33 MHz
DIO_5 DIO_6 DIO_7
HD_2X5_TH_2.54MM
Te chnologic Sys t e ms Tit le :
TS-7553-V2
Re v: A
Da t e
Oct . 22, 2015
RS-485
De s igne r
She e t
14 of 17
LCD Ba ck Light Conne ct or
Monochrome 128 x 64 LCD Conn. CN2
75 mA 20
LCD_CS#
19
LCD_RESET#
18
LCD_CMD#
17 16 15
LCD_SPI_CLK
14
LCD_SPI_MOSI AUX_3.3V
13 12 11 10 9 8
C80 1 uF
7 6 5 4 3 2 C81 1 uF
1
CN7
CS# RESET#
TAB
21
2
SW_5V
1
DATA/ CMD# WR#
3
RD#
4
A K
Looking int o conne ct or
FRAME
Pin 1 on right
FRAME
D
SER_CLK
Q8
CONN_LCD.3IN_BKLT_RA_SMT
SER_DATA_MOSI 3.3V
G
EN_LCD_BK_LT
GND
LCD us e s Re d wire on Anode
S
VOUT
4
C1N
RN15-D 1.5K
C1P
Looking int o conne ct or
C2P
5
Pin 1 on le ft s ide
C2N NC V4 V3 TAB
22
V2 V1 V0
CONN_20-PIN_LXD.M4492C_SMT C82 1 uF
C83 1 uF
C84 1 uF
C85 1 uF
C86 1 uF
C87 1 uF
Me mbra ne Swit che s AUX_3.3V 1
2 RN18-A 1.5K
8 DIO_8 DIO_9 DIO_10 DIO_11
3 RN18-B 1.5K
7
4 RN18-C 1.5K
6
RN18-D 1.5K 5
HD_6X1_RA_TH 1 2 3 4 5 6 HD4
Te chnologic Sys t e ms Tit le :
Da t e
Oct . 22, 2015
TS-7553-V2 Supe r Ca ps
Re v: A
De s igne r
She e t
15 of 17
Supe rCa p 15 Se cond Powe r Hold
Supe rCa p Cha rge r U7
FB13
L3 3
REG_5V
VIN
SW
4 x 6.2 ohm = 1.55 ohm
D4
1.2V t o 5.0V
4
AN_CHRG 2.2uH
220 ohm C76 10 uF 600 mV
FB GND
2
1.5V = H
EN
0.4V = L
GND PAD
R67 76.8K
6
C33 100 pF
C75 10 uF R104 6.2 ohm
1 R101 6.2 ohm
5
R102 6.2 ohm
R103 6.2 ohm
7
10F Supe rCa ps
Q7
EN_CHRG#
BOOST_5.1V
RC = 4 x e -6
D
R83 9.1K
5
2
3
1
1
4
G
AUX_3.3V VCC
POWER_FAIL
REG_1A_RT8016_DFN6 S
U30
2 GND
1
3
RN11-A 10K
NC7SZ02_SC70
1
30 mV t o 600 mV
D5
RN21-A 47K
8
V_SCa p
8
2
1
REG_5V
4.8V ma x
C74 10 uF
R106 R109
U20
6
2.0K
D SILAB_PWM
1
6
2
5
2.0K
RN9-A 10K
GND
VCC
3
4
AUX_3.3V
R58 475
BOOST_5.1V
Q2-A
G 1
R22 25.5K
2 EN_TOP_OFF
S 1 3
POWER_FAIL
C92
C179 .1 uF
R107 2.0K
10F
RN16-C 1.5K
8
R81 6
NC7WZ14P6X_SC70
270
6 3
-
U9
V+
R77
4 1 MAINS_FAIL#
5
RN21-D
EN
+ V-
4
SW_5V
AN_SCAP_2
270
5
2
47K
R78
C93
LMV341_SOT23
10F
270 R108 2.0K
R79 270
MAINS_FAIL#
Cha rging curre nt doe s not go t hrough SW_5V IC - 1A not e nough
AN_SCAP_1
Ba la nce Op Amp is OFF during Dis cha rge
15 s e conds a s s ume s 2 wa t t loa d 10F Supe rCa ps cha rge d t o 4.8V Funct ions down t o Supe rCa p = 2.5V Te chnologic Sys t e ms Tit le :
Da t e
Oct . 22, 2015
TS-7553-V2 Supe r Ca ps
Re v: A
De s igne r
She e t
16 of 17
Boos t 5V Re g
CPU Re s e t
L9
4.7 uH
5V_Boos t
U34 REG_5V 3
BOOST_5.1V
4 RN24-C 47K
8
C113 .1 uF
RN24-D 47K
2
6
SW 5.5V
SW
1
VOUT
CPU_RESET#
VOUT
GND
11 9
4.73V Thre s h
VOUT
EN
STM1001S-2.9V_SOT23
U33 only popula t e d whe n SiLa b is not
4
1 15 16
C98
R122 237K
C34 100 pF
220uF 6.3V
LBI 500 mV
12 mohm 500 mV
FB
14
R28 28K
NC
12
MAINS_FAIL#
3
5.1V t yp
R121 237K
VCC RESET#
3
5
1.8V t o
C73 10 uF
U33 AUX_3.3V
BAT_IN
LBO# PGND PGND
10
SYNC PGND
13
GND
PAD_GND
R23 25.5K
2
5
Figure 2
6 7 17
3A loa d whe n Vin > 4.6V
REG_5V is norma lly 5V
REG_BOOST_TPS61030_QFN16
2A loa d whe n Vin > 3.5V But whe n Ma ins fa il, a nd in Powe r Hold,
1A loa d whe n Vin > 1.8V
it will ra nge from 4.5V down t o 2.2V
Da ught e r Ca rd Int e rfa ce
Acce le rome t e r U13
VDD VDIO
14 FB11 1
HD1
SW_5V
AUX_3.3V
220 ohm I2C_CLK I2C_DAT
4 6
C107 .1 uF
SCL
DC_DIO_4
SDA UART3_TXD RXD_DC_5V
ACCEL_INT ACCEL_INT2
11 9
3 8 13 15 16
POE_RX
14 12
5V
5V USB+ USB-
15 13
USB_OTG_P USB_OTG_M
11
10
9
8
7
DC_DIO_5
INT1 CAP
1
2 POE_TX
INT2
POE_45
C109 .1 uF DNC
POE_78
6 4
GND GND
8
DC_DIO_6
5 10K 3 2
2
RN4-A
1
RN4-B
6 7
10K RN4-C
10K
VIN
NC
3 HD_2X8_DC_2.54MM_TH
NC NC NC GND
7
16
I2C_LSB
GND GND
5 10
Da ught e r Ca rd
5
ACCEL_MMA8451_QFN16
1 MT125
MT8
1 MT125
4
10K
12 MT7
RN4-D
MT9
1 MT125
Te chnologic Sys t e ms Tit le :
Da t e
Oct . 22, 2015
TS-7553-V2 Boos t 5V Re g.
Re v: A
De s igne r
She e t
17 of 17
