Transcript
TSEK03 Integrated Radio Frequency Circuits 2016/Ted Johansson
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Tutorial 6: Repetition, solutions Problem 1: Noise A cascode amplifier stage is shown in figure below. Assume that both transistors are long-channel devices and Vb is the bias voltage for M2. Furthermore, assume that gm1 ≠ gm2 and λ≠0. Determine the input-referred noise voltage. Consider only the thermal noise sources and ignore the gate noise of the transistors. Vdd
Vb
M2 Vout
Vin
M1
A cascode stage.
TSEK03 Integrated Radio Frequency Circuits 2016/Ted Johansson
Solution:
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Alternative solution, using gm1 = gm2 = gm. There are two thermal noise sources as shown below.
Vin Vout
Since for long-channel devices:
Then because of uncorrelation, we can use superposition. Using KCL at the output node for In,M1:
Similarly, we get the effect of In,M2 at the output. Then by superposition:
To get the input-referred noise voltage we should divide the total output noise by the gain square ( :
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Problem 2: Mixer Consider the active mixer shown below, where the LO has abrupt edges and a 50 % duty cycle. Channel-length modulation and body effect are negligible. The load resistors exhibits mismatch, but the circuit is otherwise symmetric. Assume M1 carries a bias current of ISS. Determine the output offset voltage.
Solution: VRF = 0 I 2 = I SS ⋅ s(t ) I 3 = I SS ⋅ s (t −
TLO ) 2
Vout = VIF = I 3 RD (1 + α ) − I 2 RD = I SSαRD s (t −
TLO T ⎡ ⎤ ) + I SS RD ⎢ s (t − LO ) − s (t )⎥ 2 2 ⎣ ⎦
$!! !#!!! " $!!!#!!!" offset
original output
⇒ output offset
= I SSαRD
2
π
TSEK03 Integrated Radio Frequency Circuits 2016/Ted Johansson
Problem 3: Oscillator
Answer:
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Problem 4: PLL (problem 9.1, 9.2, 9.3 from the book) a. The mixer phase detector (PD) characteristics shown in the figure exhibits a zero gain at the peaks, e.g., at ∆φ = 0. A PLL using such a PD would therefore suffer from a zero loop gain at these point. Does this mean the PLL would not lock?
Input/output characteristics of a transistor operating as a mixer. b. If KVCO in the PLL of the figure below is very high and the PD has the characteristics shown in the figure above, can we estimate the value of ∆φ?
c. Repeat Problem b if the sign of KVCO is changed.
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Answer:
Figure above (Fig 9.12 from Razavi) shows the response of a PLL when the input frequency changes from ω1 to ω2 = ω1 + ∆ω. When the input frequency changes, the phase difference between the input and output increases resulting in a higher voltage at the output of the lowpass filter (which follows the PD). A higher control voltage, Vcont, causes the VCO output frequency to increase. Even though the output frequency, ωout, becomes equal to input frequency, ω2, at t = t1, the output frequency continues to increase and settles back to ω2 only after the phase difference between the input and output settles to a constant value. A single MOS switch can be used as a simple PD. In this case, the output of the PD will be a product of the two inputs. Hence, if the two inputs are A1cosωint and A2cos(ωoutt+∆φ), the output of the PD, VPD is given by
where α is a proportionality constant related to the conversion gain. When ωin = ωout, the output of the PD after lowpass filtering will be
This is the PD response shown in Fig. 1. Whenever the input frequency changes, the phase error, ∆φ, increases as long as the input and output frequencies are not matched. Hence, when the loop is in action, the PLL tends accumulate ∆φ and moves away from ∆φ = 0. It will shown in b) that in such a PLL, ∆φ stays close to 90°.
TSEK03 Integrated Radio Frequency Circuits 2016/Ted Johansson
b.
c.
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