Transcript
Written Test TSTE80, Analog and Discrete-time Integrated Circuits Date
June 3, 2002
Time:
8 - 12
Max. no of points:
70; 40 from written test, 15 for project, and 15 for assignments.
Grades:
30 for 3, 42 for 4, and 56 for 5.
Allowed material:
All types of calculators except Lap Tops. All types of tables and handbooks. The textbook Johns & Martin: Analog Integrated Circuit Design
Examiner:
Lars Wanhammar.
Responsible teacher: Robert Hägglund. Tel.: 013 - 28 16 76 (3). Correct (?) solutions: Solutions and results will be displayed in House B, entrance 25 - 27, 1st floor.
Good Luck!
TSTE 80, Analog and discrete-time integrated circuits
20020603
Student’s Instructions The CMOS transistor operation regions, small signal parameters, and noise characteristics are found on the last page of this test. Generally, do not just answer yes or no to a short question. You always have to answer with figures, formulas, etc., otherwise no or fewer points will be given. Basically, there are few numerical answers to be given in this test. You may write down your answers in Swedish or English. NOTE: Exercise 6 is only for those that have taken the course before 2002, and have not handed in more than one assignment during the course.
Exercise 1.
Basic building block In an operational amplifier a buffer at the output is needed to increase the output conductance of the amplifier and thereby be able to drive resistive loads. The buffer is shown in Figure 1.1. In this exercise neglect the influence of the channel length modulation. a) Derive a large signal expression for the output voltage as a function of the input voltage. Assume that all transistors are operating in the saturation region. (2p) b) Express the first pole as a function of the bias voltage, V bias . (3p) c) What is the maximum value of the pole when both transistors are operating in the saturation region? (3p) VDD
Vin
M1 Vout
Vbias
Figure 1.1
M2
CL
A CMOS gain stage.
2 (7)
TSTE 80, Analog and discrete-time integrated circuits
2.
20020603
Small signal analysis A new type of transistor has been developed. The approximate expression for the transistor is as follows:
I 1 = I 2 ⁄ V AC I 2 = I BS e
(2.1)
V AC ---------VT
V BC 1 + -------- K
(2.2)
I3 = I1 + I2
(2.3)
kT
where I BS and K are process dependent constants and V T = ------ . q B
I2
A
B
A I1
g1 .C
Figure 2.1
g2VBC
I3
g3VAC
g4
C
A new type of transistor a) the transistor symbol b) the small signal model.
a) Derive a small signal model equivalent to the one shown in Figure 2.1 for the transistor. (7p) b) Is it good to use this transistor as input transistor in an operational amplifier that are going to be used in a switched capacitor circuit? Motivate your answer carefully. (1p)
3.
Operational amplifier / Operational transconductance amplifier An operational amplifier is used in a feedback configuration shown in Figure 3.1. The transfer function of the amplifier is given by
A0 A ( s ) = -------------s 1 + ----p1
(3.1)
R2
Vin
R1
C A(s)
Figure 3.1
Vout
A operational amplifier in a feedback configuration.
a) Find an expression for the feedback factor, β . Sketch the magnitude and 3 (7)
TSTE 80, Analog and discrete-time integrated circuits
20020603
phase responses of the loop gain as a function of the frequency. Assume that R 2 = 10R 1 and that R 2 C = 0.5 ⁄ p 1 (5p) b) Assume that the last stage, a common drain gain stage, in the operational amplifier is the stage that limits the slew rate. How large must the current through the last stage be to have a slew rate of SR = 40V ⁄ µs (1p) c) In the circuit shown in Figure 3.1 the capacitor and the resistor forms the time constant in the building block. Process and temperature variations yields a large component spread, low matching of the time constant. Assume instead that we can form the time constant by a capacitor ratio. State two ways to improve the matching of the two capacitors where C 2 = C 1 = 50pF . (2p)
4.
Switched capacitor circuit A switched capacitor circuit in clock cycle 1 is shown in Figure 4.1. a) Derive the transfer function for the clock cycle 1 of the switched capacitor circuit shown in Figure 4.1, i.e., V out ( z ) ⁄ V in ( z ) . Assume that the OTA is ideal. (4p) b) Is the circuit insensitive to capacitive parasitics? Motivate your answer carefully. (2p) c) What are the benefits and drawbacks of an SC circuit compared to a continuos time circuit? (2p)
C1 Vin
C3 Vout
C2
Figure 4.1
A switched capacitor circuit.
4 (7)
TSTE 80, Analog and discrete-time integrated circuits
5.
20020603
A mixture of questions a) Linus has a 10-bit DA converter och needs a SNR of more than 65dB. Propose one way to achieve this SNR. (2p) b) We have designed a folded cascode operational transconductance amplifier but the Common-Mode Rejection Ratio is too low. This comes from the fact that when the input common-mode voltage is increased the current generated by current source transistor will increase. How can we decrease this sensitivity to common-mode signals? (1p) c) In mixed signal designs it is common that the noise from the digital circuits is passed via the substrate to the analog circuits. Assume that we have a common source amplifier with resistive load that are close to a digital switching network. We assume that the switching noise can be modelled as a white noise source with the spectral density of V n2 = S sub . Derive the equivalent input referred noise spectral density. The only noise to be considered except the substrate noise is the thermal noise of the transistor and the resistor. (3p) VDD
R Vout Vin
Figure 5.1
CL Vn2
A noisy common source amplifier with resistive load.
d) State two ways to decrease the input noise power in exercise c) and thereby the SNR (if the input signal power is constant) by changing two different relevant design parameters? What will happen to the DC gain of the circuit in both cases? Assume that the resistance R is much smaller than the output resistance of the transistor. (2p)
6.
Extra exercise NOTE: This exercise is only for the students that have taken the course before 2002 and not handed in three assignments during the course. The circuit shown in Figure 6.1 is to be used in a analog signal processing circuit. a) Draw a small signal model of the amplifier, neglect the influence of the parasitic capacitanses introduced in the transistors. (1p) b) The transfer function of the amplifier can be computed to
5 (7)
TSTE 80, Analog and discrete-time integrated circuits
20020603
V out g m1 ( g m3 + g ds3 )α ---------- = ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------V in ( g ds4 g ds5 + αsC L ) ( g ds3 + g m3 ) + ( g ds1 + g ds2 ) ( g ds4 g ds5 + ( g ds3 + sC L )α ) where α = g ds4 + g ds5 + g m4 when the body effect is neglected. Approximate the transfer function and find simple expressions for the DC gain, first pole, and the unity-gain frequency. (3p) c) What will happen to the DC gain and the first pole if we ... ...increase the current through transistor M 2 . ...increase the size of the load capacitor. ...insert a gain boosting stage to transistor M 3 and M 4 Assume that the increased sizes does not change the operation region of the transistors. (6p) VDD
Vbias1
M2
Vin
M1
M3
Vbias2 Vout
Figure 6.1
Vbias3
M4
Vbias4
M5
CL
A CMOS amplifier stage.
6 (7)
TSTE 80, Analog and discrete-time integrated circuits
20020603
Transistor formulas and noise CMOS transistors Current formulas and operating regions Cut-off:
V GS < V T
ID ≈ 0
Linear:
V GS – V T > V DS > 0
µ 0 C ox W I D ≈ --------------- ⋅ ----- ⋅ ( 2 ( V GS – V T ) – V DS ) ⋅ V DS 2 L
Saturation:
0 < V GS – V T < V DS
µ 0 C ox W 2 I D ≈ --------------- ⋅ ----- ⋅ ( V GS – V T ) ⋅ ( 1 + λV DS ) 2 L
Small-signal parameters Linear region:
W g m ≈ µ 0 C ox ⋅ ----- ⋅ V DS L
W g ds ≈ µ 0 C ox ⋅ ----- ⋅ ( V GS – V T – V DS ) L
Saturation region:
dI D W g m = ------------- ≈ 2µ 0 C ox ----- I D dV GS L
dI D g ds = ------------- ≈ λI D dV DS
Circuit noise Thermal noise The thermal noise spectral density at the gate of a CMOS transistor is 2
8kT 1 v ------ = ---------- ⋅ -----3 gm ∆f Flicker noise The flicker noise spectral density at the gate of a CMOS transistor is 2
v K ------ = --------------------∆f WLC ox f
7 (7)
