Transcript
TSC2003 TSC 2003
TSC2 003
SBAS162D – NOVEMBER 2000 – REVISED SEPTEMBER 2004
I2C TOUCH SCREEN CONTROLLER DESCRIPTION
FEATURES ● 2.5V TO 5.25V OPERATION ● INTERNAL 2.5V REFERENCE ● DIRECT BATTERY MEASUREMENT (0.5V TO 6V) ● ON-CHIP TEMPERATURE MEASUREMENT ● TOUCH-PRESSURE MEASUREMENT ● I2C INTERFACE SUPPORTS: Standard, Fast, and High-Speed Modes ● AUTO POWER DOWN ● TSSOP-16 AND VFBGA-48 PACKAGES
The TSC2003 is a 4-wire resistive touch screen controller. It also features direct measurement of two batteries, two auxiliary analog inputs, temperature measurement, and touchpressure measurement. The TSC2003 has an on-chip 2.5V reference that can be utilized for the auxiliary inputs, battery monitors, and temperature-measurement modes. The reference can also be powered down when not used to conserve power. The internal reference will operate down to 2.7V supply voltage while monitoring the battery voltage from 0.5V to 6V. The TSC2003 is available in the small TSSOP-16 and VFBGA-48 packages and is specified over the –40°C to +85°C temperature range.
APPLICATIONS ● ● ● ● ● ●
PERSONAL DIGITAL ASSISTANTS PORTABLE INSTRUMENTS POINT-OF-SALES TERMINALS PAGERS TOUCH SCREEN MONITORS CELLULAR PHONES VDD
PENIRQ TEMP0
X+ X–
TEMP1 SCL
VDD SAR SDA Y+ Y–
I2C Interface and Control Logic
Comparator MUX
CDAC
A0 IN1 IN2 VBAT1
Internal Clock Channel Select
A1
VBAT2
Internal +2.5VREF
VREF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2000-2004, Texas Instruments Incorporated
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PACKAGE/ORDERING INFORMATION(1)
PRODUCT
MAXIMUM MAXIMUM RELATIVE ACCURACY GAIN ERROR (LSB) (LSB)
TSC2003
" TSC2003
PACKAGE-LEAD
PACKAGE DESIGNATOR
SPECIFIED TEMPERATURE RANGE
PACKAGE MARKING
ORDERING NUMBER
TRANSPORT MEDIA, QUANTITY
±2
±4
TSSOP-16
PW
–40°C to +85°C
TSC2003I
"
"
"
"
"
"
TSC2003IPW TSC2003IPWR
Tube, 94 Tape and Reel, 2500
±2
±4
VFBGA-48
ZQC
–40°C to +85°C
BC2003
TSC2003IZQCR
Tape and Reel, 2500
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
ELECTROSTATIC DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS(1) +VDD to GND ........................................................................ –0.3V to +6V Digital Input Voltage to GND ................................. –0.3V to +VDD + 0.3V
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
Analog Input Voltage to GND. All Pins Except 7, 8 ...... –0.3V to +VDD + 0.3V
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
TSSOP Package
Analog Input Voltage Pins 7, 8 to GND ........................... –0.3V to +6.0V Operating Temperature Range ........................................ –40°C to +85°C Storage Temperature Range ......................................... –65°C to +150°C Power Dissipation .......................................................... (TJ Max – TA)/θJA Junction Temperature (TJ Max) .............................................. +150°C
θJA Thermal Impedance ................................................... +115.2°C/W Lead Temperature, Soldering Vapor Phase (60s) ............................................................ +215°C Infrared (15s) ..................................................................... +220°C VFBGA Package
PIN CONFIGURATION
Junction Temperature (TJ Max) .............................................. +125°C
Top View
θJA Thermal Impedance ........................................................ +50°C/W
TSSOP
Lead Temperature, Soldering +VDD
1
16
IN1
X+
2
15
IN2
Vapor Phase (60s) ............................................................ +215°C Infrared (15s) ..................................................................... +220°C
Y+
3
X–
4 TSC2003
NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.
14
A0
13
A1
12
SCL
Y–
5
GND
6
11
SDA
VBAT1
7
10
PENIRQ
VBAT2
8
9
VREF
PIN DESCRIPTIONS TSSOP VFBGA
Top View
PIN #
PIN #
NAME
DESCRIPTION
1
C1, D1
+VDD
Power Supply
2
E1
X+
3
F1
Y+
Y+ Position Input
4
G1
X–
X– Position Input Y– Position Input
X+ Position Input
VFBGA A0
1
A1
2
SCL
3
SDA PENIRQ
4
5
A
6
7
NC
IN2 B
NC
C
NC
D
NC
E
NC
5
G2
Y–
6
G3, G4
GND
Ground
7
G5
VBAT1
Battery Monitor Input
8
G6
VBAT2
Battery Monitor Input
NC
NC
NC
9
B7
VREF
NC
NC
NC
NC
10
A7
PENIRQ
NC
NC
NC
NC
NC
11
A6
SDA
NC
NC
NC
NC
NC
12
A4
SCL
13
A3
A1
I2C Bus Address Input A1
14
A2
A0
I2C Bus Address Input A0
15
A1
IN2
Auxiliary A/D Converter Input
16
B1
IN1
Auxiliary A/D Converter Input
NC
VREF
IN1
+VDD
+VDD X+ NC
F
NC
NC
NC
NC
NC
Y+ G
NC
X−
Y−
GND
GND
VBAT1
Voltage Reference Input/Output Pen Interrupt. Open Drain Output (Requires 30kΩ to 100kΩ pull-up resistor externally). Serial Data Serial Clock
VBAT2
NC = No Connection
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SBAS162D
ELECTRICAL CHARACTERISTICS At TA = –40°C to +85°C, +VDD = +2.7V, VREF = 2.5V external voltage, I2C bus frequency = 3.4MHz, 12-bit mode and digital inputs = GND or +VDD, unless otherwise noted. TSC2003I PARAMETER
CONDITIONS
ANALOG INPUT Full-Scale Input Span Absolute Input Range Capacitance Leakage Current SYSTEM PERFORMANCE Resolution No Missing Codes Integral Linearity Error Offset Error Gain Error Noise Power-Supply Rejection Ratio SAMPLING DYNAMICS Throughput Rate Channel-to-Channel Isolation SWITCH DRIVERS On-Resistance Y+, X+ Y–, X– Drive Current(2) REFERENCE OUTPUT Internal Reference Voltage Internal Reference Drift Output Impedance Quiescent Current REFERENCE INPUT Range Resistance BATTERY MONITOR Input Voltage Range Input Impedance Accuracy TEMPERATURE MEASUREMENT Temperature Range Resolution Accuracy DIGITAL INPUT/OUTPUT Logic Family Logic Levels, Except PENIRQ VIH VIL VOH VOL PENIRQ VOL Data Format Input Capacitance
TYP
0 –0.2
MAX
UNITS
VREF +VDD +0.2
V V pF µA
25 0.1 12 Standard and Fast Mode High-Speed Mode Standard and Fast Mode High-Speed Mode
70 70
Bits Bits Bits LSB(1) LSB LSB LSB µVrms dB
50 100
ksps dB
5.5 7.3
Ω Ω mA
11 10 ±2 ±4 ±6 ±4
Including Internal VREF
VIN = 2.5Vp-p at 50kHz
Duration 100ms
50 2.45
Internal Reference ON Internal Reference OFF PD1 = 1, PD0 = 0, SDA, SCL High
2.50 25 300 1 750
2.0 PD1 = PD0 = 0
2.55
V ppm/°C Ω GΩ µA
VDD
V GΩ
6.0
V kΩ GΩ % %
1 0.5
Sampling Battery Battery Monitor OFF External VREF = 2.5V Internal Reference
10 1 –2 –3
+2 +3
–40 Differential Method(3) TEMP0(4) Differential Method(3) TEMP0(4)
+85
°C °C °C °C °C
+VDD + 0.3 +VDD • 0.3 0.4 0.4
V V V V V
10
pF
1.6 0.3 ±2 ±3 CMOS
| IIH | ≤ +5µA | IIL | ≤ +5µA IOH = –250µA IOL = 250µA 30kΩ Pull-Up
+VDD • 0.7 –0.3 +VDD • 0.8
Straight Binary SDA, SCL Lines
TSC2003 SBAS162D
MIN
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ELECTRICAL CHARACTERISTICS (Cont.) At TA = –40°C to +85°C, +VDD = +2.7V, VREF = 2.5V external voltage, I2C bus frequency = 3.4MHz, 12-bit mode and digital inputs = GND or +VDD, unless otherwise noted. TSC2003I PARAMETER POWER-SUPPLY REQUIREMENTS +VDD Quiescent Current
Power-Down Current when Part is Not Addressed
Power Dissipation
CONDITIONS
Specified Performance Operating Range Internal Reference OFF, PD1 = PD0 = 0 High-Speed Mode: SCL = 3.4MHz Fast Mode: SCL = 400kHz Standard Mode: SCL = 100kHz Internal Reference ON, PD0 = 0 Internal Reference OFF, PD1 = PD0 = 0 High-Speed Mode: SCL = 3.4MHz Fast Mode: SCL = 400kHz Standard Mode: SCL = 100kHz PD1 = PD0 = 0, SDA = SCL = +VDD +VDD = +2.7V
TEMPERATURE RANGE Specified Performance
MIN
TYP
2.7 2.5
254 95 63 1005
MAX
3.6 5.25
V V
650
µA µA µA µA
3 1.8
µA µA µA µA mW
+85
°C
90 21 4
–40
UNITS
NOTES: (1) LSB means Least Significant Bit. With VREF equal to +2.5V, one LSB is 610µV. (2) Ensured by design, but not tested. Exceeding 50mA source current may result in device degradation. (3) Difference between TEMP0 and TEMP1 measurement. No calibration necessary. (4) Temperature drift is –2.1mV/°C.
TIMING CHARACTERISTICS At TA = –40°C to +85°C, +VDD = +2.7V, unless otherwise noted. All values referred to VIHMIN and VILMAX levels. PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
SCL Clock Frequency
fSCL
Standard Mode Fast Mode High-Speed Mode, Cb = 100pF max High-Speed Mode, Cb = 400pF max
0 0 0 0
100 400 3.4 1.7
kHz kHz MHz MHz
Bus Free Time Between a STOP and Start Condition
tBUF
Standard Mode Fast Mode
4.7 1.3
µs µs
Standard Mode Fast Mode High-Speed Mode
4.0 600 160
µs ns ns
Hold Time (Repeated) START Condition
tHD;
STA
LOW Period of the SCL Clock
tLOW
Standard Mode Fast Mode High-Speed Mode, Cb = 100pF max High-Speed Mode, Cb = 400pF max
4.7 1.3 160 320
µs µs ns ns
HIGH Period of the SCL Clock
tHIGH
Standard Mode Fast Mode High-Speed Mode, Cb = 100pF max High-Speed Mode, Cb = 400pF max
4.0 600 60 120
µs ns ns ns
Standard Mode Fast Mode High-Speed Mode
4.7 600 160
µs ns ns
Standard Mode Fast Mode High-Speed Mode
250 100 10
ns ns ns
Standard Mode Fast Mode High-Speed Mode, Cb = 100pF max High-Speed Mode, Cb = 400pF max
0 0 0 0
3.45 0.9 70 150
µs µs ns ns
Standard Mode Fast Mode High-Speed Mode, Cb = 100pF max High-Speed Mode, Cb = 400pF max
20 + 0.1Cb 10 20
1000 300 40 80
ns ns ns ns
Standard Mode Fast Mode High-Speed Mode, Cb = 100pF max High-Speed Mode, Cb = 400pF max
20 + 0.1Cb 10 20
1000 300 80 160
ns ns ns ns
Setup Time for a Repeated START Condition
tSU;
STA
Data Setup Time
tSU;
DAT
Data Hold Time
tHD;
DAT
Rise Time of SCL Signal
Rise Time of SCL Signal After a Repeated START Condition and After an Acknowledge Bit
trCL
trCL1
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SBAS162D
TIMING CHARACTERISTICS (Cont.) At TA = –40°C to +85°C, +VDD = +2.7V, unless otherwise noted. All values referred to VIHMIN and VILMAX levels. PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
tfCL
Standard Mode Fast Mode High-Speed Mode, Cb = 100pF max High-Speed Mode, Cb = 400pF max
20 + 0.1Cb 10 20
300 300 40 80
ns ns ns ns
Standard Mode Fast Mode High-Speed Mode, Cb = 100pF max High-Speed Mode, Cb = 400pF max
20 + 0.1Cb 10 20
1000 300 80 160
ns ns ns ns
Standard Mode Fast Mode High-Speed Mode, Cb = 100pF max High-Speed Mode, Cb = 400pF max
20 + 0.1Cb 10 20
300 300 80 160
ns ns ns ns
Standard Mode Fast Mode High-Speed Mode
4.0 600 160
Fall Time of SCL Signal
Rise Time of SDA Signal
trDA
Fall Time of SDA Signal
tfDA
Setup Time for STOP Condition
tSU;
STO
µs ns ns
Capacitive Load for SDA or SCL Line
Cb
Standard Mode Fast Mode High-Speed Mode, SCL = 1.7MHz High-Speed Mode, SCL = 3.4MHz
Pulse Width of Spike Suppressed
tSP
Fast Mode High-Speed Mode
0 0
Noise Margin at the HIGH Level for Each Connected Device (Including Hysteresis)
VnH
Standard Mode Fast Mode High-Speed Mode
0.2VDD
V
Standard Mode Fast Mode High-Speed Mode
0.1VDD
V
Noise Margin at LOW Level for Each Connected Device (Including Hysteresis)
VnL
400 400 400 100
pF pF pF pF
50 10
ns ns
TIMING DIAGRAM
trDA tfDA SDA tBUF tLOW
trCL
tfCL
tHD; STA
tSP
SCL tHD; STA tHD; DAT
tSU; DAT tSU; STA
tHIGH
STOP START
trCL1
tSU; STO
REPEATED START
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TYPICAL CHARACTERISTICS: +2.7V At TA = +25°C, +VDD = +2.7V, VREF = External +2.5V, I2C bus frequency = 3.4MHz, PD1 = PD0 =0, unless otherwise noted.
SUPPLY CURRENT vs VDD
SUPPLY CURRENT vs TEMPERATURE 300 High-Speed Mode = 3.4MHz
Supply Current (µA)
Supply Current (µA)
250 200 150 Fast Mode = 400kHz 100 50 Standard Mode = 100kHz 0 –40
–20
0
20
40
60
80
1200 1100 1000 900 800 700 600 500 400 300 200 100 0
High-Speed Mode = 3.4MHz
Fast Mode = 400kHz Standard Mode = 100kHz
2.5
100
3.0
3.5
4.0
SUPPLY CURRENT vs I2C BUS FREQUENCY 300
900
5.5
High-Speed Mode = 3.4MHz
800 High-Speed Mode
Supply Current (µA)
Supply Current (µA)
250
200
150
100
700 600 500 Fast Mode = 400kHz
400 300 Standard Mode = 100kHz
200 100
Fast/Standard Mode
0 10
100
1000
10000
2.5
3.0
3.5
I2C Bus Frequency (kHz)
90
3.0 High-Speed Mode = 3.4MHz
70 60 Fast Mode = 400kHz
40 30 20
Standard Mode = 100kHz
Gain Delta from +25˚C (LSB)
4.0
50
4.5
5.0
5.5
CHANGE IN GAIN vs TEMPERATURE
100
80
4.0 VDD (V)
SUPPLY CURRENT (Part Not Addressed) vs TEMPERATURE
Supply Current (µA)
5.0
SUPPLY CURRENT (Part Not Addressed) vs VDD
1000
50
4.5
VDD (V)
Temperature (°C)
10
2.0 1.0 0.0 –1.0 –2.0 –3.0 –4.0
0 –40
–20
0
20
40
60
80
100
–40
Temperature (°C)
–20
0
20
40
60
80
100
Temperature (°C)
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SBAS162D
TYPICAL CHARACTERISTICS: +2.7V (Cont.) At TA = +25°C, +VDD = +2.7V, VREF = External +2.5V, I2C bus frequency = 3.4MHz, PD1 = PD0 =0, unless otherwise noted.
EXTERNAL REFERENCE CURRENT vs TEMPERATURE
6.0
10
5.0
9
External Reference Current (µA)
Offset Delta from +25°C (LSB)
CHANGE IN OFFSET vs TEMPERATURE
4.0 3.0 2.0 1.0 0.0 –1.0 –2.0 –3.0 –4.0 –5.0
8 High-Speed Mode = 3.4MHz
7 6 5 4
Fast Mode = 400kHz
3
Standard Mode = 100kHz
2 1 0
–6.0 –40
–20
0
20
40
60
80
–40
100
–20
0
Temperature (°C)
9
9
8
8 X–
7
7
6
6 Y–
RON (Ω)
RON (Ω)
SWITCH-ON RESISTANCE vs VDD (X+, Y+: +VDD to Pin; X–, Y–: Pin to GND)
5 4 X+
3
Y+
40
60
80
100
SWITCH-ON RESISTANCE vs TEMPERATURE (X+, Y+: +VDD to Pin; X–, Y–: Pin to GND) X–
Y–
5 Y+
4 X+
3
2
2
1
1 0
0 2.5
3
3.5
4
4.5
5
–40
5.5
–20
INTERNAL VREF vs TEMPERATURE 2.54
2.54
2.53
2.53
2.52
2.52
Internal VREF (V)
2.55
2.50 2.49 2.48
60
80
100
2.51 2.50 2.49 2.48 2.47
2.46
2.46
2.45
2.45 –40 –35 –30 –25 –20 –15 –10 –05 0 05 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
2.47
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
Temperature (°C)
TSC2003 SBAS162D
40
20
INTERNAL VREF vs VDD
2.55
2.51
0
Temperature (°C)
VDD (V)
Internal VREF (V)
20
Temperature (°C)
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TYPICAL CHARACTERISTICS: +2.7V (Cont.) At TA = +25°C, +VDD = +2.7V, VREF = External +2.5V, I2C bus frequency = 3.4MHz, PD1 = PD0 =0, unless otherwise noted.
TEMP DIODE VOLTAGE vs TEMPERATURE
TEMP0 DIODE VOLTAGE vs VDD (25°C)
850
614 TEMP1
TEMP0 Diode Voltage (mV)
Temp Diode Voltage (mV)
800 750 700 650 600
TEMP0
550 500 450
613
612
611
–40 –35 –30 –25 –20 –15 –10 –05 0 05 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
610 2.5
3.0
3.5
Temperature (°C)
4.0
4.5
5.0
5.5
VDD (V)
TEMP1 DIODE VOLTAGE vs VDD (25°C) 738
TEMP1 Diode Voltage (mV)
736 734 732 730 728 726 724 722 720 2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
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SBAS162D
THEORY OF OPERATION
a differential input to the converter, and a differential reference architecture, it is possible to negate the switch’s onresistance error (should this be a source of error for the particular measurement).
The TSC2003 is a classic Successive Approximation Register (SAR) Analog-to-Digital (A/D) converter. The architecture is based on capacitive redistribution which inherently includes a sample-and-hold function. The converter is fabricated on a 0.6µ CMOS process.
ANALOG INPUT See Figure 2 for a block diagram of the input multiplexer on the TSC2003, the differential input of the A/D converter, and the converter's differential reference.
The basic operation of the TSC2003 is shown in Figure 1. The device features an internal 2.5V reference and an internal clock. Operation is maintained from a single supply of 2.7V to 5.25V. The internal reference can be overdriven with an external, low-impedance source between 2V and +VDD. The value of the reference voltage directly sets the input range of the converter.
When the converter enters the Hold mode, the voltage difference between the +IN and –IN inputs (see Figure 2) is captured on the internal capacitor array. The input current on the analog inputs depends on the conversion rate of the device. During the sample period, the source must charge the internal sampling capacitor (typically 25pF). After the capacitor has been fully charged, there is no further input current. The amount of charge transfer from the analog source to the converter is a function of conversion rate.
The analog input (X, Y, and Z parallel coordinates, auxiliary inputs, battery voltage, and chip temperature) to the converter is provided via a multiplexer. A unique configuration of low on-resistance switches allows an unselected A/D converter input channel to provide power, and an accompanying pin to provide ground for an external device. By maintaining
Voltage Regulator
+2.7V to +5V
1.2kΩ
1µF + to 10µF (Optional)
50kΩ
TSC2003 0.1µF
Touch Screen
1
+VDD
IN1 16
Auxiliary Input
2
X+
IN2 15
Auxiliary Input
3
Y+
A0 14
4
X–
A1 13
5
Y–
SCL 12
Serial Clock
6
GND
SDA 11
Serial Data
7
VBAT1
PENIRQ 10
8
VBAT2
VREF
Pen Interrupt
9 0.1µF
Main Battery
1.2kΩ
+
1µF to 10µF (Optional)
Secondary Battery
FIGURE 1. Basic Operation of the TSC2003.
TSC2003 SBAS162D
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+VDD
PENIRQ TEMP1
VREF
TEMP0
C2-C0 (Shown 101B)
C3 (Shown HIGH)
X+ X– Ref ON/OFF Y+ +IN
Y–
+REF Converter
–IN
2.5V Reference
–REF
7.5kΩ VBAT1 7.5kΩ VBAT2 2.5kΩ
2.5kΩ
Battery On
Battery On
IN1 IN2 GND
FIGURE 2. Simplified Diagram of the Analog Input.
INTERNAL REFERENCE
Reference Power Down
The TSC2003 has an internal 2.5V voltage reference that can be turned ON or OFF with the power-down control bits, PD0 and PD1 (see Table II and Figure 3). The internal reference is powered down when power is first applied to the device. The internal reference voltage is only used in the single-ended reference mode for battery monitoring, temperature measurement, and for measuring the auxiliary input. Optimal touch screen performance is achieved when using a ratiometric conversion; thus, all touch screen measurements are done automatically in the differential mode.
Band Gap
VREF Buffer
To CDAC
Optional
FIGURE 3. Simplified Diagram of the Internal Reference.
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SBAS162D
REFERENCE INPUT
REFERENCE MODE
The voltage difference between +REF and –REF (see Figure 2) sets the analog input range. The TSC2003 will operate with a reference in the range of 2V to +VDD. There are several critical items concerning the reference input and its wide-voltage range. As the reference voltage is reduced, the analog voltage weight of each digital output code is also reduced. This is often referred to as the LSB (Least Significant Bit) size, and is equal to the reference voltage divided by 4096 (256 if in 8-bit mode). Any Offset or Gain error inherent in the A/D converter will appear to increase, in terms of LSB size, as the reference voltage is reduced. For example, if the offset of a given converter is 2LSBs with a 2.5V reference, it will typically be 2.5LSBs with a 2V reference. In each case, the actual offset of the device is the same, 1.22mV. With a lower reference voltage, more care must be taken to provide a clean layout including adequate bypassing, a clean (low-noise, lowripple) power supply, a low-noise reference (if an external reference is used), and a low-noise input signal.
There is a critical item regarding the reference when making measurements while the switch drivers are ON. For this discussion, it is useful to consider the basic operation of the TSC2003 (see Figure 1). This particular application shows the device being used to digitize a resistive touch screen. A measurement of the current Y position of the pointing device is made by connecting the X+ input to the A/D converter, turning on the Y+ and Y– drivers, and digitizing the voltage on X+, as shown in Figure 4. For this measurement, the resistance in the X+ lead does not affect the conversion; it does, however, affect the settling time, but the resistance is usually small enough that this is not a concern. However, since the resistance between Y+ and Y– is fairly low, the on-resistance of the Y drivers does make a small difference. Under the situation outlined so far, it would not be possible to achieve a 0V input or a full-scale input regardless of where the pointing device is on the touch screen because some voltage is lost across the internal switches. In addition, the internal switch resistance is unlikely to track the resistance of the touch screen, providing an additional source of error.
The voltage into the VREF input is not buffered, and directly drives the Capacitor Digital-to-Analog Converter (CDAC) portion of the TSC2003. Therefore, the input current is very low, typically < 6µA.
VREF
+VDD
This situation is remedied, as shown in Figure 5, by using the differential mode: the +REF and –REF inputs are connected directly to Y+ and Y–, respectively. This makes the A/D converter ratiometric. The result of the conversion is always a percentage of the external reference, regardless of how it changes in relation to the on-resistance of the internal switches.
+VDD Y+
X+
+IN
+REF
Y+ Converter
–IN
–REF
Y–
X+
+IN
+REF Converter
–IN
–REF
GND
Y–
FIGURE 4. Simplified Diagram of Single-Ended Reference. GND
FIGURE 5. Simplified Diagram of Differential Reference (Y Switches Enabled, X+ is Analog Input).
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Differential reference mode always uses the supply voltage, through the drivers, as the reference voltage for the A/D converter. VREF cannot be used as the reference voltage in differential mode. It is possible to use a high-precision reference on VREF in single-ended reference mode for measurements which do not need to be ratiometric (i.e., battery voltage, temperature measurement, etc.). In some cases, it could be possible to power the converter directly from a precision reference. Most references can provide enough power for the TSC2003, but they might not be able to supply enough current for the external load, such as a resistive touch screen.
the Temperature Coefficient (TC) of this voltage is very consistent at –2.1mV/°C. During the final test of the end product, the diode voltage would be stored at a known room temperature, in memory, for calibration purposes by the user. The result is an equivalent temperature measurement resolution of 0.3°C/LSB.
X+ MUX
A/D Converter
TOUCH SCREEN SETTLING In some applications, external capacitors may be required across the touch screen for filtering noise picked up by the touch screen (i.e., noise generated by the LCD panel or backlight circuitry). These capacitors will provide a low-pass filter to reduce the noise, but they will also cause a settling time requirement when the panel is touched. The settling time will typically show up as a gain error. The problem is that the input and/or reference has not settled to its final steadystate value prior to the A/D converter sampling the input(s), and providing the digital output. Additionally, the reference voltage may still be changing during the measurement cycle. To resolve these settling time problems, the TSC2003 can be commanded to turn on the drivers only without performing a conversion (see Table I). Time can then be allowed before the command is issued to perform a conversion. Generally, the time it takes to communicate the conversion command over the I2C bus is adequate for the touch screen to settle.
TEMPERATURE MEASUREMENT In some applications, such as battery recharging, a measurement of ambient temperature is required. The temperature measurement technique used in the TSC2003 relies on the characteristics of a semiconductor junction operating at a fixed current level to provide a measurement of the temperature of the TSC2003 chip. The forward diode voltage (VBE) has a well-defined characteristic versus temperature. The temperature can be predicted in applications by knowing the 25°C value of the VBE voltage and then monitoring the delta of that voltage as the temperature changes. The TSC2003 offers two modes of temperature measurement. The first mode requires calibrations at a known temperature, but only requires a single reading to predict the ambient temperature. A diode is used during this measurement cycle. The voltage across the diode is connected through the MUX for digitizing the diode forward bias voltage by the A/D converter with an address of C3 = 0, C2 = 0, C1 = 0, and C0 = 0 (see Table I and Figure 6 for details). This voltage is typically 600mV at +25°C, with a 20µA current through it. The absolute value of this diode voltage can vary a few millivolts;
Temperature Select TEMP0
TEMP1
FIGURE 6. Functional Block Diagram of Temperature Measurement Mode. The second mode does not require a test temperature calibration, but uses a two-measurement method to eliminate the need for absolute temperature calibration and for achieving 2°C/LSB accuracy. This mode requires a second conversion with an address of C3 = 0, C2 = 1, C1 = 0, and C0 = 0, with an 91 times larger current. The voltage difference between the first and second conversion using 91 times the bias current will be represented by kT/q • 1n (N), where N is the current ratio = 91, k = Boltzmann's constant (1.38054 • 10–23 electrons volts/degrees Kelvin), q = the electron charge (1.602189 • 10–19 C), and T = the temperature in degrees Kelvin. This mode can provide improved absolute temperature measurement over the first mode, but at the cost of less resolution (1.6°C/LSB). The equation to solve for °K is: °K =
q • ∆V k • 1n(N)
(1)
where: ∆V = V(I91) – V(I1) (in mV) ∴ oK = 2.573∆VoK/mV o
C = 2.573 • ∆V(mV) – 273o K
NOTE: The bias current for each diode temperature measurement is only turned ON during the acquisition mode, and, therefore, does not add any noticeable increase in power, especially if the temperature measurement only occurs occasionally.
TSC2003
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SBAS162D
BATTERY MEASUREMENT An added feature of the TSC2003 is the ability to monitor the battery voltage on the other side of the voltage regulator (DC/DC converter), as shown in Figure 7. The battery voltage can vary from 0.5V to 6V, while the voltage regulator maintains the voltage to the TSC2003 at 2.7V, 3.3V, etc. The input voltage (VBAT1 or VBAT2) is divided down by 4 so that a 6.0V battery voltage is represented as 1.5V to the A/D converter. The simplifies the multiplexer and control logic. In order to minimize the power consumption, the divider is only ON during the sample period which occurs after control bits C3 = 0, C2 = 0, C1 = 0, and C0 = 1 (VBAT1) or C3 = 0, C2 = 1, C1 = 0, and C0 = 1 (VBAT2) are received. See Tables I and II for the relationship between the control bits and configuration of the TSC2003.
The second method requires knowing both the X-Plate and Y-Plate resistance, measurement of X-Position and Y-Position, and Z1. Equation 3 calculates the touch resistance using the second method: R TOUCH =
R X −Plate • X − Position 4096 – 1 4096 Z 1
Y − Position –R Y −Plate • 1– 4096
(3)
Measure X-Position X+
Y+ Touch
2.7V
DC/DC Converter Battery 0.5V to 6.0V
X-Position
+
Y–
X–
VDD
Measure Z1-Position Y+
X+ 0.125V to 1.5V VBAT
A/D Converter
Touch
7.5kΩ
Z1-Position
2.5kΩ
X–
Y+
X+
FIGURE 7. Battery Measurement Functional Block Diagram.
Y–
Touch
PRESSURE MEASUREMENT Measuring touch pressure can also be done with the TSC2003. To determine pen or finger touch, the pressure of the “touch” needs to be determined. Generally, it is not necessary to have high accuracy for this test, therefore, the 8-bit resolution mode is recommended. However, calculations will be shown with the 12-bit resolution mode. There are several different ways of performing this measurement—the TSC2003 supports two methods. The first method requires knowing the X-Plate resistance, measurement of the X-Position, and two additional cross-panel measurements (Z2 and Z1) of the touch screen, as shown in Figure 8. Using Equation 2 will calculate the touch resistance: RTOUCH = RX −Plate •
X − Position 4096
Z2 – 1 Z1
(2)
Z2-Position X–
Measure Z2-Position
FIGURE 8. Pressure Measurement Block Diagrams.
DIGITAL INTERFACE The TSC2003 supports the I2C serial bus and data transmission protocol in all three defined modes: standard, fast, and high-speed. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are slaves. The bus must be controlled by a master device which generates the
TSC2003 SBAS162D
Y–
13 www.ti.com
serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The TSC2003 operates as a slave on the I2C bus. Connections to the bus are made via the open-drain I/O lines SDA and SDL.
stable LOW during the HIGH period of the acknowledge clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
The following bus protocol has been defined, as shown in Figure 9:
Figure 9 details how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two types of data transfer are possible:
• Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as control signals.
• Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after the slave address and each received byte.
Accordingly, the following bus conditions have been defined: Bus Not Busy: Both data and clock lines remain HIGH. Start Data Transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH defines a START condition.
• Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next, a number of data bytes are transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last one. At the end of the last received byte, a ‘not acknowledge’ is returned.
Stop Data Transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH defines a STOP condition. Data Valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data.
The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus will not be released.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise, and each receiver acknowledges with a ninth-bit.
The TSC2003 may operate in the following two modes: • Slave Receiver Mode: Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit.
Within the I2C bus specifications, a standard mode (100kHz clock rate), a fast mode (400kHz clock rate), and a high-speed mode (3.4MHz clock rate) are defined. The TSC2003 works in all three modes.
• Slave Transmitter Mode: The first byte (the slave address) is received and handled as in the slave receiver mode. However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted on SDA by the TSC2003 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer.
Acknowledge: Each receiving device, when accessed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse, which is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is
SDA Slave Address
R/W Direction Bit
Acknowledgement Signal from Receiver
Acknowledgement Signal from Receiver 1
SCL
2
6
7
8
9 ACK
START Condition
1
2
3-7
8
9 ACK
Repeated If More Bytes Are Transferred
STOP Condition or Repeated START Condition
FIGURE 9. I2C Bus Protocol.
TSC2003
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SBAS162D
Address Byte The address byte, as shown in Figure 10, is the first byte received following the START condition from the master device. The first five bits (MSBs) of the slave address are factory preset to 10010. The next two bits of the address byte are the device select bits: A1 and A0. Input pins (A1-A0) on the TSC2003 determine these two bits of the device address for a particular TSC2003. Therefore, a maximum of four devices with the same preset code can be connected on the same bus at one time.
It is recommended to set PD0 = 0 in each command byte to get the lowest power consumption possible. If multiple X-, Y-, and Z-position measurements will be done one right after another, such as when averaging, PD0 =1 will leave the touch screen drivers on at the end of each conversion cycle.
LSB
MSB 0
1
0
1
0
A1
A0
R/W
FIGURE 10. Address Byte. The A1-A0 Address Inputs can be connected to VDD or digital ground. The last bit of the address byte (R/W) defines the operation to be performed. When set to a “1”, a read operation is selected; when set to a “0”, a write operation is selected. Following the START condition, the TSC2003 monitors the SDA bus and checks the device type identifier being transmitted. Upon receiving the 10010 code, the appropriate device select bits, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line. The TSC2003’s operating mode is determined by a command byte, which is shown in Figure 11. LSB
MSB C2
C1
• M: Mode bit. If M is 0, the TSC2003 is in 12-bit mode. If M is 1, 8-bit mode is selected. • X: Don’t care. PD1
PD0
PENIRQ
DESCRIPTION
0 0 1 1
0 1 0 1
Enabled Disabled Enabled Disabled
Power-Down Between Conversions Internal reference OFF, ADC(1) ON Internal reference ON, ADC(1) OFF Internal reference ON, ADC(1) ON
NOTE: (1) ADC = Analog-to Digital Converter.
TABLE II. Power-Down Bit Functions.
Command Byte
C3
The internal reference voltage can be turned ON or OFF independently of the A/D converter. This can allow extra time for the internal reference voltage to settle to its final value prior to making a conversion. Make sure to allow this extra wakeup time if the internal reference was powered down. Also note that the status of the internal reference power down is latched into the part (internally) when a STOP or repeated START occurs at the end of a command byte (see Figures 12 and 14). Therefore, in order to turn the internal reference OFF, an additional write to the TSC2003, with PD1 = 0, is required after the channel has been converted.
C0
PD1
PD0
M
X
When the TSC2003 powers up, the power-down mode bits need to be written to ensure that the part is placed into the desired mode to achieve lowest power. Therefore, immediately after power-up, a command byte should be sent which sets PD1 = PD0 = 0, so that the device will be in the lowest power mode, powering down between conversions.
FIGURE 11. Command Byte.
Start A Conversion/Write Cycle
The bits in the device command byte are defined as follows:
A Conversion/Write Cycle begins when the master issues the address byte containing the slave address of the TSC2003, with the eighth bit equal to a 0 (R/W = 0), as shown in Figure 10. Once the eighth bit has been received, and the address matches the A1-A0 address input pin setting, the TSC2003 issues an acknowledge.
• C3-C0: Configuration bits. These bits set the input multiplexer address and functions that the TSC2003 will perform, as shown in Table I. • PD1-PD0: Power-down bits. These two bits select the power-down mode that the TSC2003 will be in after the current command completes, as shown in Table II.
C3
C2
C1
C0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
FUNCTION Measure TEMP0 Measure VBAT1 Measure IN1 Reserved Measure TEMP1 Measure VBAT2 Measure IN2 Reserved Activate X– Drivers Activate Y– Drivers Activate Y+, X– Drivers Reserved Measure X Position Measure Y Position Measure Z1 Position Measure Z2 Position
INPUT to ADC TEMP0 VBAT1 IN1 – TEMP1 VBAT2 IN2 – – – – – Y+ X+ X+ Y–
X-DRIVERS OFF OFF OFF – OFF OFF OFF – ON OFF X– ON – ON OFF X– ON X– ON
Y-DRIVERS OFF OFF OFF – OFF OFF OFF – OFF ON Y+ ON – OFF ON Y+ ON Y+ ON
REFERENCE MODE Single-Ended Single-Ended Single-Ended Single-Ended Single-Ended Single-Ended Single-Ended Single-Ended Differential Differential Differential Differential Differential Differential Differential Differential
TABLE I. Possible Input Configurations.
TSC2003 SBAS162D
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Read A Conversion/Read Cycle
Once the master receives the acknowledge bit from the TSC2003, the master writes the command byte to the slave (see Figure 11). After the command byte is received by the slave, the slave issues another acknowledge bit. The master then ends the Write Cycle by issuing a repeated START or a STOP condition, as shown in Figure 12. If the master sends additional command bytes after the initial byte, before sending a STOP or repeated START condition, the TSC2003 will not acknowledge those bytes.
For best performance, the I2C bus should remain in an idle state while an A/D conversion is taking place. This prevents digital clock noise from affecting the bit decisions being made by the TSC2003. The master should wait for at least 10µs before attempting to read data from the TSC2003 to realize this best performance. However, the master does not need to wait for a completed conversion before beginning a read from the slave, if full 12-bit performance is not necessary.
The input multiplexer for the A/D converter has its channel selected when bits C3 through C0 are clocked in. If the selected channel is an X-,Y-, or Z-position measurement, the appropriate drivers will turn on once the acquisition period begins.
Data access begins with the master issuing a START condition followed by the address byte (see Figure 10) with R/W = 1. Once the eighth bit has been received, and the address matches, the slave issues an acknowledge. The first byte of serial data will follow (D11-D4, MSB first).
When R/W = 0, the input sample acquisition period starts on the falling edge of SCL once the C0 bit of the command byte has been latched, and ends when a STOP or repeated START condition has been issued. A/D conversion starts immediately after the acquisition period. The multiplexer inputs to the A/D converter are disabled once the conversion period starts. However, if an X-, Y-, or Z-position is being measured, the respective touch screen drivers remain on during the conversion period. A complete Write Cycle is shown in Figure 12.
After the first byte has been sent by the slave, it releases the SDA line for the master to issue an acknowledge. The slave responds with the second byte of serial data upon receiving the acknowledge from the master (D3-D0, followed by four 0 bits). The second byte is followed by a NOT acknowledge bit (ACK = 1) from the master to indicate that the last data byte has been received. If the master acknowledges the second data byte, then the data will repeat on subsequent reads with ACKs between bytes. This is true in both 12-bit and 8-bit mode. The master will then issue a STOP condition, which ends the Read Cycle, as shown in Figure 13.
SCL
Address Byte
1
SDA
0
0
1
Command Byte
0
A1
A0
R/W 0
0
C3
C2
C1
C0 PD1 PD0
TSC2003 ACK
M
0
X
TSC2003 ACK Acquisition
START
Conversion STOP or REPEATED START
FIGURE 12. Complete I2C Serial Write Transmission.
SCL Address Byte
SDA
START
1
0
0
1
0
Date Byte 2
Date Byte 1
A1 A0 R/W 1
0
D11 D10
D9 D8 D7 D6 D5 D4
TSC2003 ACK
0
D3 D2 D1 D0
MASTER ACK
0
0
0
0
1
MASTER NACK STOP or REPEATED START
FIGURE 13. Complete I2C Serial Read Transmission.
TSC2003
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SBAS162D
I2C High-Speed Operation FS = Full-Scale Voltage = VREF(1) 1LSB = VREF(1)/4096
The TSC2003 can operate with high-speed I2C masters. To do so, the simple resistor pull-up on SCL must be changed to the active pull-up, as recommended in the I2C specification.
1LSB 11...111
I2C
bus will be operating in standard or fast mode The initially. Following a START condition, the master will send the code 00001xxx, which the slave will not acknowledge. At this point, the bus is now operating in high-speed mode. The bus will remain in high-speed mode until a STOP condition occurs. Therefore, to maximize throughput only repeated STARTs should be used to separate transactions.
Output Code
11...110
00...000
Input Voltage(2) (V) NOTES: (1) Reference voltage at converter: +REF – (–REF). See Figure 2. (2) Input voltage at converter, after multiplexer: +IN – (–IN). See Figure 2
FIGURE 15. Ideal Input Voltages and Output Codes.
The TSC2003 output data is in Straight Binary format, as shown in Figure 15. This shows the ideal output code for the given input voltage, and does not include the effects of offset, gain, or noise.
LAYOUT The following layout suggestions should provide optimum performance from the TSC2003. However, many portable applications have conflicting requirements concerning power, cost, size, and weight. In general, most portable devices have fairly “clean” power and grounds because most of the internal components are very low power. This situation would mean less bypassing for the converter's power, and less concern regarding grounding. Still, each situation is unique, and the following suggestions should be reviewed carefully.
8-Bit Conversion The TSC2003 provides an 8-bit conversion mode (M = 1) that can be used when faster throughput is needed, and the digital result is not as critical (for example, measuring pressure). By switching to the 8-bit mode, a conversion result can be read by transferring only one data byte. This shortens each conversion by four bits and reduces data transfer time which results in fewer clock cycles and provides lower power consumption.
HS-Mode Enabled
F/S Mode 0
0
Sr
1
0
0
0
1
X
X
X
N
A/D Converter Powers Up and Begins Sampling
A/D Converter Power-Down Mode 1
0
FS – 1LSB
0V
Data Format
0
00...010 00...001
Since the TSC2003 may not have completed a conversion before a read to the part can be requested, the TSC2003 is capable of stretching the clock until the converted data is stored in its internal shift register. Once the data is latched, the TSC2003 will release the clock line so that the master can receive the converted data. A complete high-speed Conversion Cycle is shown in Figure 14.
S
11...101
A1
A0
W
A
C3
C2
C1
C0
PD1
PD0
M
X
A
Programmable
Fixed Address Part
A/D Converter Stops Sampling and Begins Conversion Using Internal Clock Sr
1
0
0
1
0
A1
A0
R
A
SCLH is stretched LOW until A/D Converter is finished converting data.
A/D Converter Goes Into Power-Down Mode After Finishing Conversion (If PD0 = 0) D11
D10
D9
D8
D7
D6
D5
D4
A
D3
D2
Exit HS-Mode and Enter F/S Mode D1
D0
0
0
0
0
N
P
16 Bits + Ack S = START Sr = REPEATED START P = STOP
= Master Controls Bus = Slave Controls Bus
FIGURE 14. High-Speed I2C Mode Conversion Cycle.
TSC2003 SBAS162D
17 www.ti.com
For optimum performance, care should be taken with the physical layout of the TSC2003 circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Therefore, during any single conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and high-power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. The error can change if the external event changes in time with respect to the SCL input. With this in mind, power to the TSC2003 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1µF to 10µF capacitor may also be needed if the impedance of the connection between +VDD and the power supply is high. A bypass capacitor is generally not needed on the VREF pin because the internal reference is buffered by an internal op amp. If an external reference voltage originates from an op amp, make sure that it can drive any bypass capacitor that is used without oscillation. The TSC2003 architecture offers no inherent rejection of noise or voltage variation in regards to using an external reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. While high-frequency noise can be filtered out, voltage variation due to line frequency (50Hz or 60Hz) can be difficult to remove. The GND pin should be connected to a clean ground point. In many cases, this will be the “analog” ground. Avoid connections which are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply entry point. The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry.
PENIRQ output is HIGH. While in the power-down mode, with PD0 = 0, the Y– driver is ON and connected to GND, and the PENIRQ output is connected to the X+ input. When the panel is touched, the X+ input is pulled to ground through the touch screen, and PENIRQ output goes LOW due to the current path through the panel to GND, initiating an interrupt to the processor. During the measurement cycle for X-, Y-, and Z-Position, the X+ input will be disconnected from the PENIRQ pull-down transistor to eliminate any leakage current from the pull-up resistor to flow through the touch screen, thus causing no errors. In addition to the measurement cycles for X-, Y-, and Zposition, commands which activate the X-drivers, Y-drivers, Y+ and X-drivers without performing a measurement also disconnect the X+ input from the PENIRQ pull-down transistor and disable the pen-interrupt output function regardless of the value of the PD0 bit. Under these conditions, the PENIRQ output will be forced LOW. Furthermore, if the last command byte written to the TSC2003 contains PD0 = 1, the pen-interrupt output function will be disabled and will not be able to detect when the panel is touched. In order to re-enable the pen-interrupt output function under these circumstances, a command byte needs to be written to the TSC2003 with PD0 = 0. Once the bus master sends the address byte with R/W = 0 (see Figure 10) and the TSC2003 sends an acknowledge, the pen-interrupt function is disabled. If the command which follows the address byte has PD0 = 0, then the pen-interrupt function will be enabled at the end of a conversion. This is approximately 10µs (12-bit mode) or 7µs (8-bit mode) after the TSC2003 receives a STOP/START condition following the reception of a command byte (see Figures 12 and 14 for further details of when the conversion cycle begins). In both cases listed above, it is recommended that the master processor mask the interrupt which the PENIRQ is associated with whenever the host writes to the TSC2003. This will prevent false triggering of interrupts when the PENIRQ line is disabled in the cases listed above. VDD
In the specific case of use with a resistive touch screen, care should be taken with the connection between the converter and the touch screen. Since resistive touch screens have fairly low resistance, the interconnection should be as short and robust as possible. Longer connections will be a source of error, much like the on-resistance of the internal switches. Likewise, loose connections can be a source of error when the contact resistance changes with flexing or vibrations.
30kΩ to 100kΩ VDD
PENIRQ VDD
10kΩ TEMP0
TEMP1
Y+
As indicated previously, noise can be a major source of error in touch screen applications (e.g., applications that require a backlit LCD panel). This EMI noise can be coupled through the LCD panel to the touch screen and cause “flickering” of the converted data. Several things can be done to reduce this error, such as utilizing a touch screen with a bottom-side metal layer connected to ground. This will couple the majority of noise to ground. Additionally, filtering capacitors from Y+, Y–, X+, and X– to ground can also help.
HIGH except when TEMP0, TEMP1 activated
TEMP DIODE
X+
Y– ON Y+ or X+ drivers on, or TEMP0, TEMP1 measurements activated
PENIRQ OUTPUT The pen-interrupt output function is shown in Figure 16. By connecting a pull-up resistor to VDD (typically 100kΩ), the
FIGURE 16. PENIRQ Functional Block Diagram.
TSC2003
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SBAS162D
PACKAGE OPTION ADDENDUM www.ti.com
29-Sep-2004
PACKAGING INFORMATION ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
TSC2003IPW
ACTIVE
TSSOP
PW
16
94
TSC2003IPWR
ACTIVE
TSSOP
PW
16
2500
TSC2003IPWRG4
PREVIEW
TSSOP
PW
16
2000
TSC2003IZQCR
ACTIVE
BGA MICROSTAR JUNIOR
ZQC
48
2500
(1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
MECHANICAL DATA MPBG309 – SEPTEMBER 2002
ZQC (S-PBGA-N48)
PLASTIC BALL GRID ARRAY
4,10 SQ 3,90
3,00 TYP 0,50
G F 0,50
E D
3,00 TYP
C B A 1
A1 Corner
2
3
4
5
6
7
Bottom View 0,77 0,71
1,00 MAX
Seating Plane 0,35 0,25
0,25 0,15
0,08
0,05
4204695/A 09/02 NOTES: A. B. C. D. E.
All linear dimensions are in millimeters. This drawing is subject to change without notice. MicroStar Junior BGA package configuration. Falls within JEDEC MO-225 This package is lead-free.
MicroStar Junior is a trademark of Texas Instruments.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30 0,19
0,65 14
0,10 M
8
0,15 NOM 4,50 4,30
6,60 6,20 Gage Plane 0,25
1
7 0°– 8° A
0,75 0,50
Seating Plane 0,15 0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97 NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
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