Transcript
Tunable Integrated Channel Select Filter at RF using Differential Quadrature Feedback Mackenzie Cook Department of Electronics, Carleton University Ottawa, Ontario, K1S 5B6 Email:
[email protected]
Abstract— A tunable integrated channel select filter was designed using differential quadrature feedback. This paper describes a feedback technique used to create a channel select filter for a heterodyne FM receiver. Full system level study and simulation in Simulink is presented to demonstrate the method’s viability. A full transistor level design and simulation demonstrates the implementation of this technique in an IC design. The IC prototype was fabricated in a 2.5µm NMOS process at Carleton University and had a layout area of approximately 4mm2. The simulated transistor level design achieved 18.6dB stop band attenuation with 11.3dB adjacent channel rejection.
I.
INTRODUCTION
A modern cellular phone utilizes a multitude of radios, including CDMA, LTE, GSM, Bluetooth, GPS, Near Field Communication, Wifi, and FM Radio. All of these standards require band pass filters and could benefit from this technique. To put the cost measures into perspective, a cost savings as little as 10 cents can be substantial for a product of high volume. Samsung, for example [1], sold nearly 400 million phones in 2012. 10 cents savings per phone equates to $40 million, therefore it is advantageous to attempt even minor cost saving measures. This method of channel selection is a significant step forward for filter design [2]. Modern filter techniques usually produce a non-tunable, off-chip filter. This technique enables a designer to produce an on-chip tunable filter. A reduction in off chip components will reduce product area requirements and could have significant cost savings on high volume products. Any developer that produces an integrated product with a band pass filter would see benefits from using this technique. Typical receivers contain several filters. Eventually after down conversion, the desired signal will be centered in the pass band of a channel select filter to eliminate adjacent channels. The feedback loop system presented in this paper acts as a tunable channel select filter at RF frequencies. This will eliminate much of the filtering requirements in the front end and only use a single high pass filter within the loop. It
will allow for the removal of the traditionally off chip channel select filter to enable much greater system integration. This method of channel selection is able to achieve a very high Q with a single series capacitor. Reduction in off chip components will allow a manufacturer to either reduce overall board size, or add additional features without increasing the required board area. This may allow the product to be more competitive by reducing the overall cost, having more features for a similar cost, or having a smaller form factor. II.
THEORY
A simplified block diagram of the feedback structure presented in this paper is shown in Figure 1. This system transforms a first order high pass filter into a high ordered band pass filter through negative feedback with frequency translation within the loop.
Figure 1: Simplified Block Diagram of Feedback Structure
The high pass filter in the loop is translated to a notch filter centered at ωLO via the mixer. This notch is then subtracted from the input (flat response) to give an overall band-pass response centered at ωLO. The bandwidth of the band pass is determined by the corner frequency of the high pass filter, and the loop gain, A. A generic first-order high pass filter response is given by:
(1) The transfer function in (1) is shifted by ωLO in the mixer to give: (2) which can be simplified to:
From (7), it can be noted that the closed loop gain is inversely proportional to the loop gain, A. Thus, more loop gain will provide greater rejection. Given a desired rejection ratio, the required loop gain can be calculated and used with the desired bandwidth to calculate the open loop pole location from (6) to meet those specifications. III.
(3) The frequency response of (3) is a notch filter. Applying a negative feedback transformation to (3) results in:
QUADRATURE STRUCTURE
The analysis performed in the previous section assumes single side band (SSB) mixers, as shown in figure 1. In order to implement SSB operation, a quadrature structure was implemented, as shown in figure 3.
(4) which simplifies to the closed loop system response, given by: (5) The bode plots of equations (1), (3) and (5) are shown in figure 2. Note that a loop gain of 1, LO frequency of 1MHz and high pass corner frequency of 100kHz was used.
Figure 3. Quadrature Feedback Block Diagram
Figure 2. Bode Plot Realizations of Transfer Functions in (1),(3),and (5)
The (1+A) factor in the denominator of (5) shifts the original pole frequency down by (1+A), therefore the loop gain will reduce the bandwidth by a factor of (1+A). When designing the band pass filter, this needs to be accounted for by placing the open loop high pass filter pole according to (6) based on the desired bandwidth and loop gain. (6) where BW is the desired filter bandwidth. The zero in (5) is not affected by the loop gain, therefore the loop gain will dictate the frequency separation of the pole and zero. Increased gain will provide a greater separation, and therefore greater attenuation will be achieved. This can be observed mathematically by noting that: (7)
This structure has two identical feedback loops, however, the LO signals are 90 out of phase. Each feedback loop produces sum and difference frequencies at the input to the summer. For a single input tone, two of the generated tones from the feedback path will add constructively, and the other two will cancel due to a 180 phase shift from two sine driven mixers. This can be seen below in equations (8), (9) and (10). The cosine feedback loop will produce (8) The sine feedback loop will produce (9) (10) where B depends on the loop gain at that frequency, as determined by the filter and amplifier. When both signals converge in the summer, the undesired byproducts cancel because they are 180° out of phase, while the desired products add in phase. Thus, SSB operation is achieved and the analysis used for the block diagram in figure 1 can be applied.
The system is fully tunable as the center frequency of the filter is dictated by the LO frequency. The LO must produce a 4-phase output, i.e. 0°, 90°, 180°, 270°, corresponding to ±cos(ωLOt) and ±sin(ωLOt). IV.
CIRCUIT DESIGN
The system consists of four Gilbert cell double balanced mixers, two differential amplifiers, a current summer comprised of three differential pairs, four series capacitors to form the first-order filter, and four source follower DC level shifters. The entire system is differential and is DC coupled with the exception of the filter which requires a voltage divider bias at its output. The 4-phase reference is generated by an external VCO. Figure 4 shows the schematic design.
offered at Carleton. The limited number of wafers produced meant that the projects of the 4th year course needed to be measured for the course grading, so the priority for the measurement of this device was rather low. Additionally, due to the complex nature of the design (with 26 bond pads, 31 including the VCO), the chip needs to be wire bonded to a PCB which still needs to be designed. The university has a wire bonder capable of bonding large numbers of pads efficiently; however it has not be installed or configured yet. A combination of these reasons and a lack of time before the end of the term meant that this prototype analysis will occur during the summer of 2013 when the project is continued as part of graduate research.
Figure 5. Photomicrograph of Fabricated Chip Figure 4. Schematic for the Quadrature Feedback Loop Channel Select Filter
V.
CHIP FABRICATION
Once the layout was designed, the channel select filter was fabricated at Carleton University in a 2.5µm NMOS process. This was the first time the process produced 2.5µm designs; previously it used 5µm channel lengths. The in-house process at Carleton was chosen for a number of reasons. The cost to produce in-house was much less than at an external process. Additionally, this was the only process that had a turnaround time short enough to have chips produced before the 4th year project was completed. The designs were submitted in midFebruary and the wafers were completed in March, having a turnaround time of approximately 4 weeks. The photomicrograph is shown below in Figure 5. The in-house Carleton fabrication process provided some limitations in the circuit design. The process is NMOS-only therefore all of the components needed to be designed without PMOS transistors. There was only a single metal layer available, therefore cross connections needed to be routed through the polysilicon layer, which is much more resistive than metal. Additionally, the process is incapable of producing useful capacitors or inductors, and as a result, the chip prototype has off-chip connections for the first-order capacitor filter. Moving forward, a CMOS commercial process will be used for the second design iteration. The 4th year project group, in an effort to efficiently use resources, shared the wafer with the 4th year fabrication course
VI.
RESULTS
The circuit was simulated using PSPICE. The filter was able to achieve 18.6dB stop band rejection for a 150kHz bandwidth in the commercial FM Band (88-108MHz). With 200kHz channel spacing the adjacent channel rejection was 11.3dB. The desired channel was passed, and the channel selection frequency followed the LO frequency. Figure 6 shows the results. Various frequencies around 100MHz were fed in at the same amplitude (10mV) in order to provide an illustration of the filter shape. The power consumption was 125mW. Power consumption minimization was not a design focus for the prototype but would be a focus in the next iteration. The Q of this configuration at 100MHz with 150kHz bandwidth is calculated to be 667.
VII. CONCLUSION The objective of this project was to investigate the possibilities of quadrature feedback for creating a high-order filter with only a first-order high pass filter. A high Q filter has been realized in 2.5µm NMOS using only first order filtering. The filter in simulation was able to achieve 18.6dB of stop band rejection and 11.3dB adjacent channel rejection. Moving forward with the project, the prototype chip will be measured in the summer to continue the research in this promising field. Future work will be to implement the design in a commercial RF CMOS process in order to obtain higher levels of rejection. This will require stability at high loop gain which is currently not possible using the 2.5µm process. ACKNOWLEDGMENT
Figure 6. PSPICE Measured Results Showing Channel Selectivity
Table 1 below summarizes the performance of the filter. TABLE I.
SUMMARY OF FILTER PERFORMANCE
Parameter Stop Band Rejection Adjacent Channel Rejection Bandwidth Frequency Range1 Quality Factor2 Power Consumption Supply Voltage IC Area IC Technology 1 2
Performance 18.6dB 11.3dB 150kHz 88-108MHz 667 126mW 5V 4 mm2 2.5µm NMOS
Frequency Range determined by LO frequency range Q calculated at 100MHz center frequency with 150kHz bandwidth
I would like to personally thank my supervisors C. Plett and J. Rogers for the guidance they provided during this project. I would like to extend a special thanks to Professor Rogers; had he not had faith in my abilities I would not have had the opportunity to attempt this advanced project. I would like to thank Professor Plett for his valued assistance in my participation in the IEEE Eastern Ontario Paper Competition. Without his guidance I wouldn’t have had the tools I needed to win the competition. I would also like to thank Garry Tarr for his assistance with the fabrication process. REFERENCES [1]
[2]
Business Wire. (March 26, 2013) “Strategy Analytics: Global Mobile Phone Shipments Reach 1.6 Billion Units in 2012:, [online] Available: http://www.businesswire.com/news/home/20130124006626/en S. Youssef, R. van der Zee, B. Nauta, "Active Feedback Receiver with Integrated Tunable RF Channel Selectivity, Distortion Cancelling, 48dB Stop-Band Rejection and > +12dBm Wideband IIP3, Occupying < 0.06mm2 in 65nm CMOS", ISSCC, 2012
