Transcript
AN-655 APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: 781/329-4700 • Fax: 781/326-8703 • www.analog.com
Tunable Laser Reference Design for Designers with the ADuC832/ADN8830/ADN2830 by Nobuhiro Matsuzoe FEATURES Single Board Solution for Tunable Lasers 8-Channel Selectable Wavelength Control Wavelength Locking at 25 GHz/50 GHz Spacing AutoPower Control (APC) AutoTemperature Control (ATC) AutoFrequency Control (AFC) Laser Bias, Temperature Monitoring EEPROM-Based Autorestoring Serial Interfaces (SPI®/I2C®/RS-232) to Host System Wavelength Stability < 2 pm (typ) LD Temperature Stability < 0.01°C APPLICATIONS DWDM Transmission System Optical Instrumentation GENERAL DESCRIPTION This tunable laser reference design offers a single board solution with complete control requirements for DFB tunable laser subsystems. Designed to work from +3 V/–5 V power supplies, it provides a low cost, low power tunable laser solution designed for ease of use with standard serial control interfaces. A mixed-signal monolithic microprocessor, the ADuC832based wave locker feedback loop is designed to meet the requirements of ITU-T grid spacing in a 50 GHz/25 GHz system. An integrated 12-bit ADC with an 8-channel multiplexer allows users to monitor laser bias current and laser temperature via SPI, I2C, or RS-232C serial interfaces. The ADN2830 laser bias controller can sink up to 200 mA (single)/400 mA (dual) and its integrated feedback control loop can maintain output optical power constant over temperature changes during wave locking. The ADN8830 TEC controller enables excellent laser temperature stability and precise wavelength control with 1 pm resolution. A patented PWM/linear based TEC drive architecture enables high efficiency and minimizes external filtering components.
FUNCTIONAL BLOCK DIAGRAM
MUX
MICROCONVERTER
GPIO
12-BIT DAC
i8051
12-BIT DAC
AUTO-ZERO OP AMP
AD8628
ADuC832
AUTO-ZERO OP AMP
TEC CONTROLLER
2.5V REFERENCE
ADN8830
AD8628
ADR291 TEC
ETALON FILTER WAVELENGTH MONITOR PD POWER MONITOR PD
AD8565
REV. B
12-BIT SER ADC
T/H
THERMISTOR
CW LASER
8 TUNABLE LASER CW LASER AVERAGE POWER CONTROLLER
ADN2830
AN-655 TURNABLE LASER MODULE
THERMISTOR
TEC
WAVE LOCKER
POWER MONITOR
LASER DIODE
MODULATOR
CONTINUOUS OPTICAL OUT
TEC CONTROLLER ADN8830
I/V AD8628
DIGITAL I/O
MICROPROCESSOR
SERIAL PORT
MODULATED OPTICAL OUT
TRANSMIT DATA
LASER CONTROLLER ADN2830
ANALOG I/O
2
2 I2C LINK TO HOST
MICROCONVERTER ADuC832
Figure 1. Typical Block Diagram of Optical Transmitter with DFB Laser Module Free Spectral Range (FSR) cycle FS, is precalibrated by the manufacturer to align with the ITU grid spacing as shown in Figure 2b. Because the monitor signal has periodic cycles, the algorithm of wavelength locking requires two different tuning methods, coarse tuning, and fine tuning. During the first phase, the laser temperature must settle to the particular temperature corresponding to the target wavelength, where the wavelength is assumed within the capture range. In the case of Figure 2b, there are two locking points on both slopes, positive slope and negative slope, within a single FSR. Thus, the capture range must be half of the SFR. Feedforward control with a look-up table is used in this coarse tuning phase. After the wavelength settles within the capture range, the fine tuning phase acquires the wave length errors between the target wavelength and actual wavelength by monitoring the wave locker signal. Then the wavelength errors will be fed back to the temperature control circuit. The fine tuning phase maintains the wavelength within an allowable wavelength deviation range over ambient temperature changes. The ITU-T recommendation specifies wavelength stability as a frequency deviation in G.692. This deviation is defined as the difference between the nominal central frequency and the actual central frequency (Figure 2c). A maximum frequency deviation is given by
WAVELENGTH TUNING Because an optical transmitter requires a small formfactor design, use of the refractive index of a semiconductor laser is commonly used to alter the wavelength. As the refractive index can be changed by both the temperature and the density of carriers, transmitter designers can choose from two different types of the wavelength-tunable laser modules—distributed feedback (DFB) lasers and distributed Bragg reflector (DBR) lasers. In general, the DBR laser is capable of a fast tuning speed and a wide tuning range. However, it requires multiple programmable current sources for wavelength control, which results in a complex system design. In contrast, the DFB lasers can be controlled by temperature of the laser chip, which results in a lower system cost and higher reliability since the DFB lasers are widely used today. The wavelength of the DFB laser is related to temperature with a typical temperature coefficient of 0.1 nm/K. By using a thermoelectric cooler (TEC) and a thermistor with a built-in module, the laser chip temperature can be adjusted, thus wavelength is controlled. Figure 1 shows a simplified block diagram of an optical transmitter designed with the DFB laser. The wavelength tuning range of the DFB laser is limited by an allowable operating temperature range. In fact, DFB lasers provide a tuning range of a couple of nanometers which is equivalent to 8 to 16 ITU-T grid channels depending on the channel-to-channel spacing of the wavelength.
∆f < (FS – 2.0B ) /4 where: FS is the frequency slot
WAVELENGTH LOCKING The internal or external wavelength locker generates two monitor signals corresponding to the wavelength and optical output power respectively. The wavelength locker consists of the wavelength selective element and the photodetector diode as shown in Figure 2a. The builtin Fabry Perot etalon works as a wavelength filter which has a periodic characteristic similar to a comb filter. The peak-to-peak range of the etalon filter, referred to as the
B is the bit rate. In 10 Gbps transmit applications with 50 GHz Grid spacing, the frequency deviation f must be less than 7.5 GHz which means wavelength deviation must be less than 67 pm. The test result of the wavelength deviation taken by the reference design is shown in Figure 2d.
–2–
REV. B
AN-655 OPTICAL INPUT
POWER MPD
TO µC
I/V
TO µC
I/V
DEMONSTRATION BOARD The tunable laser reference design board (demo board) demonstrates autopower control (APC), autotemperature control (ATC) and autofrequency control (AFC). Figure 3 shows simplified setup of the demo board. The demo board has a mount space for a tunable DFB laser module in a 14-lead butterfly package. The demo board also provides a power supply terminal, analog I/O ports, and a serial port. To mount laser modules, a power photodetector must be floating within the laser module package as seen in Figure 4.
OPTICAL OUTPUT
ETALON FILTER
WAVELENGTH MPD WAVELENGTH LOCKER
COMPUTER
Figure 2a. Wavelength Locker Block Diagram
POWER SUPPLY (+5V/–5V)
RS-232C CABLE
WAVELENGTH MONITOR PD MONITOR CURRENT (A)
LOCK POINT
POWER MONITOR PD
FSR WAVELENGTH (nm)
LASER MODULE
Figure 2b. Wavelength Locker Characteristics
FC-APC (PANDA FIBER)
WAVELENGTH METER
OPTICAL POWER (dB)
TUNABLE RANGE = 3nm FS F
Figure 3. Demo Board Setup 6
7
5
4
3
2
1
WAVELENGTH (THz) TEC
Figure 2c. Frequency Slots and Allowable Frequency Deviation
RTH
PD1
PD2
8
9
10
11
12
13
14
Figure 4. Laser Module Pin Assignment (reference: Fujitsu Quantum Devices, FLD5F6CA Data Sheet)
NOTES 1. 1-HOUR WAVELENGTH STABILITY AT 25C, WAVE LOCKER ENABLED, 2 SEC INTERVAL. 2. F: LOCK POINT 1.5pm MAX TO MIN: 3pm. 3. LASER: FLD5F15CA, FUJITSU QUANTUM DEVICES LTD. 4. THE WAVELENGTH STABILITY IS MEASURED IN 3pm ACCURACY. 5. AFC STABILITY IS AFFECTED BY ACCUMULATIVE ERRORS OF APC AND ATC CONTROL LOOP.
Figure 2d. AFC Typical Performance
REV. B
–3–
AN-655 GETTING STARTED To ensure proper operation, follow the steps below. 1)
Calculate the target voltages of the wavelength lock point according to the following equation:
[ ]
VLOCKPOINT = VREF – (R 46 × Im2 ) V where:
[ ] [ ]
VREF = 2.50 V
R 46 = 2490 Ω
The photo current Im2 needs to be solved at each lock point, because the Im2 may differ from lock point to lock point, laser to laser. Table 1 is an example of the calculation result from the 8-channel wavelength tunable laser module. Table 1. Wavelength [nm]
2)
Im2
VLOCKPOINT
Lock Point ADC Code
[THz]
[mA]
[V]
[Dec]
[Hex]
0
1582.439
189.4496
521.4
1.202
1969
07B1
1
1582.851
189.4003
573.4
1.072
1757
06DD
2
1583.265
189.3508
511.4
1.227
2010
07DA
3
1583.692
189.2997
563.4
1.097
1798
0706
4
1584.110
189.2498
527.4
1.187
1944
0798
5
1584.529
189.1997
556.8
1.114
1824
0720
6
1584.942
189.1504
524.3
1.194
1957
07A5
7
1585.365
189.1000
553.3
1.122
1839
072F
Calculate the voltage setpoint for ADN8830 according to the following equation:
[ ]
VDAC = (G × TLASER ) – VOFFSET V
where: TLASER is target temperature of the thermistor in Celsius. G = 0.0658
[ ]
VOFFSET = –0.659 V
Table 2 is an example of the calculation result from the 8-channel wavelength tunable laser module. Table 2. Wavelength [nm]
RTH
TLASER
VDAC
DAC Code
[THz]
[]
[C]
[V]
[Dec]
[Hex]
Curve Slope
0
1582.439
189.4496
16810
12.191
0.144
236
00EC
Positive
1
1582.851
189.4003
14370
15.941
0.390
639
027F
Negative
2
1583.265
189.3508
12350
19.658
0.634
1040
0410
Positive
3
1583.692
189.2997
10630
23.433
0.883
1447
05A7
Negative
4
1584.110
189.2498
9220
27.106
1.125
1843
0733
Positive
5
1584.529
189.1997
8040
30.728
1.363
2233
08B9
Negative
6
1584.942
189.1504
7060
34.247
1.594
2612
0A34
Positive
7
1585.365
189.1000
6210
37.802
1.828
2996
0BB4
Negative
–4–
REV. B
AN-655 3)
Compile and download the software to the ADuC832. To select the download/debug mode, position the switch (S5) to DEBUG, and then press the reset button (S3).This sets the ADuC832 to download mode. To select the normal mode, position the switch (S5) to NORMAL and press the reset button (S3). ADuC832 executes downloaded program after reset.
4)
Mount the laser module to the mount pads labeled U13. The ADN2830 is capable of sinking a current up to 200 mA. The maximum TEC voltage limit is set at 3.5 V ±5% by default. To change the TEC voltage limiter, change the value of R24 and R25 which is configured as a voltage divider to set the voltage to the VLIM pin of ADN8830. Maximum TEC voltage can be given by:
[ ]
Maximum TEC voltage = (1.5 V − VLIM ) × 4 V 5)
Set JP1 and JP2. To protect the laser module from accidental damage, it is recommended to close JP1 and JP2 if the program has been changed. Shorting JP1 enables the ADN8830 to shut down mode regardless of control signals from the ADuC832. Shorting JP2 enables the ADN2830 to ALS (Automatic Laser Shutdown) mode regard less of control signals from ADuC832.
6)
Apply +3 V and –5 V to the power supply terminal block (J1) located at the top of the demo board.
7)
Leave JP2 open. ADN2830 starts to drive the laser diode.
8)
Calibrate the optical output power by adjusting the multiturn potentiometer (R48).
9)
Leave JP1 open. ADN8830 starts to control the laser temperature to the initial temperature setpoint selected by switch (S4).
10) Press S1 or S2 buttons to change the wavelength lock point. S1 increments and S2 decrements the wavelength point by 1. 11)
To change the target wavelength lock point directly, configure the 3-bit DIP switch (S4) according to Table 3. This change is effective only when the ADuC832 is powered up or after reset. Table 3. Ch#
S4(1)
S4(2)
S4(3)
0
OFF
OFF
OFF
1
ON
OFF
OFF
2
OFF
ON
OFF
3
ON
ON
OFF
4
OFF
OFF
ON
5
ON
OFF
ON
6
OFF
ON
ON
7
ON
ON
ON
12) 7-segment LED (DS1) displays the selected wavelength and DS1 blinks until the laser temperature is set. TEMPLOCK LED (D1) is lit when the laser temperature is settled within the capture range. WL_LOCK LED (D2) is lit when the wavelength is locked within ITU grid ±12pm.
REV. B
–5–
AN-655 To maintain optimal linearity over the required temperature range, the value of the thermistor resistance should be calculated at the lowest and the highest operating temperature according to the following equation:
INTERFACING WAVELENGTH MONITOR PD Figure 5 shows the current-to-voltage conversion circuit on the demo board. The conversion gain is set by R46. The input range of the wavelength monitor current Im2 is up to 1.0 mA by default. The wavelength monitor voltage, Vim2, is calculated by:
1 1 RTH = R25 × exp B – Tx T25
[ ]
Vim2 = 2.5 – (2490 × Im2 ) V
where:
AVDO
Im2
R25 is thermistor resistance at 25 °C. B is thermistor constant
R46 249
T25 is temperature in K. DAC1
2.5V REF
Typically, B = 3450 and R25 = 10K
Vm2
R58 NOT POPULATED
R1, R2, and R3 are given by:
R57 0
R1 =
Figure 5. I/V Conversion Circuit INTERFACING 12-BIT DAC AND ADN8830 By using the interface circuit shown in Figure 6, the laser temperature is controlled by DAC output voltage. This scales the DAC voltage range from 0 V to 2.5 V for temperature range from 10°C to 50°C. The interface circuit linearizes the thermistor transfer function. The TEMPSET pin of ADN8830 is fixed at 1.25 V. The THERMIN pin is connected to the resistor network which includes the thermistor. The characteristic of voltage-to-temperature is shown in Figure 7.
R2 = R3 =
ADN8830
THERMIN R3
RTH
Figure 6. Application Circuit Using DAC Control Voltage 2.5
IDEAL
CONTROL VOLTAGE (V)
R mid R high + R mid R low – 2R high R low R high + R low – 2 R mid
IMPLEMENTING THE WAVELENGTH LOCK As the first phase, the program executes the coarse tuning with the ADN8830 TEC controller. The program reads S4 switch position, then generates the fixed control voltage to let the ADN8830 settle the laser temperature corresponding to the selected wavelength set by S4. Because the ADN8830 has a local control loop for the temperature control, the program waits for the temperature locked signal from the ADN8830. After the laser temperature is settled within the capture range of the wavelength lock, the program starts the fine tuning. This phase uses the monitor signal from the wavelength locker. The program reads the actual wavelength and compares with the target wavelength being stored in the memory. Then the program adjusts the temperature control voltage, which corresponds to the error amount between the target wavelength and the monitored wavelength. Figure 8 shows the overview of the program flow including the course and fine tuning. Details of the course and fine tuning are shown in Figure 9 and Figure 10 respectively.
TEMPSET DAC0
2R low ′ R high ′ R low ′ + R high ′
R low ′ = R low + R 3
R2
R1
R low ′ – R high ′
where: R high ′ = R high + R 3
2.5V ADuC832
2R low ′ R high ′
ACTUAL
LINEARIZATION ERROR < 0.5%
0
10
50 THERMISTOR TEMPERATURE (C)
Figure 7. V-to-Temperature Characteristic
–6–
REV. B
AN-655 START
START COARSE TUNE
LOAD AND SET AN INITIAL TEMPERATURE
NEGATE LASER AND TEC SHUTDOWN
LASER TEMP IN CAPTURE RANGE OF WAVE LOCKER?
NO
YES START FINE TUNE
YES
TARGET CHANNEL CHANGED? NO START A/D CONVERSION
UPDATE D/A CONVERTER TO INCREMENT LASER TEMP
SET LOOP GAIN
MOVING AVERAGE FILTERING
COMPARE ACQUIRED DATA WITH TARGET DATA
UPDATE D/A CONVERTER TO DECREMENT LASER TEMP
SET LOOP GAIN
Figure 8. Overview of Program Flow Chart
REV. B
–7–
AN-655 START COARSE TUNE
TURN OFF LASER/TEC
LOAD TARGET DATA
READ S4 SWITCH
ADC GAIN/OFFSET CALIBRATION
LOCK POINT CALIBRATION
SET LOCKING SLOPE
SET TARGET TEMPERATURE
TURN ON LASER/TEC
DELAY NO
TEMPERATURE LOCKED?
GO TO FINE TUNE
Figure 9. Coarse Tuning Flow Chart
–8–
REV. B
AN-655 START FINE TUNE BACK TO COARSE TUNE
BACK TO COARSE TUNE
POSITIVE SLOPE
NEGATIVE SLOPE
CHECK SLOPE POLARITY
YES
GRID CHANNEL CHANGED?
YES
GRID CHANNEL CHANGED?
NO
NO
8 A/D CONVERSIONS
8 A/D CONVERSIONS
AVR. FILTERING
AVR. FILTERING
DELAY
DELAY
LOCKPOINT–ADC LP < ADC FLAG = 0
LOCKPOINT–ADC ELSE
DECREMENT LASER TEMPERATURE
LP > ADC FLAG = 1
INCREMENT LASER TEMPERATURE
ELSE
DECREMENT LASER TEMPERATURE
INCREMENT LASER TEMPERATURE
Figure 10. Fine Tuning Flow Chart ADuC832 SOFTWARE The demo software is written in i8051 assembly that uses 1.2 kB out of 62 kB on-chip EE/Flash and 80 bytes out of 256 bytes of on-chip RAM in ADuC832. The transaction time of the wavelength lock routine is approximately 0.3 ms at 4 MHz of the CPU core clock setting. The essential part of the program is listed below. The first control phase is labeled FF_Tune (Feed-Forward Tuning), and second control phase is labeled L_Lock (Lambda Lock). ORG 0060H
; MAIN PROGRAM
MAIN:
; ===cpu configure===
REV. B
SETB ALS
; Shutdown laser driver, ADN2830 (ACTIVE HIGH)
CLR SD
; Shutdown TEC, ADN8830 (ACTIVE LOW)
MOV ADCCON1, #11001100b
; Select Ext. Vref, single conversion
MOV DACCON, #00011111b
; DAC0 On, 12bit, Asynchronous
MOV DAC0H, #007h
; DAC0 to 4th WL, Set TEMP =28.033degC
MOV DAC0L, #096h
;
MOV PLLCON, #00000000b
; Set core clock to 16MHz
SETB EA
; Enable Interrupt
MOV P0, #00101000b
; Turn on 7SEG display with ‘8’
CLR LLOCK_LED
; Turn off WL Lock LED
MOV CALN_L, #020h
; Lock point calib. value at neg. slope
MOV CALN_H, #000h
;
MOV CALP_L, #010h
; Lock point calib. value at pos. slope
MOV CALP_H, #000h
;
MOV CALDAC_L, #000h
; DAC initial value calib. low byte
MOV CALDAC_H, #000h
; DAC initial value calib. high byte
–9–
AN-655 CALL DACDATA
; Load DAC data table to ram (30h to 3Fh)
CALL LP_DATA
; Load lock point data table to ram (40h to 4Fh)
CALL SW_DETECT
; Read 3-bit DIP SW position
CALL ADCCAL
; ADC Gain and Offset calib.
CALL AUTO_DEMO
; Enable Auto demo if S1/S2 pushed
MOV ECON, #06H
; Erase all pages of data Flash/EE
CALL REV_WRITE
; Write board and firm revision to Flash/EE
FF_TUNE:
; ===Feed-forward tuning (coarse-tune)===
SETB ALS
; Turn off Laser, Active High
CLR SD
; Turn off TEC, Active LOW
CLR PBFLAG
; Clear PBFLAG
CLR P3.6
; Turn off Temp lock LED
CALL CH_LOAD
; Load selected DAC initial value
CALL LP_LOAD
; Load selected Lock point value
CALL SLOPE_CHECK
; Check slope polarity
MOV P0, WL_SEL
; display selected wavelength ch# on 7seg
SETB LEDBI
; Turn on 7seg display
SETB LEDLE
; 7seg Latch enabled
CALL LP_CAL
; Lock point offset calibration
CALL DAC_CAL
; DAC initial value calibration
MOV DAC0H, DACINT_H
; Update DAC to target temp
MOV DAC0L, DACINT_L
; Update DAC to target temp
SETB SD
; Turn on TEC
CLR ALS
; Turn on Laser
CLR TMPLKFLAG
; Clear temp lock indicate flag
MOV R0, #00H
; SET Page Pointer ADDRESS
MOV R1, #03H
; SET Byte Location ADDRESS
MOV R2, WL_SEL
; SET 1byte Value to write
CALL EE_WRITE
; Call Flash/EE Write routine
CALL TEMP_LOCK
; Sit here until FF_Tune completion
L_LOCK:
; ===Lambda lock Loop (fine tune)=== SETB LEDBI
; Turn on 7seg display
MOV A, #07h
; Set delay time, A*12.5msec
CALL DELAY
; Call delay program, 100msec
JNB SLOPEFLAG, LL_POS
; Check slope polarity, positive or negative
LL_NEG:
; ==Lambda locking at Negative slope== CALL PB_DETECT
; Detect push-button sw
JNB PBFLAG, LOOP_N
; Jump LOOP_N if PB is not pushed
JMP FF_TUNE
; if PBFLAG=1(PB detected), back to FF_TUNE
LOOP_N: MOV A, #40d
; Set delay time, A * 12.5msec
–10–
REV. B
AN-655 CLR P2.7
; Test signal for cpu transaction monitoring
CALL DELAY
; Call delay program
SETB P2.7
; Test signal for cpu transaction monitoring
CALL ADC
; Take 8 * samples
CALL AVR
; Averaging
CALL SUBTRACT
; Subtract (LOCKPOINT - ADCDATA)
CALL LOCK_INDICATE
; Turn LED on if result is in lock range
CALL GAIN_DECISION
; Check if error amount is <2LSB, <16LSB
CALL ADJUST_N
; Call dac update routine
CALL LD_BIAS_MONITOR
; Monitor Laser Bias on ADC1
CALL LD_TEMP_MONITOR
; Convert DAC0H/L code to temperature value
CALL CPU_TEMP_MONITOR
; Monitor on-chip temp sensor
JMP LL_NEG
; Back to loop top
LL_POS:
; ==Lambda locking at Positive slope== CALL PB_DETECT
; Detect push-button sw
JNB PBFLAG, LOOP_P
; Jump LOOP_P if PB is not pushed
JMP FF_TUNE
; if PBFLAG=1(PB detected), back to FF_TUNE
LOOP_P: MOV A, #40d
; Set delay time, A * 12.5msec
CLR P2.7
; Test signal for cpu transaction monitoring
CALL DELAY
; Call delay program
SETB P2.7
; Test signal for cpu transaction monitoring
CALL ADC
; Take 8 * samples
CALL AVR
; Averaging
CALL SUBTRACT
; Subtract (LOCKPOINT - ADCDATA)
CALL LOCK_INDICATE
; Turn LED on if result is in lock range
CALL GAIN_DECISION
; Check if error amount is <2LSB, <16LSB
CALL ADJUST_P
; Call dac update routine
CALL LD_BIAS_MONITOR
; Monitor Laser Bias on ADC1
CALL LD_TEMP_MONITOR
; Convert DAC0H/L code to temperature value
CALL CPU_TEMP_MONITOR
; Monitor on-chip temp sensor
JMP LL_POS
; Back to loop top ; END OF MAIN PROGRAM
REV. B
–11–
AN-655 SOFTWARE MEMORY MAP Table 4. Internal RAM, Lower 128 Bytes Byte Address
Byte Name
Byte Description
00 to 1F
–
Reserved
20
Control Flags
Detailed in Bit Memory Map
21
WL_SEL
Wavelength select
22
CALDAC_L
Offset calibration for DAC
23
CALDAC_H
24
CALP_H
25
CALP_L
26
CALN_H
27
CALN_L
28
DACINT_H
29
DACINT_L
2A
LOCKPOINT_H
2B
LOCKPOINT_L
2C
RES_H
2D
RES_L
2E
DACNEW_L
2F
DACNEW_H
30 to 4F
–
Not used
50
AVR_H
Averaged wave locker output value
51
AVR_L
52
SUM_H
53
SUM_L
54
GAIN
Temperature control gain
58
SMPL1_H
ADC raw data #1
59
SMPL1_L
5A
SMPL2_H
5B
SMPL2_L
5C
SMPL3_H
5D
SMPL3_L
5E
SMPL4_H
5F
SMPL4_L
60
SMPL5_H
61
SMPL5_L
62
SMPL6_H
63
SMPL6_L
64
SMPL7_H
65
SMPL7_L
66
SMPL8_H
67
SMPL8_L
Offset calibration for positive locking points Offset calibration for positive locking points DAC initial voltage Wave lock point being selected Errors between actual wavelength and target wavelength Updated DAC output data
Accumulated wave locker output value
ADC raw data #2 ADC raw data #3 ADC raw data #4 ADC raw data #5 ADC raw data #6 ADC raw data #7 ADC raw data #8
–12–
REV. B
AN-655 Table 5. Internal RAM, Upper 128 Bytes
REV. B
Byte Address
Byte Name
Byte description
80
MSB
DAC initial data for channel 1
81
LSB
82
MSB
83
LSB
84
MSB
85
LSB
86
MSB
87
LSB
88
MSB
89
LSB
8A
MSB
8B
LSB
8C
MSB
8D
LSB
8E
MSB
8F
LSB
90
MSB
91
LSB
92
MSB
93
LSB
94
MSB
95
LSB
96
MSB
97
LSB
98
MSB
99
LSB
9A
MSB
9B
LSB
9C
MSB
9D
LSB
9E
MSB
9F
LSB
DAC initial data for channel 2 DAC initial data for channel 3 DAC initial data for channel 4 DAC initial data for channel 5 DAC initial data for channel 6 DAC initial data for channel 7 DAC initial data for channel 8 Wave lock point data for channel 1 Wave lock point data for channel 2 Wave lock point data for channel 3 Wave lock point data for channel 4 Wave lock point data for channel 5 Wave lock point data for channel 6 Wave lock point data for channel 7 Wave lock point data for channel 8
–13–
AN-655 Table 6. Internal RAM Bit Memory Map Byte
Bit Address
Bit Name
Bit Value
Description
20h
00h
SLOPEFLAG
1
Negative Lock curve
0
Positive Lock curve
1
Lock Point < ADCDATA
0
Lock Point > ADCDATA
1
Laser Temperature locked
0
Laser Temperature not locked
1
Button is pushed
0
Button is not pushed
01h
RESFLAG
02h
TEMPLKFLAG
03h
PBFLAG
04h
–
Not used
05h
–
Not used
06h
–
Not used
07h
–
Not used
Table 7. Internal DATA Flash/EE ROM Byte1
Byte2
Byte3
Page 000
Board rev
Farm rev
Wavelength Grid
Page 001
Laser bias
Laser bias
Laser temp
Page 002
CPU temp
CPU temp
Page 003
Not used
Byte4 Laser temp
: Page 3FF
–14–
REV. B
DAC0
VREF
1BMON
WLMON
–15–
Figure 11. Schematic–CPU
2
3
4
1 2 3 4
HEADER 4 SPI/I2C
JP7
HEADER 4 UART
1 2 JP4 3 4
PVDD
R37 1k
SW-PB
S3
C26 0.1F
DAC1
AD8628ART
U8
PVDD
1
5
AVDD
C25 0.1F
R44 0
ANALOG AUX I/O
1 2 3 JP3 4 5 6 7
16 17 18 19 22 23 24 25 26 27
7 8 9 10 15
1 2 3 4 11 12 13 14
AVDD
ADuC834
XTAX2 XTAL1 ALE PSEN EA
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
C24 0.1F
LLOCK
P3.0/RxD P2.7/PWM1 P3.1/TxD P2.6/PWM0 P3.2/INT0 P2.5 P3.3/INT1/M1SO/PWM1 P2.4 P3.4/T0/PWMC/PWM0/EXTCLK P2.3 P3.5/T1/CONVST P2.2 P3.6/WR P2.1 P3.7/RD P2.0 SCLOCK SDATA/MOSI
CREF VREF DAC0 DAC1 RESET
ADC0/P1.0/T2 ADC1/P1.1/T2EX ADC2/P1.2 ADC3/P1.3 ADC4/P1.4 ADC5/P1.5/SS ADC6/P1.6 ADC7/P1.7
PVDD
C21 0.1F
C22 0.1F
C23 0.1F
34 DVDD 20 DVDD 48 DVDD 5 AVDD
6 AGND 35 DGND 47 DGND 21 DGND
39 38 37 36 31 30 29 28
33 32 42 41 40
43 44 45 46 49 50 51 52
10k 10k 10k 10k 10k 10k SW DIP-3
S4 3 2 1
R6 R7 R8 R9 R10 R11 4 5 6
16
2
1
U9 13 12 11 10 9 15 14
Y1
3
4
3
1
R39 1k
R13 10k
R12 10k
SW-PB
HEADER 2 PWM
HEADER 2 ICE JP6 1 2
JP5 1 2
1 10 8 5 4 2 3 7
SW-PB S2
S1
287 287 287 287 287 287 287 200
ALS: ACTIVE HIGH SD: ACTIVE LOW
TEMPLOCK
SD
ALS
SW SPDT
S5 2
R49 R50 R51 R52 R53 R54 R55 R47 PVDD
C28 15pF
CD4511BCWM
SEG A SEG B SEG C SEG D SEG E SEG F SEG G
32.768kHz
8
R38 1k
C27 15pF
INA INB INC IND LE BI LT
PVDD
PVDD
7 1 2 6 5 4 3
PVDD
VDD
REV. B VSS
PVDD
d
g
b c dp 9 ccom 6 cdp
DPY a
PVDD
PVDD
DPY_7-SEG_DP
a b c f d e e f g dp
DS1
AN-655
APPENDIX [A-1] SCHEMATIC–CPU
–16–
VREF
JP1 1 2
R2 10k
AVDD
SHORT JP1 SHUTDOWN TEC [SD: ACTIVE LOW]
JUMPER
SD
PVDD
TH
DAC0
TEMPLOCK
R21 10k
8 7 6 5
C5 0.1F
R19 8.2k
R18 24k
R17 36.5k
ADR291GRU
U2 1 NC 2 NC VIN NC 3 NC VOUT 4 GND NC
R25 1k
R24 150k
R20 10k 1%
C1 0.1F
R27 205k
R28 100k C14 330pF C15 10F
R26 1M
C9 1F
R22 14.7k
PVDD
U11 3 2 B 4 Y 1 A NC7S32 5
PVDD
MM74HC123AM
U1 A1 DVCC B1 RCEXT1 CLR1 CEXT1 Q1 Q1 Q2 Q2 CEXT2 CLR2 RCEXT2 B2 DGND A2
C7 0.1F
AVDD
C10 10nF
18 17
9 10 11
19 22 21
29 28 27 26 25 24
C3 0.1F
PVDD 16 15 14 13 12 11 10 9
31 PHASE 32 TEMPOUT SYNCOUT NC SOFTSTART 1 THERMFAULT FREQ 2 THERMIN SYNCIN 3 SD OSC 4 TEMPSET 5 TEMPLOCK OUTA 6 N1 NC 7 ADN8830 VREF P1 15 OUTB VLIM 16 VTEC N2 P2 12 TEMPCTL 13 COMPFB SWIN 14 COMPOUT SWOUT
C2 0.1F
1 2 3 4 5 6 7 8
PVDD
20 PVDD 23 PGND
8 AVDD 30 AGND
AVDD
R23 150k
2
3
2 3 4
1
2 3 4
1
FDW2520C
Q6
FDW2520C
Q5
Q1 FDV301N
D1 LED (G)
R14 150
PVDD
C12 2.2nF
1
C4 0.1F
R1 10k
PVDD
1
7 6 5
8
7 6 5
8
L1
C11 10nF
PVDD
4.7F
L1
C6 0.1F
4.7F PVDD
Q2 FDV301N
D2 LED (R)
R15 150
LLOCK
2
32
1
PVDD
C13 3.3nF
TEC+
TEC– C8 22F CDE ESRD
AN-655 APPENDIX [A-2] SCHEMATIC–TEC CONTROL
Figure 12. Schematic–TBC Control
REV. B
ALS
IBMON
Figure 13. Schematic–Laser Control 1
R5 10k VSS
3
R34 10k
C20 0.1F
R36 1k
VSS
VSS
SHORT JP2 TO SHUTDOWN LASER [ALS: ACTIVE HIGH]
JP2 HEADER 2
2 1
VSS
VSS
R32 100k
Q3 FDV301N
VSS
2
3
R4 10k
R31 100k
Q7 FDV304P
R33 3k
PVDD
2
3
4
AD8565AKS VSS
5
U4
2
Q7 GATE HIGH: ALS ACTIVE Q7 GATE LOW: ALS DISABLE
1
R3 10k
PVDD
1
AVDD
R30 100k
1
R36 1k
NC
ADN2830
VSS
Q4 FDV301N
D3 LED (R)
R16 150
VSS
2
32
1
19 FAIL 18 DEGRADE
13
9 PAVCAP 10 PAVCAP 20 ALS 17 MODE
6 IMPDMON 23 IBMON 24 IBMON
8 11 12 21 25 28 IBIAS 31 IBIAS
ASET
NC NC NC NC NC 2
16 15 3 32 26
5 IMPD 4 PSET
VCC VCC VCC VCC VCC
GND GND GND GND GND GND GND
–17– 1 7 22 14 27 26 30
REV. B VSS
R42 0
8 9
4 5
3 12 13
11
3
4
2
U7
5
R58 0
R57 0
AD8628ART
1
FLD5F15
AVDD
R46 2.49k 0.1%
7 LD_C TEC– 6 LD_C TEC+ LD_A/GND 1 PD1_A TH 2 PD1_C TH 10 PD2_C NC 14 PD2_A NC
U6
IMPDMON DISABLE: R42-SHORT, R43-OPEN, R41-SHORT IMPDMON ENABLE: R42-OPEN, R43-SHORT, R41-OPEN
VSS
C19 10nF
AVDD R43 0
R48 5k
VSS
R45 1k
R41 0
C18 10nF
VSS
C17 10nF
R40 1.24k
C16 10nF
GND
R29 100k
TEC–
DAC1
VREF
WLMON
TH
TEC+
AN-655
APPENDIX [A-3] SCHEMATIC–LASER CONTROL
AN-655 APPENDIX [A] SCHEMATIC–POWER SUPPLY PVDD
J1 3 2 1 TERMINAL BLOCK
R56 150 D4 LED (G)
1
1 2
2
L2 10F
C29 100F
L3 10F
–5V 2 1
C30 100F
AVDD
1
C31 22F
2
VSS
2 1
C32 22F
Figure 14. Schematic–Power Supply APPENDIX [B] PCB LAYOUT
Figure 15. Top Layer
Figure 17. Bottom Layer
Figure 16. AGND/PGND Planes
Figure 18. AVDD/PVDD/VSS Planes
–18–
REV. B
AN-655 APPENDIX [C] BILL OF MATERIALS Provided as a software copy. APPENDIX [D] SOFTWARE SOURCE CODE Provided as a software copy. REFERENCES Analog Devices, ADuC832 Data Sheet Analog Devices, ADN8830 Data Sheet Analog Devices, ADN2830 Data Sheet Fujitsu Quantum Devices, FLD5F6CA Data Sheet Fujitsu Quantum Devices, FLD5F15CA Data Sheet ITU-T G.692
Figure 19. Top Overlay
REV. B
–19–
E03717–0–8/04(B) Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
–20–
