Transcript
Evaluation Board User Guide UG-566
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
240 W Evaluation Board Kit for the ADP1051, Digital Controller for Isolated Power Supply with PMBus Interface FEATURES
GENERAL DESCRIPTION
Full support evaluation kit for the ADP1051 240 W full bridge topology (adjustable to phase shifted full bridge topology or half bridge topology) Input voltage range: 36 V dc to 75 V dc Output voltage: 12 V dc Nominal output current: 20 A Direct paralleling with multiple boards connected to a common bus Synchronization as master device and slave device Droop current sharing and analog current sharing extension On-board tests for housekeeping functions LED indicated key status PMBusTM communication Graphical user interface (GUI) software
The ADP1051-240-EVALZ evaluation board, together with a ADP1051DC1-EVALZ daughter card, allows the user to evaluate the ADP1051 in a power supply unit (PSU) environment. The boards are fully compatible with the ADP1051 GUI software. With the ADP-I2C-USB-Z USB-to-I2C connector and the GUI software, the ADP1051 on the evaluation board can be interfaced with a PC via a USB port.
EVALUATION KIT CONTENTS ADP1051-240-EVALZ evaluation board ADP1051DC1-EVALZ daughter card CD with ADP1051 GUI installer, ADP1051 data sheet, UG-566 user guide, project sample files, schematics and BOMs for the ADP1051-240-EVALZ, ADP1051DC1-EVALZ, and current share daughter card
ADDITIONAL EQUIPMENT/SOFTWARE NEEDED
The evaluation board allows the ADP1051 to be exercised without the need of external components. The board is set up to act as an isolated PSU, outputting a rated load of 12 V, 20 A from a 36 V dc to 75 V dc source. Two parallel connectors on the evaluation board provide synchronization, share bus, and PMBus interfaces. They allow the direct paralleling evaluation when multiple evaluation boards are connected in parallel to a common bus. One analog current share daughter card connector allows analog current share extension. Multiple test points allow easy access to all critical points/pins. Three LEDs give the user a direct visual indication of variations in the board status, such as the system input voltage, PGOOD output, and FLAGIN input. Full performance details are provided in the ADP1051 data sheet, and the ADP1051 data sheet should be consulted in conjunction with this user guide.
ADP-I2C-USB-Z USB-to-I2C connector ADP-I2C-USB-Z drivers CD
EVALUATION BOARD SETUP ADP1051-240-E VALZ VIN+
VOUT+
VOUT–
VIN– ADP1051DC1-E VALZ
11529-001
PC
ADP-I2C-USB-Z
Figure 1. ADP1051 Evaluation Board Setup PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS.
Rev. 0 | Page 1 of 40
UG-566
Evaluation Board User Guide
TABLE OF CONTENTS Features .............................................................................................. 1
Digital Compensator and Load Transient Response ............. 14
Evaluation Kit Contents ................................................................... 1
Input Voltage Settings ................................................................ 16
Additional Equipment/Software Needed ...................................... 1
Output Voltage Settings ............................................................. 17
General Description ......................................................................... 1
Input Current Settings ............................................................... 19
Evaluation Board Setup ................................................................... 1
Output Current Setting.............................................................. 19
Revision History ............................................................................... 2
Temperature Settings ................................................................. 22
Evaluation Board Hardware ............................................................ 3
Flags and Fault Response Configurations ............................... 22
Overview........................................................................................ 3
Trimming..................................................................................... 22
Evaluation Board Characteristics ............................................... 5
Synchronization .......................................................................... 23
Connectors .................................................................................... 5
Power Good Signal ..................................................................... 23
Hardware Connection ................................................................. 6
Phase Shifted Full Bridge Operation ....................................... 24
Evaluation Board GUI Software ..................................................... 8
Direct Paralleling ........................................................................ 24
Overview........................................................................................ 8
Additional Graphs .......................................................................... 26
Downloading the GUI ................................................................. 8
Schematics and Artwork ............................................................... 27
Installing the GUI ......................................................................... 8
ADP1051-240-EVALZ ............................................................... 27
Launching the GUI ...................................................................... 8
ADP1051DC1-EVALZ .............................................................. 33
Getting Started ............................................................................ 11
Current Share Daughter Card .................................................. 35
Project Sample Files ................................................................... 11
Ordering Information .................................................................... 37
Evaluating the Board ...................................................................... 12
Bill of Materials ........................................................................... 37
On/Off Control and Soft Start .................................................. 12 PWM Settings ............................................................................. 14
REVISION HISTORY 7/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 40
Evaluation Board User Guide
UG-566
EVALUATION BOARD HARDWARE OVERVIEW The ADP1051-240-EVALZ evaluation board and the ADP1051DC1-EVALZ daughter card feature the ADP1051 in a dc-to-dc switching power supply in full bridge topology with synchronous rectification. Figure 2 shows a hardware photo of the evaluation board. Figure 3 shows a block diagram of the main components on the board. The circuit is designed to provide a rated load of 12 V, 20 A from a dc input voltage source of 36 V dc to 75 V dc. The ADP1051 provides functions such as output voltage regulation, synchronization, constant current control, prebias start up, direct paralleling, and comprehensive protection. The main transformer on the evaluation board breaks the dc-to-dc power supply into primary side and secondary side; therefore, creating isolation. On the primary side, the full bridge stage switches and inverts the dc voltage derived from the input terminals (J1 and J5) into ac voltage. The control signals for the full bridge stage come from the ADP1051 through the digital isolators (ADuM3210) and the half bridge drivers. There is also a current transformer (CT) sensing and transmitting the primary side current information to the ADP1051 on the secondary side. On the secondary side, the full wave synchronous rectifiers (SR) rectify the ac voltage to dc voltage. An LC filter smooths the pulsated dc voltage. The current information is sensed through a current sense resistor and fed to the CS2+ and CS2− pins in the ADP1051. Output terminals, J2 and J6, are used for the load connection.
An auxiliary power supply on the evaluation board is used to generate a 10V_PRI bias power for full bridge drivers, a 5V_PRI bias power for the primary side power supply of the ADuM3210, and a 10V_SEC bias power for the ADP3654 driver. A 10V_VCC bias power is generated from an OR-diode network using a 10V_SEC bias power and 5 V voltage source from the USB-to-I2C connector. This allows the GUI access to the ADP1051 when the auxiliary power circuit is not powered up. The ADP3303 LDO converts 10V_VCC to a 3V3_SEC bias power for the ADP1051 and the secondary side power of the ADuM3210. Alternatively, the auxiliary power input can also come from an independent dc source through TP47 and TP50. An analog current share connector (J15) allows an external current share daughter card to be used for analog current sharing control. Two parallel connectors (J17 and J18) allow the synchronization, current share, and PMBus communication between multiple evaluation boards. There are wholly three blue color LEDs in the evaluation board to provide the status of the evaluation board. D7 indicates the input voltage signal. D17 indicates the PGOOD output (PG/ALT pin output signal). D18 indicates the FLAGIN signal. There are three complete switches on the evaluation board. The SW1 switch is used to control the voltage level of the hardware CTRL pin. The SW2 and SW3 switches are used to change the part operating state between as master device and as slave device when the synchronization is enabled.
The ADP1051DC1-EVALZ daughter card shown in Figure 4 can be plugged into the daughter card connector (J8). It provides the signals that are used to regulate the output voltage, limit the output current, and control the on/off switch of the evaluation board. A 4-pin connector (J2) on the daughter card is used for I2C/PMBus communication through a USB-to-I2C connector, ADP-I2C-USB-Z. This allows the GUI software to communicate with the evaluation board through the USB port of the PC. If the J17 or J18 parallel connector is connected, the GUI can visit all the evaluation boards through a single USB-toI2C connector. With this interface, users can monitor and program the ADP1051.
Rev. 0 | Page 3 of 40
Evaluation Board User Guide
11529-002
UG-566
Figure 2. ADP1051-240-EVALZ Evaluation Board FULL BRIDGE FETs OUTPUT FILTER
SR FETs
MAIN TRANSFORMER
VOUT (12V @ 20A)
VIN = 36V TO 75V
CT ADP3654 HIP 2101
HIP 2101 ADuM3210 CS1
ON/OFF AND UVP CONTROL
SR1/SR2
ADuM3210
OUTA/OUTB/ OUTC/OUTD
ADuM3210
CTRL
CS2–
CS2+ OVP VS+ VS–
ADP1051
AGND AUX TRANSFORMER
VDD
RTD
ADD
RES
SCL
SDA
10V_PRI
10V_SEC
I2C CONNECTOR
ADP3303
11529-004
Figure 3. Block Diagram of ADP1051-240-EVALZ Evaluation Board
Figure 4. ADP1051DC1-EVALZ Daughter Card
Rev. 0 | Page 4 of 40
11529-003
NCP1031
Evaluation Board User Guide
UG-566
EVALUATION BOARD CHARACTERISTICS Table 1. Evaluation Board Characteristics Parameter INPUT VOLTAGE OUTPUT VOLTAGE SETPOINT VOUT OV Fault Limit (Default) Output Voltage Ripple OUTPUT CURRENT IOUT OC Fault Limit (Default) OPERATION TEMPERATURE
Symbol VIN VOUT
Min 36
Typ 48 12 14 200
IOUT
0
OT Fault Limit (Default) EFFICIENCY SWITCHING FREQUENCY DIMENSION Width Length Component Height
TOT_FAULT η fSW
25 25 25 110 94.5 120
W L H
210 110 40
Max 75
20
TA
50 85
Unit V dc V dc V dc mV A
Test Conditions/Comment
°C °C °C % kHz
Natural convection Airflow = 200 LFM or above
VIN = 48 V, VOUT = 12 V, IOUT = 20 A
VIN = 48 V, VOUT = 12 V, IOUT = 20 A
mm mm mm
CONNECTORS
Daughter Card Connector J8
The connections to the ADP1051-240-EVALZ evaluation board are shown in Table 2. Table 3 to Table 6 show the details about these connectors.
The connections to J8 are shown in Table 3.
Table 2. Evaluation Board Connections Connector J1 J5 J2 J6 J8 J15 J17 J18
Function VIN+, dc input VIN−, ground return for dc input VOUT+, dc output VOUT−, ground return for dc output ADP1051 daughter card connector Analog current share daughter card connector Parallel Connector 1 Parallel Connector 2
Table 3. J8 Connections Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Rev. 0 | Page 5 of 40
Function 10V_VCC VS− VS+ CS2− CS2+ VF CS1 SR1 SR2 OUTA OUTB OUTC OUTD SCL SDA CTRL PG/ALT SYNI/FLGI 3V3_SEC AGND RTD OVP
UG-566
Evaluation Board User Guide
Analog Current Share Connector J15
Daughter Card I2C/PMBus Connector
The connections to J15 are shown in Table 4.
The connections to J2 in the ADP1051 daughter card are shown in Table 6.
Table 4. J15 Connections Pin 1 2 3 4 5 6 7 8
Function CS2+ CS2− 10V_SEC 3V3_SEC IBUS VF_ISHARE AGND AGND
Table 6. J2 Connections Pin 1 2 3 4
HARDWARE CONNECTION Caution
Parallel Connector J17 and J18 The connections to J17 and J18 are shown in Table 5. Pin 1 2 3 4 5 6 7 8
Function SCL SDA SYNC CTRL AGND 10V_VCC IBUS AGND
This evaluation board is supplied with high voltages and currents. Take extreme caution, especially on the primary side, to ensure safety for the user. It is strongly advised to switch off the evaluation board when not in use. A current-limit dc source is recommended to use as the input.
Required Equipment • • • • • • •
DC power supply capable of 36 V dc to 75 V dc, 10 A output Electronic load capable of 12 V, 25 A input Oscilloscope capable of 500 MHz bandwidth or higher PC with Microsoft Windows XP (32-bit), Vista (32-bit), Windows 7 (32-bit), or Windows 8 (32-bit) Precision digital multimeters (6-digit HP34401 or equivalent) Portable digital multimeters (fluke) for measuring up to 25 A dc current ADP-I2C-USB-Z USB-to-I2C connector (see Figure 5) available from Analog Devices, Inc.
11529-005
Table 5. J17 and J18 Connections
Function 5V SCL SDA AGND
Figure 5. ADP-I2C-USB-Z USB-to-I2C Interface Connector
Rev. 0 | Page 6 of 40
Evaluation Board User Guide
UG-566
Evaluation Board Configurations
Table 7. Jumpers Configuration
There are a series of jumpers used for ADP1051-240-EVALZ hardware settings. All the jumper configurations have been completed during the evaluation board assembly. Table 7 shows the details of jumper configurations.
Jumper JP1 JP2 JP3
J3 and J4 are short pins for configuring the low-side output current sense method and high-side output current sense method. The low-side current sense method is used by default. T1 and T4 are current transformers for primary side current sense. Typically, T4 is used while T1 is not connected by default.
JP4
JP5
Users do not need to complete any hardware configuration unless special test items will be conducted.
JP11 JP12 JP13 JP14
Function Short this jumper to short the R46. This jumper can be used as signal injection point during the control loop test. It is open by default. Short this jumper to short R53. It is open by default. When SW1 is used to control the PSU, short this jumper. It is shorted by default. When multiple evaluation boards are connected in parallel, proper configuration of this jumper allows a single switch to control all evaluation boards. It is shorted by default. Short this jumper to configure the on/off pin at an off state. It is open by default. Short this jumper to select OUTD as a SYNO signal to J17 connector. It is open by default. Short this jumper to select OUTC as a SYNO signal to J17 connector. It is open by default. Short this jumper to select OUTD as a SYNO signal to J18 connector. It is open by default. Short this jumper to select OUTC as a SYNO signal to J18 connector. It is open by default.
Connecting the Hardware Do not connect the ADP-I2C-USB-Z connector to the evaluation board until after the GUI software has been installed. Figure 6 shows the test configuration of the evaluation board. The digital multimeters are optional. An independent dc source can be applied on TP47 and TP50 to generate all bias power supplies even if the dc input is lower than 30 V. The board evaluation can start when the dc input voltage is increased from 0 V.
20.00A
5.40A
I
ADP1051-240-EVALZ
COM
J18
COM
J2
J1
+
I
SW3
+
DC POWER SUPPLY
ELECTRONIC LOAD
–
ADP1051DC1-EVALZ J15 J2
J5
I
V
–
J8
TP47 COM
J6
JP4 SW1
TP50
J17
SW2
COM
I
V
12.00V
48.00V
MULTIMETER
MULTIMETER ADP-I2C-USB-Z
11529-006
PC
Figure 6. Test Configuration for the Evaluation Board
Rev. 0 | Page 7 of 40
UG-566
Evaluation Board User Guide
EVALUATION BOARD GUI SOFTWARE OVERVIEW The ADP1051 GUI is a free software tool for programming and configuring the ADP1051. For more information on the GUI, refer to the ADP1051 GUI user guide.
DOWNLOADING THE GUI The ADP1051 GUI setup file is included on the CD in the ADP1051 evaluation kit. Users can also visit http://www.analog.com/ADP1051 to obtain the latest version of GUI software.
INSTALLING THE GUI Warning 11529-007
Do not connect the USB cable to the evaluation board until the software has been installed.
Installation Steps To install the ADP1051 GUI software, use the following steps:
3. 4. 5. 6.
7. 8.
9.
Insert the CD. Double click ADP1051 Setup.msi installation file to start the installation. Click through the following windows (such as Figure 7). In the Total Phase USB Setup window, click Next. Check I accept the terms in the License Agreement after reading it and click Next. Check the Install USB drivers option when the driver is not installed. If the driver has been installed, uncheck the Install USB drivers option. Then click Install. After the installation, click Close to complete the driver installation. When the Adobe Flash Player Installer window appears, check I have read and agree to the terms of the Flash Player License Agreement after reading it. Click INSTALL. If a newer version of Adobe Flash Player is already installed in the system, click Quit and continue. Click Close to exit setup.
LAUNCHING THE GUI To launch the GUI, use the following steps: 1. 2. 3. 4.
5. 6.
7. 8.
Plug the ADP1051 daughter card into the J8 connector. Ensure that the CTRL switch (SW1) is turned to the off position. The off position is the left side by default. Plug the ADP-I2C-USB-Z connector into the USB port in the PC. If the Found New Hardware - Total Phase Aardvark I2C/SPI Host Adapter window appears, the PC automatically installs the hardware driver. Wait until the installation is finished. If this window does not appear, skip this step. Connect the ADP-I2C-USB-Z connector to J2 on the ADP1051 daughter card. Launch the ADP1051.exe file. The GUI software should report that the ADP1051 has been located on the board as shown in Figure 8. Click Finish to proceed to the Monitor window (see Figure 10). Click Unlock Chip Password (Button I in Figure 10) and enter the chip password in the following pop-up window. The default chip password is 0xFFFF. Click Enter after keying in the password to process the Setup tab as shown in Figure 11.
11529-008
1. 2.
Figure 7. GUI Installation
Figure 8. Getting Started.
Rev. 0 | Page 8 of 40
Evaluation Board User Guide
UG-566
11529-009
If the user wants to load the default command and board settings file from a local folder, click Load Command and Board settings from a ‘.51s’ file to ADP1051 (Button A in Figure 11) and select the ADP1051-240W-EVALZ-Default.51s file when specifying the folder as shown in Figure 9. Because the ADP1051 in the evaluation kit is preprogrammed with the board and command settings, this step is optional.
Figure 9. Load Board and Command Settings File
Rev. 0 | Page 9 of 40
UG-566
Evaluation Board User Guide
Table 8. shows a list of key buttons in the GUI. For more information about the ADP1051 GUI, refer to the ADP1051 GUI user guide. Table 8. Key Buttons in the GUI Button Letter A
Button
Description Load command and board settings from a ‘.51s’ file to the ADP1051 device.
B
Save command and board settings from the ADP1051 device to a ‘.51s’ file.
C
Generate a hex file of the command and board settings.
D
Access to the EEPROM.
E
Scan for the ADP1051 device.
F
Open a spy window to monitor I2C communication between the GUI and the ADP1051 device.
G
Program command and board settings into the EEPROM.
H
Unlock/lock the trim password.
I
Unlock/lock the chip password.
D E F
G H
I
11529-010
A B C
Figure 10. Monitor Window in the GUI
Rev. 0 | Page 10 of 40
Evaluation Board User Guide
UG-566
GETTING STARTED
Moreover, the user can use the Save Command and Board settings from ADP1051 to a ‘.51s’ file button (Button B in Figure 11) to generate a .51s file for the command and board settings.
Connect a dc source (voltage range of 36 V dc to 75 V dc) at the J1 and J5 input terminals and connect an electronic load at the J2 and J6 output terminals. See Figure 6 for the correct configuration.
Software Main Window
Connect the multimeters on the input terminals and output terminals separately as shown in Figure 6. Connect the voltage probes at different test pins. Ensure that the differential probes are used and that the grounds of the probe are isolated if the measurements are made on the primary and secondary side of the transformer simultaneously. Turn the CTRL switch (SW1) to the on position. The evaluation board is now up and running, and ready for evaluation. The output should read 12 V dc. After a successful startup, the PSU is in a steady state. The board’s LEDs provide the status of the board. D17 is turned on indicating that there are no faults detected. In case of a fault, the PGOOD LED will be turned off indicating that a flag has tripped. The Monitor tab in the GUI displays the appropriate state of the PSU. After completing the programming of ADP1051, click Program command and board settings into EEPROM (Button G in Figure 11) to program the command and board settings into the EEPROM once the user wants to save the settings in the device.
Figure 11 shows the main window. There are four tabs total in the main window: • Setup tab: All the setting windows are in this tab. It includes the board settings and command setting windows. • Monitor tab: The readings and flags are monitored in this tab. • Commands Access tab: This tab provides the command maps for direct access. • Password Settings tab: The PMBus command WRITE_ PROTECT and chip password can be configured in this tab.
PROJECT SAMPLE FILES There are a series of project sample files on the CD. Using the GUI software, the user can load the different project sample file from the CD to do different types of evaluation. The evaluation board hardware should be configured to half bridge topology if the half bridge sample settings are to be evaluated. The default settings file is also stored as ADI_Default.51s in the GUI. After the GUI is stalled, the user can load the ADI_Default.51s file in the default folder to learn the default settings of the evaluation board.
Table 9. Project Sample Files File Name ADP1051-240-EVALZ-Default.51s ADP1051-240-EVALZ-HSFB-SAMPLE.51s ADP1051-240-EVALZ-FSFB-SAMPLE.51s ADP1051-240-EVALZ-HB-SAMPLE.51s ADP1051-240-EVALZ-OLFB-SAMPLE.51s ADP1051-240-EVALZ-OLFF-SAMPLE.51s
Description ZVS full bridge converter sample file. This is the default settings file. Hard-switched full bridge converter sample file. Phase-shifted full bridge converter sample file. Half bridge sample file. Open-loop full bridge converter sample file. Open-loop input voltage feed forward converter sample file.
A B C
D G H
I
11529-011
E F
Figure 11. Main Setup Window of the ADP1051 GUI (See Also Table 8) Rev. 0 | Page 11 of 40
UG-566
Evaluation Board User Guide
EVALUATING THE BOARD This ADP1051 evaluation kit allows the user to get an insight into the flexibility offered by the extensive ADP1051 programming options. The following sections provide an overview of evaluation items to evaluate the key features of the ADP1051. Unless otherwise specified, use the project sample file ADP1051-240-EVALZ-Default.51s (it is preprogrammed in the ADP1051 of the daughter card) to do all the evaluation.
ON/OFF CONTROL AND SOFT START
11529-014
This section specifies the power-on control behavior, poweroff control behavior, and the soft start timing of the PSU. By default, the AND logic of the hardware CTRL pin logic and software OPERATION command are used to turn on the ADP1051, as shown in the CTRL Settings window of the Setup tab (Figure 12). It is recommended that Switch SW1 be used to control the operation state of the PSU.
Figure 14. Additional Soft Start Settings Window
11529-015
The turn-on delay time, turn-on rise time, and the turn-off delay time can be programmed in Soft Start and Stop window of the Setup tab (see Figure 13). Additional soft start settings are programmed in Figure 14. Figure 15 and Figure 16 show the results of soft start at 0 A load and 20 A load separately. The soft start rise time is programmed to 40 ms. Figure 17 gives an example of soft start with disabled synchronous rectifiers during soft start ramp.
Figure 12. CTRL Settings Window
11529-016
11529-012
Figure 15. Soft Start at 48 V DC Input, 0 A Load
11529-017
11529-013
Figure 16. Soft Start at 48 V DC Input, 20 A Load
Figure 17. Soft Start with Disabled SRs
Figure 13. Soft Start and Stop Settings Window Rev. 0 | Page 12 of 40
Evaluation Board User Guide
UG-566
Prebias Start Up The prebias start-up function provides the capability to start up with a prebiased voltage on the output. To set up the prebias startup, use the following steps:
•
•
If the closed-loop input voltage feed forward operation is enabled and the input voltage information is available for the ADP1051 before the PSU starts up, select the Feed Forward always Activated option (Option A). If the closed-loop input voltage feedforward operation is disabled and the input voltage information is available for the ADP1051 before the PSU starts up, select the Feed Forward only during Startup option (Option B). If the closed-loop feed forward operation is disabled and the input voltage information is not aviable for ADP1051 before the PSU starts up, select the Feed Forward always Disabled option (Option C).
11529-019
•
Figure 19. Prebias Start Up at 36 V DC Input and Low Residual Voltage
A
11529-020
2.
Enable the prebias start up and program the appropriate nominal modulation value for prebias startup through the additional soft start settings window shown in Figure 14. Select the type of prebias start up as shown in Figure 18:
B
Figure 20. Prebias Start Up at 60 V DC Input and High Residual Voltage
C
Because the input voltage cannot be sensed through the windings of auxiliary power supply in this evaluation board, it is recommended that the Feed Forward always Disabled option (Option C) be selected for evaluation. 11529-018
1.
Figure 19 and Figure 20 show the prebias start up waveforms when the Feed Forward always Activated option (Option A) is selected.
Figure 18. Feed Forward Selection Option
Other evaluation options are: • • • •
Rev. 0 | Page 13 of 40
Program different turn-on rise time in combination with different turn-on delay time. Blank different flags during soft start ramp as shown in Figure 14. Choose different soft start gains to derive a best soft start ramp. Enable the SR soft start and select a different SR soft start speed to prevent a glitch at the output voltage ramp.
UG-566
Evaluation Board User Guide
PWM SETTINGS
Although the switching frequency can be adjusted, the GUI software does not account for the dead times and the PWM timings have to be programmed manually to guarantee the normal operation of the PWM outputs.
11529-022
The PWM timings for the primary side switches and secondary side synchronous rectifiers are programmed in the PWM SR Settings window of the Setup tab as shown in Figure 21. This window allows the programming of the switching frequency, rising edge and falling edge timings, the type of modulating edge (rising edge or falling edge), modulation type (positive or negative), and modulation limit. Figure 21 shows the gate drive signals at the output pins of the ADP1051. The QA, QB, QC, QD, Q7/Q8, and Q3/Q4 switches in the evaluation board ADP1051-240-EVALZ are driven separately by PWM outputs OUTA, OUTB, OUTC, OUTD, SR1, and SR2. Figure 22. Adaptive Dead Time Compensation Settings Window
DIGITAL COMPENSATOR AND LOAD TRANSIENT RESPONSE
11529-021
The digital compensator can be configured by the Filter Settings window of the Setup tab as shown in Figure 23. The digital compensator can be changed by manipulating the position of the poles and zeros in the s-domain. The ADP1051 allows two different sets of compensator responses to be programmed. One is normal mode compensator and the other is light load mode compensator. The digital compensator is a Type III compensator. The first pole is placed at a dc position to eliminate the steady state error. The second pole can be freely placed (ideally at the ESR zero position). However, the third pole is fixed at half of the switching frequency.
Figure 21. PWM SR Settings Window
Enable and disable the pulse skipping mode and measure the standby power of the PSU. Double the switching frequency from 120 kHz to 240 kHz. The board is designed to operate at a switching frequency of up to 240 kHz with airflow cooling. Program an imbalance in the on time of the QA and QC switches, and evaluate the volt-second balance control function. Run the software in simulation mode and program the PWM settings for different topologies such as zero-voltageswitched full bridge, hard-switched full bridge, phase shifted full bridge, half bridge, push-pull, two-switch forward, or active clamp forward converters. The project sample files listed in Project Sample Files section can also be loaded. Align all SR edges to OUTA, OUTB, OUTC, OUTD edges and adjust the primary-secondary propagation delay by programming the SR1 and SR2 delay. Program the adaptive dead time compensation function as shown in Figure 22 to improve the efficiency at light load condition.
11529-023
Additional PWM and SR evaluation options are:
Figure 23. Filter Settings Window
Warning While varying the compensator's parameters is possible when the part is running, the wrong combination of parameters can cause the system to become unstable.
Rev. 0 | Page 14 of 40
Evaluation Board User Guide
UG-566
Control Loop Configuration
Transient Response for the Load Step
To configure the control loop, use the following steps:
A dynamic electronic load can be connected to the output of the evaluation board to evaluate the load transient response. Set up an oscilloscope to capture the transient waveforms of the PSU output. Figure 25 and Figure 26 show an example of the load transient response.
5.
40
200
32
160
MAGNITUDE (B ÷ A) (dB)
24
Figure 25. Transient Response with Load Steps: 25% to 50% to 25%
120 PHASE
16
80 40
8 MAGNITUDE
0
0 –8
–40
–16
–80
–24
–120
–32
–160
–40 100
11529-025
4.
1k
10k FREQUENCY (Hz)
–200 100k
Figure 24. Control Loop Test by AP300 Loop Analyzer
Rev. 0 | Page 15 of 40
11529-026
3.
The user can vary the digital compensator via the GUI software to change the transient response. This evaluation kit allows the digital compensator to be easily programmed to optimize the load transient response of the PSU.
PHASE (B – A) (Degrees)
2.
Make sure the board parameters are set correctly, including the topology, the turn ratio of the main transformer, the output LC filter parameters, and the output voltage sense network parameters. Using the information, the GUI software generates the Bode plots of the power stage and output voltage sense network separately. The switching frequency is determined in the PWM SR Settings window. Changing of the switching frequency changes the low frequency gain and the third pole position. The user can start to place the zeros and poles, and set the low frequency gain and high frequency gain of the digital compensator, based on the stability rules. The GUI then displays the full loop gain crossover frequency, the phase margin, the gain margin, and the phase crossover frequency. Using the loop analyzer, the user can verify the programmed control loop as shown in Figure 24. During the test on the control loop, the test signal from the loop analyzer can be easily injected in JP1 of the evaluation board.
11529-024
1.
Figure 26. Transient Response with Load Steps: 50% to 75% to 50%
UG-566
Evaluation Board User Guide
INPUT VOLTAGE SETTINGS If the input voltage can be sensed by ADP1051 before the PSU is turned on (for example, the input voltage is sensed through the transformer windings of the auxiliary power circuit), the VIN on and VIN off limits can be programmed to control the input UVLO protection. Using the VIN Settings window in the Setup tab as shown in Figure 27, the user can program the VIN On limit and VIN Off limit. 11529-028
By proper selection of the input voltage feed forward options as shown in Figure 18, the input voltage feed forward can be evaluated in different ways. Figure 28 gives a result of the input voltage transient with the feed forward being disabled (Option C—Feed Forward always Disabled in Figure 18). While Figure 29 gives a result of the input voltage transient with the input voltage feed forward being enabled (Option A— Feed Forward always Activated in Figure 18).
Figure 28. Input Voltage Transient Response with Feed Forward Disabled
Additional input voltage related evaluation options are:
11529-029
•
Apply a different input voltage compensation multiplier (Register 0xFE59) to get an accurate input voltage sense at both no load and heavy load conditions. Select the input voltage signal to trigger the VIN_LOW flag or the VIN_UV_FAULT flag in the feed forward selection window shown in Figure 18. Figure 29. Input Voltage Transient Response with Feed Forward Enabled
11529-027
•
Figure 27. VIN Settings Window
Rev. 0 | Page 16 of 40
Evaluation Board User Guide
UG-566
OUTPUT VOLTAGE SETTINGS
11529-032
The VOUT Settings windows (shown in Figure 30 and Figure 31) set all the output voltage related parameters, such as the output voltage settings, the droop resistor (through the VOUT_DROOP command), the output voltage transition rate (through the VOUT_TRANSITION_RATE), and conditional overvoltage protection setting. Figure 32 and Figure 33 provide results of output voltage adjustment when the VOUT transition rate is programmed as 3.125 µV/µs.
11529-030
Figure 32. VOUT Adjusted from 10 V to 12.5 V with 3.125 µV/µs Transition Rate
11529-033
Figure 30. VOUT Settings Window 1
11529-031
Figure 33. VOUT Adjusted from 12.5 V to 10 V with 3.125 µV/µs Transition Rate
Figure 31. VOUT Settings Window 2
Rev. 0 | Page 17 of 40
UG-566
Evaluation Board User Guide
Droop Current Sharing This test can be conducted by plotting the V-I curve when the load current is gradually increased from 0 A to 20 A. It can also be conducted by applying a dynamic load to test the transient performance. Moreover, the drooping current share test can be conducted using two or more evaluation boards connected in parallel. The settings of drooping current sharing are shown in Figure 31. The droop resister is programmed as 20 mΩ and the IOUT update rate is programmed as 82 µs. Figure 34 gives drooping current sharing accuracy using two ADP1051-240-EVALZ evaluation boards connected in parallel. 11529-035
20
PSU OUTPUT CURRENT (A)
16
Figure 35. Overvoltage Protection Waveform 12 BOARD A 8 BOARD B 4
11529-034
0
–4 0
6
12 18 24 LOAD CURRENT (A)
30
36
11529-036
Figure 34. Droop Current Sharing Accuracy
Output Overvoltage Protection This test can be conducted in a number of ways. The simplest way is to set the output voltage to a value higher than the VOUT OV fault limit shown in Figure 30. Alternatively, shorting of the VS+ pin to AGND in the ADP1051 daughter card can cause a fast output overvoltage condition. The responses of the fault conditions can be programmed in the Flags and Fault Response Configurations section (see Figure 48). Figure 35 shows the waveforms when the response to an output overvoltage condition occurred. The ADP1051 also supports the conditional overvoltage protection. The settings of conditional output overvoltage protection are shown in Figure 31. Figure 36 shows a result of conditional overvoltage protection when the outputs of two evaluation boards are connected to a common bus.
Figure 36. Conditional Overvoltage Protection with Two Evaluation Boards Connected to a Common Bus
Output Undervoltage Protection This test can be done in a number of ways. The simplest way is to set the output voltage to a value lower than the VOUT UV fault limit value shown in Figure 30. Even a shorted load or an internal short (such as shorting of the synchronous rectifiers) can cause an output undervoltage condition. The response of the fault condition can be programmed in the Flags and Fault Response Configurations section.
Rev. 0 | Page 18 of 40
Evaluation Board User Guide
UG-566 OUTPUT CURRENT SETTING
The input current settings are accessed using the CS1 and CS3 Settings window as shown in Figure 37. This window is used to program the cycle-by-cycle current limiting, the input overcurrent fast fault protection, the CS3 overcurrent protection and the volt-second balance control.
The output current settings window is accessed using the IOUT Settings window. This window features the output overcurrent fault limit, the thresholds for the light load threshold and the deep light load, the responses for the light load threshold and the deep light load, the constant current mode, and the SR reverse current control.
11529-038
11529-037
INPUT CURRENT SETTINGS
Figure 37. CS1 and CS3 Settings Window Figure 38. IOUT Settings Window 1
CS1 Cycle-by-Cycle Current Limiting The leading edge blanking time, the leading edge blanking reference, debounce time, the PWM disabling selection, and the matched cycle-by-cycle current limiting can be programmed in CS1 Settings window shown in Figure 37.
Input Overcurrent Fast Fault Protection
11529-039
This test can be conducted by shorting the load. Using the setting window shown in Figure 37, the user can specify the IIN OC fast fault limit value by 2, 8, 16, 64, 128, 256, 512, or 1024. The fault response can be configured in the Flags and Fault Response Configurations section.
Figure 39. IOUT Settings Window 2
Rev. 0 | Page 19 of 40
UG-566
Evaluation Board User Guide
Output Overcurrent Protection
Figure 42 and Figure 43 show results that the constant current mode happens during a soft start when two evaluation boards are connected in parallel. The load is a CR load.
This test can be conducted by applying a load current larger than the value programmed by the IOUT OC fault limit (shown in Figure 38). The fault response is programmed in the Fault Response window shown in Figure 48.
11529-041
Figure 40 gives an experimental result by setting the IOUT OC fault limit at 25 A and enabling soft start after every 250 ms.
11529-040
Figure 41. Constant Current Control During Startup; Constant Current Threshold is 10 A
Figure 40. IOUT OC Response Experimental Result
Constant Current Mode 11529-042
Prior to the constant current mode test, the user needs to configure the constant current mode settings in Figure 39, including the output voltage change rates and the output current averaging speeds. This test can be conducted in multiple ways: • • • • •
•
The constant current mode happens during a soft start at a CR load. The test is done on a standalone evaluation board. The constant current mode happens during a soft start at a CV load. The test is done on a standalone evaluation board. The constant current mode happens during a CR load transient. The test is done on a standalone evaluation board. The constant current mode happens during a CV load transient. The test is done on a standalone evaluation board. The constant current mode happens during a soft start when two or more evaluation board are connected in parallel. The load is a CR load. The constant current mode happens during a soft start when two or more evaluation boards are connected in parallel. The load is a CC load.
11529-043
Figure 42. Constant Current Control with Two Evaluation Boards in Parallel; Turn-On Timing is the Same
Figure 43. Constant Current Control with Two Evaluation Boards in Parallel; Turn-On Timing Difference is 50 ms
Figure 41 shows a result that the constant current mode happens during a soft start at a CR load. The test is done on a standalone evaluation board.
Rev. 0 | Page 20 of 40
Evaluation Board User Guide
UG-566
SR Reverse Current Protection
Light Load Efficiency Optimization
This test can be conducted by several ways:
The ADP1051 can be programmed to optimize performance when the output current drops below a certain level. The light load mode threshold and deep light load mode threshold are programmed in a manner to reduce the losses and increase the efficiency. A hysteresis for the light load mode and the deep light load mode is provided on the thresholds to avoid the current oscillations. The thresholds for light load mode and deep light load mode can also be programmed in the IOUT window as shown in Figure 39.
•
• •
At a no load condition, the VOUT voltage is adjusted from a higher voltage to a lower voltage with the fastest VOUT transition rate. Up to 10,000 µF capacitance is connected at output terminals. Switch the load current between full load and no load with the fastest current slew rate programmed by E-load. At a no load condition, use an air switch to short the input terminals. A capacitor with up to 10,000 µF capacitance can be connected at the output terminals. This is a typical input voltage dip test.
Figure 44 shows a result where the output voltage is adjusted from a higher voltage to a lower voltage. Figure 45 shows a result that the input is shorted by an air switch.
When operating in the light load mode or deep light load mode, the mode flag is set in the Monitor tab. In combination with the pulse skipping mode, the standby power consumption can be reduced. The user can try the test items as follows: • •
•
11529-044
•
Try different thresholds for light load mode and deep light load mode to test the efficiency improvement. Try different averaging speed for light load mode and deep light load mode to test the transient response by applying a dynamic load. Program the threshold for the pulse skipping mode to test the efficiency improvement during standby mode. Select the PWM channels to be disabled during the deep light load mode as shown in Figure 46.
11529-046
Figure 44. SR Reverse Current Protection During Output Voltage Adjustment
11529-045
Figure 46. Deep Light Load Response Check Box
Figure 45. SR Reverse Current Protection During Input Dip Test; 10,000 µF Capacitance is Connected at Output Terminal
Rev. 0 | Page 21 of 40
UG-566
Evaluation Board User Guide
TEMPERATURE SETTINGS
11529-048
This test can be conducted by enclosing the evaluation board in a thermal chamber at the desired ambient temperature to simulate the operating condition. The user can program the OT fault limit and OT warning limit through the Temperature Settings window shown in Figure 47. The OT hysteresis is the value difference of OT fault limit and OT warning limit.
Figure 48. Fault Response Window
TRIMMING
11529-047
This test allows the entire power supply to be calibrated and trimmed digitally through the ADP1051 in the production environment.
Figure 47. Temperature Settings Window
FLAGS AND FAULT RESPONSE CONFIGURATIONS The fault responses can be programmed in the Fault Response window of the Setup tab as shown in Figure 48. The state of faults can be monitored in the Monitor tab as shown in Figure 11. There are two groups of fault responses: • •
All the ADP1051 parts are factory calibrated. The trimming is not needed if the voltage and current sense resistors have a high enough accuracy (see the ADP1051 data sheet for details). However, the ADP1051 can be retrimmed by the user to compensate for the errors introduced by external components. All the trimming can be done in the Trim Settings window of the Setup tab as shown in Figure 49.
PMBus faults responses, including IOUT OC, VOUT OV, VOUT UV, and OT. Manufacturer specific fault responses, including IIN OC FAST, CS3 OC, VIN UV, Flagin, SR RC, VDD OV. There is a global reenabling timing for all manufacturer specific fault responses.
When there is a fault causing the power supply to be shut down and a soft start is required if the PWM outputs are reenabled, the first fault ID information is shown in the Monitor tab. The first flag ID register gives the user more information for fault diagnosis than a simple flag.
Rev. 0 | Page 22 of 40
11529-049
The user can test this section by applying a fault condition. By changing the settings of the debounce timing, delay timings, responses and reenable timings, the user can see different protection performance. Figure 49. Trimming Window
Evaluation Board User Guide
UG-566
SYNCHRONIZATION
POWER GOOD SIGNAL
Synchronization as a Master Device
This test can be conducted by applying a fault condition, which is used to trigger a PGOOD flag and pull down the PG/ALT pin. The user can follow the PGOOD Settings window shown in Figure 51 to program which fault signal asserts the PGOOD flag. In the case of a fault to trigger the PGOOD flag, the D17 LED is turned off indicating that the power supply is not good. Figure 52 shows that a VOUT_UV_FAULT flag triggers the PGOOD output (PG/ALT pin).
This test can be done by specifying OUTC or OUTD as a SYNO signal using the Sync Settings window of the Setup tab as shown in Figure 50. The SYNO signal should be stable to constantly represent the internal switching frequency once the ADP1051 VDD voltage is applied. Jumper JP11 to Jumper JP13 can be used to configure OUTC or OUTD connected to SYNO. The user can test the SYNO clock through the test point TP35 or the SYNC pin in the JP17 and JP18 connectors.
Synchronization as a Slave Device This test can be done by applying an external clock signal in the TP25 test point. Alternatively, the external clock signal (such as SYNO signal in the master device) can be applied in the SYNC pin of the J17 or J18 connector. The settings can be programmed in the Sync Settings window (see Figure 50). To view the synchronization performance, try the following items: 11529-051
Figure 51. PGOOD Configurations
11529-052
• •
Enable and disable synchronization. Set different delays to see the phase shift between master device and slave device. Program the different phase capture range. If the external clock signal is generated by a signal generator, the user can try to program the clock signal in sweep mode or burst mode to see the synchronization locking or unlocking.
Figure 52. A VOUT_UV_FAULT Flag to Trigger PGOOD
11529-050
• •
Figure 50. Synchronization Configurations
Rev. 0 | Page 23 of 40
UG-566
Evaluation Board User Guide
PHASE SHIFTED FULL BRIDGE OPERATION
All the test items are similar to the general full bridge operation. The only difference is the SR reverse current protection. In case of SR reverse current, configure the synchronous rectifier to be disabled. The user can load the phase shifted full bridge project sample file, ADP1051-240-EVALZ-FSFB-SAMPLE.51s, to do the evaluation.
11529-054
The PWM settings for phase shifted full bridge operation is highly flexible. Either the QA/QB leg (controlled by OUTA/ OUTB PWM outputs) or the QC/QD leg (controlled by OUTC/ OUTD PWM outputs) can be configured to run in modulation mode. Figure 53 provides a PWM setting example of the QA/QB leg in positive modulation mode. In this case, the QA/QB leg is the leading leg and the QC/QD leg is the lagging leg.
Figure 54. PWM Waveforms under PSFB Operation
DIRECT PARALLELING The direct paralleling function is that multiple power supplies output rails are connected directly to a common bus without the existing of OR’ing devices. To overcome the challenges for direct paralleling, implement the following series of features: • • •
11529-053
• • •
Figure 53. Phase Shifted Full Bridge PWM Setting Window
Prebias start up. Current sharing. Use drooping current sharing or active current sharing (through the current share daughter card). Synchronous rectifiers reverse current protection to avoid sinking current in a power supply. Constant current control and hot-switching control. Synchronization to reduce the output voltage ripple. Conditional overvoltage protection for redundant control.
All the previous features are implemented in the ADP1051-240EVALZ evaluation board.
Rev. 0 | Page 24 of 40
Evaluation Board User Guide
UG-566 All the features listed in this section can be conducted in this direct paralleling system.
11529-056
Figure 56 shows the setup of two ADP1051-240-EVALZ evaluation boards connected in parallel for direct paralleling test. Each board can be controlled by SW1 on each board (R73 should be removed). Alternatively, the SW1 on Board B can be configured to control both Board A and Board B. In this case, remove the JP4 jumper on Board A. For synchronization, if the ADP1051 in Board A is assigned as a slave device, then assign the ADP1051 in Board B as a master device. In this case, the SW2 in Board A should be turned to the slave position and the SW3 in Board B should be turned to the master position.
Figure 55. Parallel Cable to Connect Two Evaluation Boards
BOARD A
ADP1051-240-EVALZ
J18
SW3
J2
J1
ADP1051DC1-EVALZ J2
J5
+
+
J8
DC POWER SUPPLY
JP4 SW1
J17
ELECTRONIC LOAD
SW2
BOARD B
–
ADP1051-240-EVALZ
J18
SW3
J2
J1
ADP1051DC1-EVALZ J2
J5
J6
J8 JP4 SW1
PC
J17
SW2
ADP-I2C-USB-Z 11529-055
–
J6
Figure 56. Direct Paralleling Configuration when Two Evaluation Boards are Connected in Parallel
Rev. 0 | Page 25 of 40
UG-566
Evaluation Board User Guide
ADDITIONAL GRAPHS 100
EFFICIENCY (%)
95
90 VIN = 36V DC VIN = 48V DC VIN = 60V DC VIN = 75V DC
85
11529-057
11529-060
80
75 0
5
10 LOAD CURRENT (A)
15
20
Figure 60. Thermal Image at 60 V DC Input, 20 A Load, No Airflow
11529-061
11529-058
Figure 57. Efficiency Curve at 36 V DC, 48 V DC, 60 V DC and 75 V DC Input
Figure 58. Thermal Image at 36 V DC Input, 20 A load, No Airflow
11529-059
Figure 61. Thermal Image at 75 V DC Input, 20 A Load, No Airflow
Figure 59. Thermal Image at 48 V DC Input, 20 A Load, No Airflow
Rev. 0 | Page 26 of 40
1
SW2
DRIVE C
SW1
DRIVE A
BANANA JACK
J5
VIN –
20mA/4.9V D7
R14 30.1kΩ
TP45
TP6
TP15
TP14
TP11
VIN –
+
TP9
220µF/100V 2 1
C1
VIN +
2
220µF/100V 2 1
C2
BANANA JACK
+
C27
C22
C28
1µF/25V
R32 0Ω
C23
1µF/25V
R26 0Ω
0.1µF/25V
10V_PRI
0.1µF/25V
10V_PRI
1 2 3 4
D2 1A/30V
VDD HB HO HS
VDD HB HO HS
8 7 6 5
R6 2Ω
R30 0Ω
R27 0Ω
R36 NC
TP8
DRIVE B
R21 10kΩ
R19 2Ω
1
Q5 90A/100V/ 6.8mΩ
SW1
R7 10kΩ
1
Q1 90A/100V/ 6.8mΩ
T4 PA1005.100NL
2 NC
R37
R34 0Ω
R33 0Ω
L3 560nH/20A/3.4mΩ
C29 0.1µF/25V
5V_PRI
C24 0.1µF/25V
5V_PRI
FULL BRIDGE MOSFET DRIVER CIRCUIT
LO VSS LI HI
U4 HIP2101EIBZT
DRIVE D
1 DRIVE A
TP13
LO VSS LI HI
8 7 6 5
D9 1A/30V
U1 HIP2101EIBZT
TP45 GROUND TEST POINT
1 2 3 4
3
DRIVE B
C18
C6
C17
C5
C4
C3
2.2µF/100V
L1 1µH/32A/2mΩ
2.2µF/100V
1
2.2µF/100V
J1
2.2µF/100V
2 1
1
2.2µF/100V
CS1+
2.2µF/100V
2 1 2
NC C64 NC C67
8 6 5 1 2
NC C65 NC C68
3 2 3
NC C66 NC C69
D3
8 7 6 5
8 7 6 5
U2
DRIVE D
2Ω
R20
D10 1A/30V
U5
VDD1 VIA VIB GND1
VDD1 VIA VIB GND1
ISOLATION BARRIER
VDD2 VOA VOB GND2
ADUM3210BRZ
VDD2 VOA VOB GND2
SW2
DRIVE C
R11 2Ω R8 10kΩ
1 2 3 4
1 2 3 4
R22 10kΩ
C85
C13
1 2 J12 JUMPER
NC
NC
2
R91 0Ω
R35 0Ω
R92 0Ω
TP39 GROUND TEST POINT
0
R93 0Ω C30 0.1µF/25V
3V3_SEC
TP44 GROUND TEST POINT
0
C25 0.1µF/25V
3V3_SEC
FULL BRIDGE STAGE
1
Q6 90A/100V/ 6.8mΩ
ADUM3210BRZ
D8 2A/100V
2A/100V
1
Q2 90A/100V/ 6.8mΩ D4 1A/30V 1 2 1 2
2 3 2 3
CS+ 3 4 7
CS– 1
8 6 5 OUTD OUTC
OUTB OUTA
T1 NC
TP4
TR5
2
D1 1A/30V
1
D33
1
D34
R25 2Ω
TP12
2
R4 2Ω
2 D5
3
R5
R2
2
2
3
SSR1
D11 1A/30V
TP30
10V_SEC
R9 2Ω
3
NC. OUTA VDD OUTB ADP3654
8 7 6 5
SW4
2
R88 10kΩ
R90 10kΩ
1 2 3 4
10nF 250V
R31 NC
3.6µH/24A/3.04mΩ
L2
R89 10kΩ
C71
NC INA PGND INB
U3
10nF 250V
C70
R103 10kΩ 1
R100 10kΩ R94 0Ω
R95 0Ω
SR MOSFET DRIVER CIRCUIT
C26 1µF/25V
1A/30V
D6
R24 10kΩ
R96 10kΩ
2 JUMPER
Q7 90A/100V/ 6.8mΩ
2A/100V
2
2A/100V 1 J13
10kΩ
10kΩ
1A/30V
Q4 90A/100V/ 6.8mΩ
2
Q3 90A/100V/ 6.8mΩ
3
Q8 90A/100V/ 6.8mΩ
TP10
SSR2
SSR1
TP5
7
6
5
TP3
ERI 25 5-2-2
3 4
1 2
T2
SW3
TR3
R1 2Ω 2 1
SSR2
1
CS1–
1
R97 10kΩ
2 1
1 2
R101 10kΩ 4.7µF/50V C12
1 1
J3 2
0.002Ω
Short
JUMPER Short
1
R3
TP42
SR2
SR1
TP7
R23
1 J4
0.002Ω
2 JUMPER
4.7µF/50V
R108 10kΩ 4.7µF/50V C8
CS2+_H
C9
R109 10kΩ 4.7µF/50V C14
1 1 2
R104 10kΩ PAD
1
+
Vo-
Vo+
SW4
PGND
10V_SEC
5V_PRI
10V_PRI
AGND
Vin-
Vin+
1
J2
+
BANANA JACK
Vo–
Vo+
SW4
PGND
10V_SEC
5V_PRI
10V_PRI
AGND
Vin–
Vin+
3V3_SEC
1
VO– J6
BANANA JACK VO+
TP41
3V3_SEC
2
4 7 PAD
9 PAD
9
Figure 62. ADP1051 Evaluation Board Schematic—Part I 2 1
Rev. 0 | Page 27 of 40
9
R110 10kΩ
4.7µF/50V C15 CS2–_L
1 2
CS2–_H
4.7µF/50V C16 CS2+_L
470µF/35V C10
470µF/35V C11
TP1
Evaluation Board User Guide UG-566
SCHEMATICS AND ARTWORK
ADP1051-240-EVALZ 11529-062
220Ω 2A/100V
0
C31 100nF/50V
1 2 3 4 5 6 7 8 9 10 11 OVP RTD AGND 3.3V SYNI/FLGI PG/ALT# CTRL SDA SCL OUTD OUTC
ADP1051 SOCKET
10V_VCC VS– VS+ CS2CS2+ VF CS1 SR1 SR2 OUTA OUTB
J8 22 21 20 19 18 17 16 15 14 13 12
FEED FORWARD FILTER
0
C35 100pF/50V
R58 NC
C42
CS2 CURRENT SENSE
R57 0Ω
CS2–
R59 0Ω
CS2+
TP19
OVP RTD AGND 3V3_SEC FLAGIN PGOOD CTRL SDA SCL OUTD OUTC
R60 NC
0Ω
R54
ADP1051 DAUGHTER CARD SOCKET
10V_VCC VSVS+ CS2CS2+ VF CS1 SR1 SR2 OUTA OUTB
SW4
CS2-_L
VF
2
0 0
t
RT1 100kΩ
RTD
CON8 SINGLE ROW
1 2 3 4 5 6 7 8
J15
CS1–
CS1+
CS–
0
0Ω
R123
R98 10kΩ
Q9
BSS138
2
R39 10Ω
IBUS
SYNC1
R56
R40 10Ω
TP16
0
FLAGIN
R10 1kΩ D16
D30
D29
D28
R74 1Ω
NC
NC
200mA/30V
CS1
OUTD
OUTC
OUTB
OUTA
100pF/50V
C34
200mA/30V
0
0
D39 200mA/30V
SYNC2
200mA/30V
D40
3V3_SEC
AGND
D44
J18
SW
SW3
SW
SW2
2
2
8
6
4
2
D43 200mA/30V
CTRL_1
SYNC2
SYNC1
0
2
SDA
SCL
TP18
TP17
NC
R43 10Ω
TP20
IBUS SR1
10V_SEC
OUTD
OUTC
OUTB
OUTA
SR2
R49 NC
R47 0Ω
NC
C40
C38 NC
TEST POINT
AGND
PGND
TP35
TP25
TP21
TP39
TP49
TP34
Vo-
Vo+
TP33
TP29
TP28
TP27
TP26
TP24
TP23
TP48
OUTPUT VOLTAGE SENSE
OVP
SDA_FILTER
SCL_FILTER
10Ω
1
AGND
PGND
SYNO
FLAGIN
PGOOD
AGND
VF_ISHARE
3V3_SEC
VF_ISHARE
JP2 JUMPER
R53
2
R52 NC
R48 0Ω
R105 0Ω
I2C/PMBUS FILTER
0
33pF/50V
C36
0
33pF/50V
R41 10Ω
NC
C41
NC
C39
2
R46 10Ω
10V_VCC
JP1 JUMPER
1
200mA/70V
D14
R107
C32
TP22
VS-
VS+
10V_SEC
3V3_SEC
R45 4.7kΩ
R102 4.7kΩ
JP9 SHORTPIN
1
D52 200mA/30V
SDA_FILTER
200mA/30V
D51
AGND
10V_VCC
CTRL_1
SDA_FILTER
R99 1Ω
D45 200mA/30V
SCL_FILTER
200mA/30V
D46
CON8 SHROUDED
7
5
3
1
200mA/30V
IBUS
SYNC2
SCL_FILTER
3
1
3
1
PARALLELING CONNECTOR
100Ω
D31 200mA/30V
R38
1
2 JP14 JUMPER
JP13 JUMPER 1 SYNO
2
10V_VCC
CTRL_1
D36 200mA/30V
SYNC1
1
2 JP12 JUMPER
JP11 JUMPER 1 SYNO
2
SDA_FILTER
FLAGIN
OUTC
OUTD
FLAGIN
OUTC
OUTD
200mA/30V
D38
CON8 SHROUDED
8
7
4
2
6
J17
5
3
1
20mA/4.9V D18
1kΩ
SCL_FILTER
CS1 CURRENT SENSE
3
D37 200mA/70V
D15 NC
NC
R140 NC
D13
CURRENT SHARE CONNECTOR
CS+
10nF/50V
C72
FLAGIN/SYNC/RTD CIRCUIT
R50 16.5kΩ
20mA/4.9V
D17
1kΩ
R51
PGOOD
CS2+ CS210V_SEC 3V3_SEC IBUS VF_ISHARE AGND AGND
1
D12
CS2+_L
2 1
R106
CS2+_H
Rev. 0 | Page 28 of 40 CS2-_H
Figure 63. ADP1051 Evaluation Board Schematic—Part II 1
UG-566 Evaluation Board User Guide 11529-063
TP37
JUMPER
JP5
VIN +_AUX
VIN +
TP50
TEST POINT
1
2
VEN
TP47
C48 10nF/50V
R76 220Ω
D32
2
2A/100V
1
D35
2
C62 220pF/100V
2A/100V
1
D21 200mA/70V
R68 8K2Ω
10kΩ
R64 1kΩ
C45 1µF/25V
D19 ZR431
0.1µF/100V
R81 1MΩ
C52
2.2µF/100V
Figure 64. ADP1051 Evaluation Board Schematic—Part III R87 36kΩ
R86 54.9kΩ
C56 1µF/25V
R72 5.1kΩ
Q10 800mA/60V R65 5.1kΩ
10V_PRI
D25 500mA/100V
C49
2.2µF/100V C50 1 2
R67
8 7 6 5
C59 1nF/50V
NCP1031DR2G
1 2 3 4
R78 20kΩ
C46 10nF/50V
VD GND VCC CT UV VFB OV COM
U14
VEN
R69 1kΩ
C57 0.1µF/25V
R85 10kΩ
TP38 2A/100V
D24
8 7 6 5
3V3_SEC
TP40
680Ω
R82
0
C63 1000pF/2000V
PGND
7
5
C61 1µF/25V
5V_PRI
R83 680Ω
ISOLATION BARRIER
3
2 4
8
3
1 2
D22 1 2A/100V
2
10V_SEC
SW
SW1
JP3 JUMPER
T3 FLYBACK TRANSFORMER 1
2
D20 1A/30V 1
R77 10kΩ
0
C43 0.1µF/25V
0 R70 0Ω
D26 MMBZ5231BLT1G
VDD2 VOA VOB GND2
D23 200mA/200V
C51 470pF/250V
10V_PRI
R79 20kΩ
C55 390pF/50V
VDD1 VIA VIB GND1
U7 ADUM3210BRZ
ON/OFF AND UVP CIRCUIT
1 2 3 4
AUXILIARY POWER SUPPLY
C44 0.1µF/25V
R80 14kΩ R84 5.1kΩ
2 1
R63 220kΩ
C60 10µF/16V
R66 100kΩ
10µF/16V C58
1 2
6
VIN +
3
2
1
0
FLAGIN
JUMPER
JP4
10µF/16V
5V_PRI
1
Rev. 0 | Page 29 of 40 2
10µF/16V C54 C53
5V_PRI
R111 NC
R71 C47 10nF/50V
220Ω
NC
D41
0
TP36
5.1kΩ
R75
CTRL
0Ω
R73
CTRL_1
MH1 R30-1011602
PGND
AGND
PGND
AGND
3V3_SEC
5V_PRI
10V_SEC
10V_PRI
VIN–
VIN+
MH3 R30-1011602
HEADERS
3V3_SEC
5V_PRI
10V_SEC
10V_PRI
VIN –
VIN +
MH2 R30-1011602
MH5 R30-1011602
MH4 R30-1011602
Evaluation Board User Guide UG-566
11529-064
Evaluation Board User Guide
11529-065
UG-566
11529-066
Figure 65. PCB Layout, Silkscreen Layer
Figure 66. PCB Layout, Top Layer
Rev. 0 | Page 30 of 40
UG-566
11529-067
Evaluation Board User Guide
11529-068
Figure 67. PCB Layout, Layer 2
Figure 68. PCB Layout, Layer 3
Rev. 0 | Page 31 of 40
Evaluation Board User Guide
11529-069
UG-566
11529-070
Figure 69. PCB Layout, Layer 4
Figure 70. PCB Layout, Layer 5
Rev. 0 | Page 32 of 40
UG-566
11529-071
Evaluation Board User Guide
Figure 71. PCB Layout, Bottom Layout
ADP1051DC1-EVALZ 10V R1
4.99kΩ
R2
4.99kΩ
3.3V
0.1% RESISTOR
VS– VS+
C2
C3
NC
NC
R3 C4 1nF/50V 200Ω
CS2– 0
PSON PGOOD FLAGIN 3.3V AGND RTD OVP
10
OUTA
11
OUTB
12
7 8 9
OUTC
13
OUTD
14
SCL
15
SDA
10 11 12 3.3V
16
PSON
17
ADP3303
10Ω
C8 1µF/16V
FLAGIN 3.3V
20
1
2
OVP RTD
U2
ADP1051
OUTA
ADD
OUTB
RES
OUTC
AGND
OUTD
100pF/50V
VS–
3
SR1 SR2
C12
1kΩ
VDD
24
0
23
J2
22
R10
10kΩ
21
R11
10kΩ
20
R13 2.2kΩ
R14 2.2kΩ
2 3 4 1
SCL SDA
0.1% RESISTOR 3.3V
19
C13
0.1µF/25V D2 200mA/70V
0 2 R12
CONN HEADER 4POS 0
1 2Ω
C14
330nF/50V 0
21 22
6 5
0.1µF/25V
10V
PGOOD
18
VS+
SR2
CS2–
9
R9
0
5
SR1
4
8
19
#SD
C10 0.1µF/25V
CS2+
CS1
6
7
VCORE
SDA
0
C11 100pF/50V
6
PG/ALT#
SCL
GND
7
0
CTRL
OUTD
#ERR
R8
18
OUTC
IN1
NR
11kΩ
17
OUTB
C9
0.1% RESISTOR
IN2
OUT2
R7 1kΩ
5
16
OUTA
3
SDA
SR2
2.2µF/10V
R16
R5 1kΩ
4
15
SR1
OUT1
3 C6 0.1µF/25V 4
8
0
VF
CS1
R4 11kΩ 0.1% RESISTOR
19.1kΩ
CS1
VF
0
R6
SCL
CS2+
VF
SYNCI/FLGI
VS+ CS2-
CS2+
14
VS–
1 2
13
10V
U1
2 C5 1nF/50V C7
J1
10V_VCC C1 0.1µF/25V 1
0.1% RESISTOR
0 3.3V R15
2.2kΩ
11529-072
CONN HEADER FEMALE 22PIN RTD OVP
Figure 72. ADP1051 Daughter Schematic
Rev. 0 | Page 33 of 40
Evaluation Board User Guide
11529-073
11529-076
UG-566
Figure 73. PCB Layout, Silkscreen Layer
11529-077
11529-074
Figure 76. PCB Layout, Layer 3
Figure 74. PCB Layout, Top Layer
11529-075
Figure 77. PCB Layout, Bottom Layer
Figure 75. PCB Layout, Layer 2
Rev. 0 | Page 34 of 40
Evaluation Board User Guide
UG-566
CURRENT SHARE DAUGHTER CARD D1
R1
1
51kΩ
1PS79SB31
2
VF_ISHARE
C24 R2
0.1µF/25V
1MΩ
R3 100kΩ R5 1MΩ
VSENSE C46
R45 1kΩ C47 10nF/50V
R11
10V_SEC
C23 66.5kΩ 0.1µF/25V
R10
R12 5.11kΩ
OUT1 –IN1 +IN1 +VS +IN2 –IN2 OUT2
OUT4 –IN4 +IN4 –VS +IN3 –IN3 OUT3
14 13 12 11 10 9 8
R15 169kΩ
0
OPC
VSENSE
0 3V3_SEC
3V3_SEC
0
8 POS
169kΩ
OPC
2 1
33.2kΩ 33.2kΩ
R13
R14 2kΩ
VSENSE
R7 R9
J1 1 2 3 4 5 6 7 8
CS2+ CS2– 10V_SEC 3V3_SEC IBUS VF_ISHARE AGND AGND
D2 1PS79SB31
R16 169kΩ
R17
169kΩ
IBUS
11529-078
R18 20.5kΩ
0
11529-081
Figure 78. Current Share Daughter Card Schematic
11529-079
CS2+
1 2 3 4 5.11kΩ 5 6 7
66.5kΩ
R4
R44 1kΩ
U1 ADA4851-4
Figure 79. PCB Layout, Silkscreen Layer
Figure 81. PCB Layout, Layer 2
11529-080
CS2–
10nF/50V
Figure 80. PCB Layout, Top Layer
Rev. 0 | Page 35 of 40
Evaluation Board User Guide
11529-083
11529-082
UG-566
Figure 83. PCB Layout, Bottom Layer
Figure 82. PCB Layout, Layer 3
Rev. 0 | Page 36 of 40
Evaluation Board User Guide
UG-566
ORDERING INFORMATION BILL OF MATERIALS Table 10. ADP1051 Evaluation Board Qty 2 8
1 4 4 1
Reference Designator C1, C2 C3, C4, C5, C6, C17, C18, C49, C50 C8, C9, C12, C14, C15, C16 C10, C11 C13, C85 C22, C26, C27, C45, C56, C61 C23, C24, C25, C28, C29, C30, C43, C44, C57 C31 C32, C36 C34, C35 C38, C39, C40, C41 C42 C46, C47, C48, C72 C51 C52 C53, C54, C58, C60 C55 C59 C62 C63 C64, C65, C66, C67, C68, C69 C70, C71 D1, D2, D4, D5, D6, D9, D10, D11, D20 D3, D8, D12, D22, D24, D32, D33, D34, D35 D7, D17, D18 D13, D15 D14, D21, D37 D16, D28, D31, D36, D38, D39, D40, D43, D44, D45, D46, D51, D52 D19 D23 D25 D26 D29, D30, D41 JP1, JP2, JP3, JP4, JP5, JP11, JP12, JP13, JP14 JP9 J1, J2, J5, J6 J3, J4, J12, J13 J8
1 2 1 1
J15 J17, J18 L1 L2
1
L3
6 2 2 6 9 1 2 2 4 1 4 1 1 4 1 1 1 1 6 2 9 9 3 2 3 13
1 1 1 1 3 9
Manufacturer EEEFK2A221AM C3225X7R2A225K
Part Number Digi-Key1 PCE4866TR-ND 445-4497-2-ND
Footprint SMC-AEC-TG-K16 C1210
Description Capacitor ALUM 220 μF 100 V 20% SMD Capacitor 2.2 μF/100 V X7R 1210
GRM32ER71H475KA88
490-1864-2-ND
C1210
Capacitor ceramic 4.7 μF 50 V 10% X7R 1210
EEEFK1V471AQ C3225X7R2A225K C2012X7R1E105K
PCE4862TR-ND 445-4497-2-ND 445-1354-2-ND
AL_CAP_H13 C1210 C0805
Capacitor ALUM 470 μF 35 V 20% SMD Capacitor ceramic 2.2 μF 100 V 10% X7R 1210 Capacitor ceramic 1 μF 25 V 10% X7R 0805
C1608X7R1E104K
445-1316-2-ND
C0603
Capacitor ceramic 0.1 μF 25 V 10% X7R 0603
C1608X7R1H104K C1608COG1H330J C1608COG1H101J C1608COG1H102J C1608X7R1H104K C1608X7R1H103J C1608C0G2E471J C2012X7R2A104K C3216X7R1C106K C1608C0G1H391J C1608COG1H102J C1608COG2A221J 202S43W102KV4E C3225X7R1H335K
445-1314-2-ND 445-1257-2-ND 445-1281-2-ND 445-1293-2-ND 445-1314-2-ND 445-5089-2-ND 445-2318-2-ND 445-1418-2-ND 445-4042-2-ND 445-1288-2-ND 445-1293-2-ND 445-2308-2-ND 709-1053-2-ND 445-3936-2-ND
C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0805 C1206 C0603 C0603 C0603 C1812 C1210
Capacitor ceramic 0.1μF 50 V 10% X7R 0603 Capacitor ceramic 33 pF 50 V 5% NP0 0603 Capacitor ceramic 100 pF 50 V 5% NP0 0603 Capacitor ceramic 1000 pF 50 V 5% NP0 0603 Capacitor ceramic 0.1 μF 50 V 10% X7R 0603 Capacitor ceramic 10 nF 50 V 5% X7R 0603 Capacitor ceramic 470 pF 250 V 5% NP0 0603 Capacitor ceramic 0.1 μF 100 V 10% X7R 0805 Capacitor ceramic 10 μF 16 V 10% X7R 1206 Capacitor ceramic 390 pF 50 V 5% NP0 0603 Capacitor ceramic 1 nF 50 V 5% NP0 0603 Capacitor ceramic 220 pF 100 V 5% NP0 0603 Capacitor ceramic 1 nF 2 KV 10% X7R 1812 Capacitor ceramic 3.3 μF 50 V 10% X7R 1210
C2012X7R2E103K MBR130LSFT1G
445-2280-2-ND MBR130LSFT1GOSTR-ND
C0805 SOD123
Capacitor ceramic 10 nF 250 V X7R 0805 Schottky diode 1 A 30 V SOD-123FL
MURA110T3G
MURA110T3GOSTR-ND
SMA
Diode ultrafast 2 A 100 V SMA
CMD15-21UBC/TR8 BAV99 BAV70WT1G BAT42WS-7
L62206CT-ND BAV99FSTR-ND BAV70WT1GOSTR-ND BAT42WSDITR-ND
D1206 SOT23 SOT323 SOD323
LED blue clear 1206 SMD Diode ultrafast HI COND 70 V SOT-23 Diode switch dual CC 70 V SOT323 Schottky diode 30 V 200MW SOD-323
ZR431F01TA MMBD1504A EGL34B-E3/83 MMBZ5231BLT1G BAT42WS-7 STC02SYAN
ZR431F01TR-ND MMBD1504ATR-ND EGL34B-E3/83-ND MMBZ5231BLT1GOSTR-ND BAT42WSDITR-ND S9000-ND
SOT23-IC SOT23 DO-213AA SOT23 SOD323 HEADER-SR-2
IC VREF shunt PREC ADJ SOT-23 Diode SS 200 V 200 MA SOT23 Diode 0.5A 100 V 50 NS MELF Diode Zener 5.1 V 225 MW SOT-23 Schottky diode 30 V 200 MW SOD-323 Connector jumper shorting tin
N/A 108-0740-001 N/A TSW-111-14-T-D
N/A J147-ND N/A SAM1058-11-ND
Shortpin B-JACK PADJUMPER HEADER-DR-22
PPC081LFBN-RC 75869-132LF IHLP5050FDER1R0M01 #7443630420 LER-20-63 IHLP2525EZERR56M01
S4108-ND 609-3530-ND 541-1032-2-ND N/A N/A IHLP2525EZERR56M01-ND
HEADER-I-SR-8 313-208-s2 IND-IHLP-5050FD LER-20-63
Single connect point of AGND and PGND Connector jack banana Power connector jumper on PCB Connector header 22POS 0.100 dual tin 22 male pin 2.54 Single row 8 female pin 2.54 mm Connector header 8POS dual vert PCB Power inductor 1.0 μH 32 A SMD Power inductor 4.2uH 24 A 3.04 mΩ SMD Power Inductor 3.6 μH 30 A 2.3 mΩ SMD power Inductor 0.56 μH 20 A SMD
Rev. 0 | Page 37 of 40
2525ez
UG-566 Qty 5 8 1 1 1 12
2 8 1 1 2 19
9
1 2 4 2 1 4 1 1 3 1 1 3 2 2 1 1 2 1 1 1 10
1 3
Evaluation Board User Guide
Reference Designator MH1, MH2, MH3, MH4, MH5 QA, QB, QC, QD, Q3, Q4, Q7, Q8 Q9 Q10 RT1
Manufacturer R30-1011602
R2, R5, R7, R8, R21, R22, R24, R67, R77, R85, R96, R98 R3, R23 R1, R4, R6, R9, R11, R19, R20, R25 R10 R14 R26, R32 R27, R30, R33, R34, R35, R47, R48, R54, R57, R59, R70, R73, R91, R92, R93, R94, R95, R105, R123 R31, R36, R37, R49, R58, R60, R107, R111, R140 R38 R39, R40 R41, R43, R46, R53 R45, R102 R50 R51, R56, R64, R69 R52 R63 R65, R72, R75 R66 R68 R71, R76, R106 R74, R99 R78, R79 R80 R81 R82, R83 R84 R86 R87 R88, R89, R90, R100, R101, R103, R104, R108, R109, R110 R97 SW1, SW2, SW3
Part Number Digi-Key1 952-1492-ND
Footprint MH
Description Standoff HEX M3 THR Brass 16 mm
IPD068N10N3 G
IPD068N10N3 G-ND
DPAK
MOSFET N-CH 100 V 90 A TO252-3
BSS138 MMBT2907A NCP15WF104F03RC
BSS138TR-ND MMBT2907AFSTR-ND 490-4803-2-ND
SOT23 SOT23 R0402
CRCW060310K0JNTA
CRCW060310K0JNTA-ND
R0603
MOSFET N-CH 50 V 220 MA SOT-23 Transistor GP PNP AMP SOT-23 Thermistor 100 kΩ NTC 0402 SMD resistance 1% beta Resistor 10 kΩ 5% 1/10 W 0603 SMD
ERJ-M1WTF2M0U CRCW08052R00JNEA
P2.0NDTR-ND 541-2.0ATR-ND
R2512 R0805
Resistor 0.002 Ω 1 W 1% 2512 Resistor 2 Ω 5% 1/8 W 0805 SMD
CRCW060310K0JNTA CRCW120630K1FKEA CRCW08050000Z0EA CRCW06030000Z0EA
CRCW060310K0JNTA-ND 541-30.1KFTR-ND 541-0.0ATR-ND 541-0.0GTR-ND
R0603 R1206 R0805 R0603
Resistor 10 kΩ 5% 1/10 W 0603 SMD Resistor 30.1 kΩ 1/4 W 1% 1206 SMD Resistor 0.0 Ω 1/8 W 0805 SMD Resistor 0.0 Ω 1/10 W 0603 SMD
CRCW06030000Z0EA
541-0.0GTR-ND
R0603
Resistor 0.0 Ω 1/10 W 0603 SMD
CRCW0603100RFKEA CRCW080510R0FKEA CRCW060310R0FKEA CRCW06034K10JNEA CRCW060316K5FKTA CRCW06031K00FKEA CRCW06031K00FKEA CRCW0603220KFKEA CRCW06035K10JNEA CRCW0805100KJNEA CRCW06038K20FKEA CRCW0603220RJNEA CRCW08051R00JNEA CRCW080520R0JNEA CRCW060314K0FKEA CRCW08051M00FKEA CRCW0805680RJNEA CRCW06035K10FKEA CRCW060354K9FKEA CRCW060336K0FKEA CRCW120620K0JNEA
541-100HCT-ND 541-10.0CTR-ND 541-10.0HTR-ND 541-4.7KGCT-ND CRCW060316K5FKTA-ND 541-1.00KHCT-ND 541-1.00KHCT-ND 541-220KHTR-ND 541-5.1KGCT-ND 541-100KATR-ND 541-8.20KHCT-ND 541-220GCT-ND 541-1.0ATR-ND 541-20ACT-ND 541-14.0KHTR-ND 541-1.00MCTR-ND 541-680ACT-ND 541-5.10KHTR-ND 541-54.9KHTR-ND 541-36.0KHTR-ND 541-20KETR-ND
R0603 R0805 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0805 R0603 R0603 R0805 R0805 R0603 R0805 R0805 R0603 R0603 R0603 R1206
Resistor 100 Ω 1/10 W 1% 0603 SMD Resistor 10.0 Ω 1/8 W 1% 0805 SMD Resistor 10.0 Ω 1/10 W 1% 0603 SMD Resistor 4.7 kΩ 1/10 W 5% 0603 SMD Resistor 16.5 kΩ 1% 1/10 W 0603 SMD Resistor 1.00 kΩ 1/10 W 1% 0603 SMD Resistor 1.00 kΩ 1/10 W 1% 0603 SMD Resistor 220 kΩ 1/10 W 1% 0603 SMD Resistor 5.1 kΩ 1/10 W 5% 0603 SMD Resistor 100 kΩ 1/8 W 5% 0805 SMD Resistor 8.20 kΩ 1/10 W 1% 0603 SMD Resistor 220 Ω 1/10W 5% 0603 SMD Resistor 1 Ω 5% 1/8W 0805 Resistor 20 Ω 1/8 W 5% 0805 SMD Resistor 14.0 kΩ 1/10 W 1% 0603 SMD Resistor 1.00 M Ω 1/8 W 1% 0805 SMD Resistor 680 Ω 1/8 W 5% 0805 SMD Resistor 5.10 kΩ 1/10 W 1% 0603 SMD Resistor 54.9 kΩ 1/10 W 1% 0603 SMD Resistor 36.0 kΩ 1/10 W 1% 0603 SMD Resistor 20 kΩ 1/4 W 5% 1206 SMD
CRCW080510K0JNEA EG1218
541-10KATR-ND EG1903-ND
R0805 SPDT-SLSW
Resistor 10 kΩ 1/8 W 5% 0805 SMD Switch slide SPDT 30 V.2A PC MNT
Rev. 0 | Page 38 of 40
Evaluation Board User Guide Qty 43
3 1 1
Reference Designator TP1, TP3, TP4, TP5, TP6, TP7, TP8, TP9, TP10, TP11, TP12, TP13, TP14, TP15, TP16, TP17, TP18, TP19, TP20, TP21, TP22, TP23, TP24, TP25, TP26, TP27, TP28, TP29, TP30, TP33, TP34, TP35, TP36, TP37, TP38, TP40, TP41, TP42, TP47, TP48, TP49, TP50, TP51 TP39, TP44, TP45 T1 T2
1
T3
1 2 3 1 1 1
T4 U1, U4 U2, U5, U7 U3 U14
Manufacturer 5010
UG-566 Part Number Digi-Key1 5010K-ND
GTP002 PA1005.100NL #750341378 BDC-25-69 #750341379
N/A 553-1529-2-ND N/A N/A N/A
BSER9-77
N/A
PA1005.100NL HIP2101EIBZT ADUM3210BRZ-RL7 ADP3654ARDZ-R7 NCP1031DR2G
553-1529-2-ND HIP2101EIBZTTR-ND ADUM3210BRZ-RL7TR-ND ADP3654ARDZ-R7-ND NCP1031DR2GOSTR-ND
Footprint TP-70
Description Test point PC
TP-70 dual P820X BDC_2512
Ground test point XFRMR current sense 2.0 MH 1:100 SMD Transformer ER25 5:2:2 Transformer ER25 5:2:2 36 V to 75 V input, 12 V 0.25 A pri output, 12 V, 0.25 A sec output, ER9.5 22:8:8 36 V to 75 V input, 12 V pri output, 12 V sec output, ER9.5 22:8:8 XFRMR current sense 2.0 MH 1:100 SMD IC driver half bridge 100 V 8EPSOIC iCoupler 2CH 8-SOIC IC MOSFET DVR 4 A dual HS SOIC_N_EP IC CTRLR PWM OTP OVD HV 8SOIC
PBSER9-77
P820X 8-SOIC-EP 8-SOIC 8-SOIC_N_EP 8-SOIC
N/A = not applicable.
Table 11. ADP1051 Daughter Card Qty 5 2 2 1 1 2 1 1 1 1 2 1 1 1 1 2 1 1 1 1 3 1 1 1 1
Reference Designator C1, C6, C9, C10, C13 C2, C3 C4, C5 C7 C8 C11, C12 C14 D2 J1 J2 R1, R2 R3 R4 R5 R6 R7, R9 R8 R10 R11 R12 R13, R14, R15 R16 U1 U2
Part Number Manufacturer Digi-Key1 C1608X7R1H104K 445-1316-2-ND C1608X7R1H104K 445-1316-2-ND C1608COG1H102J 445-1293-2-ND C1608X7R1A225K 445-5958-6-ND C1608X7R1C105K 445-1604-2-ND C1608COG1H101J 445-1281-2-ND C1608X7R1H334K 445-5950-2-ND BAV70WT1G BAV70WT1GOSTR-ND PPPC112LFBN-RC S7114-ND 69167-104HLF 609-2411-ND 9-1879360-4 9-1879360-4-ND CRCW0603200RFKEA 541-200HTR-ND TNPW060311K0BEEA TNP11.0KAATR-ND TNPW06031K00BEEA TNP1.00KAATR-ND CRCW080519K1FKEA 541-19.1KCTR-ND CRCW06031K00FKEA 541-1.00KHCT-ND CRCW060311K0FKEA 541-11.0KHTR-ND CRCW060310K0FKEA 541-10.0KHTR-ND TNPW060310K0BEEA TNP10.0KAATR-ND CRCW06032R00FKEA 541-2.00HHTR-ND CRCW06032K20FKEA 541-2.20KHTR-ND CRCW060310R0FKEA 541-10.0HTR-ND ADP3303ARZ-3.3 ADP3303ARZ-3.3-ND ADP1051ACPZ N/A
N/A = not applicable.
Rev. 0 | Page 39 of 40
Footprint C0603 C0603 C0603 C0603 C0603 C0603 C0603 SOT323 Header-dr-22 HEADER-L-SR-4 R0603 R0603 R0603 R0603 R0805 R0603 R0603 R0603 R0603 R0603 R0603 R0603 SO8 CP-24-7
Description Capacitor ceramic 0.1 μF 25 V 10% X7R 0603 Capacitor ceramic 0.1 μF 25 V 10% X7R 0603 Capacitor ceramic 1 nF 50 V 5% NP0 0603 Capacitor ceramic 2.2 μF 10 V 10% X7R 0603 Capacitor ceramic 1 μF 16 V 10% X7R 0603 Capacitor ceramic 100 pF 50 V 5% NP0 0603 Capacitor ceramic 330 nF 50 V 10% X7R 0603 Diode switch dual CC 70 V SOT323 Connector header FMAL 22PS.1" DL gold Connector header 4POS SGL PCB 30GOLD Resistor 4.99 kΩ 1/16 W 0.1% 0603 10PPM Resistor 200 Ω 1/10 W 1% 0603 SMD Resistor 11 kΩ 1/10 W 0.1% 0603 SMD Resistor 1.00 kΩ 1/10 W 0.1% 0603 SMD Resistor 19.1 kΩ 1/8 W 1% 0805 SMD Resistor 1.00 kΩ 1/10 W 1% 0603 SMD Resistor 11 kΩ 1/10 W 1% 0603 SMD Resistor 10 kΩ 1% 1/10 W 0603 SMD Resistor 10 kΩ 0.1% 1/10 W 0603 SMD Resistor 2 Ω 1% 1/10 W 0603 SMD Resistor 2.2 kΩ 1% 1/10 W 0603 SMD Resistor 10 Ω 1% 1/10 W 0603 SMD IC regulator LDO 200 MA 3.3 V 8-SOIC Digital controller ADP1051 CP-24-7
UG-566
Evaluation Board User Guide
Table 12. Current Share Daughter Card Qty 2 2 2 1 1 2 1 2 2 2 4 1 1 2 1
Reference Designator C23, C24 C46, C47 D1, D2 J1 R1 R2, R5 R3 R4, R11 R7, R9 R10, R12 R13, R15, R16, R17 R14 R18 R44, R45 U1
Part Number Manufacturer Digi-Key C1608X7R1H104K 445-1316-2-ND C1608X7R1H103J 445-5089-2-ND 1PS79SB31 1PS79SB31,315-ND PPC081LFBN-RC 09-3321-ND CRCW060351K0FKEA 541-51.0KHTR-ND CRCW06031M00FKEA 541-1.00MHTR-ND CRCW0603100KFKEA 541-100KHTR-ND CRCW060366K5FKEA 541-66.5KHTR-ND CRCW060333K2FKEA 541-33.2KHTR-ND CRCW06035K11FKEA 541-5.11KHTR-ND CRCW0603169KFKEA 541-169KHTR-ND CRCW06032K00FKEA 541-2.00KHTR-ND CRCW060320K5FKEA 541-20.5KHTR-ND CRCW06031K00FKEA 541-1.00KHCT-ND ADA4851-4YRUZ ADA4851-4YRUZ-ND
Footprint C0603 C0603 SOD523 HEADER-SR-8 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 R0603 TSSOP14
Description Capacitor ceramic 0.1 μF 25 V 10% X7R 0603 Capacitor ceramic 10000 pF 50 V 5% X7R 0603 Diode Schottky 30 V 200 mA SC-79 CONN HEADER 8POS 0.100 R/A 15AU Resistor 51.0 kΩ 1/10 W 1% 0603 SMD Resistor 1.00 MΩ 1/10 W 1% 0603 SMD Resistor 100 kΩ 1/10 W 1% 0603 SMD Resistor 66.5 kΩ 1/10 W 1% 0603 SMD Resistor 33.2 kΩ 1/10 W 1% 0603 SMD Resistor 5.11 kΩ 1/10 W 1% 0603 SMD Resistor 169 kΩ 1/10 W 1% 0603 SMD Resistor 2.00 kΩ 1/10 W 1% 0603 SMD Resistor 20.5 kΩ 1/10 W 1% 0603 SMD Resistor 1.00 kΩ 1/10 W 1% 0603 SMD IC op amp VF R-R quad LP 14-lead TSSOP
ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed. ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG11529-0-7/13(0)
Rev. 0 | Page 40 of 40
